Computer architecture

Lecture 11: Reduced Instruction Set Computers

Piotr Bilski

Characteristics of the RISC architecture

• Processor contains large number of the general purpose registers

• RISC compilers use procedures for the register usage optimization

• Number of the instructions is small in comparison with CISC architecture

• Instructions have basic structure• Instruction pipeline is optimized

Comparison between the selected processors

ParameterIBM 370

VAX 11

80486 SPARCMIPS R4000

PowerPCUltra Sparc

Prod. year 1973 1978 1989 1987 1991 1993 1996

Instructions number

208 303 235 69 94 225

Instruction size

2-6 B 2-57 B 1-11 B 4 B 4 B 4 B 4 B

Addressing modes

4 22 11 1 1 2 1

Register number

16 16 8 40-520 32 32 40-520

Cache size 64 kB 64 kB 8 kB 32 kB 128 kB 16/32 kB 32 kB

RISC and the programming languages

• High-level language – alleviations for the programmer, multiple hidden details

• Necessity to translate high-level language into the machine language

• Small high-level programs large machine programs

• Increase of the effectiveness requires construction of the complex compilers

Characteristics of the executed instructions

• Instruction types – instructions executed by the processor

• Types and number of the instruction arguments

• Instruction scheduling – pipelining

Analysis of the frequency of the executed instructions [%]

Language Pascal Fortran Pascal C SAL

Task Scientific Student System System System

Assigning 73 67 45 38 42

Loops 4 3 5 3 4

Call 1 3 15 12 12

If 20 11 29 43 36

Goto 2 9 0 3 0

Other 0 7 6 1 6

Dynamic occurenceWeighted according to the machine instruction

Weighted according to the memory reference

Language Pascal C Pascal C Pascal C

ASSIGN 45% 38% 13% 13% 14% 15%

LOOP 5% 3% 42% 32% 33% 26%

CALL 15% 12% 31% 33% 44% 45%

IF 29% 43% 11% 21% 7% 13%

GOTO 0 3% 0 0 0 0

other 6% 1% 3% 1% 2% 1%

Analysis of the frequency of the executed instructions (cont.)

Arguments processed by the instructions

Pascal C Average

Constant numbers

16 % 23 % 20 %

Scalar variables

58 % 53 % 55 %

Tables/ structures 26 % 24 % 25 %

Exploitation of the arguments in the procedure calls

Programs including: Compiler, interpreterSmall, non-numerical

programs

3-4 arguments 0-7 % 0-5 %

5-7 arguments 0-3 % 0 %

8-11 arguments 1-20 % 0-6 %

12 and more arguments

1-6 % 0-3 %

Register tables

• Requirement for the assignment operations optimization – registers

• Local variables should be stored in one register block

• Problem of passing arguments to funcions and returning variables

• Nested function calls and the number of the registers

Register windows

• Functions use small number of the local variables, so every function requires small number of registers

• Every function has different set of the registers assigned (so-called window)

• Neighbor windows overlap, allowing to pass arguments between functions

Register windows - organization

Parameter registers

Local registers

Temporary registers

Parameter registers

Local registers

Temporary registers

level I

level I+1

Call/return

Window registers - example

• Current window pointer (CWP)

• Saved window pointer (SWP)

Global variables

• Handled by the global registers set

• Problem of the global register addressing in the window – uniform addressing mode

• Decision about assignment of the variables to the register depends on the compiler

Registers table and cache

Large register table Cache memory

All local scalars Recently used local scalars

Single variables Memory blocks

Global variables pointed by the compiler

Global variables recently used

Variables stored depending on the function nesting

Variables stored depending on the swap algorithm

Register addressing Memory addressing

Registers table and cache (cont.)

R

Instruction

DecoderRow number

Data

DataA

Instruction

comparison

Data

Poi

nter

s

a)

b)

Register olptimization using compiler

• For the small number of registers, decision must be made, which variables should be assigned to them

• An infinite number of the symbolic registers is created, which are further mapped onto the real registers

• Assignment is the graph coloring problem

Graph coloring example

1

2 3

4

56

• Vertices are symbolic registers

• Colors are real registers

Register interference

Problems of the compiler design

• Does smaller program mean smaller machine code?

• Are programs containing more complex procedures faster?

proc. 1 proc. 2 proc. 3

RISC I 1,0 1,0 1,0

VAX 11 0,8 0,67

M68000 0,9 0,9

RISC instruction characteristics

• One instruction executed during the cycle

• Data transfer operations „from register to register”

• Only simple addressing modes

• Simple instruction formats

RISC machine instruction

• One instruction during one machine cycle

• Machine cycle is the time required to fetch two arguments from registers, performing ALU operation and storing result into the register

• no microcode, instruction executed by the hardware!

Data transfer register-register

• All data should be in registers

• Exceptions are memory references (LOAD, STORE)

• Smaller instruction list, simpler control unit

Add B C A

Add A C B

Subtract B D D

8 16 16 16

Add rA rB rC

Add rB rA rC

Subtract rD rD rB

8 4 4 4

Instruction size = 168 B Instruction size = 60 B

Simple instruction formats

• All instructions have constant size!• Simple instructions are easier to optimize

during compilation• ALU for the simpler instructions is simpler

and faster• Pipelining is more effective• Easier interrupt handling• The most frequently executed instructions

can be implemented in the hardware

CISC vs RISC

Processor Type Instruction sizeIndirect

addressingArgument number

R2000 RISC 4 B no 1

SPARC RISC 4 B no 1

IBM RS/6000 RISC 4 B no 1

Intel i860 RISC 4 B no 1

80486 CISC 12 B no 2

M68040 CISC 22 B yes 2

VAX CISC 56 B yes 6

Pipelining

• Register-to-register processing– Instruction fetching (F)– Instruction execution (E)

• Loading and writing into memory– Instruction fetching (F)– Instruction execution (E)– Memory operation (M)

Sequential operation and pipelining

F E M

F E M

F E M

F E M

F E M

F E M

F E M

Pipelining• 2-stage – one memory access

• 3-stage – two memory accesses

• 4-stage

F E M

F E

F E M

F E M

F E M

F E M

F E1 E2 M

F E1 E2 M

Pipelining with branch

Program:

100 LOAD X,A

101 ADD 1,A

102 JUMP 105

103 ADD A,B

104 SUB C,B

105 STORE A,Z

F E M

F E

F E

F

F E M

1 2 3 4 5 6 7 8

Insertion of the empty instruction

Program:

100 LOAD X,A

101 ADD 1,A

102 JUMP 106

103 NOOP

106 STORE A,Z

F E M

F E

F E

F E M

1 2 3 4 5 6 7 8

F E

Reversed instruction sequence

Program:

100 LOAD X,A

101 JUMP 105

102 ADD 1,A

105 STORE A,Z

F E M

F E

F E

F E M

1 2 3 4 5 6 7 8

RISC example – MIPS R4000

• 64-bit architecture processor (with such registers and ALU bus)

• In the R4000 there is one processor and one Memory Management Unit – MMU

• 32 general purpose registers, up to 128 kB of the cache memory (half for the instructions and data)

• Constant instruction format – 4 bytes

• No conditional codes

• Three instruction formats

MIPS R4000 instruction formats

Operation rs rt Immediate

Operation Target

6 5 5 16

6 26

Operation rs rt rd offset function

6 5 5 5 5 6

Operation with the immediate operand

branch

Register addressing

RISC example – Sun SPARC

• processor uses register windows (2 to 32 windows 24 registers each)

• Eight global registers (0-7)• Output registers (called with the called

procedure, 8-15)• Input registers (used with the calling

procedure, 24-31)• Local registers, labelled with 16-23• All instructions 32-bit long

SPARC instruction formats

Op relative shifting of the program counter

2 30

Op a cond. op2 rel. shift. of the progr. Count.

2 1 4 3 22

Op Target op2 Immediate constant

2 5 3 22

Op Target Op3 Src-1 FP-op Src-2

2 5 6 5 9 5

Op Target Op3 Src-1 0 dism. Src-2

2 5 6 5 1 8 5

Op Target Op3 Src-1 1 Imm. constant

2 5 6 5 1 13

call

branch

SETHI

Floating point format

Generic format