computer architecture: a constructive approach implementing smips arvind

Computer Architecture: A Constructive Approach

Implementing SMIPS

ArvindComputer Science & Artificial Intelligence Lab.Massachusetts Institute of Technology

January 12, 2012 L4-1http://csg.csail.mit.edu/SNU

The SMIPS ISAProcessor State

32 32-bit GPRs, R0 always contains a 0PC, the program countersome other special registers

Data types8-bit byte, 16-bit half word 32-bit word for integers

Load/Store style instruction setdata addressing modes- immediate & indexedbranch addressing modes- PC relative & register indirectByte addressable memory- big endian mode

All instructions are 32 bits


Instruction ExecutionExecution of an instruction involves

1. Instruction fetch2. Decode3. Register fetch4. ALU operation5. Memory operation (optional)6. Write back

and the computation of the address of the next instruction


Implementing an ISAInstructions fetch

requires an Instruction memory, PCDecode

requires understanding the instruction formatRegister Fetch

requires interaction with a register file with a specific number of read/write ports

ALU must have the ability to carry out the specified ops

Memory operations requires a data memory

Write-back requires interaction with the register file


Instruction formats

Only three formats but the fields are used differently by different types of instructions

6 5 5 16opcode rs rt immediate I-type

6 5 5 5 5 6opcode rs rt rd shamt func R-type

6 26opcode target J-type


Instruction formats cont

Computational Instructions

Load/Store Instructions

opcode rs rt immediate rt (rs) op immediate

6 5 5 5 5 6 0 rs rt rd 0 func rd (rs) func (rt)

rs is the base registerrt is the destination of a Load or the source for a Store

6 5 5 16 addressing modeopcode rs rt displacement (rs) + displacement31 26 25 21 20 16 15 0


Control InstructionsConditional (on GPR) PC-relative branch

target address = (offset in words)4 + (PC+4) range: 128 KB range

Unconditional register-indirect jumps

Unconditional absolute jumps

target address = {PC<31:28>, target4} range : 256 MB range

6 5 5 16opcode rs offset BEQZ, BNEZ

6 26opcode target J, JAL

6 5 5 16opcode rs JR, JALR

jump-&-link stores PC+4 into the link register (R31)


A single-cycle implementation

A single-cycle MIPS implementation requires: A register file with 2 read ports and a write port An instruction memory , separate from data memory

so that we can fetch an instruction as well as perform a data operation (Load/store) on the memory

fetch & execute

pc

iMem dMem

rfCPU


but first a digression on types …


Example: Complex Addition

typedef struct{ Int#(t) r; Int#(t) i;} Complex#(numeric type t) deriving (Eq,Bits); function Complex#(t) \+ (Complex#(t) x, Complex#(t) y); Int#(t) real = x.r + y.r; Int#(t) imag = x.i + y.i; return(Complex{r:real, i:imag});endfunction

What is the type of this + ?


Example: A 4-Instruction ISA

typedef enum {R0;R1;R2;…;R31} RName;

typedef union tagged { struct {RName dst; RName src1; RName src2;} Add; struct {RName condR; RName addrR;} Bz; struct {RName dst; RName addrR;} Load; struct {RName valueR; RName addrR;} Store} Instr deriving(Bits, Eq);

typedef Bit#(32) Iaddress;typedef Bit#(32) Daddress;typedef Bit#(32) Value;


Deriving Bits

To store datatypes in register, fifo, etc. we need to know how to represent them as bits (pack) and interpret their bit representation (unpack)Deriving annotation automatically generates the “pack” and “unpack” operations on the type (simple concatenation of bit representations of components)

typedef struct { … } Foo deriving (Bits);


Tagged Unions: Bit Representation

00 dst src1 src2

01 condR addrR

10 dst addrR

11 dst imm

typedef union tagged { struct {RName dst; RName src1; RName src2;} Add; struct {RName condR; RName addrR;} Bz; struct {RName dst; RName addrR;} Load; struct {RName dst; Immediate imm;} AddImm;} Instr deriving(Bits, Eq);

Automatically derived representation; can be customized by the user written pack and unpack functions


Pattern-matching: A convenient way to extract datastructure components

The &&& is a conjunction, and allows pattern-variables to come into scope from left to right

case (m) matches tagged Invalid : return 0; tagged Valid .x : return x;endcase

if (m matches (Valid .x) &&& (x > 10))

typedef union tagged { void Invalid; t Valid;} Maybe#(type t);

x will get bound to the appropriate part of m


now back to SMIPS …


Single-Cycle SMIPS

PC

InstMemory

Decode

Register File

Execute

DataMemory

+4


Datapath is shown only for convenience; it will be derived automatically from the high-level textual description

Single-Cycle SMIPS code structure

module mkProc(Proc); Reg#(Addr) pc <- mkRegU; RFile rf <- mkRFile; Memory mem <- mkMemory; rule fetchExecute; //fetch

let instResp <- mem.iside(MemReq{…}); //decode let decInst = decode(instResp); //execute let execInst = exec(decInst, pc, rVal1, rVal2); if(instType Ld || St) … mem.dside(MemReq{…}); pc <= execInst.brTaken ? execInst.addr : pc + 4; //writeback if(instType Alu || Ld) rf.wr(rDst,data); endrule endmodule;


Type: Instr (partial definition)Captures the fields for each instructiontypedef union tagged { struct{Rindx rbase; Rindx rdst; Simm offset;} LW; struct{Rindx rbase; Rindx rsrc; Simm offset;} SW;

struct{Rindx rsrc; Rindx rdst; Simm imm;} ADDIU; struct{Rindx rsrc; Rindx rdst; Shamt shamt;} SLL; struct{Rindx rsrc1; Rindx rsrc2; Rindx rdst; } ADDU;

struct{Target target; } J; struct{Rindx rsrc; } JR; struct{Rindx rsrc; Rindx rdst; } JALR; struct{Rindx rsrc1; Rindx rsrc2; Simm offset;} BEQ; struct{Rindx rsrc; Simm offset; } BLEZ; void ILLEGAL;} Instr deriving(Eq);

We need to define our own pack/unpack functions to match the MIPS instruction formats


Miscellaneous type defs


typedef Bit#(5) Rindx;typedef Bit#(16) Simm;typedef Bit#(16) Zimm;typedef Bit#(5) Shamt;typedef Bit#(26) Target;

typedef enum {Alu, Ld, St, Other} IType deriving(Bits, Eq);

typedef enum {Eq, Neq, Le, Lt, Ge, Gt, J, JR, N} BrType deriving(Bits, Eq);

typedef enum {Add, Sub, And, Or, Xor, Nor, Slt, Sltu, LShift, RShift, Sra}

Func deriving(Bits, Eq);

pack for type Instr partial definition

function Bit#(32) pack( Instr instr ); case ( instr ) matches tagged LW .it : return {opLW, it.rbase, it.rdst, it.offset}; tagged SW .it : return

{opSW, it.rbase, it.rsrc, it.offset}; tagged ADDIU .it : return

{opADDIU, it.rsrc, it.rdst, it.imm}; tagged SLL .it : return

{opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSLL}; tagged J .it : return {opJ, it.target}; tagged BEQ .it : return {opBEQ, it.rsrc1, it.rsrc2, it.offset}; endcaseendfunction

Also need to define constants opLW, …January 12, 2012 L4-20http://csg.csail.mit.edu/SNU

unpack for type Instr partial definition

function Instr unpack( Bit#(32) instrBits ); let opcode = instrBits[ 31 : 26 ]; let rs = instrBits[ 25 : 21 ]; let rt = instrBits[ 20 : 16 ]; let rd = instrBits[ 15 : 11 ]; let shamt = instrBits[ 10 : 6 ]; let funct = instrBits[ 5 : 0 ]; let imm = instrBits[ 15 : 0 ]; let target = instrBits[ 25 : 0 ];

case ( opcode ) opLW : return

LW {rbase:rs, rdst:rt, offset:imm }; … default : return ILLEGAL; endcaseendfunction


unpack for type Instr partial definition

case ( opcode ) opLW : return LW {rbase:rs, rdst:rt, offset:imm}; opADDIU : return ADDIU {rsrc:rs, rdst:rt, imm:imm}; opJ : return J {target:target }; opJAL : return JAL {target:target }; opFUNC : case ( funct ) fcSLL : return SLL

{ rsrc:rt, rdst:rd, shamt:shamt }; fcADDU : return ADDU

{ rsrc1:rs, rsrc2:rt, rdst:rd }; fcJR : return JR { rsrc:rs }; fcJALR : return JALR {rsrc:rs, rdst:rd}; default : return ILLEGAL; endcase default : return ILLEGAL; endcase


Decoding Instructions: extracts fields needed for execution from each instruction

decode

instbranchComp

rDst

rSrc1

rSrc2

immext

aluFunc

instType31:26

31:26

5:0

31:26

20:16

15:11

25:21

20:16

15:0

25:0


Pure combinational logic: will be derived automatically from the high-level description

Decoding Instructionsfunction DecodedInst decode(Bit#(32) inst, Addr pc); DecodedInst dInst = ?;

let opcode = instrBits[ 31 : 26 ]; let rs = instrBits[ 25 : 21 ]; let rt = instrBits[ 20 : 16 ]; let rd = instrBits[ 15 : 11 ]; let shamt = instrBits[ 10 : 6 ]; let funct = instrBits[ 5 : 0 ]; let imm = instrBits[ 15 : 0 ]; let target = instrBits[ 25 : 0 ];

case (opcode) ... endcase return dInst;endfunction


Decoding Instructions:Load & Store case (opcode) LW, SW: begin dInst.instType = opcode==LW ? Ld : St; dInst.aluFunc = Add; dInst.rDst = rt dInst.rSrc1 = rs dInst.rSrc2 = rt dInst.imm = signExtned(imm); end … endcase


Decoding Instructions:R-Type ALU case (opcode) … RAlu: begin dInst.instType = Alu; dInst.aluFunc = case (funct) ... endcase; dInst.rDst = rd; dInst.rSrc1 = rs; dInst.rSrc2 = rt; end … endcase


Decoding Instructions:I-Type ALU case (opcode) … IAlu: begin dInst.instType = Alu; dInst.aluFunc = case (funct) ... endcase; dInst.rDst = rt; dInst.rSrc1 = rs; dInst.imm = opcode==SignedIAlu ? signExtend(imm): zeroExtend(imm); end … endcase


Decoding Instructions:Jump case (opcode) … J, JAL: begin dInst.instType = opcode==J ? J : Jal; dInst.rDst = 31; dInst.imm = zeroExtend({target, 2’b00}); end rJump: begin dInst.instType = funct==JR ? Jr : Jalr; dInst.rDst = rd; dInst.rSrc1 = rs; end …. endcase


Decoding Instructions:Branch case (opcode) … Branch: begin dInst.instType = Br; dInst.branchComp = case (opcode) ... endcase; dInst.rSrc1 = rs; dInst.rSrc2 = rt; dInst.imm = signExtend({imm, 2’b00}); end … endcase


computer architecture: a constructive approach implementing smips arvind

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