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COMP541COMP541

More on More on State Machines;State Machines;and Video Monitorsand Video Monitors

Montek SinghMontek Singh

Feb 22, 2012Feb 22, 2012

OutlineOutline Last FridayLast Friday’’s labs lab

Tips/discussionTips/discussion

How to generate video signalHow to generate video signal

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What did you have trouble What did you have trouble with in lab?with in lab?

How about making a BCD stop How about making a BCD stop watch?watch? Each digit counts 0 to 9, and then wraps aroundEach digit counts 0 to 9, and then wraps around

i.e., display is decimal number, not hexi.e., display is decimal number, not hex

Do the following:Do the following: Separate the 16-bit number into four 4-bit numbersSeparate the 16-bit number into four 4-bit numbers

reg [3:0] A3, A2, A1, A0;reg [3:0] A3, A2, A1, A0;For A0: on each clock tick…For A0: on each clock tick…

– if this digit is 9, change it to 0, else add 1 to itif this digit is 9, change it to 0, else add 1 to itFor A1, A2, A3: on each clock tick…For A1, A2, A3: on each clock tick…

– if all lower A’s are at 9, thenif all lower A’s are at 9, then» if this digit is 9, change it to 0, else add 1 to itif this digit is 9, change it to 0, else add 1 to it

– else this digit does not changeelse this digit does not change

Slow it down to tick once per secondSlow it down to tick once per secondhave a separate counter to count 2have a separate counter to count 22626 or 2 or 22727 clock ticks clock ticksupdate the 4-digit number only whenever this counter fills update the 4-digit number only whenever this counter fills

up!up! 4

Reminder: Good Verilog PracticesReminder: Good Verilog Practices Best to use single clock for all FFsBest to use single clock for all FFs

Make all signals synchronous to one clkMake all signals synchronous to one clkNo: (posedge button) etc.No: (posedge button) etc.No: (posedge button or negedge button)No: (posedge button or negedge button)

– not supported by current boardnot supported by current board– just use either posedge or negedge onlyjust use either posedge or negedge only

Avoids Avoids ““weirdweird”” and frustrating problems and frustrating problems

Multiple modulesMultiple modules Tested individuallyTested individually Top level has input and outputsTop level has input and outputs

One module per fileOne module per file Just to make it easier to follow and testJust to make it easier to follow and test

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Reminder: Comb. vs. sequentialReminder: Comb. vs. sequential Continuous assignment (assign)Continuous assignment (assign)

works only for combinational logicworks only for combinational logicwire X;wire X;

assign X = …assign X = …

Procedural assignment (always/if-else/case-Procedural assignment (always/if-else/case-default)default) works for sequential logicworks for sequential logic

generate FFs and latches (plus gates)generate FFs and latches (plus gates)

also for combinational but only under some strict also for combinational but only under some strict conditionsconditionscan optimize away unnecessary registers …can optimize away unnecessary registers …… … if synthesizer detects all possibilities covered (i.e. no if synthesizer detects all possibilities covered (i.e. no state needed)state needed)

Look at the synthesizer logLook at the synthesizer log

Procedural Assignment 1Procedural Assignment 1module C2(output reg C = 0, input A, input B);module C2(output reg C = 0, input A, input B);

always @ (*)always @ (*)

case ({A, B})case ({A, B})

2'b11: C <= 1;2'b11: C <= 1;

default: C <= 0;default: C <= 0;

endcaseendcase

endmoduleendmodule

Schematic next pageSchematic next page

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SchematicSchematic

LUT is a look-up tableLUT is a look-up table Double clicking it showsDouble clicking it shows

Procedural Assignment 2Procedural Assignment 2module C1(output reg C = 0, input A, input B);module C1(output reg C = 0, input A, input B);

always @ (*)always @ (*)beginbegin

if(A == 1 && B == 1)if(A == 1 && B == 1)C <= 1;C <= 1;

endendendmoduleendmodule

Synthesizer now saysSynthesizer now saysWARNING:Xst:737 - Found 1-bit latch for signal <C>.WARNING:Xst:737 - Found 1-bit latch for signal <C>.WARNING:Xst:1426 - The value init of the FF/Latch C hinder the constant WARNING:Xst:1426 - The value init of the FF/Latch C hinder the constant cleaning in the block C1.cleaning in the block C1.

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SchematicSchematic ExplanationsExplanations

LDE is latchLDE is latch Small box is a buffer for the clockSmall box is a buffer for the clock VVcccc or V or Vdddd is voltage supply is voltage supply

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In fact…In fact… If I change the INIT of C to:If I change the INIT of C to:

output reg C = 1output reg C = 1

Synthesizer saysSynthesizer says

INFO:Xst:1304 - Contents of register <C> in INFO:Xst:1304 - Contents of register <C> in unit <C1> never changes during circuit unit <C1> never changes during circuit operation. The register is replaced by logic.operation. The register is replaced by logic.

SchematicSchematicmodule C1(output reg C = 1, input A, input B);module C1(output reg C = 1, input A, input B);

always @ (A or B)always @ (A or B)beginbegin

if(A == 1 && B == 1)if(A == 1 && B == 1)C <= 1;C <= 1;

endendendmoduleendmodule

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VGA MonitorsVGA Monitors

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How Do Monitors Work?How Do Monitors Work? Origin is TV, so letOrigin is TV, so let’’s look at thats look at that

LCDs work on different principle, but all signaling still LCDs work on different principle, but all signaling still derived from TV of 1940sderived from TV of 1940s

Relies on your brain to do two thingsRelies on your brain to do two things Integrate over spaceIntegrate over space Integrate over timeIntegrate over time

Many Still ImagesMany Still Images Video (and movies) are a series of stillsVideo (and movies) are a series of stills

If stills go fast enough your brain interprets as moving If stills go fast enough your brain interprets as moving imageryimagery50-60 Hz or more to not see flicker50-60 Hz or more to not see flicker

– ““1 Hz” means once per second1 Hz” means once per second

In fact, even if the scene does not change…In fact, even if the scene does not change…… … a single a single ““stillstill”” image is displayed repeatedly over time image is displayed repeatedly over timeWhy? Phosphor persistence variesWhy? Phosphor persistence varies

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Cathode Ray Tube (CRT)Cathode Ray Tube (CRT)

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From wikipedia: http://en.wikipedia.org/wiki/Cathode_ray_tube

Deflection CoilsDeflection Coils

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Simple Scanning TVSimple Scanning TV Electron beam scans acrossElectron beam scans across Turned off whenTurned off when

Scanning back to the left (horizontal retrace Scanning back to the left (horizontal retrace --------)) Scanning to the top (vertical retrace Scanning to the top (vertical retrace ________))

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Scanning: Interlaced vs. Scanning: Interlaced vs. ProgressiveProgressive TVs use TVs use interlacinginterlacing

Every other scan line is swept per fieldEvery other scan line is swept per field Two fields per frame (30Hz)Two fields per frame (30Hz) Way to make movement less disturbingWay to make movement less disturbing

Computers use Computers use progressive scanprogressive scan Whole frame refreshed at onceWhole frame refreshed at once 60Hz or more, 72Hz looks better60Hz or more, 72Hz looks better

Similar notation used for HDSimilar notation used for HD ii = interlaced (1080i) = interlaced (1080i) pp = progressive (1080p) = progressive (1080p) which better?which better?

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ColorColor Three colors of phosphorThree colors of phosphor

three beams, one each for the three phosphorsthree beams, one each for the three phosphors Black: all beams offBlack: all beams off White: all beams onWhite: all beams on

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Picture is a bit misleading. Mask (or aperture grill) ensures beams hit only correct color phosphor.

What about LCD?What about LCD? How do LCD monitors work?How do LCD monitors work?

internals are very differentinternals are very differentno beams, tubesno beams, tubesmade up of tiny LCD cellsmade up of tiny LCD cells

However, external signaling is the same!However, external signaling is the same! for compatibilityfor compatibility

Same goes for micro-mirror projectorsSame goes for micro-mirror projectors

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VGA SignalingVGA Signaling Timing signalsTiming signals

horizontal synchorizontal sync vertical syncvertical sync

Color valuesColor values R, G, BR, G, B

VGA TimingVGA Timing You supply two pulsesYou supply two pulses

hsync and vsynchsync and vsync allow the monitor to lock onto allow the monitor to lock onto

timingtiming

One vsync per frameOne vsync per frame One hsync per scan lineOne hsync per scan line

hsync does not stop during hsync does not stop during vsync pulsevsync pulse

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Image from dell.com

Horizontal Timing TermsHorizontal Timing Terms Horizontal timing:Horizontal timing:

hsync pulsehsync pulse Back porch (left side of display)Back porch (left side of display) Active VideoActive Video

Video should be Video should be blankedblanked (not sent) at other times (not sent) at other times Front porch (right side)Front porch (right side)

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Picture not accurate for our case; just for illustration.

Video and HSYNC not on same wire

Horizontal TimingHorizontal Timing

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640 Horizontal Dots 640 Horizontal Dots Horiz. Sync Polarity NEG Horiz. Sync Polarity NEG Scanline time (A) 31.77 usScanline time (A) 31.77 usSync pulse length (B) 3.77 usSync pulse length (B) 3.77 usBack porch (C) 1.89 usBack porch (C) 1.89 usActive video (D) 25.17 us Active video (D) 25.17 us Front porch (E) 0.94 usFront porch (E) 0.94 us

Image from http://www.epanorama.net/documents/pc/vga_timing.html

This diagram shows video as a digital signal. It’s not – video is an analog level.

us = microsecond

Vertical Timing (note ms, not us)Vertical Timing (note ms, not us)

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Vert. Sync Polarity NEGVert. Sync Polarity NEGVertical Frequency 60HzVertical Frequency 60HzTotal frame time (O) 16.68 ms Total frame time (O) 16.68 ms Sync length (P) 0.06 msSync length (P) 0.06 msBack porch (Q) 1.02 msBack porch (Q) 1.02 msActive video (R) 15.25 msActive video (R) 15.25 msFront porch (S) 0.35 msFront porch (S) 0.35 ms

Timing as PixelsTiming as Pixels Easiest to derive all timing from single-pixel Easiest to derive all timing from single-pixel

timingtiming

How How ““longlong”” is a pixel? is a pixel? Active video / number of pixelsActive video / number of pixels 25.17 us / 640 = 39.32ns25.17 us / 640 = 39.32ns Conveniently close to 25 MHz – just use thatConveniently close to 25 MHz – just use that Actual VESA spec is 25.175 MHzActual VESA spec is 25.175 MHz

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StandardsStandards 640 x 480 (sometimes x 60Hz) is 640 x 480 (sometimes x 60Hz) is ““VGAVGA””

I will give you spec sheets in labI will give you spec sheets in lab

You can try for 800x600 at 60 Hz (40 MHz You can try for 800x600 at 60 Hz (40 MHz exactly) exactly) or 800x600 at 72 Hz (50 MHz exactly)or 800x600 at 72 Hz (50 MHz exactly)

Note that some standards have vsync and Note that some standards have vsync and hsync positive true, some negative truehsync positive true, some negative true choose correct polaritychoose correct polarity determine by experimentation!determine by experimentation!

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Color DepthColor Depth Voltage of each of RGB determines colorVoltage of each of RGB determines color

3-bit for red and green3-bit for red and green 2-bit for blue (why?)2-bit for blue (why?) All on for whiteAll on for white

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What To Do FridayWhat To Do Friday1.1. First finish previous labFirst finish previous lab

2.2. Make Verilog module to generate Make Verilog module to generate hsync, vsync, horizontal count, vertical count, and hsync, vsync, horizontal count, vertical count, and

signal to indicate active videosignal to indicate active video

3.3. Use higher-level module to drive RGB using Use higher-level module to drive RGB using counts gated by activecounts gated by active Just do something simple; need to meet 25MHz Just do something simple; need to meet 25MHz

constraintconstraint

4.4. Later we will use memory addressed by Later we will use memory addressed by counts to make terminalcounts to make terminal

I will post lab writeup on website by ThursdayI will post lab writeup on website by Thursday

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What do you Need for VGA?What do you Need for VGA? Think firstThink first

Need counter(s)?Need counter(s)? Will you need a state machine?Will you need a state machine?

Sketch out a designSketch out a design Block diagramBlock diagram

Test individually in labTest individually in lab Keep in mindKeep in mind

Verilog has all these operators (and more; see Verilog Verilog has all these operators (and more; see Verilog ref.)ref.)

==, <, >, <=, >===, <, >, <=, >=

Future Labs PreviewFuture Labs Preview VGA timing generator (Feb 24)VGA timing generator (Feb 24) Character terminal (learn memories)Character terminal (learn memories) MIPS datapathMIPS datapath Add load/store; add branchingAdd load/store; add branching Add peripherals (joystick or keyboard)Add peripherals (joystick or keyboard) Final projectFinal project

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VGA LinksVGA Links VGA TimingVGA Timing

Recommended: Recommended: http://tinyvga.com/vga-timinghttp://tinyvga.com/vga-timing http://www.epanorama.net/documents/pc/vga_timing.htmlhttp://www.epanorama.net/documents/pc/vga_timing.html

InterestingInteresting http://www.howstuffworks.com/tv.htmhttp://www.howstuffworks.com/tv.htm http://computer.howstuffworks.com/monitor.htmhttp://computer.howstuffworks.com/monitor.htm http://www.howstuffworks.com/lcd.htmhttp://www.howstuffworks.com/lcd.htm http://plc.cwru.edu/http://plc.cwru.edu/

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Next WeekNext Week Sequential TimingSequential Timing MemoriesMemories

Homework #1 due (Wed, Feb 29)Homework #1 due (Wed, Feb 29)

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