communicating transaction processes
DESCRIPTION
Communicating Transaction Processes. P.S. Thiagarajan National University of Singapore Joint Work with: Abhik Roychoudhury; ……. The Main Features. To support System Level Design One Level of Abstraction higher than C, C++, VHDL .. UML-compatible MSCS + Asynchronous control flow - PowerPoint PPT PresentationTRANSCRIPT
21.10.02 ES Seminar 1
Communicating Transaction Processes
P.S. ThiagarajanNational University of Singapore
Joint Work with: Abhik Roychoudhury; ……
21.10.02 ES Seminar 2
The Main Features
• To support System Level Design– One Level of Abstraction higher than C, C++,
VHDL ..• UML-compatible
– MSCS + Asynchronous control flow– Based on MSCs (Message Sequence Charts)– Sequence Diagrams
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Why System Level Design?
• Closer to end-use(r) .• Less detailed and more architecture-neutral.• Easier reuse/adaptaton.• Easier to verify.
– Safety-critical applications need to be correct.– Catch design errors early.– Coupling with a correct-by-construction
synthesis method is an attractive option.
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What is Available?
• Data flow graphs.• Automata of various kinds.• Petri nets.• State charts.• Esterel, Lustre.• SDL, UML.
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Why UML-compatible?
• UML is getting rapidly established as a standard.– Mainly in software engineering projects– Increasingly so in embedded systems domain.
• Offers a suite of graphical notations:– Multiple views– Behavioral and structural diagrams.– Object orientation.
Reuse, adaptation
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An Idealized Design FlowRequirements
Exec. Specifications.
Intermediate representation
SW/HW Implementation.
High Level Description
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Requirements and Exec. Specifications
• Requirements : Message Sequence Charts (MSCs)
• Exec. Specifications :– State charts.
• UML supports both but no clear distinction made.• Other Exec. Spec. :
– Petri nets, – MPAs (Message Passing Automata), ….
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MSCs
• Message Sequence Charts:– Describe scenarios.– A finite pattern of interaction between agents
(object instances,..).– A story
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Message Sequence Charts
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Message Sequence Charts
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Message Sequence Charts
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internal action
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Message Sequence Charts
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internal actions
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Message Sequence Charts
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Message Sequence Charts
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Message Sequence Charts
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Message Sequence Charts
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Message Sequence Charts
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Message Sequence Charts
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Message Sequence Charts
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Message Sequence Charts
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Message Sequence Charts
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CTPs
• Communicating Transaction Processes.• An executable spec. mechanism.
– Based on MSCs.• A network of interacting agents.
– Agent’s interaction pattern behavior: Standard distributed system model
– Interaction: Guarded choice of MSCs. Transaction schemes.
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Distributed System Models
• Petri nets• Data flow graphs• Statecharts• Distributed transition systems (many
kinds!)• Process algebras (CCS, CSP, …)
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PI1 IB1 IB2 PI2
I1
B
I2
P2
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PI1 IB1 IB2 PI2
I1
B
I2
P2
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PI1 IB1 IB2 PI2
I1
B
I2
P2
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PI1 IB1 IB2 PI2
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B
I2
P2
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PI1 IB1 IB2 PI2
I1
B
I2
P2
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PI1 IB1 IB2 PI2
I1
B
I2
P2
But the boxes will have internal structure.
A complex Transaction Scheme.
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Transaction Scheme
waitcount2:= waitcount2 + 1
2data.present & B.free 2data.present & B.free
I2 B
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adddata
I2 B
reqn
I2 B
2data.present
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PI1 IB1 IB2 PI2
I1
B
I2
reqy
adddata
2data.present & B.free
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PI1 IB1 IB2 PI2
I1
B
I2
reqy
adddata
2data.present & B.free
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PI1 IB1 IB2 PI2
I1
B
I2
reqy
adddata
2data.present & B.free
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PI1 IB1 IB2 PI2
I1
B
I2
reqy
adddata
2data.present & B.free
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PI1 IB1 IB2 PI2
I1
B
I2
reqy
adddata
2data.present & B.free
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PI1 IB1 IB2 PI2
I1
B
I2
reqy
adddata
2data.present & B.free
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PI1 IB1 IB2 PI2
I1
B
I2
reqy
adddata
2data.present & B.free
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P11
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1data.present
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no-data
1data.present
1data.present
data
1data.present
P11 Transaction SchemeI1
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Analysis Issues
• Determine whether a CTP is bounded.• Determine if a CTP can deadlock.• Determine if a CTP is well-formed.
Current Status
The CTP Model
SMV ES Representation
Verilog
AnalysisVerification
Simulation;
Synthesis
Case Studies
Modeling
Current Status
The CTP Model
SMV ES Representation
Verilog
AnalysisVerification
Simulation;
Synthesis
Case Studies
Modeling
Pankaj Jain
Nikhil Jain
Kamrul Hasan Talukdar
Tran Tuan Anh
Ge Zhiguo
21.10.02 ES Seminar 42
Future Work
• Add multiple instances of a process.– Object features
• Add timing constraints.• Develop the computational model.
– Interactions with environment (sense, actuate)– Computational steps (control law)– Schedulability is a key issue.
• HW/SW Partitioning; Architectural mapping; Synthesis?