combo logic case
TRANSCRIPT
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case Statement
Nesting if past two levels is error prone and possibly inefficient.
case excels when many tests are performed on the same expression.
case works well for muxes, decoders, and next state logic.
CASE Statement Structure
case (case_expression)
case_item1 : case_item_statement1;
case_item2 : case_item_statement2;
case_item3 : case_item_statement3;
case_item4 : case_item_statement4;default : case_item_statement5;
endcase
case is shorthand to describe a complicated if/then/else structure.
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8/13/2019 Combo Logic Case
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case Statement
//"full case" case statement
module case1 (
input [7:0] a_in, b_in, c_in, d_in,
input [1:0] sel,
output reg [7:0] d_out);
always_comb
case (sel)
2b00 : d_out = a_in;
2b01 : d_out = b_in;
2b10 : d_out = c_in;
2b11 : d_out = d_in;endcase
endmodule
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8/13/2019 Combo Logic Case
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case Statement
Is the simulation correct?
//"full case" case statementmodule case1 (
input [7:0] a_in, b_in, c_in, d_in,
input [1:0] sel,
output reg [7:0] d_out);
always_comb
case (sel)2b00 : d_out = a_in;
2b01 : d_out = b_in;
2b10 : d_out = c_in;
2b11 : d_out = d_in;
endcase
endmodule
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/case1/a_in
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/case1/b_in 20
/case1/c_in 30
/case1/d_in 40
/case1/sel 0 1 2 3 X
/case1/d_out 10 20 30 40
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8/13/2019 Combo Logic Case
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case Statement
Use default case to propagate x
//"full case" case statementmodule case1 (
input [7:0] a_in, b_in, c_in, d_in,input [1:0] sel,output reg [7:0] d_out);
always_combcase (sel)
2b00 : d_out = a_in;
2b01 : d_out = b_in;2b10 : d_out = c_in;2b11 : d_out = d_in;default : d_out = 8bx;
endcaseendmodule
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/case1/a_in 10
/case1/b_in 20
/case1/c_in 30
/case1/d_in 40
/case1/sel 0 1 2 3 X
/case1/d_out 10 20 30 40 xx
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case Statement
//incomplete case statementmodule case2 (
input [7:0] a_in, b_in, c_in,
input [1:0] sel,
output reg [7:0] d_out);
always_comb
case (sel)2b00 : d_out = a_in;
2b01 : d_out = b_in;
2b10 : d_out = c_in;
endcase
endmodule
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...g[5]
...g[0]
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...g[7]
...g[2]
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Inferred memory devices in process in routine case2 line 6 in file case2.sv.===========================================================================| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |===========================================================================| d_out_reg | Latch | 8 | Y | N | N | N | - | - | - |===========================================================================Warning: Netlist for always_comb block contains a latch. (ELAB-974)
Presto compilation completed successfully.
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case Statement
//incomplete case statement
//with default case_item
module case2 (
input [7:0] a_in, b_in, c_in,
input [1:0] sel,
output reg [7:0] d_out);
always_comb
case (sel)
2b00 : d_out = a_in;
2b01 : d_out = b_in;
2b10 : d_out = c_in;
default : d_out = 8bx;
endcase
endmodule
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a_in[2]
c_in[6]
a_in[1]
a_in[0]
c_in[7]
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b_in[3]
b_in[4]
b_in[2]
b_in[5]
b_in[1]
b_in[6]
sel[0]
b_in[0]
b_in[7]
sel[1]
a_in[7]
c_in[0]
c_in[1]
a_in[6]
c_in[2]
a_in[5]
c_in[3]
a_in[4]
c_in[4]
a_in[3]
c_in[5]
c_in[7:0]
d_out[7:0]
b_in[7:0]
sel[1:0]
a_in[7:0]
c_in[7:0]
sel[1:0]
a_in[7:0]
b_in[7:0] d_out[7:0]
Does RTL and gate simulation differ when sel = 2b11?
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case Statement
System Verilog priority Modifier
SystemVerilog introduced two case and if statement modifiers priority unique
Both give information to synthesis to aid optimization.
Both are assertions (simulation error reporting mechanisms)
Both imply that there is a case item for all the possible legal valuesthat case expression might assume.
Priority
Priority tells the simulator that if all is well, you will find a match If a match is not found at run-time, emit an error or warning. Since all legal combinations are listed, synthesis is free to optimize any
other unlisted case items since they are effectively dont-cares. Priority does not guarantee removal of unintended latches.
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case Statement
//incomplete case statement
//with systemverilog priority modifier
module case2 (
input [7:0] a_in, b_in, c_in,
input [1:0] sel,
output reg [7:0] d_out);
always_comb
priority case (sel)
2b00 : d_out = a_in;
2b01 : d_out = b_in;
2b10 : d_out = c_in;
endcase
endmodule
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c_in[2]
b_in[1]
c_in[3]
b_in[0]
c_in[4]
c_in[5]
a_in[7]
c_in[6]
a_in[6]
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sel[1]
c_in[0]
b_in[3]
c_in[1]
b_in[2]
a_in[7:0]
c_in[7:0]
d_out[7:0]
b_in[7:0]
sel[
1:0]
b_in[7:0]
c_in[7:0]
sel[1:0]
a_in[7:0]
d_out[7:0]
Warning: case2.sv:7: Case statement marked priority does not cover all possible conditions. (VER-504)
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case Statement
System Verilog priority Modifier
OK, so what happens in simulation with 2b11 ?
No x propagation in RTL simulation, but warning is emitted Go back, fix the error that caused the unallowed case to occur.
After fixing, the RTL and gate simulation should match.
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8/13/2019 Combo Logic Case
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case Statement
//incomplete case statement//with systemverilog priority modifier
module case2 (input [7:0] a_in, b_in, c_in,
input [1:0] sel,output reg [7:0] d_out);
always_combpriority case (sel)
2b00 : d_out = a_in;2b01 : d_out = b_in;2b10 : d_out = c_in;
endcase
endmodule
** Warning: (vsim-8315) case2.sv(7): No condition is true in the unique/priority if/case statement.
** Warning: (vsim-8315) case2.sv(7): No condition is true in the unique/priority if/case statement.
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case Statement
System Verilog priority Modifier Bottom line...
If case is full, use default expression. If case is not full, use priority modifier.
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casez Statement
casez is a special version of the case expression
Allows dont care bits in the comparison
Uses ? or Z values as dont care instead of as a logic value (weird!)
Recommendation: use ? as dont care
Use caution when using this statement
casez Example
module interrupt_ctl1 (
output reg int2, int1, int0,
input [2:0] irq );
always_comb begin
{int2, int1, int0} = 3b0; //defaultcasez (irq)
3b1?? : int2 = 1b1;
3b?1? : int1 = 1b1;
3b??1 : int0 = 1b1;
endcase
end
endmodule
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casez Statement
casez Example
module interrupt_ctl1 (
output reg int2, int1, int0,
input [2:0] irq );
always_comb begin
{int2, int1, int0} = 3b0; //default
casez (irq)3b1?? : int2 = 1b1;
3b?1? : int1 = 1b1;
3b??1 : int0 = 1b1;
endcase
end
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casez Statement
Parallel or Unique encoding
If the irq bus has any of the values: 3b011, 3b101, 3b110 or3b111, more than one case item could match the irq value.
This is known as a non-parallel case statement.
Synthesis will produce a priority encoder structure.
If code could be rewritten to have parallel or unique case items, nopriority structure would be needed. Thus, faster/smallerimplementation.
We indicate this situation with the modifier unique.
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casez Statement
Parallel or Unique Encoding
module interrupt_ctl2a (output reg int2, int1, int0,
input [2:0] irq );
always_comb begin
{int2, int1, int0} = 3b0; //default
unique casez (irq)
3b1?? : int2 = 1b1;
3b01? : int1 = 1b1;3b001 : int0 = 1b1;
endcase
end
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int2,irq[1]
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SYNTHESIS RESULTS ARE INCORRECT!
S
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casez Statement
Now what?
Further work has shown unique to be of at most little benefit.
I only got it to work properly once. Synthesis does not stick strictly to priority encoding, its smarter.
Using unique, I get about 10% decrease in delay and area at best.
At this point, until I can bet a better handle on it, avoid unique.
S
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casex Statement
One more case expression exists: casex.
Can be useful for testbenches. Current recommendations are to not use it in synthesizible code.
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