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Published by ER/TY 1063 BU TV Consumer Care, the Netherlands Subject to modification EN 3122 785 18990
2010-Apr-02
©Copyright 2010 Koninklijke Philips Electronics N.V.All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted, in any form or by any means, electronic, mechanical, photocopying, or otherwise without the prior permission of Philips.
Colour Television Chassis
Q552.1ALA
18990_000_100330.eps100330
Contents Page Contents Page1. Revision List 22. Technical Specifications, Diversity, and Connections23. Precautions, Notes, and Abbreviation List 54. Mechanical Instructions 95. Service Modes, Error Codes, and Fault Finding 126. Alignments 307. Circuit Descriptions 368. IC Data Sheets 489. Block Diagrams
Wiring diagram Matisse 42" - 46" 59Block Diagram Video 60Block Diagram Audio 61Block Diagram Control & Clock Signals 62Block Diagram I2C 63Supply Lines Overview 64
10. Circuit Diagrams and PWB Layouts Drawing PWBAL1 820400089786 AmbiLight Common 65 71AL1 820400089691 9 LED LiteOn 67 71AL1 820400089703 15 LED LiteOn 69 71AL1 820400090592 AmbiLight Common 72 78AL1 820400090601 9 LED Everlight 74 78AL1 820400090621 15 LED Everlight 76 78B01 820400089943 Tuner, HDMI & CI 79 118B02 820400089506 PNX85500 90 118B03 820400089514 CLASS D 99 118B04 820400089524 Analog I/O 107 118B05 820400089535 DDR 112 118B06 820400089572 LVDS Non DVBS 113 118B09 820400089812 Non DVBS Con. 117 118
11. Styling SheetsMatisse 32" - 46" 120
Revision ListEN 2 Q552.1A LA1.
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1. Revision ListManual xxxx xxx xxxx.0• First release.
2. Technical Specifications, Diversity, and Connections
Index of this chapter:2.1 Technical Specifications2.2 Directions for Use2.3 Connections2.4 Chassis Overview
Notes:• Figures can deviate due to the different set executions.• Specifications are indicative (subject to change).
2.1 Technical Specifications
For on-line product support please use the CTN links in Table 2-1. Here is product information available, as well as getting started, user manuals, frequently asked questions and software & drivers.
Table 2-1 Described Model Numbers and Diversity
2.2 Directions for Use
You can download this information from the following websites:http://www.philips.com/supporthttp://www.p4c.philips.com
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42PFL8605/98 Matisse11-1
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Technical Specifications, Diversity, and Connections EN 3Q552.1A LA 2.
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2.3 Connections
Figure 2-1 Connection overview
Note: The following connector colour abbreviations are used (acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy= Grey, Rd= Red, Wh= White, Ye= Yellow.
2.3.1 Side Connections
1 - Common Interface68p- See diagram B01F HDMI & CI ��
2 - USB2.0
Figure 2-2 USB (type A)
1 - +5V �
2 - Data (-) ��3 - Data (+) ��
4 - Ground Gnd �
3 - HDMI: Digital Video, Digital Audio - In
Figure 2-3 HDMI (type A) connector
1 - D2+ Data channel �
2 - Shield Gnd �3 - D2- Data channel �
4 - D1+ Data channel �
5 - Shield Gnd �
6 - D1- Data channel �7 - D0+ Data channel �
8 - Shield Gnd �
9 - D0- Data channel �10 - CLK+ Data channel �
11 - Shield Gnd �
12 - CLK- Data channel �13 - Easylink/CEC Control channel ��
14 - n.c. 15 - DDC_SCL DDC clock �16 - DDC_SDA DDC data ��
17 - Ground Gnd �
18 - +5V �19 - HPD Hot Plug Detect �
20 - Ground Gnd �
2.3.2 Rear Connections
4 - RJ45: Ethernet (optional)
Figure 2-4 Ethernet connector
1 - TD+ Transmit signal �
2 - TD- Transmit signal �
3 - RD+ Receive signal �4 - CT Centre Tap: DC level fixation
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5 - CT Centre Tap: DC level fixation 6 - RD- Receive signal �
7 - GND Gnd �8 - GND Gnd �
5 - CVI 2: Cinch: Video YPbPr - In, Audio - InGn - Video Y 1 VPP / 75 ohm ��Bu - Video Pb 0.7 VPP / 75 ohm ��
Rd - Video Pr 0.7 VPP / 75 ohm ��
Rd - Audio - R 0.5 VRMS / 10 kohm ��Wh - Audio - L 0.5 VRMS / 10 kohm ��
6 - Service Connector (UART)1 - Ground Gnd �2 - UART_TX Transmit �
3 - UART_RX Receive �
7 - Cinch: Video CVBS - In, Audio - InYe - Video CVBS 1 VPP / 75 ohm ��
Wh - Audio L 0.5 VRMS / 10 kohm ��
Rd - Audio R 0.5 VRMS / 10 kohm ��
8 - S-Video (Hosiden): Video Y/C - In1 - Ground Y Gnd �
2 - Ground C Gnd �3 - Video Y 1 VPP / 75 ohm �
4 - Video C 0.3 VPPP / 75 ohm �
9 - Head phone (Output)Bk - Head phone 32 - 600 ohm / 10 mW ��
2.3.3 Rear Connections - Bottom
10 - CVI 1: Video RGB - In, CVBS - In/Out, Audio - In/OutSee 5 - CVI 2: Cinch: Video YPbPr - In, Audio - In
11 - Cinch: S/PDIF - OutBk - Coaxial 0.4 - 0.6VPP / 75 ohm ��
12 - HDMI 2 (& 3 optional): Digital Video, Digital Audio - InSee 3 - HDMI: Digital Video, Digital Audio - In
13 - HDMI 1: Digital Video - In, Digital Audio with ARC - In/Out
Figure 2-5 HDMI (type A) connector
1 - D2+ Data channel �2 - Shield Gnd �
3 - D2- Data channel �
4 - D1+ Data channel �5 - Shield Gnd �
6 - D1- Data channel �
7 - D0+ Data channel �8 - Shield Gnd �
9 - D0- Data channel �
10 - CLK+ Data channel �
11 - Shield Gnd �
12 - CLK- Data channel �
13 - Easylink/CEC Control channel ��14 - ARC Audio Return Channel �
15 - DDC_SCL DDC clock �
16 - DDC_SDA DDC data ��17 - Ground Gnd �
18 - +5V �
19 - HPD Hot Plug Detect �20 - Ground Gnd �
14 - Cinch: Audio - In (VGA/DVI)Rd - Audio R 0.5 VRMS / 10 kohm ��Wh - Audio L 0.5 VRMS / 10 kohm ��
15 - Aerial - In- - IEC-type (EU) Coax, 75 ohm �
16 - VGA: Video RGB - In
Figure 2-6 VGA Connector
1 - Video Red 0.7 VPP / 75 ohm �2 - Video Green 0.7 VPP / 75 ohm �
3 - Video Blue 0.7 VPP / 75 ohm �
4 - n.c. 5 - Ground Gnd �
6 - Ground Red Gnd �
7 - Ground Green Gnd �8 - Ground Blue Gnd �
9 - +5VDC +5 V �
10 - Ground Sync Gnd �11 - n.c. 12 - DDC_SDA DDC data �
13 - H-sync 0 - 5 V �14 - V-sync 0 - 5 V �
15 - DDC_SCL DDC clock �
2.4 Chassis Overview
Refer to chapter Block Diagrams for PWB/CBA locations.
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3. Precautions, Notes, and Abbreviation List
Index of this chapter:3.1 Safety Instructions3.2 Warnings3.3 Notes3.4 Abbreviation List
3.1 Safety Instructions
Safety regulations require the following during a repair:• Connect the set to the Mains/AC Power via an isolation
transformer (> 800 VA).• Replace safety components, indicated by the symbol ,
only by components identical to the original ones. Any other component substitution (other than original type) may increase risk of fire or electrical shock hazard. Of de set ontploft!
Safety regulations require that after a repair, the set must be returned in its original condition. Pay in particular attention to the following points: • Route the wire trees correctly and fix them with the
mounted cable clamps.• Check the insulation of the Mains/AC Power lead for
external damage. • Check the strain relief of the Mains/AC Power cord for
proper function.• Check the electrical DC resistance between the Mains/AC
Power plug and the secondary side (only for sets that have a Mains/AC Power isolated power supply): 1. Unplug the Mains/AC Power cord and connect a wire
between the two pins of the Mains/AC Power plug. 2. Set the Mains/AC Power switch to the “on” position
(keep the Mains/AC Power cord unplugged!). 3. Measure the resistance value between the pins of the
Mains/AC Power plug and the metal shielding of the tuner or the aerial connection on the set. The reading should be between 4.5 MΩ and 12 MΩ.
4. Switch “off” the set, and remove the wire between the two pins of the Mains/AC Power plug.
• Check the cabinet for defects, to prevent touching of any inner parts by the customer.
3.2 Warnings
• All ICs and many other semiconductors are susceptible to electrostatic discharges (ESD ). Careless handling during repair can reduce life drastically. Make sure that, during repair, you are connected with the same potential as the mass of the set by a wristband with resistance. Keep components and tools also at this same potential.
• Be careful during measurements in the high voltage section.
• Never replace modules or other components while the unit is switched “on”.
• When you align the set, use plastic rather than metal tools. This will prevent any short circuits and the danger of a circuit becoming unstable.
3.3 Notes
3.3.1 General
• Measure the voltages and waveforms with regard to the chassis (= tuner) ground (�), or hot ground (�), depending on the tested area of circuitry. The voltages and waveforms shown in the diagrams are indicative. Measure them in the Service Default Mode with a colour bar signal and stereo sound (L: 3 kHz, R: 1 kHz unless stated otherwise) and
picture carrier at 475.25 MHz for PAL, or 61.25 MHz for NTSC (channel 3).
• Where necessary, measure the waveforms and voltages with (�) and without (�) aerial signal. Measure the voltages in the power supply section both in normal operation ( ) and in stand-by (�). These values are indicated by means of the appropriate symbols.
3.3.2 Schematic Notes
• All resistor values are in ohms, and the value multiplier is often used to indicate the decimal point location (e.g. 2K2 indicates 2.2 kΩ).
• Resistor values with no multiplier may be indicated with either an “E” or an “R” (e.g. 220E or 220R indicates 220 Ω).
• All capacitor values are given in micro-farads (μ = × 10-6), nano-farads (n = × 10-9), or pico-farads (p = × 10-12).
• Capacitor values may also use the value multiplier as the decimal point indication (e.g. 2p2 indicates 2.2 pF).
• An “asterisk” (*) indicates component usage varies. Refer to the diversity tables for the correct values.
• The correct component values are listed on the Philips Spare Parts Web Portal.
3.3.3 Spare Parts
For the latest spare part overview, consult your Philips Spare Part web portal.
3.3.4 BGA (Ball Grid Array) ICs
IntroductionFor more information on how to handle BGA devices, visit this URL: http://www.atyourservice-magazine.com. Select “Magazine”, then go to “Repair downloads”. Here you will find Information on how to deal with BGA-ICs.
BGA Temperature ProfilesFor BGA-ICs, you must use the correct temperature-profile. Where applicable and available, this profile is added to the IC Data Sheet information section in this manual.
3.3.5 Lead-free Soldering
Due to lead-free technology some rules have to be respected by the workshop during a repair:• Use only lead-free soldering tin. If lead-free solder paste is
required, please contact the manufacturer of your soldering equipment. In general, use of solder paste within workshops should be avoided because paste is not easy to store and to handle.
• Use only adequate solder tools applicable for lead-free soldering tin. The solder tool must be able:– To reach a solder-tip temperature of at least 400°C.– To stabilize the adjusted temperature at the solder-tip.– To exchange solder-tips for different applications.
• Adjust your solder tool so that a temperature of around 360°C - 380°C is reached and stabilized at the solder joint. Heating time of the solder-joint should not exceed ~ 4 sec. Avoid temperatures above 400°C, otherwise wear-out of tips will increase drastically and flux-fluid will be destroyed. To avoid wear-out of tips, switch “off” unused equipment or reduce heat.
• Mix of lead-free soldering tin/parts with leaded soldering tin/parts is possible but PHILIPS recommends strongly to avoid mixed regimes. If this cannot be avoided, carefully clear the solder-joint from old tin and re-solder with new tin.
Precautions, Notes, and Abbreviation ListEN 6 Q552.1A LA3.
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3.3.6 Alternative BOM identification
It should be noted that on the European Service website, “Alternative BOM” is referred to as “Design variant”.
The third digit in the serial number (example: AG2B0335000001) indicates the number of the alternative B.O.M. (Bill Of Materials) that has been used for producing the specific TV set. In general, it is possible that the same TV model on the market is produced with e.g. two different types of displays, coming from two different suppliers. This will then result in sets which have the same CTN (Commercial Type Number; e.g. 28PW9515/12) but which have a different B.O.M. number.By looking at the third digit of the serial number, one can identify which B.O.M. is used for the TV set he is working with.If the third digit of the serial number contains the number “1” (example: AG1B033500001), then the TV set has been manufactured according to B.O.M. number 1. If the third digit is a “2” (example: AG2B0335000001), then the set has been produced according to B.O.M. no. 2. This is important for ordering the correct spare parts!For the third digit, the numbers 1...9 and the characters A...Z can be used, so in total: 9 plus 26= 35 different B.O.M.s can be indicated by the third digit of the serial number.
Identification: The bottom line of a type plate gives a 14-digit serial number. Digits 1 and 2 refer to the production centre (e.g. AG is Bruges), digit 3 refers to the B.O.M. code, digit 4 refers to the Service version change code, digits 5 and 6 refer to the production year, and digits 7 and 8 refer to production week (in example below it is 2006 week 17). The 6 last digits contain the serial number.
Figure 3-1 Serial number (example)
3.3.7 Board Level Repair (BLR) or Component Level Repair (CLR)
If a board is defective, consult your repair procedure to decide if the board has to be exchanged or if it should be repaired on component level.If your repair procedure says the board should be exchanged completely, do not solder on the defective board. Otherwise, it cannot be returned to the O.E.M. supplier for back charging!
3.3.8 Practical Service Precautions
• It makes sense to avoid exposure to electrical shock. While some sources are expected to have a possible dangerous impact, others of quite high potential are of limited current and are sometimes held in less regard.
• Always respect voltages. While some may not be dangerous in themselves, they can cause unexpected reactions that are best avoided. Before reaching into a powered TV set, it is best to test the high voltage insulation. It is easy to do, and is a good service precaution.
3.4 Abbreviation List
0/6/12 SCART switch control signal on A/V board. 0 = loop through (AUX to TV), 6 = play 16 : 9 format, 12 = play 4 : 3 format
AARA Automatic Aspect Ratio Adaptation: algorithm that adapts aspect ratio to remove horizontal black bars; keeps the original aspect ratio
ACI Automatic Channel Installation: algorithm that installs TV channels directly from a cable network by means of a predefined TXT page
ADC Analogue to Digital ConverterAFC Automatic Frequency Control: control
signal used to tune to the correct frequency
AGC Automatic Gain Control: algorithm that controls the video input of the feature box
AM Amplitude ModulationAP Asia PacificAR Aspect Ratio: 4 by 3 or 16 by 9ASF Auto Screen Fit: algorithm that adapts
aspect ratio to remove horizontal black bars without discarding video information
ATSC Advanced Television Systems Committee, the digital TV standard in the USA
ATV See Auto TVAuto TV A hardware and software control
system that measures picture content, and adapts image parameters in a dynamic way
AV External Audio VideoAVC Audio Video ControllerAVIP Audio Video Input ProcessorB/G Monochrome TV system. Sound
carrier distance is 5.5 MHzBDS Business Display Solutions (iTV)BLR Board-Level RepairBTSC Broadcast Television Standard
Committee. Multiplex FM stereo sound system, originating from the USA and used e.g. in LATAM and AP-NTSC countries
B-TXT Blue TeleteXTC Centre channel (audio)CEC Consumer Electronics Control bus:
remote control bus on HDMI connections
CL Constant Level: audio output to connect with an external amplifier
CLR Component Level RepairComPair Computer aided rePairCP Connected Planet / Copy ProtectionCSM Customer Service ModeCTI Color Transient Improvement:
manipulates steepness of chroma transients
CVBS Composite Video Blanking and Synchronization
DAC Digital to Analogue ConverterDBE Dynamic Bass Enhancement: extra
low frequency amplificationDCM Data Communication Module. Also
referred to as System Card or Smartcard (for iTV).
DDC See “E-DDC”D/K Monochrome TV system. Sound
carrier distance is 6.5 MHzDFI Dynamic Frame Insertion
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Precautions, Notes, and Abbreviation List EN 7Q552.1A LA 3.
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DFU Directions For Use: owner's manualDMR Digital Media Reader: card readerDMSD Digital Multi Standard DecodingDNM Digital Natural MotionDNR Digital Noise Reduction: noise
reduction feature of the setDRAM Dynamic RAMDRM Digital Rights ManagementDSP Digital Signal ProcessingDST Dealer Service Tool: special remote
control designed for service technicians
DTCP Digital Transmission Content Protection; A protocol for protecting digital audio/video content that is traversing a high speed serial bus, such as IEEE-1394
DVB-C Digital Video Broadcast - CableDVB-T Digital Video Broadcast - TerrestrialDVD Digital Versatile DiscDVI(-d) Digital Visual Interface (d= digital only)E-DDC Enhanced Display Data Channel
(VESA standard for communication channel and display). Using E-DDC, the video source can read the EDID information form the display.
EDID Extended Display Identification Data (VESA standard)
EEPROM Electrically Erasable and Programmable Read Only Memory
EMI Electro Magnetic InterferenceEPG Electronic Program GuideEPLD Erasable Programmable Logic DeviceEU EuropeEXT EXTernal (source), entering the set by
SCART or by cinches (jacks)FDS Full Dual Screen (same as FDW)FDW Full Dual Window (same as FDS)FLASH FLASH memoryFM Field Memory or Frequency
ModulationFPGA Field-Programmable Gate ArrayFTV Flat TeleVisionGb/s Giga bits per secondG-TXT Green TeleteXTH H_sync to the module HD High DefinitionHDD Hard Disk DriveHDCP High-bandwidth Digital Content
Protection: A “key” encoded into the HDMI/DVI signal that prevents video data piracy. If a source is HDCP coded and connected via HDMI/DVI without the proper HDCP decoding, the picture is put into a “snow vision” mode or changed to a low resolution. For normal content distribution the source and the display device must be enabled for HDCP “software key” decoding.
HDMI High Definition Multimedia InterfaceHP HeadPhoneI Monochrome TV system. Sound
carrier distance is 6.0 MHzI2C Inter IC busI2D Inter IC Data busI2S Inter IC Sound busIF Intermediate FrequencyIR Infra RedIRQ Interrupt RequestITU-656 The ITU Radio communication Sector
(ITU-R) is a standards body subcommittee of the International Telecommunication Union relating to radio communication. ITU-656 (a.k.a.
SDI), is a digitized video format used for broadcast grade video. Uncompressed digital component or digital composite signals can be used. The SDI signal is self-synchronizing, uses 8 bit or 10 bit data words, and has a maximum data rate of 270 Mbit/s, with a minimum bandwidth of 135 MHz.
ITV Institutional TeleVision; TV sets for hotels, hospitals etc.
LS Last Status; The settings last chosen by the customer and read and stored in RAM or in the NVM. They are called at start-up of the set to configure it according to the customer's preferences
LATAM Latin AmericaLCD Liquid Crystal DisplayLED Light Emitting DiodeL/L' Monochrome TV system. Sound
carrier distance is 6.5 MHz. L' is Band I, L is all bands except for Band I
LPL LG.Philips LCD (supplier)LS LoudspeakerLVDS Low Voltage Differential SignallingMbps Mega bits per secondM/N Monochrome TV system. Sound
carrier distance is 4.5 MHzMHEG Part of a set of international standards
related to the presentation of multimedia information, standardised by the Multimedia and Hypermedia Experts Group. It is commonly used as a language to describe interactive television services
MIPS Microprocessor without Interlocked Pipeline-Stages; A RISC-based microprocessor
MOP Matrix Output ProcessorMOSFET Metal Oxide Silicon Field Effect
Transistor, switching deviceMPEG Motion Pictures Experts GroupMPIF Multi Platform InterFaceMUTE MUTE LineMTV Mainstream TV: TV-mode with
Consumer TV features enabled (iTV)NC Not ConnectedNICAM Near Instantaneous Compounded
Audio Multiplexing. This is a digital sound system, mainly used in Europe.
NTC Negative Temperature Coefficient, non-linear resistor
NTSC National Television Standard Committee. Color system mainly used in North America and Japan. Color carrier NTSC M/N= 3.579545 MHz, NTSC 4.43= 4.433619 MHz (this is a VCR norm, it is not transmitted off-air)
NVM Non-Volatile Memory: IC containing TV related data such as alignments
O/C Open CircuitOSD On Screen DisplayOAD Over the Air Download. Method of
software upgrade via RF transmission. Upgrade software is broadcasted in TS with TV channels.
OTC On screen display Teletext and Control; also called Artistic (SAA5800)
P50 Project 50: communication protocol between TV and peripherals
PAL Phase Alternating Line. Color system mainly used in West Europe (color carrier= 4.433619 MHz) and South America (color carrier PAL M=
Precautions, Notes, and Abbreviation ListEN 8 Q552.1A LA3.
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3.575612 MHz and PAL N= 3.582056 MHz)
PCB Printed Circuit Board (same as “PWB”)PCM Pulse Code ModulationPDP Plasma Display PanelPFC Power Factor Corrector (or Pre-
conditioner)PIP Picture In PicturePLL Phase Locked Loop. Used for e.g.
FST tuning systems. The customer can give directly the desired frequency
POD Point Of Deployment: a removable CAM module, implementing the CA system for a host (e.g. a TV-set)
POR Power On Reset, signal to reset the uPPSDL Power Supply for Direct view LED
backlight with 2D-dimmingPSL Power Supply with integrated LED
driversPSLS Power Supply with integrated LED
drivers with added Scanning functionality
PTC Positive Temperature Coefficient, non-linear resistor
PWB Printed Wiring Board (same as “PCB”)PWM Pulse Width ModulationQRC Quasi Resonant ConverterQTNR Quality Temporal Noise ReductionQVCP Quality Video Composition ProcessorRAM Random Access MemoryRGB Red, Green, and Blue. The primary
color signals for TV. By mixing levels of R, G, and B, all colors (Y/C) are reproduced.
RC Remote ControlRC5 / RC6 Signal protocol from the remote
control receiver RESET RESET signalROM Read Only MemoryRSDS Reduced Swing Differential Signalling
data interfaceR-TXT Red TeleteXTSAM Service Alignment ModeS/C Short CircuitSCART Syndicat des Constructeurs
d'Appareils Radiorécepteurs et Téléviseurs
SCL Serial Clock I2CSCL-F CLock Signal on Fast I2C busSD Standard DefinitionSDA Serial Data I2CSDA-F DAta Signal on Fast I2C busSDI Serial Digital Interface, see “ITU-656”SDRAM Synchronous DRAMSECAM SEequence Couleur Avec Mémoire.
Color system mainly used in France and East Europe. Color carriers= 4.406250 MHz and 4.250000 MHz
SIF Sound Intermediate FrequencySMPS Switched Mode Power SupplySoC System on ChipSOG Sync On GreenSOPS Self Oscillating Power SupplySPI Serial Peripheral Interface bus; a 4-
wire synchronous serial data link standard
S/PDIF Sony Philips Digital InterFaceSRAM Static RAMSRP Service Reference ProtocolSSB Small Signal BoardSSC Spread Spectrum Clocking, used to
reduce the effects of EMISTB Set Top BoxSTBY STand-BYSVGA 800 × 600 (4:3)
SVHS Super Video Home SystemSW SoftwareSWAN Spatial temporal Weighted Averaging
Noise reductionSXGA 1280 × 1024TFT Thin Film TransistorTHD Total Harmonic DistortionTMDS Transmission Minimized Differential
SignallingTS Transport StreamTXT TeleteXTTXT-DW Dual Window with TeleteXTUI User InterfaceuP MicroprocessorUXGA 1600 × 1200 (4:3)V V-sync to the module VESA Video Electronics Standards
AssociationVGA 640 × 480 (4:3)VL Variable Level out: processed audio
output toward external amplifierVSB Vestigial Side Band; modulation
methodWYSIWYR What You See Is What You Record:
record selection that follows main picture and sound
WXGA 1280 × 768 (15:9)XTAL Quartz crystalXGA 1024 × 768 (4:3)Y Luminance signalY/C Luminance (Y) and Chrominance (C)
signalYPbPr Component video. Luminance and
scaled color difference signals (B-Y and R-Y)
YUV Component video
Mechanical Instructions EN 9Q552.1A LA 4.
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4. Mechanical Instructions
Index of this chapter:4.1 Cable Dressing Matisse styling4.2 Service Positions4.3 Assy/Panel Removal Matisse Styling4.4 Set Re-assembly
Notes: • Figures below can deviate slightly from the actual situation,
due to the different set executions.
4.1 Cable Dressing Matisse styling
Note: pictures are taken from the European equivalent (with SCART connector).
Figure 4-1 Cable dressing 42" 8000-series
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Figure 4-2 Cable dressing 46" 8000-series
18990_101_100401.eps100401
Mechanical Instructions EN 11Q552.1A LA 4.
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4.2 Service Positions
For easy servicing of a TV set, the set should be put face down on a soft flat surface, foam buffers or other specific workshop tools. Ensure that a stable situation is created to perform measurements and alignments. When using foam bars take care that these always support the cabinet and never only the display. Caution: Failure to follow these guidelines can seriously damage the display! Ensure that ESD safe measures are taken.
4.3 Assy/Panel Removal Matisse Styling
No detailed information is available at time of publishing.
4.4 Set Re-assembly
To re-assemble the whole set, execute all processes in reverse order.
Notes:• While re-assembling, make sure that all cables are placed
and connected in their original position. • Pay special attention not to damage the EMC foams in the
set. Ensure that EMC foams are mounted correctly.
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5. Service Modes, Error Codes, and Fault Finding
Index of this chapter:5.1 Test Points5.2 Service Modes5.3 Stepwise Start-up5.4 Service Tools5.5 Error Codes5.6 The Blinking LED Procedure5.7 Protections5.8 Fault Finding and Repair Tips5.9 Software Upgrading
5.1 Test Points
As most signals are digital, it will be difficult to measure waveforms with a standard oscilloscope. However, several key ICs are capable of generating test patterns, which can be controlled via ComPair. In this way it is possible to determine which part is defective. Perform measurements under the following conditions:• Service Default Mode.• Video: Colour bar signal.• Audio: 3 kHz left, 1 kHz right.
5.2 Service Modes
Service Default mode (SDM) and Service Alignment Mode (SAM) offers several features for the Service technician, while the Customer Service Mode (CSM) is used for communication between the call centre and the customer.
This chassis also offers the option of using ComPair, a hardware interface between a computer and the TV chassis. It offers the abilities of structured troubleshooting, error code reading, and software version read-out for all chassis. (see also section “5.4.1 ComPair”).
Note: For the new model range, a new remote control (RC) is used with some renamed buttons. This has an impact on the activation of the Service modes. For instance the old “MENU” button is now called “HOME” (or is indicated by a “house” icon).
5.2.1 Service Default Mode (SDM)
Purpose• To create a pre-defined setting, to get the same
measurement results as given in this manual.• To override SW protections detected by stand-by
processor and make the TV start up to the step just before protection (a sort of automatic stepwise start-up). See section “5.3 Stepwise Start-up”.
• To start the blinking LED procedure where only LAYER 2 errors are displayed. (see also section “5.5 Error Codes”).
Specifications
Table 5-1 SDM default settings
• All picture settings at 50% (brightness, colour, contrast).• Sound volume at 25%.
• All service-unfriendly modes (if present) are disabled, like: – (Sleep) timer.– Child/parental lock.– Picture mute (blue mute or black mute).– Automatic volume levelling (AVL).– Skip/blank of non-favourite pre-sets.
How to Activate SDMFor this chassis there are two kinds of SDM: an analogue SDM and a digital SDM. Tuning will happen according Table 5-1.• Analogue SDM: use the standard RC-transmitter and key
in the code “062596”, directly followed by the “MENU” (or HOME) button. Note: It is possible that, together with the SDM, the main menu will appear. To switch it “off”, push the “MENU”(or HOME) button again.
• Digital SDM: use the standard RC-transmitter and key in the code “062593”, directly followed by the “MENU” (or HOME) button.Note: It is possible that, together with the SDM, the main menu will appear. To switch it “off”, push the “MENU” (or HOME) button again.
• Analogue SDM can also be activated by grounding for a moment the solder path on the SSB, with the indication “SDM” (see figure Service mode pad).
Figure 5-1 Service mode pad
After activating this mode, “SDM” will appear in the upper right corner of the screen (when a picture is available).
How to NavigateWhen the “MENU” (or HOME) button is pressed on the RC transmitter, the TV set will toggle between the SDM and the normal user menu.
How to Exit SDMUse one of the following methods:• Switch the set to STAND-BY via the RC-transmitter. • Via a standard customer RC-transmitter: key in “00”-
sequence.
Region Freq. (MHz)Default system
Europe, AP(PAL/Multi) 475.25 PAL B/G
Europe, AP DVB-T 546.00 PID Video: 0B 06 PID PCR: 0B 06 PID Audio: 0B 07
DVB-T
18770_249_100215.eps100215
SDM
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5.2.2 Service Alignment Mode (SAM)
Purpose• To perform (software) alignments.• To change option settings.• To easily identify the used software version.• To view operation hours.• To display (or clear) the error code buffer.
How to Activate SAMVia a standard RC transmitter: Key in the code “062596” directly followed by the “INFO”/”HOME” button. After activating SAM with this method a service warning will appear on the screen, continue by pressing the “OK” button on the RC.
Contents of SAM (see also Table 6-8)• Hardware Info.
– A. SW Version. Displays the software version of the main software (example: Q555X-1.2.3.4 = AAAAB_X.Y.W.Z). • AAAA= the chassis name.• B= the SW branch version. This is a sequential
number (this is no longer the region indication, as the software is now multi-region).
• X.Y.W.Z= the software version, where X is the main version number (different numbers are not compatible with one another) and Y.W.Z is the sub version number (a higher number is always compatible with a lower number).
– B. STBY PROC Version. Displays the software version of the stand-by processor.
– C. Production Code. Displays the production code of the TV, this is the serial number as printed on the back of the TV set. Note that if an NVM is replaced or is initialized after corruption, this production code has to be re-written to NVM. ComPair will foresee in a possibility to do this.
• Operation Hours. Displays the accumulated total of operation hours (not the stand-by hours). Every time the TV is switched “on/off”, 0.5 hours is added to this number.
• Errors (followed by maximum 10 errors). The most recent error is displayed at the upper left (for an error explanation see section “5.5 Error Codes”).
• Reset Error Buffer. When “cursor right” (or the “OK button) is pressed and then the “OK” button is pressed, the error buffer is reset.
• Alignments. This will activate the “ALIGNMENTS” sub-menu. See Chapter 6. Alignments.
• Dealer Options. Extra features for the dealers.• Options. Extra features for Service. For more info
regarding option codes, 6. Alignments.Note that if the option code numbers are changed, these have to be confirmed with pressing the “OK” button before the options are stored. Otherwise changes will be lost.
• Initialize NVM. The moment the processor recognizes a corrupted NVM, the “initialize NVM” line will be highlighted. Now, two things can be done (dependent of the service instructions at that moment):– Save the content of the NVM via ComPair for
development analysis, before initializing. This will give the Service department an extra possibility for diagnosis (e.g. when Development asks for this).
– Initialize the NVM.
Note: When the NVM is corrupted, or replaced, there is a high possibility that no picture appears because the display code is not correct. So, before initializing the NVM via the SAM, a picture is necessary and therefore the correct display option has to be entered. Refer to Chapter 6. Alignments for details. To adapt this option, it’s advised to use ComPair (the correct values for the options can be found in Chapter 6. Alignments) or a method via a standard RC (described below).Changing the display option via a standard RC: Key in the code “062598” directly followed by the “MENU” (or HOME)
button and “XXX” (where XXX is the 3 digit decimal display code as mentioned in Table 6-7). Make sure to key in all three digits, also the leading zero’s. If the above action is successful, the front LED will go out as an indication that the RC sequence was correct. After the display option is changed in the NVM, the TV will go to the Stand-by mode. If the NVM was corrupted or empty before this action, it will be initialized first (loaded with default values). This initializing can take up to 20 seconds.
Figure 5-2 Location of Display Option Code sticker
• Store - go right. All options and alignments are stored when pressing “cursor right” (or the “OK” button) and then the “OK”-button.
• SW Maintenance.– SW Events. Not useful for Service purposes. In case
of specific software problems, the development department can ask for this info.
– HW Events. Not useful for Service purposes. In case of specific software problems, the development department can ask for this info.
• Test settings. For development purposes only.• Development file versions. Not useful for Service
purposes, this information is only used by the development department.
• Upload to USB. To upload several settings from the TV to an USB stick, which is connected to the SSB. The items are “Channel list”, “Personal settings”, “Option codes”, “Display-related alignments”, “Identification data” and “History list”. First a directory “repair\” has to be created in the root of the USB stick. To upload the settings select each item separately, press “cursor right” (or the “OK” button), confirm with “OK” and wait until “Done” appears. In case the download to the USB stick was not successful “Failure” will appear. In this case, check if the USB stick is connected properly and if the directory “repair” is present in the root of the USB stick. Now the settings are stored onto the USB stick and can be used to download onto another TV or other SSB. Uploading is of course only possible if the software is running and if a picture is available. This method is created to be able to save the customer’s TV settings and to store them into another SSB.
• Download to USB. To download several settings from the USB stick to the TV, same way of working needs to be followed as with uploading. To make sure that the download of the channel list from USB to the TV is executed properly, it is necessary to restart the TV and tune to a valid preset if necessary.
• NVM editor. For NET TV the set type must be installed.Also the production code can be entered via the RC-transmitter.
How to Navigate• In SAM, the menu items can be selected with the
“CURSOR UP/DOWN” key on the RC-transmitter. The selected item will be highlighted. When not all menu items fit on the screen, move the “CURSOR UP/DOWN” key to display the next/previous menu items.
• With the “CURSOR LEFT/RIGHT” keys, it is possible to:– (De) activate the selected menu item.– (De) activate the selected sub menu.
PHILIPSMODEL:32PF9968/10
PROD.SERIAL NO:
AG 1A0620 000001
040
39mm
27m
m
(CTN Sticker)
Display OptionCode
E_06532_038.eps240108
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• With the “OK” key, it is possible to activate the selected action.
How to Exit SAMUse one of the following methods:• Switch the TV set to STAND-BY via the RC-transmitter.• Via a standard RC-transmitter, key in “00” sequence, or
select the “BACK” key.
5.2.3 Customer Service Mode (CSM)
PurposeWhen a customer is having problems with his TV-set, he can call his dealer or the Customer Helpdesk. The Service technician can then ask the customer to activate the CSM, in order to identify the status of the set. Now, the Service technician can judge the severity of the complaint. In many cases, he can advise the customer how to solve the problem, or he can decide if it is necessary to visit the customer.The CSM is a read only mode; therefore, modifications in this mode are not possible. When in this chassis CSM is activated, a testpattern will be displayed during 5 seconds (1 second Blue, 1 second Green and 1 second Red, then again 1 second Blue and 1 second Green). This test pattern is generated by the PNX51X0. So if this test pattern is shown, it could be determined that the back end video chain (PNX51X0, LVDS, and display) of the SSB is working. For TV sets without the PNX51X0 inside, every menu from CSM will be used as check for the back end video chain. When CSM is activated and there is a USB stick connected to the TV set, the software will dump the complete CSM content to the USB stick. The file (Csm.txt) will be saved in the root of the USB stick. This info can be handy if no information is displayed. To have fast feedback from the field, a flashdump can be requested. While in CSM, push the red button + dial serial digits ‘2679’ (same keys to form the word ‘COPY’ with a cellphone). A file Dump_settype_serienumber.bin will be written on the connected USB device. This can take 1/2 minute, depending on the quantity of data that needs to be dumped. Also when CSM is activated, the LAYER 1 error is displayed via blinking LED. Only the latest error is displayed. (see also section 5.5 Error Codes).
How to Activate CSM Key in the code “123654” via the standard RC transmitter.Note: Activation of the CSM is only possible if there is no (user) menu on the screen!
How to NavigateBy means of the “CURSOR-DOWN/UP” knob on the RC-transmitter, can be navigated through the menus.
Contents of CSMThe contents are reduced to 3 pages: General, Software versions and Quality items. The group names itself are not shown anywhere in the CSM menu.
General• Set Type. This information is very helpful for a helpdesk/
workshop as reference for further diagnosis. In this way, it is not necessary for the customer to look at the rear of the TV-set. Note that if an NVM is replaced or is initialized after corruption, this set type has to be re-written to NVM. This can be done in SAM via the NVM editor, or via ComPair.
• Production Code. Displays the production code (the serial number) of the TV. Note that if an NVM is replaced or is initialized after corruption, this production code has to be re-written to NVM. This can be done in SAM via the NVM editor, or via ComPair.
• Installed date. Indicates the date of the first installation of the TV. This date is acquired via time extraction.
• Options 1. Gives the option codes of option group 1 as set in SAM (Service Alignment Mode).
• Options 2. Gives the option codes of option group 2 as set in SAM (Service Alignment Mode).
• 12NC SSB. Gives an identification of the SSB as stored in NVM. Note that if an NVM is replaced or is initialized after corruption, this identification number has to be re-written to NVM. ComPair will foresee in a possibility to do this. This identification number is the 12nc number of the SSB.
• 12NC display. Shows the 12NC of the display.• 12NC supply. Shows the 12NC of the supply.• 12NC 200Hz board. Shows the 12NC of the 200Hz Panel.
Software versions• Current main SW. Displays the build-in main software
version. In case of field problems related to software, software can be upgraded. As this software is consumer upgradeable, it will also be published on the Internet.Example: Q555X_1.2.3.4
• Standby SW. Displays the build-in stand-by processor software version. Upgrading this software will be possible via ComPair or via USB (see section 5.9 Software Upgrading).Example: STDBY_88.68.1.2.
• e-UM version. Displays the electronic user manual SW-version.
Quality items• Signal quality. bad / average /good• Ethernet MAC address. Dispays the MAC address
present in the SSB.• Wireless MAC address. Displays the wireless MAC
address to support the Wi-Fi functionality.• BDS key. Indicates if the set is in the BDS status.• CI slot present. If the common interface module is
detected.• Event counter.
How to Exit CSMPress “MENU” (or HOME) / “Back” key on the RC-transmitter.
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5.3 Stepwise Start-up
When the TV is in a protection state due to an error detected by stand-by software (error blinking is displayed) and SDM is activated via shortcutting the SDM solder path on the SSB, the TV starts up until it reaches the situation just before protection. So, this is a kind of automatic stepwise start-up. In combination with the start-up diagrams below, you can see which supplies are present at a certain moment. Caution: in case the start-up in this mode with a faulty FET 7U0X is done, you can destroy all IC’s supplied by the +1V8 and +1v1, due to overvoltage (12V on XVX-line). It is recommended to measure first the FET
7U0X or others FET’s on shortcircuit before activating SDM via the service pads.
The abbreviations “SP” and “MP” in the figures stand for:• SP: protection or error detected by the Stand-by
Processor.• MP: protection or error detected by the MIPS Main
Processor.
Figure 5-3 Transition diagram
18770_250_100216.eps100402
ActiveSemiSt by
St by
Mains on
Mainsoff
GoToProtection
- WakeUp requested- Acquisition needed- Tact switch pushed
- stby requested andno data Acquisitionrequired
- St by requested- tact SW pushed
WakeUprequested
Protection
WakeUp requested
(SDM)
GoToProtectionHibernate
- Tact switch pushed- last status is hibernateafter mains ON
Tact switchpushed
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Figure 5-4 “Off” to “Semi Stand-by” flowchart (part 1)
18770_251_100216.eps100216
No
EJTAG probe connected ?
No
Yes
Release AVC system resetFeed warm boot script
Cold boot?
Yes
No
Set I²C slave address of Standby µP to (A0h)
An EJTAG probe (e.g. WindPower ICE probe) can be connected for Linux Kernel debugging purposes.
Detect EJTAG debug probe(pulling pin of the probe interface to ground by inserting EJTAG probe)
Release AVC system resetFeed cold boot script
Release AVC system resetFeed initializing boot scriptdisable alive mechanism
Off
Standby Supply starts running.All standby supply voltages become available.
st-by µP resets
Stand by or Protection
Mains is applied
- Switch Audio-Reset high.It is low in the standby mode if the standby
mode lasted longer than 10s.start keyboard scanning, RC detection. Wake up reasons are
off.
If the protection state was left by short circuiting the SDM pins, detection of a protection condition during
startup will stall the startup. Protection conditions in a playing set will be ignored. The protection mode will
not be entered.
Detect2 is moved to an interrupt. To be checked if the detection on interrupt base is feasible or not or if we should stick to the standard 40ms interval.
+12V, +24Vs, AL and Bolt-on poweris switched on, followed by the +1V2 DCDC converter
Enable the supply detection algorithm
Switch ON Platform and display supply by switching LOW the Standby line.
Initialise I/O pins of the st-by µP:- Switch reset-AVC LOW (reset state)- Switch reset-system LOW (reset state)- Switch reset-Ethernet LOW (reset state)- Switch reset-USB LOW (reset state)- Switch reset-DVBs LOW (reset state)- keep Audio-reset and Audio-Mute-Up HIGH
Enable the DCDC converters (ENABLE-3V3n LOW)
NoDetect2 high received
within 2 seconds?
12V error: Layer1: 3
Layer2: 16
Enter protectionYes
Wait 50ms
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Figure 5-5 “Off” to “Semi Stand-by” flowchart (part 2)
18770_252_100216.eps100216
Yes
MIPS reads the wake up reasonfrom standby µP.
Semi-Standby
initialize tuner and channel decoders
Initialize video processing IC’s
Initialize source selection
initialize AutoTV by triggering CHS AutoTV Init interface
3-th try?
No
Blink Code as error code
Bootscript readyin 1250 ms?
Yes
No
Enable Alive check mechanism
Wait until AVC starts to communicate
SW initialization succeededwithin 20s?
No
Switch Standby I/O line highand wait 4 seconds
RPC start (comm. protocol)
Set I²C slave address of Standby µP to (60h)
Yes
Disable all supply related protections and switch off the +3V3 +5V DC/DC converter.
switch off the remaining DC/DC converters
Wait 5ms
Switch AVC PNX85500 in reset (active low)
Wait 10ms
Flash to Ramimage transfer succeeded
within 30s?No
Yes
Code =Layer1: 2
Layer2: 53
Code = Layer1: 2Layer2: 15
Initialize Ambilight with Lights off.
Timing need to be updated if more mature info is available.
Timing needs to be updated if more mature info is available.
Timing needs to be updated if more mature info is available.
Initialize audio
Enter protection
Reset-system is switched HIGH by the AVC at the end of the bootscript
AVC releases Reset-Ethernet, Reset-USB and Reset-DVBs when the end of the AVC boot-
script is detectedThis cannot be done through the bootscript, the I/O is on the standby µP
Reset-Audio and Audio-Mute-Up are switched by MIPS code later on in the
startup process
Reset-system is switched HIGH by the AVC at the end of the bootscript
Reset-Audio and Audio-Mute-Up are switched by MIPS code later on in the
startup process
Wake up reason coldboot & not semi-
standby?
85500 sends out startup screen
Startup screen cfg file present?
85500 starts up the display.
Startup screen visible
yes
yes
To keep this flowchart readable, the exact display turn on description is not copied here. Please see the Semi-standby to On description for the detailed display startup
sequence.
During the complete display time of the Startup screen, the preheat condition of
100% PWM is valid.
No
No
Startup screen shall only be visible when there is a coldboot to an active state end situation. The startup screen shall not be visible when waking up for reboot reasons or waking up to semi-standby conditions or waking up to enter Hibernate mode..
The first time after the option turn on of the startup screen or when the set is virgin, the cfg file is not present and hence the startup screen will not be shown.
AVC releases Reset-Ethernet, Reset-USB and Reset-DVBs when the end of the AVC boot-
script is detected
200Hz set?
No
yes
85500 sends out startup screen
200Hz Tcon has started up the display.
Startup screen visible
85500 requests Lamp on
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Figure 5-6 “Semi Stand-by” to “Active” flowchart (EEFL or LED backlight 50/100 Hz only)
18770_253_100216.eps100216
Active
Semi Standby
Initialize audio and video processing IC's and functions according needed use case.
Assert RGB video blanking and audio mute
Wait until previous on-state is left more than 2seconds ago. (to prevent LCD display problems)
The assumption here is that a fast toggle (<2s) can only happen during ON->SEMI ->ON. In these states,
the AVC is still active and can provide the 2s delay. Atransition ON->SEMI->STBY->SEMI->ON cannot be
made in less than 2s, because the standby state will be maintained for at least 4s.
Switch Audio-Reset low and wait 5ms
Constraints taken into account:- Display may only be started when valid LVDS output clock can be delivered by the AVC.- To have a reliable operation of the EEFL backlight, the backlight should be driven with a maximum PWM duty cycle during the first seconds. Only after this first one or two seconds, the PWM may be set to the required output level (Note that the PWM output should be present before the backlight is switched on). To minimize the artefacts, the picture should only be unblanked after these first seconds.
Restore dimming backlight feature, PWM and BOOST output and unblank the video.
Wait until valid and stable audio and video, corresponding to the requested output is delivered by the AVC
ANDthe backlight has been switched on for at least the time which is
indicated in the display file as preheat time.
The higher level requirement is that audio and video should be demuted without transient effects and that the audio should be demuted maximum 1s before or
at the same time as the unblanking of the video.
Release audio mute and wait 100ms before any other audio handling is done (e.g. volume change)
CPipe already generates a valid output clock in the semi-standby state: display
startup can start immediately when leaving the semi-standby state.
Switch on LCD backlight (Lamp-ON)
Switch off the dimming backlight feature, set the BOOST control to nominal and make sure PWM output is set to maximum allowed PWM
Switch on the Ambilight functionality according the last status settings.
Delay Lamp-on with the sum of the LVDS delay and the Lamp delay indicated in the display file
Switch on the display power by switching LCD-PWR-ON low
Wait x ms
Switch on LVDS output in the 85500
No
The exact timings to switch on the display (LVDS
delay, lamp delay) are defined in the
display file.
Start POK line detection algorithm
return
Display already on?(splash screen)
Yes
Display cfg file presentand up to date, according
correct display option?
Startup screen Optionand Installation setting
Photoscreen ON?
Yes
No
Prepare Start screen Display config file and copy to Flash
No
Yes
A LED set does not normally need a preheat time. The preheat remains present
but is set to zero in the display file.
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Figure 5-7 “Semi Stand-by” to “Active” flowchart (LED backlight 200 Hz)
18770_254_100216.eps100216
Active
Semi Standby
Initialize audio and video processing IC's and functions according needed use case.
Assert RGB video blanking and audio mute
Wait until previous on-state is left more than 2seconds ago. (to prevent LCD display problems)
The assumption here is that a fast toggle (<2s) can only happen during ON->SEMI ->ON. In these states, the AVC is still active and can
provide the 2s delay. If the transition ON->SEMI->STBY->SEMI->ON can be made in less than 2s, we have to delay the semi -> stby transition until
the requirement is met.
Switch Audio-Reset low and wait 5ms
unblank the video.
Wait until valid and stable audio and video, corresponding to the requested output is delivered by the AVC.
The higher level requirement is that audio and video should be demuted without transient
effects and that the audio should be demuted maximum 1s before or at the same time as the
unblanking of the video.
Release audio mute and wait 100ms before any other audio handling is done (e.g. volume change)
Request Tcon to Switch on the backlight in a direct LED or
set Lamp-on I/O line in case of a side LED
Switch on the Ambilight functionality according the last status settings.
There is no need to define the display timings since the timing
implementation is part of the Tcon.
Start POK linedetection algorithm
return
Display cfg file presentand up to date, according
correct display option?
Startup screen Optionand Installation setting
Photoscreen ON?
Yes
No
Prepare Start screen Display config file and copy to Flash
No
Yes
Backlight already on?(splash screen)
No
Yes
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Figure 5-8 “Active” to “Semi Stand-by” flowchart
18770_255_100216.eps100216
Semi Standby
Active
Wait x ms (display file)
Mute all sound outputs via softmute
Mute all video outputs
switch off LCD backlight(I/O or I²C)
Force ext audio outputs to ground (I/O: audio reset)
And wait 5ms
switch off Ambilight
Set main amplifier mute (I/O: audio-mute)
Wait 100ms
Wait until Ambilight has faded out: Output power Observer should be zero
Switch off the display power by switching LCD-PWR-ON high
Wait x ms
Switch off LVDS output in 85500The exact timings to
switch off the display (LVDS
delay, lamp delay) are defined in the
display file.
Switch off POK linedetection algorithm
200Hz set?
No
Yes
Instruct 200Hz Tcon to turn off
the display
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Figure 5-9 “Semi Stand-by” to “Stand-by” flowchart
18770_256_100216.eps100216
transfer Wake up reasons to the Stand by µP.
Stand by
Semi Stand by
Disable all supply related protections and switch off the DC/DC converters (ENABLE-3V3n)
Switch OFF all supplies by switching HIGH the Standby I/O line
Switch AVC system in reset state (reset-system and reset-AVC lines)
Switch reset-USB, Reset-Ethernet and Reset-DVBs LOW
Important remarks:
release reset audio 10 sec after entering standby to save power
Also here, the standby state has to be maintained for at least 4s before starting
another state transition.
Wait 5ms
Wait 10ms
Delay transition until ramping down of ambient light is finished. *)
If ambientlight functionality was used in semi-standby (lampadaire mode), switch off ambient light (see CHS
ambilight)
*) If this is not performed and the set is switched to standby when the switch off of the ambilights is still ongoing, the lights will switch off abruptly when the supply is cut.
Switch Memories to self-refresh (this creates a more stable condition when switching off the power).
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5.4 Service Tools
5.4.1 ComPair
IntroductionComPair (Computer Aided Repair) is a Service tool for Philips Consumer Electronics products. and offers the following:1. ComPair helps to quickly get an understanding on how to
repair the chassis in a short and effective way.2. ComPair allows very detailed diagnostics and is therefore
capable of accurately indicating problem areas. No knowledge on I2C or UART commands is necessary, because ComPair takes care of this.
3. ComPair speeds up the repair time since it can automatically communicate with the chassis (when the µP is working) and all repair information is directly available.
4. ComPair features TV software up possibilities.
SpecificationsComPair consists of a Windows based fault finding program and an interface box between PC and the (defective) product. The ComPair II interface box is connected to the PC via an USB cable. For the TV chassis, the ComPair interface box and the TV communicate via a bi-directional cable via the service connector(s).The ComPair fault finding program is able to determine the problem of the defective television, by a combination of automatic diagnostics and an interactive question/answer procedure.
How to ConnectThis is described in the chassis fault finding database in ComPair.
Figure 5-10 ComPair II interface connection
Caution: It is compulsory to connect the TV to the PC as shown in the picture above (with the ComPair interface in between), as the ComPair interface acts as a level shifter. If one connects the TV directly to the PC (via UART), ICs will be blown!
How to OrderComPair II order codes:• ComPair II interface: 3122 785 91020.• Software is available via the Philips Service web portal.• ComPair UART interface cable for Q55x.x.
(using 3.5 mm Mini Jack connector): 3138 188 75051. Note: While encounting problems, contact the local support desk.
5.5 Error Codes
5.5.1 Introduction
The error code buffer contains all detected errors since the last time the buffer was erased. The buffer is written from left to right, new errors are logged at the left side, and all other errors shift one position to the right. When an error occurs, it is added to the list of errors, provided the list is not full. When an error occurs and the error buffer is full, then the new error is not added, and the error buffer stays intact (history is maintained).To prevent that an occasional error stays in the list forever, the error is removed from the list after more than 50 hrs. of operation. When multiple errors occur (errors occurred within a short time span), there is a high probability that there is some relation between them. New in this chassis is the way errors can be displayed: • If no errors are there, the LED should not blink at all in
CSM or SDM. No spacer must be displayed as well.• There is a simple blinking LED procedure for board
level repair (home repair) so called LAYER 1 errors next to the existing errors which are LAYER 2 errors (see Table 5-2).– LAYER 1 errors are one digit errors.– LAYER 2 errors are 2 digit errors.
• In protection mode.– From consumer mode: LAYER 1.– From SDM mode: LAYER 2.
• Fatal errors, if I2C bus is blocked and the set reboots, CSM and SAM are not selectable.– From consumer mode: LAYER 1.– From SDM mode: LAYER 2.
• In CSM mode.– When entering CSM: error LAYER 1 will be displayed
by blinking LED. Only the latest error is shown.• In SDM mode.
– When SDM is entered via Remote Control code or the hardware pins, LAYER 2 is displayed via blinking LED.
• Error display on screen.– In CSM no error codes are displayed on screen.– In SAM the complete error list is shown.
Basically there are three kinds of errors:• Errors detected by the Stand-by software which lead to
protection. These errors will always lead to protection and an automatic start of the blinking LED LAYER 1 error.(see section “5.6 The Blinking LED Procedure”).
• Errors detected by the Stand-by software which not lead to protection. In this case the front LED should blink the involved error. See also section “5.5 Error Codes, 5.5.4 Error Buffer, Extra Info”. Note that it can take up several minutes before the TV starts blinking the error (e.g. LAYER 1 error = 2, LAYER 2 error = 15 or 53).
• Errors detected by main software (MIPS). In this case the error will be logged into the error buffer and can be read out via ComPair, via blinking LED method LAYER 1-2 error, or in case picture is visible, via SAM.
5.5.2 How to Read the Error Buffer
Use one of the following methods:• On screen via the SAM (only when a picture is visible).
E.g.:– 00 00 00 00 00: No errors detected– 23 00 00 00 00: Error code 23 is the last and only
detected error.– 37 23 00 00 00: Error code 23 was first detected and
error code 37 is the last detected error.– Note that no protection errors can be logged in the
error buffer.
10000_036_090121.eps091118
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• Via the blinking LED procedure. See section 5.5.3 How to Clear the Error Buffer.
• Via ComPair.
5.5.3 How to Clear the Error Buffer
Use one of the following methods:• By activation of the “RESET ERROR BUFFER” command
in the SAM menu.• If the content of the error buffer has not changed for 50+
hours, it resets automatically.
5.5.4 Error Buffer
In case of non-intermittent faults, clear the error buffer before starting to repair (before clearing the buffer, write down the
content, as this history can give significant information). This to ensure that old error codes are no longer present. If possible, check the entire contents of the error buffer. In some situations, an error code is only the result of another error code and not the actual cause (e.g. a fault in the protection detection circuitry can also lead to a protection). There are several mechanisms of error detection:• Via error bits in the status registers of ICs.• Via polling on I/O pins going to the stand-by processor.• Via sensing of analogue values on the stand-by processor
or the PNX85500.• Via a “not acknowledge” of an I2C communication.
Take notice that some errors need several minutes before they start blinking or before they will be logged. So in case of problems wait 2 minutes from start-up onwards, and then check if the front LED is blinking or if an error is logged.
Table 5-2 Error code overview
Extra Info• Rebooting. When a TV is constantly rebooting due to
internal problems, most of the time no errors will be logged or blinked. This rebooting can be recognized via a ComPair interface and Hyperterminal (for Hyperterminal settings, see section “5.8 Fault Finding and Repair Tips, 5.8.6 Logging). It’s shown that the loggings which are generated by the main software keep continuing. In this case diagnose has to be done via ComPair.
• Error 13 (I2C bus 3, SSB bus blocked). At the time of release of this manual, this error was not working as expected. Current situation: when this error occurs, the TV will constantly reboot due to the blocked bus. The best way for further diagnosis here, is to use ComPair.
• Error 14 (I2C bus 2, TV set bus blocked). At the time of release of this manual, this error was not working as expected. Current situation: when this error occurs, the TV will constantly reboot due to the blocked bus. The best way for further diagnosis here, is to use ComPair.
• Error 18 (I2C bus 4, Tuner bus blocked). At the time of release of this manual, this error was not working as expected. Current situation: when this error occurs, the TV will constantly reboot due to the blocked bus. The best way for further diagnosis here, is to use ComPair.
• Error 15 (PNX8550 doesn’t boot). Indicates that the main processor was not able to read his bootscript. This error will point to a hardware problem around the PNX8550 (supplies not OK, PNX 8550 completely dead, I2C link between PNX and Stand-by Processor broken, etc...). When error 15 occurs it is also possible that I2C1 bus is
blocked (NVM). I2C1 can be indicated in the schematics as follows: SCL-UP-MIPS, SDA-UP-MIPS.Other root causes for this error can be due to hardware problems regarding the DDR’s and the bootscript reading from the PNX8550.
• Error 16 (12V). This voltage is made in the power supplyand results in protection (LAYER 1 error = 3) in case of absence. When SDM is activated we see blinking LED LAYER 2 error = 16.
• Error 17 (Invertor or Display Supply). Here the status of the “Power OK” is checked by software, no protection will occur during failure of the invertor or display supply (no picture), only error logging. LED blinking of LAYER 1 error = 3 in CSM, in SDM this gives LAYER 2 error = 17.
• Error 23 (HDMI). When there is no I2C communication towards the HDMI mux after start-up, LAYER 2 error = 23 will be logged and displayed via the blinking LED procedure if SDM is switched “on”.
• Error 24 (I2C switch). When there is no I2C communication towards the I2C switch, LAYER 2 error = 24 will be logged and displayed via the blinking LED procedure when SDM is switched “on”. Remark : this only works for TV sets with an I2C controlled screen included.
• Error 28 (Channel dec DVB-S). When there is no I2C communication towards the DVB-S channel decoder, LAYER 2 error = 28 will be logged and displayed via the blinking LED procedure if SDM is switched “on”.
• Error 31 (Lnb controller). When there is no I2C communication towards this device, LAYER 2 error = 31
Description Layer 1 Layer 2Monitoredby
Error/Prot
Error Buffer/Blinking LED Device Defective Board
I2C3 2 13 MIPS E BL / EB SSB SSB
I2C2 2 14 MIPS E BL / EB SSB SSB
I2C4 2 18 MIPS E BL / EB SSB SSB
PNX doesn’t boot (HW cause) 2 15 Stby µP P BL PNX8550 SSB
12V 3 16 Stby µP P BL / Supply
Inverter or display supply 3 17 MIPS E EB / Supply
HDMI mux 2 23 MIPS E EB Sil9x87A SSB
I2C switch 2 24 MIPS E EB PCA9540 SSB
Channel dec DVB-S 2 28 MIPS E EB STV0903 SSB
Lnb controller 2 31 MIPS E EB LNBH23 SSB
Tuner 2 34 MIPS E EB DTT 71300 SSB
Main nvm 2 35 MIPS E EB STM24C64 SSB
Tuner DVB-S 2 36 MIPS E EB STV6110 SSB
T° sensor SSB/set 2 42 MIPS E EB LM 75 T° sensor
T° sensor LED driver/Tcon 7 42 MIPS E EB LM 75 T° sensor
PNX doesn’t boot (SW cause) 2 53 Stby µP P BL PNX8550 SSB
Display 5 64 MIPS E BL / EB Altera Display
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will be logged and displayed via the blinking LED procedure if SDM is activated.
• Error 34 (Tuner). When there is no I2C communication towards the tuner during start-up, LAYER 2 error = 34 will be logged and displayed via the blinking LED procedure when SDM is switched “on”.
• Error 35 (main NVM). When there is no I2C communication towards the main NVM during start-up, LAYER 2 error = 35 will be displayed via the blinking LED procedure when SDM is switched “on”. All service modes (CSM, SAM and SDM) are accessible during this failure, observed in the Uart logging as follows : "<< ERRO >>> PFPOW_.C : First Error (id19, Layer_1= 2 Layer_= 35)".
• Error 36 (Tuner DVB-S). When there is no I2C communication towards the DVB-S tuner during start-up, LAYER 2 error = 36 will be logged and displayed via the blinking LED procedure when SDM is switched “on”.
• Error 42 (Temp sensor). Only applicable for TV sets equipped with temperature devices.
• Error 53. This error will indicate that the PNX8550 has read his bootscript (when this would have failed, error 15 would blink) but initialization was never completed because of hardware problems (NAND flash, ...) or software initialization problems. Possible cause could be that there is no valid software loaded (try to upgrade to the latest main software version). Note that it can take a few minutes before the TV starts blinking LAYER 1 error = 2 or in SDM, LAYER 2 error = 53.
• Error 64. Only applicable for TV sets with an I2C controlled screen .
5.6 The Blinking LED Procedure
5.6.1 Introduction
The blinking LED procedure can be split up into two situations:• Blinking LED procedure LAYER 1 error. In this case the
error is automatically blinked when the TV is put in CSM. This will be only one digit error, namely the one that is referring to the defective board (see table “5-2 Error code overview”) which causes the failure of the TV. This approach will especially be used for home repair and call centres. The aim here is to have service diagnosis from a distance.
• Blinking LED procedure LAYER 2 error. Via this procedure, the contents of the error buffer can be made visible via the front LED. In this case the error contains 2 digits (see table “5-2 Error code overview”) and will be displayed when SDM (hardware pins) is activated. This is especially useful for fault finding and gives more details regarding the failure of the defective board.
Important remark: For an empty error buffer, the LED should not blink at all in CSM or SDM. No spacer will be displayed.
When one of the blinking LED procedures is activated, the front LED will show (blink) the contents of the error buffer. Error codes greater then 10 are shown as follows:1. “n” long blinks (where “n” = 1 to 9) indicating decimal digit2. A pause of 1.5 s3. “n” short blinks (where “n”= 1 to 9)4. A pause of approximately 3 s,5. When all the error codes are displayed, the sequence
finishes with a LED blink of 3 s (spacer).6. The sequence starts again. Example: Error 12 8 6 0 0. After activation of the SDM, the front LED will show: 1. One long blink of 750 ms (which is an indication of the
decimal digit) followed by a pause of 1.5 s2. Two short blinks of 250 ms followed by a pause of 3 s3. Eight short blinks followed by a pause of 3 s4. Six short blinks followed by a pause of 3 s5. One long blink of 3 s to finish the sequence (spacer).
6. The sequence starts again.
5.6.2 How to Activate
Use one of the following methods:• Activate the CSM. The blinking front LED will show only
the latest layer 1 error, this works in “normal operation” mode or automatically when the error/protection is monitored by the standby processor.In case no picture is shown and there is no LED blinking, read the logging to detect whether “error devices” are mentioned. (see section “5.8 Fault Finding and Repair Tips, 5.8.6 Logging”).
• Activate the SDM. The blinking front LED will show the entire content of the LAYER 2 error buffer, this works in “normal operation” mode or when SDM (via hardware pins) is activated when the tv set is in protection.
5.7 Protections
5.7.1 Software Protections
Most of the protections and errors use either the stand-by microprocessor or the MIPS controller as detection device. Since in these cases, checking of observers, polling of ADCs, and filtering of input values are all heavily software based, these protections are referred to as software protections.There are several types of software related protections, solving a variety of fault conditions:• Related to supplies: presence of the +5V, +3V3 and 1V2
needs to be measured, no protection triggered here.• Protections related to breakdown of the safety check
mechanism. E.g. since the protection detections are done by means of software, failing of the software will have to initiate a protection mode since safety cannot be guaranteed any more.
Remark on the Supply ErrorsThe detection of a supply dip or supply loss during the normal playing of the set does not lead to a protection, but to a cold reboot of the set. If the supply is still missing after the reboot, the TV will go to protection.
Protections during Start-upDuring TV start-up, some voltages and IC observers are actively monitored to be able to optimise the start-up speed, and to assure good operation of all components. If these monitors do not respond in a defined way, this indicates a malfunction of the system and leads to a protection. As the observers are only used during start-up, they are described in the start-up flow in detail (see section “5.3 Stepwise Start-up”).
5.7.2 Hardware Protections
The only real hardware protection in this chassis appears in case of an audio problem e.g. DC voltage on the speakers. This protection will only affect the Class D audio amplifier (item 7D10; see diagram B03A) and puts the amplifier in a continuous burst mode (cyclus approximately 2 seconds).
Repair Tip• There still will be a picture available but no sound. While
the Class D amplifier tries to start-up again, the cone of the loudspeakers will move slowly in one or the other direction until the initial failure shuts the amplifier down, this cyclus starts over and over again. The headphone amplifier will also behaves similar.
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5.8 Fault Finding and Repair Tips
Read also section “5.5 Error Codes, 5.5.4 Error Buffer, Extra Info”.
5.8.1 Ambilight
Due to degeneration process of the LED’s fitted on the ambi module, there can be a difference in the colour and/or light output of the spare ambilight modules in comparison with the originals ones contained in the TV set. Via SAM => alignments => ambilight, the spare module can be adjusted.
5.8.2 Audio Amplifier
The Class D-IC 7D10 has a powerpad for cooling. When the IC is replaced it must be ensured that the powerpad is very well pushed to the PWB while the solder is still liquid. This is needed to insure that the cooling is guaranteed, otherwise the Class D-IC could break down in short time.
5.8.3 CSM
When CSM is activated and there is a USB stick connected to the TV, the software will dump the complete CSM content to the USB stick. The file (Csm.txt) will be saved in the root of the USB stick. If this mechanism works it can be concluded that a large part of the operating system is already working (MIPS, USB...)
5.8.4 DC/DC Converter
Description basic board The basic board power supply consists of 4 DC/DC converters and 5 linear stabilisers. All DC/DC converters have +12V input voltage and deliver :• +1V1 supply voltage (1.15V nominal), for the core voltage
of PNX85500, stabilised close to the point of load; SENSE+1V1 signal provides the DC-DC converter the needed feedback to achieve this.
• +1V8 supply voltage, for the DDR2 memories and DDR2 interface of PNX85500.
• +3V3 supply voltage (3.30V nominal), overall 3.3 V for onboard IC’s, for non-5000 series SSB diversities only.
• +5V (5.15V nominal) for USB, WIFI and Conditional Access Module and +5V5-TUN for +5V-TUN tuner stabiliser.
The linear stabilisers are providing:• +1V2 supply voltage (1.2V nominal), stabilised close to
PNX85500 device, for various other internal blocks of PNX85500; SENSE+1V2 signal provides the needed feedback to achieve this.
• +2V5 supply voltage (2.5V nominal) for LVDS interface and various other internal blocks of PNX85500; for 5000 series SSB diversities the stabiliser is 7UD2 while for the other diversities 7UC0 is used.
• +3V3 supply voltage (3V3 nominal) for 5000 series SSB diversities, provided by 7UD3; in this case the 12V to 3V3 DC-DC converter is not present.
• +5V-TUN supply voltage (5V nominal) for tuner and IF amplifier.
+3V3-STANDY (3V3 nominal) is the permanent voltage, supplying the standby microprocessor inside PNX85500. Supply voltage +1V1 is started immediately when +12V voltagebecomes available (+12V is enabled by STANDBY signal when “low”). Supply voltages +3V3, +2V5, +1V8, +1V2 and +5V-TUN are switched “on” by signal ENABLE-3V3 when ‘low”, provided that +12V (detected via 7U40 and 7U41) is present.
+12V is considered OK (=> DETECT2 signal becomes “high”, +12V to +1V8, +12V to +3V3, +12V to +5V DC-DC converter can be started up) if it rises above 10V and doesn’t drop below 9V5. A small delay of a few milliseconds is introduced between the start-up of 12V to +1V8 DC-DC converter and the two other DC-DC converters via 7U48 and associated components. Description DVB-S2:• LNB-RF1 (0V = disabled, 14V or 18V in normal operation)
LNB supply generated via the second conversion channel of 7T03 followed by 7T50 LNB supply control IC.It provides supply voltage that feeds the outdoor satellite reception equipment.
• +3V3-DVBS (3V3 nominal), +2V5-DVBS (2V5 nominal) and +1V-DVBS (1.03V nominal) power supply for the silicon tuner and channel decoder. +1V-DVBS is generated via a 5V to 1V DC-DC converter and is stabilised at the point of load (channel decoder) by means of feedback signal SENSE+1V0-DVBS. +3V3-DVBS and +2V5-DVBS are generated via linear stabilisers from +5V-DVBS that by itself is generated via the first conversion channel of 7T03.
At start-up, +24V becomes available when STANDBY signal is “low” (together with +12V for the basic board), when +3V3 from the basic board is present the two DC-DC converters channels inside 7T03 are activated. Initially only the 24V to 5V converter (channel 1 of 7T03 generating +5V-DVBS) will effectively work, while +V-LNB is held at a level around 11V7 via diode 6T55. After 7T05 is initialized, the second channel of 7T03 will start and generates a voltage higher then LNB-RF1 with 0V8. +5V-DVBS start-up will imply +3V3-DVBS start-up, with a small delay of a few milliseconds => +2V5-DVBS and +1V-DVBS will be enabled.
If +24V drops below +15V level then the DVB-S2 supply will stop, even if +3V3 is still present..
DebuggingThe best way to find a failure in the DC/DC converters is to check their start-up sequence at power-on via the mains cord, presuming that the standby microprocessor and the external supply are operational. Take STANDBY signal high-to-low transition as time reference.When +12V becomes available (maximum 1 second after STANDBY signal goes “low”) then +1V1 is started immediately. After ENABLE-3V3 goes “low”, all the other supply voltages should rise within a few milliseconds.
Tips• Behaviour comparison with a reference TV550 platform
can be a fast way to locate failures.• If +12V stays “low”, check the integrity of fuse 1U40.• Check the integrity (at least no short circuit between drain
and source) of the power MOS-FETs before starting up the platform in SDM, otherwise many components might be damaged. Using a ohmmeter can detect short circuits between any power rail and ground or between +12V and any other power rail.
• Short circuit at the output of an integrated linear stabiliser (7UC0, 7UD2 or 7UD3) will heat up this device strongly.
• Switching frequencies should be 500 kHz ...600 kHz for 12 V to 1.1 V and 12 V to 1.8 V DC-DC converters, 900 kHz for 12 V to 3.3 V and 12 V to 5 V DC-DC converters. The DVB-S2 supply 24 V to 5 V and 24 V to +V LNB DC-DC converters operates at 300 kHz while for 5 V to 1.1 V DC-DC converter 900 kHz is used.
5.8.5 Exit “Factory Mode”
When an “F” is displayed in the screen’s right corner, this means the set is in “Factory” mode, and it normallyhappens after a new SSB is mounted. To exit this mode, push the “VOLUME minus” button on the TV’s local keyboard for 10 seconds (this disables the continuous mode).
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Then push the “SOURCE” button for 10 seconds until the “F” disappears from the screen.
5.8.6 Logging
When something is wrong with the TV set (f.i. the set is rebooting) you can check for more information via the logging in Hyperterminal. The Hyperterminal is available in every Windows application via Programs, Accessories, Communications, Hyperterminal. Connect a “ComPair UART”-cable (3138 188 75051) from the service connector in the TV to the “multi function” jack at the front of ComPair II box.Required settings in ComPair before starting to log :- Start up the ComPair application.- Select the correct database (open file “Q55X.X”, this will set the ComPair interface in the appropriate mode).- Close ComPairAfter start-up of the Hyperterminal, fill in a name (f.i. “logging”) in the “Connection Description” box, then apply the following settings: 1. COMx2. Bits per second = 1152003. Data bits = 84. Parity = none5. Stop bits = 16. Flow control = noneDuring the start-up of the TV set, the logging will be displayed. This is also the case during rebooting of the TV set (the same logging appears time after time). Also available in the logging is the “Display Option Code” (useful when there is no picture), look for item “DisplayRawNumber” in the beginning of the logging. Tip: when there is no picture available during rebooting you are able to check for “error devices” in the logging (LAYER 2 error) which can be very helpful to determine the failure cause of the reboot. For protection state, there is no logging.
5.8.7 Loudspeakers
Make sure that the volume is set to minimum during disconnecting the speakers in the ON-state of the TV. The audio amplifier can be damaged by disconnecting the speakers during ON-state of the set!
5.8.8 PSL
In case of no picture when CSM (test pattern) is activated and backlight doesn’t light up, it’s recommended first to check the inverter on the PSL + wiring (LAYER 2 error = 17 is displayed in SDM).
5.8.9 Tuner
Attention: In case the tuner is replaced, always check the tuner options!
5.8.10 Display option code
Attention: In case the SSB is replaced, always check the display option code in SAM, even when picture is available. Performance with the incorrect display option code can lead to unwanted side-effects for certain conditions.
New in this chassis:While in the download application (start up in TV mode + “OK” button pressed), the display option code can be changed via 062598 HOME XXX special SAM command (XXX=display option in 3 digits).
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5.8.11 SSB Replacement
Follow the instructions in the flowchart in case a SSB has to be exchanged. See figure “SSB replacement flowchart”.
Figure 5-11 SSB replacement flowchart
H_16771_007a.eps100402
STAR T
C onnect the U SB s tick to the set, go to SAM and save the current TV settings via “Upload to USB”
Set is s till operating?
Yes
1. D isconnect the WiF i module from the PC I connector (only for Q549.x SSB)2. Replace the SSB by a Service SSB.3. Place the WiFi module in the PCI connector.4. Mount the Service SSB in the set.
Set behaviour?
Yes
No
N o
Instruction note SSB replacem ent Q543.x, Q548.x, Q549.x, and Q55x.x
Before starting:- prepare a USB memory stick with the latest software- download the latest Main Software (Fus) from www.p4c.philips.com- unzip this file- create a folder ”upgrades” in the root of a USB stick (size > 50 MB) and save the autorun.upg file in this "upgrades" folder.Note: it is possible to rename this file, e.g."Q54x_SW_version.upg"; this incase there are more than one "autorun.upg" files on the USB stick.
No picture displayed Picture displayedSet is starting up without software upgrade menu appearing on screen
Picture displayedSet is starting up with software upgrade menu appearing on screen
Due to a possible wrong display option code in the received ServiceSSB (NVM), it’s possible that no picture is displayed. Due to this the download application will not be shown either. This tree enables you to load the main software step-by-step via the UART logging on the PC(this for visual feedback).
Start-up the set
1) Start up the TV set, equiped with the Service SSB, and enable the UART logging on the PC.
2) The TV set will start-up automatically in the download application if main TV software is not loaded.
3) Plug the prepared USB stick into the TV set. Follow theinstructions in the UART log file, press “Right” cursor key to enter
the list. Navigate to the “autorun.upg” file in the UART loggingprintout via the cursor keys on the remote control. When the
correct file is selected, press “Ok”.
4) Press "Down" cursor and “Ok” to start flashing the mainTV software. Printouts like: “L: 1-100%, V: 1-100% and P: 1-100%” should be visible now in the UART logging.
5) Wait until the message “Operation successful !” is logged inthe UART log and remove all inserted media. Restart the TV set.
1) Plug the USB stick into the TV set and select the “autorun .upg” file in the displayed browser.
2) Now the main software will be loaded automatically,supported by a progress bar.
3) Wait until the message “Operation successful !” is displayedand remove all inserted media. Restart the TV set.
Set the correct “Display code” via “062598 -HOME- xxx” where“xxx” is the 3 digit display panel code (see sticker on the side
or bottom of the cabinet)
After entering the “Display Option” code, the set is going to Standby
(= validation of code)
Restart the set
Connect PC via the ComPair interface to Service connector.
Start TV in Jett mode (DVD I + (OSD))Open ComPair browser Q54x
Program set type number, serial number, and display 12 NCProgram E - DFU if needed.
Go to SAM and reload settingsvia “Download from USB” function.
In case of settings reloaded from USB, the set type,serial number, display 12 NC, are automatically storedwhen entering display options.
- Check if correct “display option” code is programmed.- Verify “option codes” according to sticker inside the set.- Default settings for “white drive” > see Service Manual.
Q54x.E SSB Board swap – VDSUpdated 22-03-2010
If not already done:Check latest software on Service website.
Update main and Stand-by software via USB.
Check and perform alignments in SAM according to theService Manual. Option codes, colour temperature, etc.
Final check of all menus in CSM.Special attention for HDMI Keys and Mac address.
Check if E - D F U is present.
End
Attention point for Net TV: If the set type and serial number are notfilled in, the Net TV functionality will not work. It will not be possibleto connect to the internet.
Saved settingson USB stick?
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Figure 5-12 SSB replacement flowchart - Factory mode
H_16771_007b.eps100322
Restart the set
Set is start ing up in Factory m ode
Set is starting up in Factory mode?
Noisy picture with bands/lines is visible and theRED LED is continuous on.
An “F” is displayed (and the HDMI 1 input is displayed).
- Press the “volume minus” button on the TVs local keyboard for 5 ~10 seconds
- Press the “SOURCE” button for 10 seconds until the “F” disappears from the screen or the noise on the screen is replaced by “blue mute”
The noise on the screen is replaced with the blue mute or the “F” is disappeared!
Unplug the mains cord to verify the correctdisabling of the Factory mode.
Program display option code via “062598 MENU”, followed by
the 3 digits code of the display(this code can be found
on a sticker on - or inside - the set).
After entering “display option” code, the set is going in stand-by mode (= validation of code)
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5.9 Software Upgrading
5.9.1 Introduction
The set software and security keys are stored in a NAND-Flash, which is connected to the PNX85500.
It is possible for the user to upgrade the main software via the USB port. This allows replacement of a software image in a stand alone set, without the need of an E-JTAG debugger. A description on how to upgrade the main software can be found in the electronic User Manual.
Important: When the NAND-Flash must be replaced, a new SSB must be ordered, due to the presence of the security keys! (CI +, MAC address, ...).Perform the following actions after SSB replacement:1. Set the correct option codes (see sticker inside the TV).2. Update the TV software => see the eUM (electronic User
Manual) for instructions.3. Perform the alignments as described in chapter 6 (section
6.5 Reset of Repaired SSB).4. Check in CSM if the CI + key, MAC address.. are valid.For the correct order number of a new SSB, always refer to the Spare Parts list!
5.9.2 Main Software Upgrade
• The “UpgradeAll.upg” file is only used in the factory.
Automatic Software UpgradeIn “normal” conditions, so when there is no major problem with the TV, the main software and the default software upgrade application can be upgraded with the “AUTORUN.UPG” (FUS part of the one-zip file: e.g. 3104 337 05661 _FUS _Q555X_ x.x.x.x_commercial.zip). This can also be done by the consumers themselves, but they will have to get their software from the commercial Philips website or via the Software Update Assistant in the user menu (see eUM). The “autorun.upg” file must be placed in the root of the USB stick.How to upgrade:1. Copy “AUTORUN.UPG” to the root of the USB stick.2. Insert USB stick in the set while the set is operational. The
set will restart and the upgrading will start automatically. As soon as the programming is finished, a message is shown to remove the USB stick and restart the set.
Manual Software UpgradeIn case that the software upgrade application does not start automatically, it can also be started manually.How to start the software upgrade application manually:1. Disconnect the TV from the Mains/AC Power.2. Press the “OK” button on a Philips TV remote control or a
Philips DVD RC-6 remote control (it is also possible to use a TV remote in “DVD” mode). Keep the “OK” button pressed while reconnecting the TV to the Mains/AC Power.
3. The software upgrade application will start.
Attention!In case the download application has been started manually, the “autorun.upg” will maybe not be recognized.What to do in this case:1. Create a directory “UPGRADES” on the USB stick.2. Rename the “autorun.upg” to something else, e.g. to
“software.upg”. Do not use long or complicated names, keep it simple. Make sure that “AUTORUN.UPG” is no longer present in the root of the USB stick.
3. Copy the renamed “upg” file into this directory.4. Insert USB stick into the TV.5. The renamed “upg” file will be visible and selectable in the
upgrade application.
Back-up Software Upgrade ApplicationIf the default software upgrade application does not start (could be due to a corrupted boot sector) via the above described method, try activating the “back-up software upgrade application”.How to start the “back-up software upgrade application” manually:1. Disconnect the TV from the Mains/AC Power.2. Press the “CURSOR DOWN”-button on a Philips TV
remote control while reconnecting the TV to the Mains/AC Power.
3. The back-up software upgrade application will start.
5.9.3 Stand-by Software Upgrade via USB
In this chassis it is possible to upgrade the Stand-by software via a USB stick. The method is similar to upgrading the main software via USB.Use the following steps:1. Create a directory “UPGRADES” on the USB stick.2. Copy the Stand-by software (part of the one-zip file, e.g.
StandbySW_CFT72_88.0.0.0.upg) into this directory.3. Insert the USB stick into the TV.4. Start the download application manually (see section “
Manual Software Upgrade”.5. Select the appropriate file and press the “OK” button to
upgrade.
5.9.4 Content and Usage of the One-Zip Software File
Below the content of the One-Zip file is explained, and instructions on how and when to use it.• FUS_Q5551_x.x.x.x_commercial.zip. Contains the
“autorun.upg” which is needed to upgrade the TV main software and the software download application.
• StandbySW_CFTxx_x.x.x.x_commercial.zip. Contains the Stand-by software in “upg” and “hex” format.– The “StandbySW_xxxxx_prod.upg” file can be used to
upgrade the Stand-by software via USB.– The “StandbySW_xxxxx.hex” file can be used to
upgrade the Stand-by software via ComPair.– The files “StandbySW_xxxxx_exhex.hex” and
“StandbySW_xxxxx_dev.upg” may not be used by Service technicians (only for development purposes).
• UpgradeAll_Q555X_x.x.x.x_commercial.zip. Only for production purposes, not to be used by Service technicians.
• ProcessNVM_Q55XX_x.x.x.x.zip. Default NVM content. Must be programmed via ComPair or can be loaded via USB, be aware that all alignments stored in NVM are overwritten here.
5.9.5 UART logging 2K10 (see section “5.8 Fault Finding and Repair Tips, 5.8.6 Logging)
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6. Alignments
Index of this chapter:6.1 General Alignment Conditions6.2 Hardware Alignments6.3 Software Alignments6.4 Option Settings6.5 Reset of Repaired SSB6.6 Service SSB delivered without main software loaded6.7 Total Overview SAM modes
6.1 General Alignment Conditions
Perform all electrical adjustments under the following conditions:• Power supply voltage (depends on region):
– AP-NTSC: 120 VAC or 230 VAC / 50 Hz (± 10%).– AP-PAL-multi: 120 - 230 VAC / 50 Hz (± 10%).– EU: 230 VAC / 50 Hz (± 10%).– LATAM-NTSC: 120 - 230 VAC / 50 Hz (± 10%).– US: 120 VAC / 60 Hz (± 10%).
• Connect the set to the mains via an isolation transformer with low internal resistance.
• Allow the set to warm up for approximately 15 minutes.• Measure voltages and waveforms in relation to correct
ground (e.g. measure audio signals in relation to AUDIO_GND). Caution: It is not allowed to use heat sinks as ground.
• Test probe: Ri > 10 MΩ, Ci < 20 pF.• Use an isolated trimmer/screwdriver to perform
alignments.
6.1.1 Alignment Sequence
• First, set the correct options:– In SAM, select “Option numbers”.– Fill in the option settings for “Group 1” and “Group 2”
according to the set sticker (see also paragraph 6.4 Option Settings).
– Press OK on the remote control before the cursor is moved to the left.
– In submenu “Option numbers” select “Store” and press OK on the RC.
• OR:– In main menu, select “Store” again and press OK on
the RC.– Switch the set to Stand-by.
• Warming up (>15 minutes).
6.2 Hardware Alignments
Not applicable.
6.3 Software Alignments
Put the set in SAM mode (see Chapter 5. Service Modes, Error Codes, and Fault Finding). The SAM menu will now appear on the screen. Select ALIGNMENTS and go to one of the sub menus. The alignments are explained below.The following items can be aligned:• White point• Ambilight• TCON Alignment• Reset TCON Alignment. To store the data:• Press OK on the RC before the cursor is moved to the
left• In main menu select “Store” and press OK on the RC• Switch the set to stand-by mode.
For the next alignments, supply the following test signals via a video generator to the RF input:• EU/AP-PAL models: a PAL B/G TV-signal with a signal
strength of at least 1 mV and a frequency of 475.25 MHz• US/AP-NTSC models: an NTSC M/N TV-signal with a
signal strength of at least 1 mV and a frequency of 61.25 MHz (channel 3).
• LATAM models: an NTSC M TV-signal with a signal strength of at least 1 mV and a frequency of 61.25 MHz (channel 3).
6.3.1 White Point
• Choose “TV menu”, “Setup”, “More TV Settings” and then “Picture” and set picture settings as follows:
• In menu “Picture”, choose “Pixel Plus HD” and set picture settings as follows:
• Go to the SAM and select “Alignments”-> “White point”.
White point alignment LCD screens:• Use a 90% white screen to the HDMI input and set the
following values:– “Colour temperature”: “Normal”.– All “White point” values to: “127”.
In case you have a colour analyser:• Measure with a calibrated contactless colour analyser
(Minolta CA-210 or Minolta CS-200) in the centre of the screen. Consequently, the measurement needs to be done in a dark environment.
• Adjust the correct x, y coordinates (while holding one of the White point registers R, G or B on 127) by means of decreasing the value of one or two other white points to the correct x, y coordinates (see Table 6-1 White D alignment values CCFL backlight panels, 6-2 White D alignment values LED backlight panels - colour analyser Minolta CA-210 or 6-3 White D alignment values LED backlight panels - colour analyser Minolta CS-200). Tolerance: dx: ± 0.002, dy: ± 0.002.
• Repeat this step for the other colour temperatures that need to be aligned.
• When finished press OK on the RC and then press STORE (in the SAM root menu) to store the aligned values to the NVM.
• Restore the initial picture settings after the alignments.
Table 6-1 White D alignment values CCFL backlight panels
Picture Setting
Contrast 100
Brightness 50
Colour 0
Light Sensor Off
Picture format Unscaled
Picture Setting
Dynamic Contrast Off
Dynamic Backlight Off
Colour Enhancement Off
Gamma 0
Value Cool (11000K) Normal (9000K) Warm (6500K)
x 0.276 0.287 0.313
y 0.282 0.296 0.329
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Table 6-2 White D alignment values LED backlight panels -
colour analyser Minolta CA-210
Table 6-3 White D alignment values LED backlight panels -
colour analyser Minolta CS-200
If you do not have a colour analyser, you can use the default values. This is the next best solution. The default values are average values coming from production.• Select a COLOUR TEMPERATURE (e.g. COOL,
NORMAL, or WARM).• Set the RED, GREEN and BLUE default values according
to the values in Table 6-4 and Table 6-5.• When finished press OK on the RC, then press STORE (in
the SAM root menu) to store the aligned values to the NVM.• Restore the initial picture settings after the alignments.
Table 6-4 White tone default setting 42" 1
Notes1): data is preliminary and will be updated in next release.
Table 6-5 White tone default setting 46"
Table 6-6 TCON default settings
6.3.2 Alignment of the Ambilight modules
Method:• Go to SAM (press 062596 + OK button).• Select Alignments.• Select Ambilight: a white testpattern shall be displayed.• Select the number of module (pixel) that have to be
aligned. Module (pixel) 1 is the first one which will come across according the wire connection track as follows: start by the small signal panel and proceed towards the ambilient modules. This module (pixel) 1 will be connected to the next module (pixel) 2 and etc.
• Align the brightness compared with the neighbour modules. The brightness will be automatically stored.
• Select one of the 10 matrixes which most color respond towards the neighbour modules. The alignment is stored automatically.
6.3.3 TCON Alignment
In TV sets with forward integration where the TCON device is located on the small signal board or 200 Hz board, all TCON values needs realignment for every SSB/display swap due to repair or upgrade. The TCON alignment during assembly is normally supported by a special testpattern and the use of a camera, hence very difficult to simulate for home repair. A more practical way with predefined settings is described below:
• Go to SAM (dial 062596 + OK button pressed).• Select Alignments.• TCON alignment: value with 4 digits, this can be changed
by RC-transmitter entry according the values listed in Table 6-6. The value shall be stored in:- STVM100DC for Sharp- MAX9668 for LGD
• Reset TCON alignment: here, a default value (according the display option code) will be copied from the display file to the TCON and changes the current value to the default value.
6.4 Option Settings
6.4.1 Introduction
The microprocessor communicates with a large number of I2C ICs in the set. To ensure good communication and to make digital diagnosis possible, the microprocessor has to know which ICs to address. The presence / absence of these PNX51XX ICs (back-end advanced video picture improvement IC which offers motion estimation and compensation features (commercially called HDNM) plus integrated Ambilight control) is made known by the option codes. Notes:• After changing the option(s), save them by pressing the OK
button on the RC before the cursor is moved to the left, select STORE in the SAM root menu and press OK on the RC.
• The new option setting is only active after the TV is switched “off” / “stand-by” and “on” again with the mains switch (the NVM is then read again).
6.4.2 Dealer Options
For dealer options, in SAM select “Dealer options”.See Table 6-8 SAM mode overview.
6.4.3 (Service) Options
Select the sub menu's to set the initialisation codes (options) of the model number via text menus.See Table 6-8 SAM mode overview.
6.4.4 Opt. No. (Option numbers)
Select this sub menu to set all options at once (expressed in two long strings of numbers).An option number (or “option byte”) represents a number of different options. When you change these numbers directly,you can set all options very quickly. All options are controlled via eight option numbers.When the NVM is replaced, all options will require resetting. To be certain that the factory settings are reproduced exactly, you must set both option number lines. You can find the correct option numbers on a sticker inside the TV set and in Table 6-7 Option and display code overview.Example: The options sticker gives the following option numbers:• 08192 00133 01387 45160• 12232 04256 00164 00000
Value Cool (9420K) Normal (8120K) Warm (6080K)
x 0.282 0.292 0.320
y 0.298 0.311 0.345
Value Cool (11000K) Normal (9000K) Warm (6500K)
x 0.276 0.287 0.313
y 0.282 0.296 0.329
White Tone Black level offset
Colour Temp R G B R G
Normal 127 100 66 t.b.d. t.b.d.
Cool 127 113 118 t.b.d. t.b.d.
Warm 109 102 127 t.b.d. t.b.d.
White Tone Black level offset
Colour Temp R G B R G
Normal t.b.d. t.b.d. t.b.d. t.b.d. t.b.d.
Cool t.b.d. t.b.d. t.b.d. t.b.d. t.b.d.
Warm t.b.d. t.b.d. t.b.d. t.b.d. t.b.d.
Screen size TCON Alignment
42" 443
46" 143
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The first line (group 1) indicates hardware options 1 to 4, the second line (group 2) indicate software options 5 to 8.Every 5-digit number represents 16 bits (so the maximum value will be 65536 if all options are set).When all the correct options are set, the sum of the decimal values of each Option Byte (OB) will give the option number.See Table 6-7 Option and display code overview for the options.
DiversityNot all sets with the same Commercial Type Number (CTN) necessarily have the same option code!Use of Alternative BOM => an alternative BOM number usually indicates the use of an alternative display or power supply. This results in another display code thus in another Option code. Refer to Chapter 2. Technical Specifications, Diversity, and Connections.
6.4.5 Option Code Overview
Table 6-7 Option and display code overview
Important: after having edited the option numbers as described above, you must press OK on the remote control before the cursor is moved to the left!
6.5 Reset of Repaired SSB
A very important issue towards a repaired SSB from a Service repair shop (SSB repair on component level) implies the reset of the NVM on the SSB.A repaired SSB in Service should get the Service Set type “00PF0000000000” and Production code “00000000000000”.Also the virgin bit is to be set. To set all this, you can use the ComPair tool.
After a repaired SSB has been mounted in the set (set repair on board level), the type number (CTN) and production code of the TV has to be set according to the type plate of the set. For this (new in this platform), you can use the NVM editor in SAM. This action also ensures the correct functioning of the “Net TV” feature and access to the Net TV portals. The loading of the CTN and production code can also be done via ComPair (Model number programming).
In case of a display replacement, reset the “Operation hours display” to “0”, or to the operation hours of the replacement display.
6.5.1 SSB identification
Whenever ordering a new SSB, it should be noted that the correct ordering number (12nc) of a SSB is located on a sticker on the SSB. The format is <12nc SSB><serial number>. The ordering number of a “Service” SSB is the same as the ordering number of an initial “factory” SSB.
Figure 6-1 SSB identification
6.6 Service SSB delivered without main software loaded
Due to a changed manufacturing process, new Service SSB’s can be delivered to the warehouse without main TV software loaded. Below you find the steps to follow when such an SSB is received.
6.6.1 When a picture is available
1. Mount the Service SSB into the TV set. After start-up, normally the download application will appear on the screen.
2. Download the latest main software (FUS) from the www.p4c.philips.com website.
3. Create a folder “upgrades” in the root of a USB stick (size > 50 MB) and save the “autorun.upg” file in this “upgrades” folder. Note: it is possible to rename this file, e.g. “Q555_SW_version.upg”, this in case there are more than one “autorun.upg” files on your USB stick.
4. Plug the prepared USB stick into the TV set, and select the “autorun” file in the displayed browser on the screen
5. Now the main TV software will be loaded automatically, supported by a progress bar.
6. Set the correct “display code” via “062598-HOME-xxx”, where “xxx” is the 3-digit display panel code (see sticker on the side/bottom of the cabinet).
6.6.2 When no picture is available
Due to a possible wrong display option code in the received Service SSB (NVM), no picture can be available at start-up and thus no download application will be visible. Here you can proceed and finalize step by step to load the main TV software via the UART logging on the PC (for visual feedback). 1. Start-up the TV set, equipped with the Service SSB, and
enable the UART logging on the PC (see for settings 5.8 Fault Finding and Repair Tips 5.8.6 Logging).
2. The TV set will start-up automatically in the download application if main TV software is not loaded.
3. Plug the prepared USB stick into the TV set, press cursor “Right” to enter the list, and navigate to the “autorun” file in the UART logging printout via the cursor keys on the remote control. When the correct file is selected, press “OK”.
4. Press cursor “Down” and “OK” to start the flashing of the main TV software. Printouts like: “L: 1-100%, V: 1-100% and P: 1-100%” should be visible now in the UART logging.
5. Wait until the message “Operation successful!” is displayed and remove all inserted media. Restart the TV set
CTN(Alt. BOM#)
Options Group 1 Options Group 2 Disp.code
42PFL8605D/93 02060 12803 23359 40647 33552 34310 00000 00000 272
42PFL8605/98 02060 12803 23359 39363 00016 34304 00000 00000 272
46PFL8605D/93 02060 13059 23359 40647 33551 34310 00000 00000 271
18310_221_090318.eps090319
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6. Set the correct “display code” via “062598-HOME-xxx”, where “xxx” is the 3-digit display panel code (see sticker on the side/bottom of the cabinet).
6.6.3 Use of repaired SSBs instead of new
Repaired SSBs on stock will obviously already contain main TV software. This implies that only a main software upgrade is required if you use a “repaired” SSB for board swap instead of a “new” SSB.
6.7 Total Overview SAM modes
Table 6-8 SAM mode overview
Main Menu Sub-menu 1 Sub-menu 2 Sub-menu 3 Description
Hardware Info A. SW version e.g. “Q5521_0.33.0.0 Display TV & Standby SW version and CTN serialnumberB. Standby processor version e.g. “STDBY_42.42.0.0”
C. Production code e.g. “see type plate”
Operation hours Displays the accumulated total of operation hours.TVswitched “on/off” & every 0.5 hours is increase one
Errors Displayed the most recent errors
Reset error buffer Clears all content in the error buffer
Alignment White point Colour temperature Normal 3 different modes of colour temperature can be se-lectedWarn
Cool
White point red LCD White Point Alignment. For values, see Table 6-4 White tone default setting 42" 1 until 6-5 White tone default setting 46"
White point green
White point blue
Ambilight Select module
Brightness
Select matrix
TCON alignment used when a new display code (after a SSB exchange) is keyed-in and if you have alignment values from production; see Table 6-6 TCON default settings
Reset TCON alignment used when a new display code (after a SSB exchange) is keyed-in and if you do not have alignment values from production
Dealer options Virgin mode Off/On Select Virgin mode On/Off. TV starts up / does not start up (once) with a language selection menu after the mains switch is turned “on” for the first time (virgin mode)
E-sticker Off/On Select E-sticker On/Off (USP’s on-screen)
Auto store mode None
PDC/VPS
TXT page
PDC/VPS/TXT
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Options Digital broadcast DVB Off/On Select DVB On/Off
DVB - T installation Off/On or Country dependent Select DVB T installation On/Off or by country
DVB - T light Off/On Select DVB T light On/Off
DVB - C Off/On Select DVB C On/Off
DVB - C installation Off/On or Country dependent Select DVB C installation On/Off or by country
DVB - C light Off/On Select DVB C light On/Off
DVB - S Off/On Select DVB S On/Off
Over the air download Off/On or Country dependent Select Over the air download On/Off or by country
8 days EPG Off/On Select 8 day EPG On/Off
Digital features Ethernet Off/On Select Ethernet On/Off
Wi-Fi Off/On Select Wi-Fi On/Off
DLNA Off/On Select DLNA On/Off
On-line service On On-line service is On
Videostore SD card slot Off/On Select Videostore SD card slot On/Off
Multiview Off/On Select Multiview On/Off
Internet software update Off Internet software update is Off
Display Screen 237 / LCD Sharp D3GA23 46" Displayed the panel code & type model
LightGuide Off/On Select LightGuide On/Off
Display fans Not present/Present Select Display fans Present/Not present
Temperature sensor No sensor/On backside/In display/On SSB
Sensor present Yes/No and in case Yes, where
Temperature LUT 0 N.A.
E-box & monitor Off/On Select E-box & monitor On/Off
Video reproduction Light sensor Off/On Select Light sensor On/Off
Light sensor type 0/1/2/3 Select Light sensor type form 0 to 3 (for differencestyling)
Super resolution Off/On Super resolution Off/On
Smart bit enhancement Off/On Smart bit enhancement Off/On
Pixel Plus type Pixel Plus HD Select type of picture improvement
Perfect Pixel HD
Pixel Precise HD
Natural motion type Perfect Natural Motion Natural motion type selection
HD Natural Motion
Ambilight None Select type of Ambilight modules use
2 sided 3/3
2 sided 4/4
2 sided 5/5
2 sided 6/6
2 sided 7/7
3 sided 5/5/5
3 sided 6/6/6
3 sided 7/7/7
3 sided 6/9/6
Ambilight sunset Off/On Ambilight sunset On/Off
Audio reproduction Acoustic system Cabinet design used for setting dynamic audio pa-rameters
Source selection EXT1/AV1 type SCART CVBS RGB LR Select input source when connected with externalequipment
CVBS Y/C YPbPr LR
CVBS Y/C YPbPr HV LR
EXT2/AV2 type SCART CVBS RGB LR Select input source when connected with externalequipmentCVBS LR
YPbPr LR
None
EXT3/AV3 type None Select input source when connected with externalequipmentCVBS
CVBS LR
CVBS Y/C LR
YPbPr
YPbPr LR
YPbPr HV LR
SIDE I/O Off/On Select SIDE I/O On/Off
S-VIDEO (Y/C) Off/On Select S-VIDEO (Y/C) On/Off
HDMI 2 Off/On Select HDMI 2 On/Off
HDMI 3 Off/On Select HDMI 3 On/Off
HDMI side Off/On Select HDMI side On/Off
HDMI CEC Viewport 21:9 Off/On Select HDMI CEC Viewport 21:9 On/Off
HDMI CEC OneUX seamless Off/On Select HDMI CEC OneUX seamless On/Off
Miscellaneous Region Europe Select Region/country
AP-PAL-Multi
China
Australia
Latam
Russia
Tuner type Select type of Tuner used
Hotel mode Off Hotel mode is Off
Main Menu Sub-menu 1 Sub-menu 2 Sub-menu 3 Description
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Option numbers Group 1 e.g. “00008.01793.15421.08192” The first line (group 1) indicates hardware options 1to 4
Group 2 e.g. “44013.34315.00000.00000” The second line (group 2) indicates software options5 to 8
Store Store after changing
Initialise NVM N.A.
Store Select Store in the SAM root menu after making any changes
Operation hours display 0003 In case the display must be swapped for repair, youcan reset the “”Display operation hours” to “0”. So,this one does keeps up the lifetime of the display it-self (mainly to compensate the degeneration behav-iour)
Software maintenance Software events Display Display information is for development purposes
Clear
Test reboot
Test cold reboot
Test application crash
Hardware events Display Display information is for development purposes
Clear
Test setting Digital info Centre frequency: 774605208
QAM modulation: None Display information is for development purposes
Symbol rate:
Original network ID: 0
Network ID: 0
Transport stream ID: 0
Service ID: 0
Hierarchical modulation: 0
Selected video PID: 0
Selected main audio PID: 0
Selected 2nd audio PID: 0
Install start frequency 000 Install start frequency from “0” MHz
Install end frequency 999 Install end frequency as “999” MHz
Default install frequency
Installation Digital only Select Digital only or Digital + Analogue before instal-lationDigital + Analogue
Development file ver-sions
Development 1 file version Display parameters DISPT6.0.9.8 Display information is for development purposes
Acoustics parameters ACSTS0.39.6.16
PQ - TV550 1.0.22.1
PQS- Profile set
PQF - Fixed settings
PQU - User styles
Ambilight parameters PRFAM 5.0.2.4
Development 2 file version 12NC one zip software Display information is for development purposes
Initial main software
NVM version Q55x1_0.3.1.0
Flash units software
Temp com file version none
Upload to USB All To upload several settings from the TV to an USB stickChannel list
Personal settings
Option codes
Alignments
Identification data
History list
Download from USB All To download several settings from the USB stick to the TVChannel list
Personal settings
Option codes
Alignments
Identification data
NVM editor Type number see type plate NVM editor; re key-in type number and production code after SSB replacementAG code see type plate
Main Menu Sub-menu 1 Sub-menu 2 Sub-menu 3 Description
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7. Circuit Descriptions
Index of this chapter:7.1 Introduction7.2 Power Architecture7.3 DC/DC Converters7.4 Front-End Analogue and DVB-T, DVB-C; ISDB-T reception7.5 HDMI7.6 Video and Audio Processing - PNX855007.7 Back-End7.8 Ambilight7.9 TCON
Notes:• Only new circuits (circuits that are not published recently)
are described.• Figures can deviate slightly from the actual situation, due
to different set executions.• For a good understanding of the following circuit
descriptions, please use the wiring, block (see chapter 9. Block Diagrams) and circuit diagrams (see chapter 10. Circuit Diagrams and PWB Layouts). Where necessary, you will find a separate drawing for clarification.
7.1 Introduction
The Q552.1A LA chassis is part of the TV550 platform and comes with the following stylings: “Da Vinci” (series xxPFL6xxx) and “Matisse” (series xxPFL8xx). The TV550 platform is the successor of the TV543 platform.
7.1.1 Implementation
Key components of this chassis are:• PNX85500 System-On-Chip (SOC) TV Processor• TX31XX Hybrid Tuner (DVB-T/C, analogue)• SII9x87 HDMI Switch• TPA312xD2PWP Class D Power Amplifier• LAN8710 Dual Port Gigabit Ethernet media access
controller.
7.1.2 TV550 Architecture Overview
For details about the chassis block diagrams refer to chapter 9. Block Diagrams. An overview of the TV550 architecture can be found in Figure 7-1.
Figure 7-1 Architecture of TV550 platform - TCON integrated in display (xxPFL8xxx)
18770_244_100203.eps100219
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2010-Apr-02back to div. table
Figure 7-2 Architecture of TV550 platform - TCON integrated on SSB (xxPFL6xxx)
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Circuit DescriptionsEN 38 Q552.1A LA7.
2010-Apr-02 back to div. table
7.1.3 SSB Cell Layout
Figure 7-3 SSB layout cells (top view) TCON integrated in display (xxPFL8xxx)
Figure 7-4 SSB layout cells (top view) TCON integrated on SSB (xxPFL6xxx)
18990_200_100401.eps100401
Class-D
1M99
1M95
CA
LOW
PR
OFI
LEFLASH
Pr Pb YD
DR
Tuner
9187
OU
T0
3
RL
HDMI 1.3 HDMI 1.3 HDMI 1.3
RJ45
18990_201_100401.eps100401
DVB-STCON
Tuner
HDMI 1.3 VGAHDMI 1.3HDMI 1.3
Circuit Descriptions EN 39Q552.1A LA 7.
2010-Apr-02back to div. table
7.2 Power Architecture
Refer to figure Figure 7-5 for the power architecture of this platform.
Figure 7-5 Power Architecture TV550 platform
7.2.1 Power Supply Unit
All power supplies are a black box for Service. When defective, a new board must be ordered and the defective one must be returned, unless the main fuse of the board is broken. Always replace a defective fuse with one with the correct specifications! This part is available in the regular market.Consult the Philips Service web portal for the order codes of the boards.
Important delta’s with the TV543 platform are:• New power architecture for LED backlight (PSL, PSLS,
PSDL)• “Boost”-signal is now a PWM-signal + continuous variable.
The control signals are:• Standby• Lamp “on/off”• DIM (PWM) (not for PSDL)• Boost (PWM except for IPB)• Power-OK: indicates that the main converter is functioning
(feedback signal to the SSB).
In this manual, no detailed information is available because of design protection issues.
The output voltages to the chassis are:• +3V3-STANDBY (standby-mode only)• +12V (on-mode)• +Vsnd (+24V) (audio power) (on-mode)• +24V (bolt-on power) (on-mode)
• Output to the display; in case of - IPB: High voltage to the LCD panel- PSL and PSLS (LED-driver outputs)- PSDL (high frequent) AC-current.
7.2.2 Diversity
The diversity in power supply units is mainly determined by the diversity in displays. Table 7-1 Supply diversity lists the different types of displays with its associated PSUs:
Table 7-1 Supply diversity
The following displays can be distinguished:• CCFL/EEFL backlight: power board is conventional IPB• LED backlight:
- side-view LED without scanning: PSL power board- side-view LED with scanning: PSLS power board- direct-view LED without 2D-dimming: PSL power board- direct-view LED with 2D-dimming: PSDL power board.
• PSL stands for Power Supply with integrated LED-drivers.• PSLS stands for a Power Supply with integrated LED-
drivers with added Scanning functionality (added microcontroller).
18770_234_100127.eps100127
CTN Supplier PSU
42PFL8605D/93 LGIT PLDF-P975A
42PFL8605/98 LGIT PLDJ-P977A
46PFL8605D/93 LGIT PLDF-P975A
Circuit DescriptionsEN 40 Q552.1A LA7.
2010-Apr-02 back to div. table
• PSDL stands for a Power Supply for Direct-view LED backlight with 2D-dimming.
7.2.3 Connector overview
Table 7-2 Connector overview
7.3 DC/DC Converters
The on-board DC/DC converters deliver the following voltages (depending on set execution):• +3V3-STANDBY, permanent voltage for the standby
controller, LED/IR receiver and controls; connector 1M95 pin 1
• +12V, input from the power supply for TV550 common (active mode); connector 1M95 pins 6, 7 and 8
• +24V, input from the power supply for DVB-S2 (in active mode); connector 1M09 pins 1 and 2
• +1V1, core voltage supply for PNX85500; has to be started up first and switched “off” last (diagram B03B)
• +1V2, supply voltage for analogue blocks inside PNX85500
• +1V8, supply voltage for DDR2 (diagram B03B)• +2V5, supply voltage for analogue blocks inside
PNX85500 (see diagram B03E)• +3V3, general supply voltage (diagram B03E)• +5V, supply voltage for USB and CAM (diagram B03E)• +5V-TUN, supply voltage for tuner (diagram B03E)• +V-LNB, input voltage for LNB supply IC (item no. 7T50)• +5V-DVBS, input intermediate supply voltage for DVB-S2
(diagram B08A)• +3V3-DVBS, clean voltage for silicon tuner and DVB-S2
channel decoder• +2V5-DVBS, clean voltage for DVB-S2 channel decoder• +1V-DVBS, core voltage for DVB-S2 channel decoder.
A +12 V under-voltage detector (see diagram B03C) enables the 12V to 3.3V and 12V to 5V DC/DC converters via the ENABLE-3V3-5V line, and the 12V to 1.8V DC/DC converter via the ENABLE-1V8 line. DETECT2 is the signal going to the standby microcontroller and ENABLE-3V3n is the signal coming from the standby microcontroller.
Diagram B03D contains the following linear stabilisers:• +2V5 stabiliser, built around item no. 7UCO• +5V-TUN stabiliser, built around items no. 7UA6 and 7UA7• +1V2 stabiliser, built around items no. 7UA3 and 7UA4.
Diagram B08A contains the DVB-S2-related DC/DC converters and -stabilisers:• a +24V under-voltage detection circuitry is built around
item no. 7T04
• the switching frequency of the 24 to 14...20V switched mode converter is 350 kHz (item no. 7T03 and +V-LNB lines)
• the output signal on the +V-LNB line goes to the LNBH23Q (item no. 7T50)
• the LNBH23Q (item no. 7T50) sends a feedback signal via the V0-CNTRL line
• the switching frequency of the +5V-DVBS to +1-DVBS switched mode converter is 900 kHz (item no. 7T00)
• a delay line for the +2V5-DVBS and +1V-DVBS lines is created with item no. 3T03 (R=10k) and 2T06 (C=100n)
• a 3.3V to 2.5V linear stabiliser is built around item no. 7T01• a 5V to 3.3V linear stabiliser is built around item no. 7T02.
7.4 Front-End Analogue and DVB-T, DVB-C; ISDB-T reception
7.4.1 European/China region
The Front-End for the European/China region consist of the following key components:
• Hybrid Tuner• Switchable SAW filter 7/8 MHz (Eur.), or single SAW filter
(8 MHz) (China)• Bandpass filter • Amplifier• PNX85500 SoC TV processor with integrated DVB-T and
DVB-C channel decoder and analogue demodulator.
Below find a block diagram of the front-end application for this region.
Figure 7-6 Front-End block diagram European/China region
7.4.2 Brazil region
The Front-End for the Brazil region consist of the following key components:
• Hybrid Tuner with integrated SAW filter and amplifier• External ISDB-T channel decoder covering the Brazilian
digital terrestrial TV standard• Bandpass filter• Amplifier• PNX85500 SoC TV with integrated analogue demodulator.
Below find a block diagram of the front-end application for this region.
Connector
no. 1308 1311 1319 1316 1M95 1M99 1M09 1MP1
Descr. mains mains disp. disp. to SSB to SSB Amb. T-con
Pin CN1 CN2 CN3 CN4 CN5 CN6 CN7 CN8
1 N L’ t.b.d. t.b.d. 3V3std +12V 24Vb +12V
2 L L” t.b.d. t.b.d. Stndby +12V 24Vb +12V
3 - - - - GND1 GND1 GND1 n.c.
4 - - - - GND1 GND1 GND1 GND1
5 - - - - GND1 BL_ON_OFF
- GND1
6 - - - - +12V DIM - -
7 - - - - +12V Boost - -
8 - - - - +12V n.c. - -
9 - - - - +Vsnd POK - -
10 - - - - GND_SND
- - -
11 - - - - n.c. - - -
12 - - - - - - - -
18770_235_100127.eps100219
Circuit Descriptions EN 41Q552.1A LA 7.
2010-Apr-02back to div. table
Figure 7-7 Front-End block diagram Brazil region
7.5 HDMI
In this platform, the Silicon Image Sil9x87 HDMI multiplexer is implemented. Refer to figure 7-8 HDMI input configuration for the application.
New in this platform is the implementation of the Audio Return Channel (ARC) (pin 14 on HDMI 1). The ARC in HDMI1.4 enables a TV, via a single HDMI cable, to send audio data “upstream” to an A/V receiver or surround audio controller, increasing user flexibility and eliminating the need for any separate SPDIF audio connection.
Figure 7-8 HDMI input configuration
The following multiplexers can be used:• Sil9187A (does not support “Instaport” technology for fast
switching between input signals)• Sil9287B (supports “Instaport” technology for fast
switching between input signals).The hardware default I2C addresses are:• Sil9187A: 0xB0/0xB2 (random: software workaround)• Sil9287B: 0xB2 (fixed).
The Sil9x87 has the following specifications:• +5V detection mechanism• Stable clock detection mechanism• Integrated EDID• RT control• HPD control• Sync detection• TMDS output control• CEC control
• EDID stored in Sil9x87, therefore there are no EDID pins on the SSB.
7.6 Video and Audio Processing - PNX85500
The PNX85500 is the main audio and video processor (or System-on-Chip) for this platform. It has the following features:
• Multi-standard digital video decoder (MPEG-2, H.264, MPEG-4)
• Integrated DVB-T/DVB-C channel decoder• Integrated CI+• Integrated motion accurate picture processing (MAPP2)• High definition ME/MC• 2D LED backlight dimming option• Embedded HDMI HDCP keys• Extended colour gamut and colour booster• Integrated USB2.0 host controller• Improved MPEG artefact reduction compared with
PNX8543• Security for customers own code/settings (secure flash).
The TV550 combines front-end video processing functions, such as DVB-T channel decoding, MPEG-2/H.264 decode, analogue video decode and HDMI reception, with advanced back-end video picture improvements. It also includes next generation Motion Accurate Picture Processing (MAPP2). The MAPP2 technology provides state-of-the-art motion artifact reduction with movie judder cancellation, motion sharpness and vivid colour management. High flat panel screen resolutions and refresh rates are supported with formats including 1366 × 768 @ 100Hz/120Hz and 1920 × 1080 @ 100Hz/120Hz. The combination of Ethernet, CI+ and H.264 supports new TV experiences with IPTV and VOD. On top of that, optional support is available for 2D dimming in combination with LED backlights for optimum contrast and power savings up to 50%.
For a functional diagram of the PNX85500, refer to Figure 7-9.
18770_236_100127.eps100219
18770_243_100203.eps100203
Circuit DescriptionsEN 42 Q552.1A LA7.
2010-Apr-02 back to div. table
Figure 7-9 PNX85500 functional diagram
18770_241_100201.eps100219
TS out/in for
TS input
CVBS, Y/C,
LVDS for
analog CVBS
SPDIF
Low-IF
SSIF, LR
HDMI
CI/CAMPEG
PRIMARYLVDS
VIDEOSECONDARY
MEMORY
VIDEO 3D COMB
DIGITAL IF
AUDIO DEMOD
AUDIO IN
HDMI
SCALER,
AUDIO DSP
AUDIO DACS
AUDIO OUT
450 MHz
560 MHz
I2C PWM GPIO IR ADC UART I2C GPIO Flash
analog audio
I2S
SPDIF
SYSTEM
USB 2.0
PNX85500x
DVB-T/Cchannel decoderDVB
AV-PIP
SPI
MPEG/H.264
RECEIVER
(8051)CONTROLLER
AND DECODE
DECODER
PCMCIA
RGB
PROCESSORSYSTEM
CONTROLLER
DECODERVIDEO
24KEf CPUMIPS32
x 8
AV-DSP
REDUCTIONAND NOISE
DE-INTERLACE
OUTPUTVIDEO
SUB-PICTURE
ENCODER
OUTPUTVIDEO
quad channel)(single, dual orflat panel display
DRAWINGENGINE
DMA BLOCK
Motion-accuratepixel processing
SDMemory
Card
EthernetMAC
Circuit Descriptions EN 43Q552.1A LA 7.
2010-Apr-02back to div. table
7.7 Back-End
The following backlight types can be distinguished:• CCFL/EEFL backlight; applicable to the xxPFL54xx sets• LED backlight:
- side-view (edge) LED without scanning: PSL power board; applicable to xxPFL76xx sets- side-view (edge) LED with scanning: PSLS power board; not applicable to this chassis- direct-view LED with 0D-dimming: PSL power board; applicable to xxPFL56xx sets- direct-view LED with 2D-dimming: PSDL power board; not applicable to this chassis.
Refer to section 7.2.2 Diversity for an in-depth explanation of the different power boards that are used.
Figure 7-10 Backlight (xxPFL54xx, xxPFL56xx, xxPFL76xx sets) application
7.8 Ambilight
In this chassis, only 2-sided Ambilight is implemented. Refer to figure 7-11 Ambilight architecture.
Figure 7-11 Ambilight architecture
For an overview of the LED grouping per board, refer to figure 7-12 LED grouping per board.
18770_242_100203.eps100203
18770_209a_100202.eps100202
1M59
1M09
MTKor
PNX85500
SSB
Gluelogic
1M83
1M84
AmbiLight1M83
1M84
AmbiLight
1M09
PSU
Circuit DescriptionsEN 44 Q552.1A LA7.
2010-Apr-02 back to div. table
Figure 7-12 LED grouping per board
The communication between PNX85500, Complex Programmable Logic Device (CPLD) and the Ambilight module uses the SPI protocol; refer to figure 7-13 Communication protocol outside LED board. Between the CPLD and the LED driver, as “extra” line is mentioned:• Non-SPI signals that are required for the LED driver• Temperature sensor line.
Figure 7-13 Communication protocol outside LED board
Refer to figure for an overview of the communication inside the LED board.
Figure 7-14 Communication protocol inside LED board
The buffer is built around item no. 7B20 (diagram AL1A) and regenerates the clock signals. Refer to figure 7-15 Ambilight buffer.
Figure 7-15 Ambilight buffer
The temperature sensor is built around item no. 7B30 (diagram AL1A) and indicates overtemperature of the board. Refer to figure 7-16 Temperature sensor.
Figure 7-16 Temperature sensor
The EEPROM (item no. 7B07; diagram AL1A) contains alignment information about the mounted LEDs and is programmed during the alignment process in production. Refer to figure 7-17 EEPROM.
Figure 7-17 EEPROM
The LED driver is built around item no. 7B26 (diagram AL1A) and controls the LEDs. Refer to figure 7-18 LED driver.
18770_210_100126.eps100126
3×6LED
18
4×6LED
24
5×6LED
30
4+5LED
9
2×6LED
12
3×5LED
15
6×6LED
36
18770_211_100126.eps100126
CPLDPNXSPI SPI + extra
1M
59
18770_213_100126.eps100219
LEDDriver
EEPRO M
BufferSPI SPI
SPI
SPI
SPI
1M
83
1M
84
Extra
Tem psensor
Temp
18770_214_100126.eps100126
+3V3
83B30-1
220R
1
4 5
220R
3B30-43B01-1
100R
1 8
5
6
7B20-174LVC2G17
1
2
2B17
100n
33p
2B01
100R
3B01-22 7
100p
2B02
+3V3
3
25
4
74LVC2G177B20-2
33p
2B00
2B10
100p
PWM-CLOCK
SPI-CLOCK-BUF
PWM-CLOCK-BUF
SPI-CLOCK
18770_215_100126.eps100126
-T
+3V3
10n
2B09
FB40
2B08
10n
1K5
1%
36
3B39
-22
7
3B39
-31%1K
5
1
3
4
52
LMV331IDCK
7B30
+3V3
1K5
1%
81
3B39
-1
3B34
RES100K
10K30
04 RE
S
3B11 10
K
+3V3
FB41
TEMP-SENSOR
18770_216_100126.eps100126
S
GND
Q
HOLDW
VCC
C
D
+3V3
41
2
35
7B0674LVC1G32GW
2B20
100n
4
7
2
1
8
3+3V3
M95010-WDW67B07
(64K)Φ
6
5
+3V3
10K
3B02-2
271 83B02-1
10K
+3V3
SPI-CLOCK-BUF
SPI-DATA-IN-BUF
SPI-DATA-RETURN
SPI-CS
DATA-SWITCH
Circuit Descriptions EN 45Q552.1A LA 7.
2010-Apr-02back to div. table
Figure 7-18 LED driver
The Overvoltage Protection Circuit is built around item no. 7B50, 7B51, 7C20 and 7C22 (diagram AL1B). Refer to figure 7-19 Overvoltage Protection Circuit.
Figure 7-19 Overvoltage Protection Circuit
7.9 TCON
This section describes the application with the TCON integrated on the SSB.
For the basic application, refer to figure 7-20 TCON architecture.
18770_217_100126.eps100126
OUT
1211
GSCLKIREFMODESCLKSINSOUT
XERRXHALFXLAT 10
NC
98
VCC
01234567
BLANK
131415
GND GND_HS
VIA
VIA
VIA
VIA
2K0
3B31
FB20
3B21 150R
+3V3
+3V3
2532
FB35
910111415
1223
27
22
5
161718192021
678
31
30 33
24263
12132829
4
TLC5946RHB7B26-1
100n
2B11
3 6150R3B00-3
2B04
-4
100p
45
36
37 38 39
404142
7B26-2TLC5946RHB
3435
3B18
1K8
1 8150R
3B00-1
+3V3
18
2B04
-1
100p
150R
3B00-44 5
150R
3B00-22 72B
04-2
100p
27
36
2B04
-3
100p
10K3B22
BLANK
SPI-DATA-IN-BUF
PWM-G1PWM-R1
PWM-G3PWM-R3PWM-R2
PWM-B2PWM-G2
DATA-SWITCH
PWM-G4PWM-R4PWM-B4
PWM-R5PWM-G5PWM-B5
LATCH
SPI-DATA-INSPI-DATA-OUT
PWM-CLOCK-BUF
SPI-CLOCK-BUFPROG
PWM-B1
PWM-B3
18770_218_100126.eps100126
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
FB32
65
21
43
99-235/RSBB7C-A24/2D7005
18
10K
3B07
-1
FB30
3B07
-3
10K
36
45
FB31
10K
3B13
-4
1
43
700299-235/RSBB7C-A24/2D
65
2
65
21
43
6
700499-235/RSBB7C-A24/2D
3B03-3
1K5
3
27
3B07
-2
10K
+24V
100n
2B03
2 7
1K5
3B03-2
3B36
270R
+24V
2
6
1
BC847BS(COL)7B23-1
3B35
270R
3B37
68R5
3
4
BC847BS(COL)7B23-2
7B25BC847BW
1
3
2
36
3B13
-3
10K
65
21
43
700199-235/RSBB7C-A24/2D
4 5
1K5
3B03-4
45
10K
3B07
-4
7003
65
21
43
99-235/RSBB7C-A24/2D
1 83B03-1
1K5
+24V
43
99-235/RSBB7C-A24/2D7000
65
21
+24V
PWM-R1
PWM-G1
PWM-B1
Circuit DescriptionsEN 46 Q552.1A LA7.
2010-Apr-02 back to div. table
Figure 7-20 TCON architecture
For the TCON block diagram, refer to figure 7-21 TCON block diagram.
Figure 7-21 TCON block diagram
18770_238_100127.eps100402
EEPROM
TFT – LCD Panel
Mini - LVDS
Control Signals
+3.3 V+1.8 V
VGH (+28 V)VGL (-6 V)
+12 V
LVDS (10 bit)Timing
Controller
Power Block
GammaReference Voltage
Source Drive IC
Gat
e D
rive
IC
PN
X85
50
LCD Panel
TCO NM ain Platform
SSB
+16 V
(TCON)
18770_239_100127.eps100127
LVD S R eceiver
LVD S R eceiver
Vertica l & H orizonta l Tim ing generation
D ata Path B lock (L ine
Buffer)
M ini-LVDSTransmitter
M ini-LVDSTransmitter
O PC
(Op
tim
um
Po
wer
Co
ntr
ol)
(Ove
rD
rive
Cir
cuit
)
(Dyn
amic
Co
ntr
ast
Co
ntr
ol)
O D C D C A
Fo
rma
tte
r/S
eri
aliz
er
Spread Spectrum
SD R AM
I2C S lave
I2C M aster
R O M
EEPR O M
16 bit
H sync/Vsync
DE SS C LK (Spread Spectrum C lock)
RLV P /N
Right h alf data
Gate D riverC trl S ign als
Source D riverC trl S ign als
R 1A ~E
R 1C LK
R 2C LK
R 2A ~E
M ini-LVDS
Output
LVDSInput
ControlSignalOutput
T im ing C ontro ller IC
Circuit Descriptions EN 47Q552.1A LA 7.
2010-Apr-02back to div. table
Notes to figure 7-21 TCON block diagram:• LVDS receiver: converts the data stream back into RGB
data and SYNC signals (Vsync, Hsync, Data Enable - DE)• ODC: Over Drive Circuit - to improve LC response• Data Path Block: the video RGB data input to data path
block is delayed to align the column driver start pulse with the column driver data
• Timing Control Function: generates control signals to column drivers and row drivers (Source Enable - SOE, Gate Enable - GOE, Gate Start Pulse - GSP).
For an overview of the TCON DC/DC converters, refer to figure 7-22 TCON DC/DC converters.
Figure 7-22 TCON DC/DC converters
7.9.1 TCON Programming
For LGD - TCONs, the EEPROM can be programmed via ComPair (via I2C communication).For Sharp - TCONs, the data can be flashed with a “SPI Programmer” (via SPI communication). This device has to be ordered separately via Philips.
7.9.2 TCON Alignment
The purpose of TCON alignment is to obtain equal voltages for both positive and negative LC polarity. This is to avoid “flicker” and “image sticking”. For alignment, see 6.3.3 TCON Alignment.
18770_240_100128.eps100128
D C /D CC ontro ller+12V
LG D SHP W here Used
VG H +28V +35V To G ate D rivers (G ateH igh Voltage)
VG L -6V -6V To G ate D rivers (G ate Low Voltage)
Vcc +3V3 +3V3 Tim ing C ontro ller IC Supply Voltage
Vcc +1V8 +1V2 Tim ing C ontro ller IC Supply Voltage
Vref +16V +15V2 G am m a R eference Voltage
Vdd +16V +15V6 Source D river Supply Voltage
IC Data SheetsEN 48 Q552.1A LA8.
2010-Apr-02 back to div. table
8. IC Data Sheets
This chapter shows the internal block diagrams and pin configurations of ICs that are drawn as “black boxes” in the
electrical diagrams (with the exception of “memory” and “logic” ICs).
8.1 Diagram USB Hub B01C, USB2513B (IC 7F25)
Figure 8-1 Internal block diagram and pin configuration
18770_301_100217.eps100217
Block diagram
Pinning informationNote : The LED port indicators only apply to USB2513i.
To UpstreamVBUS
3.3 V
Upstream PHY
Upstream USB Data
Repeater ControllerSerial
Interface Engine
SerialInterface
To EEPROM or SMBus Master
SCLSDA
Port Controller
Bus-PowerDetect/
Vbus Pulse
PHY#1
USB DataDownstream
OC SenseSwitch/
LEDDrivers
USB DataDownstream
Port Power
3.3 V
PLL
24 MHz Crystal
Routing & Port Re-Ordering Logic
Regulator
CRFILT
Port Power
Regulator
PHY#xPort #xOC Sense
Switch Driver/ LED Drivers
TT#x
TT#1
...Port #1OC Sense
Switch Driver/ LED Drivers
OC SenseSwitch/
LEDDrivers
...
The ‘x’ indicates the number of available downstream ports: 2, 3, 4, or 7.
Ground Pad(must be connected to VSS)
SMSCUSB2512/12A/12B
USB2512i/12Ai/12Bi(Top View QFN-36)
26
VD
D33
25
RE
SE
T_N
24
HS
_IN
D /
CFG
_SE
L[1]
23
SC
L / S
MB
CLK
/ C
FG_S
EL[0
]
22S
DA
/ S
MB
DA
TA /
NO
N_R
EM
[1]
21N
C
20N
C
19
VBU
S_D
ET
27
NC
18 NC
17 OCS_N[2]
16 PRTPWR[2] / BC_EN[2]*
15
OCS_N[1]
14
VDD33
13
CRFILT
12 PRTPWR[1] / BC_EN[1]*
11 TEST
10 VDD33
SUSP_IND / LOCAL_PWR / NON_REM[0] 28
VDD33 29
USBDP_UP 31
XTALOUT 32
XTALIN / CLKIN 33
RBIAS
36VDD33
35
PLLFILT 34
USBDM_UP 30
VD
D33
1U
SBD
M_D
N[1
]
2U
SBD
P_D
N[1
]
3U
SBD
M_D
N[2
]
4U
SBD
P_D
N[2
]
5
NC
6
NC
7
NC
8
NC
9
Indicates pins on the bottom of the device.
IC Data Sheets EN 49Q552.1A LA 8.
2010-Apr-02back to div. table
8.2 Diagram Temp Sensor + Headphone B01J, LM75BDP (IC 7FD1)
Figure 8-2 Pin configuration
18770_300_100217.eps100217
Block diagram
Pinning information
LM75B
SDA
VCC
SCLA0
OS
DNG1AA2
BIASREFERENCE
BAND GAPTEMP SENSOR
OSCILLATOR
POWER-ONRESET
11-BITSIGMA-DELTA
A-to-DCONVERTER
POINTERREGISTER
TIMER
COMPARATOR/INTERRUPT
COUNTER
LOGIC CONTROL AND INTERFACE
CONFIGURATIONREGISTER
THYSTREGISTER
TOSREGISTER
TEMPERATUREREGISTER
LM75BDP
VADS CC
0ALCS
1ASO
2ADNG
1
2
3
4
6
5
8
7
IC Data SheetsEN 50 Q552.1A LA8.
2010-Apr-02 back to div. table
8.3 Diagram PNX NandFlash - Conditional Access B02A, PNX85500 (IC7S00)
Figure 8-3 Internal block diagram and pin configuration
18770_308_100217.eps100217
Block diagram
Pinning information
TS out/in for
TS input
CVBS, Y/C,
LVDS for
analog CVBS
SPDIF
Low-IF
SSIF, LR
HDMI
CI/CAMPEG
PRIMARYLVDS
VIDEOSECONDARY
MEMORY
VIDEO3D COMB
DIGITAL IF
AUDIO DEMOD
AUDIO IN
HDMI
SCALER,
AUDIO DSP
AUDIO DACS
AUDIO OUT
450 MHz
500 MHz
I2C PWM Px_x IR ADC UART I2C GPIO Flash
analog audio
I2S
SPDIF
SYSTEM
USB 2.0
PNX8550x
DVB-T/Cchannel decoderDVB
AV-PIP
SPI
RECEIVER
(8051)CONTROLLER
AND DECODE
DECODER
PCMCIA
RGB
PROCESSORSYSTEM
CONTROLLER
MULTI-STANDARD
VIDEODECODER
24KEf CPUMIPS32
x 10
AV-DSP
REDUCTIONAND NOISE
DE-INTERLACE
OUTPUTVIDEO
SUB-PICTURE
ENCODER
OUTPUTVIDEO
quad channel)(single, dual orflat panel display
DRAWINGENGINE
Scatter/GatherTS Demux
Motion-accuratepixel processing
SDMemory
Card
EthernetMAC
analog Y/C
Direct-IF
PNX8550xE
Transparent top view
2 4 6 8 10 1213
1415 17
1619
18 2021 23
22 2425
261 3 5 7 9 11
ball A1index area
AB
AD
AA
AC
YW
VU
R
N
T
P
ML
KJ
H
F
D
G
E
CB
A
AFAE
IC Data Sheets EN 51Q552.1A LA 8.
2010-Apr-02back to div. table
8.4 Diagram Audio B03A, TPA3120D2PWP (IC7D10)
Figure 8-4 Internal block diagram and pin configuration
I_18020_142.eps100402
Block diagram
Pinning information
123
456789
101112
242322
212019181716
151413
PVCCLSD
PVCCLMUTE
LINRIN
BYPASSAGNDAGND
PVCCRVCLAMP
PVCCR
PGNDLPGNDLLOUTBSLAVCCAVCCGAIN0GAIN1BSRROUTPGNDRPGNDR
PWP (TSSOP) PACKAGE(TOP VIEW)
1 F
SD
PVCCL
TPA3120D2
PVCCR
VCLAMP
GAIN1
BYPASS
1 F
1 F
0.22 F
AGND
} Control
ShutdownControl
LIN
RIN
BSR
BSL
PGNDR
PGNDL
0.22 F
22 H
22 H
0.68 F
470 F
0.68 F
1 F
470 F
GAIN0
AVCC
MUTE
ROUT
LOUT
IC Data SheetsEN 52 Q552.1A LA8.
2010-Apr-02 back to div. table
8.5 Diagram DC/DC B03B, TPS53126PW (IC7U03)
Figure 8-5 Internal block diagram and pin configuration
18250_300_090319.eps100402
Block diagram
Pinning informationVBST1
NC
EN1
VO1
VFB1
NC
GND
TEST1
NC
VFB2
VO2
EN2
NC
VBST2
DRVH1
LL1
DRVL1
PGND1
TRIP1
VIN
VREG5
V5FILT
TEST2
TRIP2
PGND2
DRVL2
LL2
DRVH2
28
27
26
25
24
23
22
21
20
19
18
17
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TP
S5
31
24
15
IC Data Sheets EN 53Q552.1A LA 8.
2010-Apr-02back to div. table
8.6 Diagram DC/DC B03E, ST1S10PH (IC 7UD0)
Figure 8-6 Internal block diagram and pin configuration
I_18010_083.eps100402
Block diagram
Pinning information
PowerSO-8DFN8 (4 × 4)
IC Data SheetsEN 54 Q552.1A LA8.
2010-Apr-02 back to div. table
8.7 Diagram DC/DC B03E, LD1117DT25 (IC 7UD2)
Figure 8-7 Internal block diagram and pin configuration
F_15710_166.eps100402
Block diagram
Pinning information
DPAK
LD1117DT
IC Data Sheets EN 55Q552.1A LA 8.
2010-Apr-02back to div. table
8.8 Diagram Ethernet + Service B04C, LAN8710A-EZKH (IC 7E10)
Figure 8-8 Internal block diagram and pin configuration
18770_302_100217.eps100217
Block diagram
Pinning information
10M Rx Logic
100M Rx Logic
DSP System:Clock
Data RecoveryEqualizer
Analog-to-Digital
100M PLL
Squelch & Filters
10M PLL
Receive Section
Central Bias
HP Auto-MDIX
Management ControlSMI
RM
II / MII Logic
TXP / TXN
TXD[0:3]TXENTXER
TXCLK
RXD[0:3]RXDVRXER
RXCLK
CRSCOL/CRS_DV
MDCMDIO
LED1LED2LED Circuitry
MODE Control
nINT
nRST RXP / RXN
10M Tx Logic
10M Transmitter
100M Tx Logic
100M Transmitter
Transmit Section
PLLXTAL1/CLKIN
XTAL2
MODE0MODE1MODE2
PHYAddress Latches
PHYAD[0:2]
Auto-Negotiation
InterruptGenerator
RMIISELMDIX
Control
Reset Control
RBIAS
VDD2A
LED2/nINTSEL
LED1/REGOFF
XTAL2
XTAL1/CLKIN
VDDCR
RXD3/PHYAD2
RXCLK/PHYAD1
RXD
2/R
MIIS
EL
RXD
1/M
OD
E1
RXD
0/M
DE
0
VD
DIO
RXE
R/R
XD4/
PHYA
D0
CR
S
MD
IO
CO
L/C
RS
_DV
/MO
DE
2
TXD2
MDC
nRST
nINT/TXER/TXD4
TXD0
TXEN
TXCLK
TXD1
RBI
AS
TXD
3
TXN
RXD
V
RXN
VDD
1A
TXP
RXP
1
2
3
4
5
6
7
8
SMSCLAN8710/LAN8710i
32 PIN QFN(Top View)
9 10 11 12 13 14 15
22
21
20
19
18
17
28 27 26 2516
24
23
32 31 30 29
VSS
IC Data SheetsEN 56 Q552.1A LA8.
2010-Apr-02 back to div. table
8.9 Diagram HDMI B04D, SII9287B (IC 7EC1)
Figure 8-9 Internal block diagram and pin configuration
18770_303_100217.eps100217
Block diagram
Pinning information
IC Data Sheets EN 57Q552.1A LA 8.
2010-Apr-02back to div. table
8.10 Diagram Headphone B04E, TPA6111A2DGN (IC 7EE1)
Figure 8-10 Internal block diagram and pin configuration
18770_309_100217.eps100217
Block diagram
Pinning information
BiasControl
8
1
7
4
VO1
VO2
VDD
5
2
3
6
IN1−
BYPASS
SHUTDOWN
VDD/2
IN2−
−+
−+
1234
8765
VO1IN1−
BYPASSGND
VDDVO2IN2−SHUTDOWN
D OR DGN PACKAGE(TOP VIEW)
IC Data SheetsEN 58 Q552.1A LA8.
2010-Apr-02 back to div. table
Personal Notes:
10000_012_090121.eps090121
Block Diagrams EN 59Q552.1A LA 9.
2010-Apr-02 back to div. table
9. Block Diagrams
9-1 Wiring diagram Matisse 42" - 46"
+
-
+
-
LOADSPEAKER LEFT(5215)
LOADSPEAKER RIGHT(5215)
+
-
+-
J2
3P
J1
8P
MA
INS
CO
RD
TO DISPLAY TO DISPLAY
3P J1
2P3
1311
2P3
1308
11P
1M95
9P
1M99
MAIN POWER SUPPLY42 PLDF-P975A B46 PLDG-P977A B (1005)
LCD DISPLAY(1004)
TCON
KE
YB
OA
RD
CO
NT
RO
L(1
114)
IR / LED BOARD (1112)
WIRING DIAGRAM 42"- 46" MATISSE
18990_400_100330.eps100330
1M99 (B03C)1. +12VD2. +12VD3. GND4. GND5. LAMP-ON6. BACKLIGHT-PWM_BL-VS7. BACKLIGHT-BOOST8. BACKLIGHT-PWM-ANA-DISP9. POWER-OK
1M95 (B03C)1. +3V3-STANDBY2. STANDBY3. GND4. GND5. GND6. +12V7. +12V8. +12V9. +24V-AUDIO-POWER10. GND-AUDIO11. MAINS-OK
1735 (B03A)1. LEFT-SPEAKER2. GND-AUDIO3. GND-AUDIO4. RIGHT-SPEAKER
1M20 (B09A)1. LIGHT-SENSOR2. GND3. RC4. LED-25. +3V3-STANDBY6. LED-17. KEYBOARD8. +5V
1KA2 (B14E)1. GND| 11. VLS_15V612. VLS_15V6| 33. VCC_3V334. VCC_3V3|78. VGH_25V79. VGL_6V80. GND
1KA1 (B14E)1. GND| 11. VLS_15V612. VLS_15V6| 33. VCC_3V334. VCC_3V3|78. VGH_25V79. VGL_6V80. GND
Board Level Repair
Component Level RepairOnly For Authorized Workshop
8M59
1G51
51P
1G50
41P
1M20
8P 1M09
4P
1M59
23P
SSB(1150)B
USB
TUN
ER
SPD
IF
CO
ND
ITIO
NA
L A
CC
ESS
ETHERNET
HDMIHDMIHDMI VGA
1M09
4P
1316
12P
1319
11P
8M99
8M95
TO BACKLIGHT
HD
MI
MAINSSWITCH
(8311)
8311
8191
1735
4P
1M95
11P
1M99
9P
8M09
AM
BIL
IGH
T M
OD
UL
E 2
4 L
ED
(1174)
AL
25P
1M83
AM
BIL
IGH
T M
OD
UL
E 2
4 L
ED
(1174)
AL
1M84
25P
1M83
25P
8735
8M20
1M38 (AL1A)1. +24V2. +24V3. +24V4. +24V5. +24V6. GND7. GND8. GND9. GND10. GND11. TEMP-SENSOR12. N.C.13. N.C.
14. +3V315. BLANK16. PROG17. GND18. LATCH19. SPI-CS20. +3V321. PWM-CLOCK22. GND23. SPI-DATA-RETURN24. SPI-DATA-IN25. SPI-CLOCK
1M48 (AL2A)1. SPI-CLOCK-BUF2. SPI-DATA-OUT3. SPI-DATA-RETURN4. GND5. PWM-CLOCK-BUF6. +3V37. SPI-CS8. LATCH9. GND10. PROG11. BLANK12. +3V313. N.C.
14. N.C.15. TEMP-SENSOR16. GND17. GND18. GND19. GND20. GND21. +24V22. +24V23. +24V24. +24V25. +24V
1M59 (B13)1. AMBI-SPI-CLK-OU2. AMBI-SPI-SDO-OUT3. AMBI-SPI-SDI-OUT-GI4. GND5. AMBI-PWM-CLK_B26. V-AMBI7. AMBI-SPI-CS-OUTn_R28. AMBI-LATCH1_G29. GND10. AMBI-PROG_B111. AMBI-BLANK_R112. V-AMBI13. AMBI-LATCH2_DIS14. AMBI-SPI-CS-EXTLAMPSn
15. AMBI-TEMP16. GND17. GND18. GND19. GND20. GND21. +24V22. +24V23. +24V24. +24V25. +24V
1M09 (B09)1. +24V2. +24V3. GND4. GND
8M83
8G50
8G51
EN 60Q552.1A LA 9.Block Diagrams
2010-Apr-02 back to div. table
9-2 Block Diagram Video
B02 PNX85500 B06B VIDEO OUT - LVDS
B04A ANALOGUE EXTERNALS A
B01I VGA
B04B ANALOGUE EXTERNALS B
B01A COMMON INTERFACE
B01F HDMI & CI
B05A DDR
B01C USB HUB
B01B FLASH
B14A TCON CONTROL (SHARP) B14E MINI LVDS (SHARP)
B14D MPD
B14C P GAMMA &VOM & FLASH
B01H HDMI B04D HDMI
1E08
7S00PNX85507EB
VIDEO STREAMB02A
LVDSB02F
ANALOG VIDEOB02I
HDMI_DVB02C
AV3-YVIDEO
Pb
Y
Pr
Pb
Y
Pr
EXT 1
EXT 2
EXT 3
1
1E05
2
3
14
13
R-VGA
G-VGA
B-VGA
H-SYNC-VGA
V-SYNC-VGA
1 610
11
5
15
VGACONNECTOR
AC12
AD15
AE15
AC15
AF13
AC18
AB18
AE16
AD16
AF16
63 HDMIA-RXC-
HDMIA-RX0+
HDMIA-RX0-HDMIA-RX1+
HDMIA-RX1-
HDMIA-RX2+
HDMIA-RX2-
62
61
60
59
58
57
56
HDMIA-RXC+
U26
T25
T26
W24
U25
V26
W26
W25
V25
RX1_B_P
RX2_B_N
RX2_B_P
RREF
RX1_B_N
RX0_B_P
RXC_B_P
RXC_B_N
RX0_B_N
TXC_NTXC_P
TX0_N
TX0_P
TXA_NTX1_P
TX2_N
TX2_P
PNX85500
18990_402_100331.eps100331
VIDEO
PCMCIA
CONDITIONALACCESS
2
18
14
10
15
11
7
20+3V3
MD0
MDI
TUNER_P
TUNER_N
IF_AGC
ATV_CVBS_Y3
CR
VGA_R
VSYNC_IN
VGA_G
VGA_B
PR_R_C1
Y_G1
PB_B1
AC13AV1_R
HSYNC_IN
+3V33S0W
7F0174LVC245APW
BUFFER
1P00
68P
51
52
18
17+5VCA
1
5SVHS IN
24
3
1ECB Y-SVHS
C-SVHS
CA-MDO(0-7)MDO(0-7)
CA-MDI(0-7)
PX1
PX2
PX3
PX4
PX1
PX2
PX3
PX4
QUAD LVDS1920x1080100/120HZ1G51
+VDISP
TO DISPLAY(TCON ON DISPLAY)
I2C50
51
49
40
40
3
4
2
1
1G50
TO DISPLAY(TCON ON DISPLAY)
TO TCON SSB
TO TCON SSB
N.C.
1
2
3
3
41
AD12
AE12
AF12
MEMORYB02B
V1DDR2-VREF-CTRL3
A2DDR2-VREF-CTRL2
VREF_2VREF_1
CONROLB02E
FLASHB02A
7F20*NAND02GW3B2DN6F NAND04GW3B2DN6F
NANDFLASH
256MB512MB
43
21
USB-DM
USB-DP
USB-DM2
6000 Serie
8000 Serie
USB-DP2
USB-DM1USB-DP1
SIDE USBCONNECTOR
1P08
+5V-USB1
R26
R25
12,37+3V3VCC
USB_DP
USB_DN
+5V-USB2
XIO_D
2
1
3
4
43
21
SIDE USBCONNECTOR
1P07
2
1
3
4
9F26
9F25
9F21
9F20XIO-D(00-07)
*6000 Serie 256MB8000 Serie 512MB
TO DISPLAY(TCON ON SSB)
TO DISPLAY(TCON ON SSB)
L_LV
R_LV
1KA2
59
81
48
50
13
24
25
20
19
1KA181
50
13
58
53
2
13
1
1
7KAAUPD809900F
7KQAISL24837IRZ
TIMINGCONTROL
GMA
GMA
REFVOLTAGE
GEN
7KQBM25P32
FLASH
7KUEMAX17079GTL
LEVELSHIFTER
CS(1U-12U)CS(1-12)
+VCC
+VDD
41
42
37
36+VCC
+VDD
SPI
SDOSCS
SCK
2
13
SSB 3104 313 6364* SSB 3104 313 6400*
7EC1*SII9187ACNU SII9287BCNU
HDMISWITCH
VCC33
RXC
RXD
RXB
RXA
72
71
69
68
66
65
63
62
42
41
39
39
36
35
33
32
23
22
20
19
17
16
14
13
90
89
87
86
84
83
81
80
191
182
1
1P05
3
4
7
910
12
6
DRX2+
DRX2-
DRX1+
DRX1-
DRX0+
DRX0-
DRXC+
DRXC-HDMI SIDECONNECTOR
191
182
1
1P02
3
4
7
910
12
6
CRX2+
CRX2-
CRX1+
CRX1-
CRX0+
CRX0-
CRXC+
CRXC-HDMI 1CONNECTOR
1
1P03
3
4
7
910
12
6
BRX2+
BRX2-
BRX1+
BRX1-
BRX0+
BRX0-
BRXC+
BRXC-
1
1P04
3
4
7
910
12
6
ARX2+
ARX2-
ARX1+
ARX1-
ARX0+
ARX0-
ARXC+
ARXC-
191
182
HDMI 2CONNECTOR
191
182
HDMI 3CONNECTOR
9,27,64+3V3-HDMI
Only 8000 Serie
PNX-IF-AGC
4
5
1F75
SAW 36MHZ17
2F74
2F78
2F90 3F79-1
3F79-45F70
1T01TH2603
IF-OUT1
IF-OUT2
MAIN HYBRIDTUNER
2
3
4
7
6
PNX-IF-P
PNX-IF-N11
10 1
2
7F75UPC3221GV
AGC AMPLIFIER
IN
VCC
OUTAGC CONTROL
1
SELECT-SAW
RF IN
5F73
7F70
B02ECONTROL
BANDPASSFILTER
TUN-IF-P
TUN-IF-N
DDR2-VREF-DDR
A1 E2A1 E2A1 E2A1 E2
+1V8
SDRAM128MB
7B01EDE1108AGBG
SDRAM128MB
7B02*EDE1116AEBG EDE1108AGBG
SDRAM128MB
7B03EDE1108AGBG
DQ
A
SDRAM128MB
7B00*EDE1116AGBG EDE1108AGBG
VR
EF
VD
DL
VR
EF
VD
DL
VR
EF
VD
DL
VR
EF
VD
DL
DDR2-D(0-31)
D(2
4-31
)
D(1
6-23
)
D(8
-15)
D(0
-7)
DDR2-A(0-13)
6000 Serie 256MB 8000 Serie 512MB
1E01
1E02
AV4-PB AD14 AI23
AV4-PR AC14AI33
AV4-Y AE14AI13
AV1-R
AD13AVI-BAV1_B
AE13AV1-GAV1_G
*6000 Serie mux SIL9187 - non Instaport 8000 Serie mux SIL9287 - Instaport
Block Diagrams EN 61Q552.1A LA 9.
2010-Apr-02 back to div. table
9-3 Block Diagram Audio
B01H HDMI B04D HDMI B02D PNX85500: AUDIO
B02D CLASS-D B03A AUDIO
B04E HEADPHONE
B04B ANALOGUE EXTERNALS B
B04A ANALOGUE EXTERNALS A
B01J TEMP SENSOR + HEADPHONE
B02 PNX85500B01A COMMON INTERFACE
B01F HDMI & CI
B05A DDR
B01C USB HUB
B01B FLASH
7S00PNX85507EB
AUDIOB02D
STANDBYB03H
HDMI_DVB02c
STANDBYB02G
PNX85500
18990_403_100331.eps100331
AD7
AE7
17351
2
SPEAKER L3
4
SPEAKER R
SUBWOOFER(RES)
ADAC(1)
ADAC(2)
+AUDIO-L
-AUDIO-R
RESET-AUDIOAD1
AC19
ADAC(4)
AMP1
AMP2ADAC(3)
HEADPHONEOUT 3.5mm
AF7
AD6
7EE1TPA6111A2DGN
HEADPHONEAMPLIFIER
1
7IN-1
SHUTDOWN
IN-2
2
6
5
A-PLOP B03A
B02G
B03C
7D10TPA3123D2PWP
CLASS DPOWER
AMPLIFIER
OUT-L
PVCC_L
PVCC_R
OUT-R
512
10 6
22
15
IN-R
IN-L
MUTE
SD
4
2
AUDIO-MUTE-UP
A-STBY
A-STBY
B04A
STANDBY &PROTECTION
7D03
MAIN SWITCHDETECT
7D03
LEFT-SPEAKER
RIGHT-SPEAKER
AE10
AF10
AD10
AC10
1E08
4
6
1E01
2
6
1E02
2
6
AUDIO-IN3-L
AUDIO-IN3-R
AE9
AF9AUDIO IN
L+R
ADAC_2
PO_7
PO_6
ADAC3
ADAC4
ADAC_1
1328
2
3
1
7EE0-1 7EE0-2
1D381
2
3DETECT2
MAINS-OK
AUDIO-IN2-R
AUDIO-IN2-L
AUDIO
AUDIO-IN1-L
AUDIO-IN1-R
5D03
7EC1*SII9187ACNUSII9287BCNU
HDMISWITCH
VCC33
RXC
RXD
RXB
RXA
72
71
69
68
66
65
63
62
42
41
39
39
36
35
33
32
23
22
20
19
17
16
14
13
90
89
87
86
84
83
81
80
191
182
1
1P05
3
4
7
910
12
6
DRX2+
DRX2-
DRX1+
DRX1-
DRX0+
DRX0-
DRXC+
DRXC-HDMI SIDECONNECTOR
191
182
1
1P02
3
4
7
910
12
6
CRX2+
CRX2-
CRX1+
CRX1-
CRX0+
CRX0-
CRXC+
CRXC-HDMI 1CONNECTOR
1
1P03
3
4
7
910
12
6
BRX2+
BRX2-
BRX1+
BRX1-
BRX0+
BRX0-
BRXC+
BRXC-
1
1P04
3
4
7
910
12
6
ARX2+
ARX2-
ARX1+
ARX1-
ARX0+
ARX0-
ARXC+
ARXC-
191
182
HDMI 2CONNECTOR
191
182
HDMI 3CONNECTOR
14 ARC-eHDMI+ eHDMI+
9,27,64+3V3-HDMI
8+3V3
1,3
10,12+24V-AUDIO-POWER
5D07
5D08
VDD
VO_1
VO_2
AD9
AC9
AUDIO-IN4-L
AUDIO-IN4-RVGA (OR DVI)
AUDIO
1E09
2
3
1
AIN4_L
AIN4_R
AIN1_R
AIN2_L
AIN2_R
AIN3_L
AIN3_R
AIN1_L
VIDEO STREAMB02A
ANALOG VIDEOB02I
PCMCIA
CONDITIONALACCESS
20+3V3
MD0
MDI
TUNER_P
TUNER_N
IF_AGC
7F0174LVC245APW
BUFFER
1P00
68P
51
52
18
17+5VCA
CA-MDO(0-7)MDO(0-7)
CA-MDI(0-7)
PNX-IF-AGC
4
5
1F75
SAW 36MHZ17
2F74
2F78
2F90 3F79-1
3F79-45F70
1T01TH2603
IF-OUT1
IF-OUT2
MAIN HYBRIDTUNER
2
3
4
7
6
AD12
AE12
AF12
PNX-IF-P
PNX-IF-N11
10 1
2
+5V-TUN-PIN7F75UPC3221GV
AGC AMPLIFIER
IN
VCC
OUTAGC CONTROL
1
SELECT-SAW
RF IN
5F73
7F70
B02ECONTROL
BANDPASSFILTER
MEMORYB02B
V1DDR2-VREF-CTRL3
A2DDR2-VREF-CTRL2
VREF_2VREF_1
7S05LM324P
14
8
1E07
1AF5
AF18
DIGITALAUDIO
OUT
SPDIF-OUT-PNX
SEL-HDMI-ARC
SPDIF-OUT2
1
4
5
3
8
SPDIF_OUT
P0_4
7S09&
+3V3
A-PLOP
7D15
A-PLOPB04E
CONROLB02E
FLASHB02A
7F20*NAND02GW3B2DN6F NAND04GW3B2DN6F
NANDFLASH
256MB512MB
43
21
USB-DM
USB-DP
USB-DM2
6000 Serie
8000 Serie
USB-DP2
USB-DM1USB-DP1
SIDE USBCONNECTOR
1P08
+5V-USB1
R26
R25
12,37+3V3VCC
USB_DP
USB_DN
+5V-USB2
XIO_D
2
1
3
4
43
21
SIDE USBCONNECTOR
1P07
2
1
3
4
9F26
9F25
9F21
9F20
XIO-D(00-07)
DDR2-VREF-DDR
A1 E2A1 E2A1 E2A1 E2
+1V8
SDRAM128MB
7B01EDE1108AGBG
SDRAM128MB
7B02*EDE1116AEBGEDE1108AGBG
SDRAM128MB
7B03EDE1108AGBG
DQ
A
SDRAM128MB
7B00*EDE1116AGBGEDE1108AGBG
VR
EF
VD
DL
VR
EF
VD
DL
VR
EF
VD
DL
VR
EF
VD
DL
DDR2-D(0-31)
D(2
4-31
)
D(1
6-23
)
D(8
-15)
D(0
-7)
DDR2-A(0-13)
*6000 Serie 256MB 8000 Serie 512MB
*6000 Serie 256MB 8000 Serie 512MB
Only 8000 Serie
*6000 Serie mux SIL9187 - non Instaport 8000 Serie mux SIL9287 - Instaport
5EC2
TUN-IF-P
TUN-IF-N
63 HDMIA-RXC-
HDMIA-RX0+
HDMIA-RX0-HDMIA-RX1+
HDMIA-RX1-
HDMIA-RX2+
HDMIA-RX2-
62
61
60
59
58
57
56
HDMIA-RXC+
U26
T25
T26
W24
U25
V26
W26
W25
V25
RX1_B_P
RX2_B_N
RX2_B_P
RREF
RX1_B_N
RX0_B_P
RXC_B_P
RXC_B_N
RX0_B_N
+3V33S0W
EN 62Q552.1A LA 9.Block Diagrams
2010-Apr-02 back to div. table
9-4 Block Diagram Control & Clock Signals
B04D HDMI
B02A PNX85500 B06C AMBILIGHT
B04C ETHERNET + SERVICE
B01A COMMON INTERFACE
B09A DVBS CONNECTOR BOARD
B14F CONNECTORS
B01B FLASH
B03C DC / DC
B05A DDR
B01E PNX85500-CONTROL
B04V ETHERNET + SERVICE
B02E PNX85500: MIPS B01C USB HUB
B03C DC / DC
B02G PNX85500: STANDBY CONTROLLER
B02G PNX85500: STANDBY CONTROLLER
CONTROL + CLOCK SIGNALS
1F51
1
3
4
5
2LEVEL SHIFTED
FOR DEBUG USE
ONLY
7E10LAN8710A-EZK
ETHERNET
ETHERNETCONNECTOR
RJ45
B02A
TO AMBILIGHTMODULE
VIDEO STREAMB02A
B02E ETHERNET
CA-A(00-14)
1M99
7
6
5
1M952
LED1 AD26
AE26
AA22DETECT2
AA26
AF19
RESET-STBYn
4x HDMICONNECTOR
AB22RESET-SYSTEM
AD21 ENABLE-3V3n
PNX85500
7S00PNX85507EB
AC25LED2
1S02
54M
AF17
AE17
CONTROLB02E
CONTROLB02E
STANDBYB02G
HDMI_DVB02C
AD22AV1-BLK
AF20 STANDBY
AD19
AD23KEYBOARD
RC
LIGHT-SENSOR
AE19 TACH0AB19 RESET-AUDIO
AF1 SENSE+1V1
AE25AV1-STATUS
BACKLIGHT-OUT
BACKLIGHT-BOOST
RESET-SYSTEMnAE4 B01K B02G
B03G
AC21 POWER-OK
B03B
B07A
B01E
7S20 NCP303LSN28G
2INP
1OUTP
+3V3-STANDBY
GND
B02E
B02H POWER
7EC1*SII9187ACNU SII9287BCNU
HDMISWITCH
B04A
1P001
68
PCMCIA
CONDITIONALACCESS
UA_RX_0
UA_TX_1
P1_7
P6_4
P2_2
P2_7
P1_1
P2_6
P0_6
VDD_1V1
P2_3
XTAL_I
XTAL_O
P5_1
P5_O
P3_2P3_3
P3_5P3_4
CADC_2
CADC_3
RESET_IN
P1_2
W24 RREF
HDMI_RX
P1_0
PWM_1
PWM_0
7F027F03
7F047F05
7F01
TOPOWER SUPPLY
B04A
CO
MM
ON
INT
ER
FAC
E
TOPOWERSUPPLY
+3V3-STANDBY
+5V
B04E
B03C
SDM
SPI-PROGAF22
AB20 FF04
FF29
18990_404_100331.eps100331
RXD-UP
TXD-UP
Y23
Y24UART
SERVICECONNECTOR
AG1
AH5
RXD1-MIPS
TXD1-MIPS
LED-2
LED-1
1
2
3
4
5
6
7
8
1M20
7U43
ARX-HOTPLUG
1E06
2
3
1
AC22AV2-BLKB04A
AE24AV2-STATUS B04A
P2_0AC20LCD-PWR-ONnB03H
RESET-STBYn
AA15 SENSE+1V2B03DVDDA_1V2
AE18 RESET-ETHERNETnB04CP0_3
AF18 SEL-HDMI-ARCB02DP0_4
AE20 LAMP-ON
V23 BOOST-PWMV23 B01E
BACKLIGHT-BOOST
931
BRX-HOTPLUG
CRX-HOTPLUG 41
DRX-HOTPLUG 45
35
PCEC-HDMI CEC-HDMI
1 2
19
18
1P05-19
1P04-191P03-19
1P02-19
TO PIN:1P02-131P03-131P04-131P05-13
FLASHB02A
7F20*NAND02GW3B2DN6F NAND04GW3B2DN6F
NANDFLASH
256MB512MB
12,37+3V3VCC
MDI
*6000 Serie 256MB8000 Serie 512MB
AA2ETH-TXCLKRXCLK
AA3ETH-RXCLKTXCLK
SDCD
SDWP
DDR-CLK_N
DDR-CLK_P
3
SPI_CLK
SPI_CSBSPI_SDOSPI_SDI
P6_5
7F52M25P05-AVMN6P
FLASH
512K
8+3V3-STANDBYVCC
6PNX-SPI-CLKAF24
3PNX-SPI-WPnAE22
1PNX-SPI-CSBnAF235PNX-SPI-SDOAE23
2PNX-SPI-SDIAF25
CO
NT
RO
L
+3V3-STANDBY+12V
ENABLE -1V8
ENABLE -3V3-5V
DETECT2
XIO-D(00-07)
CA-MDI(0-7)MDO
CA-MDO(0-7)MDO(0-7)
ETH-TXD
ETH-RXD
XIO_A
XIO_D
XIO-A(0-14)
CA-D(0-7)
MEMORYB02B
F8 E8F8 E8F8 E8F8 E8
SDRAM128MB
7B01EDE1108AGBG
SDRAM128MB
7B02*EDE1116AEBG EDE1108AGBG
SDRAM128MB
7B03EDE1108AGBG
DQ
A
CLK_NCLK_P
GPI0_2
RESET_SYSPNX-SPI-CS-AMBInW23 B06E B06DGPI0_6
PNX-SPI-CS-BLnV22 B01K B02GB13
B02GGPI0_7
GPI0_3
SDRAM128MB
7B00*EDE1116AGBG EDE1108AGBG
DDR2-D(0-31)
D(2
4-31
)
D(1
6-23
)
D(8
-15)
D(0
-7)
DDR2-A(0-13)
GPI0_11SELECT-SAWU23
B01F
B06C
GPI0_11BACKLIGHT-PWMU23
B13CLK_54_OUT
PXCLK54AC5B06C B13
PXCLK54B02E
B02G
+3V33S0W
TO IR / LED BOARD ANDKEYBOARD CONTROL
9U41
9CH0
B03E
B03B B03D
B02G B03AEF
7EC0
7
20
XIO-D(00-15)
43
21
USB-DM
USB-DP
USB-DM2
*6000 Serie 8000 Serie
USB-DP2
USB-DM1USB-DP1
SIDE USBCONNECTOR
1P08
+5V-USB1
R26
R25USB_DP
USB_DN
+5V-USB2
2
1
3
4
1M59
2
1
3
5
8
7
10
11
14
13
15
43
21
SIDE USBCONNECTOR
1P07
2
1
3
4
9F26
9F25
9F21
9F20
7GA0XC9572XL
CPLD
26VIO
VCCIO
41
43
40PNX-SPI-SDI
39PNX-SPI-SDO
3PNX-SPI-CS-BLnV22
2PNX-SPI-CS-AMBInW23
PNX-SPI-CLK
AMBI-SPI-CLK-OUT22
AMBI-SPI-SDO-OUT27
AMBI-SPI-SDI-OUT_G123AMBI-PWM-CLK_B229
AMBI-SPI-CS-OUTn_R230
AMBI-LATCH1_G231
AMBI-PROG_B119AMBI-BLANK_R120
AMBI-LATCH2_DIS28
AMBI-SPI-CS-EXTLAMPSn21AMBI-TEMP32
HDMIB-RC
*6000 Serie mux SIL9187 - non Instaport 8000 Serie mux SIL9287 - Instaport
6000 Serie
8000 Serie
Block Diagrams EN 63Q552.1A LA 9.
2010-Apr-02 back to div. table
9-5 Block Diagram I2CI²C
PNX85500: MIPSB02E
DDRB05A
FLASHB01B
ETHERNET + SERVICEB04C
PNX85500: CONTROLB01E PNX85500-CONTROLB01E
PNX85500: STANDBYCONTROLER
B02G
HDMIB04D
HDMIB01H
TEMP SENSOR + HEADPHONE
B01JTUNER BRAZILB01K
HDMI & CIB01F
PNX85500: ANALOG VIDEOB02I
ETHERNET + SERVICEB04C
P GAMMA & VCOM & FLASH (SHARP)B14C TCON CONTROL(SHARP)
B14A
VGAB01I
VIDEO OUT - LVDSB06B
NON DVBS CONNECTOR BOARDB09A CONNECTORS (SHARP)B14F
1F52
7S00PNX85507EB
PNX85500
SDA-SSB
SCL-SSB
C25
C26
1_SDA
1_SCL
AC23
AC24
MC_SDA
MC_SCL
B25
A24
3_SDA
3_SCL
SDA-UP-MIPS
SCL-UP-MIPS
CONTROL
STANDBY
3KT
U
3KT
V
VCC_3V3
7
8
SDA-TCON
SCL-TCON
1
3DEBUGONLY
18990_405_100331.eps100331
RES
3F63
3F62
5 6
7F58M24C64
EEPROM(NVM)
3F63
3F59
TUN-P7
TUN-P6
SDA-TUNER
SCL-TUNER
7 6
1T01TH2603
MAINTUNER
3S60
3S61
3F75
3F76
53 54
7EC1 SII9287B*SII9187A
HDMIMUX
3EC
5
3EC
3
HDMICONNECTOR 3
HDMICONNECTOR 2
1P04
16
15
29
30
1P03
16
15
33
34
1P02
16
15
39
40
HDMICONNECTOR
SIDE
1P05
16
15
3FB
F-2
3FB
F-1
DIN-5V
43
44
47
48
Y25
Y26
Y23
Y24
GPIO_2
GPIO_3
DDCA-SDA
DDCA-SCL
ARX-DDC-SDA
ARX-DDC-SCL
BRX-DDC-SDA
BRX-DDC-SCL
CRX-DDC-SDA
CRX-DDC-SCL
DRX-DDC-SDA
DRX-DDC-SCL
1 2
7FD1LM75BDP
TEMPSENSOR
3FD
3
3FD
4
46 45
7FE0TC90517FG
TUNERBRAZIL
3FE
9
3FE
8
3S56
3S57
3S2F
3S2G
3S5Y
3S5Z
3S6D
3S6E
+3V3
3S69
3S6A
+3V3
3S6V
3S6W
+3V3-STANDBY
3S81
3S80
+3V3
3S83
3S84
+3V3
3S6F
3S6G
+3V3
AD25
AD24
1E05
12
15
VGA-SDA-EDID-HDMI
VGA-SCL-EDID-HDMI
VGA-SDA-EDID
VGA-SCL-EDID
3FC
1
3FC
2
+5V-VGA
9FC2
9FC4
9FC1
9FC3
RES
3S5V-1
3S5V-3
9S15
9S14
VGA-SDA-EDID-TCON
VGA-SCL-EDID-TCON
3EC
1-1
3EC
1-3
AIN-5V
3EC
A-1
3EC
A-2
BIN-5V
3EC
A-3
3EC
A-4
CIN-5V
3EC
P-3
3EC
P-1
+5V-EDID
3EC
U-2
3EC
U-4
+3V3
1KQB
2
1
9JB
6
9JB
7 12 13
7KQAISL24837IRZ
8-CHANNELPROG I2C
REF VOLT GEN
E19 E20
7KAAUPD809900F1
CONTROL
7KQBM25P32
2 1
7KQHPCA9540B
2 CHANNELMULTIPLEXER
B24
Y5
Y6
AB4
AC1
AA3
11
10
9
8
7
A23
4_SDA
4_SCL
AE21
AF21
P3_0
P3_1
1 610
11
5
15
VGACONNECTOR
RXD1-MIPS
TXD1-MIPS
W21
W22
GPIO_2
GPIO_3
RXD2-MIPS
TXD2-MIPS
UARTSERVICE
CONNECTOR
1E06
3
2
1
3E53-3
3E53-1
3E53-4
3E53-2
1F51
2
1
B02E
B02G
MEMORY
B02B
FLASH
B02A
ANALOGUEVIDEO
VGA_EDID_SDA
VGA_EDID_SCL
B02I
B02I
ERR35
ERR15
ERR53
1M71
1
3TO
TEMPERATURESENSOR
4
52D
DIMMING
1F53
2
3
SDA-BL
SCL-BL
LVDSCONNECTOR
1G51
50
49
SDA-DISP
SCL-DISP
RES
3C83
3C81
3S67
3S65
3S68
3S66
+3V3
B26
A25
2_SDA
2_SCL
SDA-SET
SCL-SET
3S58
3S5W
3S6B
3S6C
+3V3
3S1G
3S1H
+3V3-STANDBY
RES
7
8
9S13
9S10
3C84
3C85
1M71
3
1TO
TEMPERATURESENSOR
2DDIMMING
1F53
2
3
RES
3K83
3K81
3K84
3K85
3G2W
3G2Y
uPLEVEL SHIFTED
FOR DEBUGUSE ONLY
RXD-UP
TXD-UP
3F65
3F64
2 1
7S01PCA9540B
2 CHAN.MULTIPLEX.
ERR24
ERR34
RES
SD
A-D
ISP
SC
L-D
ISP
ERR23
ERR42
RES
9S12
9S11
7E10LAN8710A-EZK
ETH-RXD(0)
ETH-RXD(3)
ETH-RXCLK
ETH-RXD(1)
ETH-RXD(2)
AA1
AA4
AB1
AB2
AA2
22
23
24
25
20
ETH-TXD(0)
ETH-TXD(3)
ETH-TXCLK
ETH-TXD(1)
ETH-TXD(2)
*6000 Serie 256MB 8000 Serie 512MB
RXD_0RXD_1
RXD_2RXD_3
RXCLK
TXD_0TXD_1
TXD_2TXD_3
TXCLK
XIO_D
DQ
A
ETHERNET
DDC_A_SDA
DDC_A_SCL
HDMI_DV
HDMICONNECTOR 1
ETHERNETCONNECTOR
RJ45
RES RES
Only for SHARP display with TCON on SSB
Only for SHARP display with TCON on SSB Only for SHARP display with TCON on SSB
SDRAM
7B01EDE1108AGBG
SDRAM
7B02*EDE1116AEBG EDE1108AGBG
FLASH(4Gx16)
SDRAM
7B03EDE1108AGBG
SDRAM
7B00*EDE1116AEBG EDE1108AGBG
DDR2-D(0-31)
XIO-D(00-07)
D(2
4-31
)
D(1
6-23
)
D(8
-15)
D(0
-7)
DDR2-A(0-13)
191
182
191
182
191
182
191
182
SPI_CLK
SPI_CSBSPI_SDOSPI_SDI
P6_5
7F52M25P05-AVMN6P
FLASH
512K
8+3V3-STANDBY VCC
6 PNX-SPI-CLK AF24
3 PNX-SPI-WPn AE22
1 PNX-SPI-CSBn AF235 PNX-SPI-SDO AE23
2 PNX-SPI-SDI AF25
7F20*NAND02GW3B2DN6F NAND04GW3B2DN6F
*6000 Serie 256MB8000 Serie 512MB
ERR13
ERR18
ERR14
ERR64
STANDBYSW
MAINSW
MAIN NVMSW
EDIDSW
TCONSW
FLASH
Programmable via USBSW
SW
SW
Programmable via ComPair
Pre-programmed device
EN 64Q552.1A LA 9.Block Diagrams
2010-Apr-02 back to div. table
9-6 Supply Lines Overview
B01A COMMON INTERFACE
B01D SD-CARD
B01F HDMI & CI
B01K TUNER BRAZIL
B01C USB HUB
B02B PNX85500: SDRAM
B01B FLASH
B02A PNX85500: NANDFLASH CONDITIONAL ACCESS
B02C PNX85500: DIGITAL VIDEO IN
B02E PNX85500: MIPS
B02G PNX85500: STANDBY CONTROLLER
B02H PNX85500: POWER
B01H HDMI
B01I VGA
B01J TEMP SENSOR + HEADPHONE
B01E PNX85500: CONTROL
B01G TOSHIBA SUPPLY
B03D DC / DC
B03E DC / DC
B09A (*NON) DVBS CONNECTOR BOARD
B03G FAN - CONTROL
B04A ANALOGUE EXTERNALS A
B04C ETHERNET + SERVICE
B03F TEMPSENSOR + AMBILIGHT
B06A DISPLAY INTERFACING-VDISP
B02D PNX85500: AUDIO
B03A AUDIO
B03B DC / DC
SUPPLY LINES OVERVIEW
PSU
B03C DC / DC
B03H VDISP - SWITCH
B04D HDMI
B04E HEADPHONE
B06B VIDEO OUT - LVDS
B06D SPI-BUFFER
B05A DDRB14D MPD
B14E MINI LVDS
B06C .
B14F CONNECTORS
B14B TCON DC / DC (SHARP)
B14C P GAMMA & VCOM & FLASH (SHARP)
B13 AMBILIGHT CPLD
B14A TCON CONTROL (SHARP)
+5V+5V
+5VCA3F01
+T
B03e
+3V3+3V3B03e
B03e
B03e
+3V3-SD3F40
+T
+3V3+3V3
+5V-TUN-PIN
+5V-TUN+5V-TUN
B03e
+5V+5V
+5V-USB23F32
+T
+5V-USB13F25
+T
B03e
+3V3+3V3B03e
+1V8+1V8
DDR2-VREF-CTRL2
DDR2-VREF-CTRL3
B03c
+3V3+3V3
+3V3+3V3
+5V+5V
B03e
+3V3+3V3B03e
B03e
B01g
B03e
B03b
+3V3+3V3B03e
B03b,d,e,g,B08b,B09a,B11d,B14f
B01e,B02e,g,h,B03a,b,h,B04d,e,B09a,B11d,B14f
B03h
B02d,B03a
+3V3+3V3B03e
+3V3-STANDBY+3V3-STANDBYB03c
+1V1+1V1B03b
+3V3-STANDBY+3V3-STANDBYB03c
+1V1+1V1B03b
+1V2+1V2B03d
+1V8+1V8B03b
+2V5+2V5B03d
+2V5-AUDIO+2V5-AUDIOB02d
+2V5-LVDS+2V5-LVDSB03d
+3V3+3V3B03e
+3V3-STANDBY+3V3-STANDBYB03c
DIN-5V
+3V3+3V3
+1V2-BRA-VDDC+1V2-BRA-VDDC
+1V2-BRA-DR1+1V2-BRA-DR1
+3V3+3V3B03e
+3V3-STANDBY+3V3-STANDBYB03c
+5V+5VB03e
B03d
B03e
B03e
9F71
+3V3-BRA
+3V3+3V3
+1V2-BRA-VDDC
+3V3+3V3
7FA3
IN OUTCOM
+1V2-BRA-DR15FA4
5FE7
5FA3
+3V3
+5V+5V
+2V5-LVDS
+2V5
B03e
+2V5-AUDIO
+3V3-ARC
+3V3+3V3
7S08
IN OUTCOM
+2V5-BRA
+3V3-BRA-FLT
+5V+5V
7FE3
IN OUTCOM
5FE9
5FE4
3S20
3S06
+24V-AUDIO-POWER+24V-AUDIO-POWER
+24V-AUDIO-VDD3S0Z
3S11
B03c
B03c+3V3-STANDBY+3V3-STANDBY
+24V-AUDIO-POWER+24V-AUDIO-POWER
+AVCC3D09
7U03TPS53126PW
+12V
+1V812
14
+1V15U01
23
24
+12V
12V/1V1COVERSION
12V/1V8COVERSION
5U02
5U00
B03c
+3V3-STANDBY+3V3-STANDBYB03c
DualSynchronousStep-DownController
7U04
7U01
7U02-2
7U02-1
1
1M95
1 1
6 67 7
8 8
1M95+3V3-STANDBY
Optional 1M99 is 12 pin connector
3V3_ST
+12V
1M99
1 1
6 67 7
2 2
3 3
4 4
8 8
5 5 LAMP-ON
1M99
BACKLIGHT-BOOST
+12VD
BACKLIGHT-PWM_BL-VS
+12V
9 9 +24V-AUDIO-POWER
10 10
+12V+12V
+VSND
GND_SND
BACKLIGHT-PWM-ANA-DISP
BL-SPI-CSn
9 9
10 10 BL-SPI-SDO
11 11
12 12 BL-SPI-CLK
POWER-OK
2 23 3
4 4
5 5
STANDBYSTANDBY
GND1
GND1
GND1
11 11N.C.
+12V
BL_ON_OFF
DIM
POK
N.C
N.C.
N.C.
+12V
BOOST
GND1
GND1
N.C.
1U40
T 3.0A
MAINS-OK
CUA0
+1V2
+1V8+1V8
+12V
7UA3B03b
+3V3-ET-ANA
+3V3+3V3B03e
B03e
B03e
+2V5-REF
+12V+12VB03c
B03b
B03c
B03e
B03c
B03e
B03e
3U16
3UA0
7UC0
IN OUTCOM
3U15
7UA0VOLT.REG.
+5V-TUN
+5V5-TUN+5V5-TUN
7UA6
ENABLE-1V8
+3V3
+12V+12V
+1V1+1V1
+12V+12V
+3V3+3V3
+5V+5V
+3V3+3V3
5UD3 5UD2
+5V
+3V3
+5V5-TUN5UD0 5UD1
6UD0
+2V57UD2
IN OUTCOM
7UD0
IN OUTCOM
7UD1
IN OUTCOM
7UD3
IN OUTCOM
B03e
B02h
+3V3+3V3
V-AMBI1UM0
T 1.0A
5UM1
B03h+VDISP-INT+VDISP-INT
1G00
T 3.0A
+VDISP1G03
T 3.0A
1C86*1T86
T 2.0A
5G02
5E08
+VDISP-INT
+12VD+12VD
+3V3+3V3
7UU2LCD-PWR-ONn
7UU1
B03c
B03e+3V3-STANDBY+3V3-STANDBY
B03c
1P0318HDMI 2
CONNECTORBIN-5V
1P0218HDMI 1
CONNECTOR
+5V-EDID
+3V3-STANDBY+3V3-STANDBY
+3V3+3V3
+3V3-HDMI
CIN-5V
1P0418HDMI 3
CONNECTORAIN-5V
5EC0B03e
B03c
+5V-VGA+5V-VGA
+5V +5V
B01I
B03eB02b,h,B03d,B05a
DIN-5VDIN-5VB01h
B03e
B03c
6EC
1
+3V3-STANDBY+3V3-STANDBY
+3V3+3V3
B03e
B06a+VDISP+VDISP
+3V3+3V3
B03e+3V3+3V3
DDR2-VREF-DDR
+1V8+1V8B03b
B02h
B02h
B01f
3B20
VIO
+3V3+3V3B03e
5G01
5GA1
VINT5GA0
ONLY FOR 5000 SERIES
NOT FOR 5000 SERIES
B06a,B11b,B14b
OR
B03d
B02h
B06b
B03e
B03c
B03e
B03c+3V3-STANDBY+3V3-STANDBY
+5V+5V
+12V+12V
+3V3+3V3
1M20
8
5
1M5921
TOIR/LEDPANEL1M09
1
2
+24V
VLS_15V6VLS_15V6
VCC_3V3VCC_3V3
VREF_15V2VREF_15V2
+VDISP+VDISP
VLS_15V6VLS_15V6
VGL_-6VVGL_-6V
VGH_35VVGH_35V
VCC_3V3VCC_3V3
B03c
B03e
B03c
B03e
B14b
B14b
B14b
B14b
B14b
B14b
B14c
B14b
+3V3-STANDBY+3V3-STANDBY
+5V+5V
+12V+12V
+3V3+3V3
1M20
8
5 TOIR/LEDPANEL
B01,a,c,e,k,B03c,d,B04a,d,B09a,B11d,B14f
B11a
B08a
1P05
B02g,h,B03e,B08a
18HDMI SIDECONNECTOR
B04d
B01k
B01k
+5V-VGA1E05
9VGACONNECTOR
B04d
B01g
18990_406_100331.eps100331
B02G
B02G
B06CB01E
B02G
B02G
B03A
B01,a,b,c,d,e,g,j,jk,B14fB02a,c,d,e,h,B03c,f,g,h,B04a,c,d,e,B06b,c,d,B08a,B09a,B11d,B13
1HA0
T 1.5A
1KFA
T 3.0A
VCC_3V3
VGH_35V
VLS_15V6
VLS_15V6_B
7KFAISL97653AIRZ
ICLCD
SUPPLY
+VDISP
+VDISP-INT+VDISP-INT
VCC_1V2VCC_1V2
VIO
+3V3+3V3B03e
+24V
5HA1
VINT5HA0
VDDQ
VCC_+3V3VCC_3V3
B14b
5KAF
VDD335KAE
VCC_1V2
SSCG_AGND
+VDISP+VDISP
1M721
2
7KAC
VIN SWGND
5KAG
5KAD
LVDS_AVDD
mini_AVDD5KAC
5KAB
VDD125KAA
7KFE
9KFC
9KFE
VGL_-6V
7KQAISL248371RZ
ICLCD
SUPPLY
VREF_15V2
VLS_15V6VLS_15V6
VCC_3V3VCC_3V3
+VDISP+VDISP
B14b
B03h
B14a
B14b
B14b
B14b
3KFP
B14d
B14a,c,d
B14a,c,d,e
B14c,d,e
B14e
B14b
B14e
Circuit Diagrams and PWB Layouts EN 65Q552.1A LA 10.
2010-Apr-02 back to div. table
10. Circuit Diagrams and PWB Layouts
10-1 AL1 820400089786 AmbiLight CommonLiteOn LED Common 1
18770_600_100212.eps100218
LiteOn 15 LED CommonAL1A AL1A
8204 000 8978AL 2K10 LiteOn
15 LED Common
2009-12-046
2009-10-285
2009-10-074
2009-08-273
2009-07-032
BLUE
GREEN
RED
-T
S
GND
Q
HOLDW
VCC
C
D
VIA
VIA
VIA
VIA
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
OUT
1211
GSCLKIREFMODESCLKSINSOUT
XERRXHALFXLAT 10
NC
98
VCC
01234567
BLANK
131415
GND GND_HS
BLUE
GREEN
RED
BLUE
GREEN
RED
2
G
1 2 3
1
4 5 6 7
3 4
F
A
H
I
B
C
9 10 11 12 13 14
E
5 6 7 9 10 11 12 13 14
D
E
F
8
H
I
A
B
C
D
8
G
3456789
2627
171819
2
202122232425
1
10111213141516
FH12-25S-0.5SH(55)
1M83
FB12
FB15
RE
S
3004
10K
FB06
+3V3
10K
3B11
+24V
3B00-2
150R
2 7
100p
2B04
-22
7
2B04
-33
6
43
+3V3
100p
LTW-008RGB
65
21
+24V
7000
3B2210K
FB41
+3V3
2B00
33p
1K5
3B03-11 8
+3V3
18
100p
2B04
-1
3B02-2
10K 27
3B39
-18
1
10K
3B02-11 8
1%1K
5
FB03
2B10
FB13
100p
100n
2B17
4142
TLC5946RHB7B26-2
343536
37 38 39
40
2
1
8
3
7B07M95010-WDW6
6
5
4
7
3B34
Φ(64K)
1
3
2
100K RES
4 5
BC847BW7B25
3B00-4
150R
1K8
3B18
10K
3B13
-33
6
33p
+3V3
2 7
2B01
3B01-2
100R
2B02
100p
5
21
43
+3V3
+24V
LTW-008RGB7001
6
+3V3
3B03-4
1K5
4 5
FB16
FB05
FB07
FB04
3B07
-4
10K
45
65
21
43
7003LTW-008RGB
2B11
100n
100R
3B01-11 8
7B20-274LVC2G17
3
25
4
1 83B00-1
150R
73B03-2
1K5
2
270R
3B36
3B39
-33
6
1K5
1%
27
1%1K
5
25
6
+24V
3B39
-2
74LVC2G177B20-1
1
7B23-1BC847BS(COL)
2
6
1
LMV331IDCK
1
3
4
52
7B30
270R
3B35
68R
3B377B23-2BC847BS(COL)
5
3
4
3 63B00-3 150R
100p
2B04
-44
5
+3V3
45
+3V3
FB08
3B13
-4
10K
3
+3V3
FB31
LTW-008RGB7002
65
21
4
FB35
15
1223
27
222532
192021
6789
101114
263
12132829
45
161718
7B26-1TLC5946RHB
31
30 33
24
FB11
21
43
FB10
LTW-008RGB7004
65
1K5
3B03-33 6
27
FB01
4 5
10K
3B07
-2
3B30-4
220R
+24V
2B03
100n
2B09
10n
3B31
2K0
10n
2B08
+3V3
5
4
74LVC1G32GW7B06
1
2
3
FB40
18
100n
2B20
3B07
-1
10K
FB20
3B21
FB30
1 8
150R
220R
3B30-1
+3V3
36
10K
3B07
-3
FB32
+3V3
5
21
43
+3V3
7005LTW-008RGB
6
TEMP-SENSOR
BLANKPROG
SPI-CS
PWM-CLOCK
SPI-DATA-RETURNSPI-DATA-INSPI-CLOCK
LATCH
PWM-CLOCK
BLANK
SPI-DATA-IN-BUF
PWM-R1
PWM-G1PWM-R1
PWM-G3PWM-R3PWM-R2
PWM-B2PWM-G2
DATA-SWITCH
TEMP-SENSOR
PWM-G4PWM-R4PWM-B4
PWM-R5PWM-G5PWM-B5
SPI-CLOCK-BUF
SPI-DATA-IN-BUF
SPI-DATA-RETURN
SPI-CS
DATA-SWITCH
LATCH
SPI-DATA-INSPI-DATA-OUT
PWM-CLOCK-BUF
SPI-CLOCK-BUFPROG
SPI-CLOCK-BUF
PWM-CLOCK-BUF
SPI-CLOCK
PWM-G1
PWM-B1
PWM-B1
PWM-B3
2B00 E82B01 F82B02 E92B03 I142B04-1 B72B04-2 B62B04-3 B8
1M83 C1
3B00-4 B63B01-1 E7
3B13-4 I33B18 A83B21 B73B22 B8
3B00-3 B6
7B23-1 F47B23-2 G47B25 H37B26-1 A87B26-2 C9
3B01-2 D73B02-1 E3
3B13-3 H3
3B30-1 D93B30-4 E9
2B04-4 B72B08 E122B09 E12
2B11 A92B17 D82B20 D43004 E123B00-1 A63B00-2 B6
7002 G8
FB16 C1FB20 B7FB30 G3FB31 H3FB32 I3FB35 A8FB40 D12
7003 G107004 G11
7B30 D13FB01 A1
3B02-2 E53B03-1 H143B03-2 H14
3B03-4 H143B07-1 F33B07-2 G33B07-3 H33B07-4 G33B11 E12
FB06 B2FB07 B1FB08 B1FB10 B2FB11 B1FB12 B2FB13 C1
7B20-1 D87B20-2 E8
FB15 C1
3B31 B103B34 D133B35 G14
2B10 F9
3B37 G143B39-1 E133B39-2 D123B39-3 D137000 G57001 G7
3B36 G14
FB41 E13
FB03 B1FB04 B1FB05 B1
3B03-3 H14
7005 G137B06 D37B07 D4
B007B001 B002
EN 66Q552.1A LA 10.Circuit Diagrams and PWB Layouts
2010-Apr-02 back to div. table
LiteOn LED Common 2
18770_601_100212.eps100212
LiteOn 15 LED Common 2AL1B AL1B
2009-12-046
2009-10-285
2009-10-074
2009-08-273
2009-07-032
8204 000 8978AL 2K10 LiteOn
15 LED Common
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
3B55-2 B33B55-3 A33B55-4 A3
7C20-2 F3
8
1 2 3
3B57-2 D33B57-3 C3
FC03 H39 10 11 12
A
B
C
7104 B67105 B5F
G
3B50 B7
D
E
7200 F8
3B53-4 C73B55-1 C3
11 12
FC02 G3
3C12 F4
C
4
3C15-1 G43C15-2 G43C15-3 G43C15-4 G47100 B117101 B107102 B97103 B7
3C10 F4
7C20-1 E3
9 10
7201 F97202 F10
3C00-2 F33C00-3 F3
7B51 C3
FB71 C3FB72 D3FC01 F3
3C11 F4D
E
3B53-2 C73B53-3 C7
H
2B50 C11
G
H
3C00-4 E3
7C22 G3FB70 B3
3 4
3B51 B7
7
3B52 B73B53-1 B7
5
3C00-1 G3
7 8
7B50-1 A37B50-2 B3
A
B
21
F
3C06-1 G33C06-2 H3
5 6
65
21
43
6
LTW-008RGB7201
10K
3B55
-33
6
100n
2B50
5
3
4
FC01
1 2
7C20-2BC847BS(COL)
1 2
270R
3C10
8
3C11
270R
10K
3B55
-11
68R
3B52
65
21
43
7104LTW-008RGB
3 6
4 5
3C15-3
1K5
3C15-4
1K5
3C12
68R
BC847BW7C22
1
3
2
36
+24V
+24V
3B57
-3
10K
4 +24V
FB70
BC847BS(COL)7B50-2
5
310
K
3B55
-44
52
7
3
3B57
-2
10K
LTW-008RGB7105
65
21
4
FB71
65
21
433
LTW-008RGB7100
65
21
4
1
43
7101LTW-008RGB
7200LTW-008RGB
65
2
10K
3C06
-11
8
+24V
27
FC03
1
4310
K
3B55
-265
2
65
21
43
7103LTW-008RGB
8
LTW-008RGB7202
3C15-1
1K5
1
3C15-2
1K5
2 7
FB72
6
1
+24V
+24V
BC847BS(COL)7C20-1
2
5
21
43
LTW-008RGB7102
6
7B50-1BC847BS(COL)
2
6
1
1
3
2
7B51BC847BW
3B51
270R
4 5
270R
3B50
3 6
1K5
3B53-4
7
1K5
3B53-3
1K5
3B53-22
1K5
3B53-11 8
27
FC02
10K
3C06
-23C
00-3
10K
36
3C00
-2
10K
27
10K
18
45
3C00
-1
+24V
3C00
-4
10K
Green
Red
PWM-R2
PWM-G2
PWM-B2
PWM-R3
PWM-G3
PWM-B3
Blue
Circuit Diagrams and PWB Layouts EN 67Q552.1A LA 10.
2010-Apr-02 back to div. table
10-2 AL1 820400089691 9 LED LiteOn9 LED LiteOn
18770_610_100212.eps100218
9 LED LiteOnAL2A AL2A
8204 000 89693104 313 63812
9 LED LiteOn AL 2K10
2009-10-071
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
1M84 A102D01 B6
7204 A4
51 9
5 6
B
C
D
10
B
C
A7205 A5
764 10
421
2
7 8 9
A
D
83
3
7203 A3
B003
100n
2D01
+3V3
+3V3
456789
26 27+24V
1819
2
202122232425
3
1
1011121314151617
FH12-25S-0.5SH(55)
1M84
FD04
43
+24V
LTW-008RGB7205
65
21
5
21
43
7204LTW-008RGB
665
21
43
7203LTW-008RGB
B004
TEMP-SENSOR
BLANKPROG
LATCHSPI-CS
PWM-CLOCK-BUF
SPI-DATA-RETURNSPI-DATA-OUTSPI-CLOCK-BUF
Blue
Green
Red
EN 68Q552.1A LA 10.Circuit Diagrams and PWB Layouts
2010-Apr-02 back to div. table
9 LED LiteOn
18770_611_100212.eps100212
9 LED LiteOnAL2B AL2B
2009-10-071
8204 000 89693104 313 63812
9 LED LiteOn AL 2K10
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
E
C
7 10
D
2
A
B
5
FD03 D1
6
3D13-3 C12
8 9
FD02 C1
7304 B10
11 12 13
A
B
C
1
3D02-1 A1
D
6 7 8 11 12 13
1 2 3 4 5
3D13-2 C12
10
3D02-3 B13D02-4 C13D05-3 C1
3D13-1 C12
3D13-4 D12
7302 B77303 B8
7305 B117D01-1 A27D01-2 B27D02 C2FD01 B1
3 4
3D02-2 B1
5
21
43
E
2D10 D13
9
3D05-4 D13D10 B123D11 B123D12 B12
7300 B57301 B6
3
7303LTW-008RGB
6
LTW-008RGB7302
65
21
4
6
+24V
3D02
-3
10K
3
10K
3D02
-22
7
3
+24V
65
21
4
1 2
7300LTW-008RGB
270R
3D10
68R
3D12
1
FD01
+24V
7D01-1BC847BS(COL)
2
6
45
FD02
10K
3D02
-4
2D10
100n
1K5
3D13-33 6
3D13-4
1K5
4 5
4
FD03
7D01-2BC847BS(COL)
5
3
65
21
4343
7305LTW-008RGBLTW-008RGB
7304
65
21
5
21
43
LTW-008RGB7301
6
BC847BW7D02
1
3
2
3D02
-1
10K
18
+24V
3D05
-4
10K
45
10K
3D05
-33
6
3D13-11 8
1K5
270R
3D111 2
3D13-2
1K5
2 7
PWM-B4
PWM-R4
PWM-G4
Circuit Diagrams and PWB Layouts EN 69Q552.1A LA 10.
2010-Apr-02 back to div. table
10-3 AL1 820400089703 15 LED LiteOn15 LED LiteOn
18770_620_100212.eps100218
15 LED LiteOnAL2A AL2A
8204 000 89703104 313 63823
15 LED LiteOn AL 2K10
2009-12-073
2009-10-072
2009-07-021
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
4 5 6 7
D
A
5 6 7 8 9
B
C
D
1M84 A102D01 B67203 A37204 A4
1 2 3
7205 A5
9 10
A
B
C
8
3 4 10
FD18 C7
1 2
100n
2D01
+3V3
+3V3
+24V
3456789
26 27
16171819
2
202122232425
1
101112131415
FH12-25S-0.5SH(55)
1M84
FD18
1
43
+24V
LTW-008RGB7205
65
2
5
21
43
7204LTW-008RGB
665
21
43
7203LTW-008RGB
B004 B005B003
TEMP-SENSOR
BLANKPROG
LATCHSPI-CS
PWM-CLOCK-BUF
SPI-DATA-RETURNSPI-DATA-OUTSPI-CLOCK-BUF
Blue
Green
Red
EN 70Q552.1A LA 10.Circuit Diagrams and PWB Layouts
2010-Apr-02 back to div. table
15 LED LiteOn
18770_621_100212.eps100219
15 LED LiteOnAL2B AL2B
2009-12-073
2009-10-072
2009-07-0218204 000 8970
3104 313 6382315 LED LiteOn
AL 2K10
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
D
E
3D13-2 C12
F
G
139 10 11 12
3D02-1 A1
9 10
7305 B117400 F57401 F6
12 13
A
B
C
3D10 B123D11 B123D12 B123D13-1 B12
7D01-2 B27D02 C2
1 2
H
3D18-4 G127300 B57301 B6
6 7 8 2D10 C132D11 H13
3D02-2 A13D02-3 B1
11
7402 F77403 F87404 F107405 F117D01-1 A2
FD04 F1FD05 G1FD06 H1
3D04-4 F23D05-3 C13D05-4 D1
E
7D03-1 E27D03-2 F27D04 G2FD01 A1FD02 C1FD03 D1
4 53
3D16 F123D17 F123D18-1 G123D18-2 G123D18-3 G12
3D02-4 B13D03-3 H23D03-4 G2
A
B
C
D
7302 B7
1 2 7 83 4 5 6
3D13-3 C123D13-4 C123D15 F12
3D04-1 F23D04-2 G23D04-3 E2
7303 B87304 B10
F
G
H
65
21
43
LTW-008RGB7300
+24V
270R
3D16
270R
3D15
3D10
270R
5
21
43
7304LTW-008RGB
6
36
+24V
3D03
-3
10K
+24V
FD06
36
FD04
FD02
3D05
-3
10K
5
FD01
3D04
-4
10K
4
65
21
43
5
3
4
7403LTW-008RGB
2 7
BC847BS(COL)7D01-2
1K5
3D13-2
3 6
100n
2D10
4 5
3D13-3
1K5
5
1K5
3D13-4
3D02
-4
10K
4
65
21
43
+24V7400LTW-008RGB LTW-008RGB
7404
65
21
43
+24V
3 6
1K5
3D18-3
1K5
3D18-11 8
FD05
FD03
27
10K
3D04
-33
63D
04-2
10K
5
21
43
LTW-008RGB7402
6
3D12
68R
68R
3D17
27
+24V
+24V+24V
3
4
3D02
-2
10K
7D03-2BC847BS(COL)
5
3D11
270R
3D18-2
1K5
2 7
7305
65
21
43
18
LTW-008RGB
1
43
10K
3D04
-1
LTW-008RGB
65
2
7D02BC847BW
1
3
2
7301
10K
3D02
-11
8
10K
3D03
-44
5
65
21
43
LTW-008RGB7401
10K
3D05
-44
5
1 8
5
3D13-1
1K5
3D18-4
1K5
47D04
1
3
2
2
6
1
BC847BW
65
21
43
BC847BS(COL)7D01-1
LTW-008RGB7303
65
21
43
7D03-1BC847BS(COL)
2
6
1
7302LTW-008RGB
36
10K
3D02
-3
43
2D11
100n
7405LTW-008RGB
65
21
PWM-R4
PWM-G4
PWM-B5
PWM-B4
PWM-G5
PWM-R5
Circuit Diagrams and PWB Layouts EN 71Q552.1A LA 10.
2010-Apr-02 back to div. table
10-4 AL1 3104313 - 63895, 63812Layout AmbiLight LiteOn
18770_602_100216.eps100218
AmbiLight LiteOn
1M83 1M842B00
2B01
2B02
2B03
2B04
2B08
2B09
2B10
2B112B17
2B20
2B50
2C15
3004 3B
00
3B01
3B02
3B03
3B07
3B11
3B13
3B18
3B21 3B22
3B30 3B
31
3B34
3B35
3B36
3B37
3B39
3B50
3B51
3B52
3B53 3B55
3B57
3C00
3C063C10
3C11
3C123C15
7000 7001 7002 7003 7004 7005 7100 7101 7102 7103 7104 7105 7200 7201 7202 7203 7204 72057B06
7B077B207B23
7B25
7B267B30
7B50
7B51
7C20
7C22B00
1
B00
2
B00
3
B00
7
FB01
FB03
FB04
FB05 FB06
FB07
FB08 FB10
FB11FB12
FB13
FB15FB16FB20
FB30 FB31
FB32
FB35FB40FB41FB70
FB71FB72
FC01
FC02 FC03
1M83 1M842B00
2B01
2B02
2B03
2B04
2B08
2B09
2B10
2B112B17
2B20
2B50 2D01 2D10
3004 3B
00
3B01
3B02
3B03
3B07
3B11
3B13
3B18
3B21 3B22
3B30 3B
31
3B34
3B35
3B36
3B37
3B39
3B50
3B51
3B52
3B53 3B55
3B57
3C00
3C063C10
3C11
3C123C15
3D023D05 3D10
3D11 3D12
3D13
7000 7001 7002 7003 7004 7005 7100 7101 7102 7103 7104 7105 7200 7201 7202 7203 7204 7205 7300 7301 7302 7303 7304 73057B06
7B077B207B23
7B25
7B26
7B307B50
7B51
7C20
7C22 7D01 7D
02
B00
1
B00
2
B00
3
B00
4
B00
7
FB01
FB03
FB04
FB05 FB06
FB07
FB08 FB10
FB11FB12
FB13
FB15FB16FB20
FB30 FB31
FB32
FB35FB40FB41FB70
FB71FB72
FC01
FC02 FC03 FD01
FD02
FD03
FD04
3104 313 6381.2
3104 313 6389.5
18 LED
24 LED
EN 72Q552.1A LA 10.Circuit Diagrams and PWB Layouts
2010-Apr-02 back to div. table
10-5 AL1 820400090592 AmbiLight CommonEverlight LED Common 1
18770_670_100212.eps100219
Everlight 15 LED CommonAL1A AL1A
8204 000 9059AL 2K10 Everlight15 LED Common
2009-11-272
2009-11-031
BLUE
GREEN
RED
BLUE
GREEN
RED
OUT
1211
GSCLKIREFMODESCLKSINSOUT
XERRXHALFXLAT 10
NC
98
VCC
01234567
BLANK
131415
GND GND_HS
BLUE
GREEN
RED
BLUE
GREEN
RED
S
GND
Q
HOLDW
VCC
C
D
VIA
VIA
VIA
VIA
BLUE
GREEN
RED
BLUE
GREEN
RED
-T
FB07 B1FB08 B1
FB15 C1
3B37 G143B39-1 E13
3B34 D13
3B36 G14
7003 G107004 G11
7B30 D13FB01 A1
3B02-2 E53B03-1 H14
3B03-4 H143B07-1 F3
FB41 E13
FB03 B1FB04 B1FB05 B1
3B03-3 H14
7005 G137B06 D3
FB12 B2FB13 C1
7B20-1 D87B20-2 E8
7B07 D4
3B30-1 D93B30-4 E9
2B04-4 B72B08 E12
3B35 G14
2B10 F92B11 A92B17 D8
3B39-2 D123B39-3 D137000 G57001 G7
FB20 B7FB30 G3
3B31 B10
FB35 A8FB40 D12
7B23-1 F4
7B25 H37B26-1 A87B26-2 C9
3B01-2 D73B02-1 E3
D
E
3B03-2 H14
G
H
I
3B07-2 G33B07-3 H33B07-4 G33B11 E12
FB06 B2
FB10 B2FB11 B1
3B18 A83B21 B73B22 B8
5 6
2B09 E12
8 9 10
2B20 D43004 E123B00-1 A63B00-2 B6
7002 G8
FB16 C1
FB31 H3FB32 I3
7B23-2 G4
3B00-4 B63B01-1 E7
B
C
F
8 9 10
A
B
C
D3B13-3 H33B13-4 I3
3 4 7 11 12 13 14
3B00-3 B6
H
I
1M83 C1
2B02 E9
2B00 E8
11 12 13 14
E
4 5 6 73
1
1 2
F
A
2
G
2B01 F8
2B03 I142B04-1 B72B04-2 B62B04-3 B8
FB32
65
21
43
+3V3
99-235/RSBB7C-A24/2D7005
+3V3
10n
2B09
2K0
3B31
4
+3V3
1
2
35
7B0674LVC1G32GW
FB40
18
2B20
100n
10K
3B07
-1
FB20
FB30
8
3B21150R
3B30-1
220R
1
B002
+3V3
FB08
3B07
-3
10K
36
45
+3V3
FB31
10K
3B13
-4
1
43
+3V3
700299-235/RSBB7C-A24/2D
65
2
2532
FB35
910111415
1223
27
22
5
161718192021
678
31
30 33
24263
12132829
4
TLC5946RHB7B26-1
FB10
FB11
65
21
43
6
700499-235/RSBB7C-A24/2D
3B03-3
1K5
3
FB01
27
4 5
3B07
-2
10K
+24V
220R
3B30-4
100n
2B03
100n
2B11
3B01-1
100R
1 8
2B08
10n
2 7
1K5
3B03-2
3B36
270R
1K5
1%
36
3B39
-22
7
3B39
-3
5
6
+24V
1%1K
5
7B20-174LVC2G17
1
2
2
6
1
1
3
4
52
BC847BS(COL)7B23-1
LMV331IDCK
7B30
3B35
270R
3B37
68R5
3
4
B001
3 6
BC847BS(COL)7B23-2
150R3B00-3
2B17
100n
2B04
-4
100p
45
36
37 38 39
404142
7B26-2TLC5946RHB
3435
4
7
2
1
8
3+3V3
M95010-WDW67B07
(64K)Φ
6
5
7B25BC847BW
1
3
2
36
3B18
1K8
+3V33B
13-3
10K
33p
2B01
100R
3B01-22 7
+24V
100p
2B02
65
21
43
+3V3
+3V3
700199-235/RSBB7C-A24/2D
4 5
FB16
1K5
3B03-4
FB05
FB07
FB04
45
10K
3B07
-4
7003
65
21
43
99-235/RSBB7C-A24/2D
3
25
4
+3V3
1 8
74LVC2G177B20-2
150R
3B00-1
33p
2B00
1 8
+3V3
18
3B03-1
1K5
2B04
-1
100p
10K
3B02-2
27
1K5
1%
81
1 8
3B39
-1
FB03
3B02-1
10K
FB13
2B10
100p
3B34
RES100K
150R
3B00-44 5
56789
2627
1819
2
202122232425
34
1M83
FH12-25S-0.5SH(55)
1
1011121314151617
FB12
B007
FB15
10K30
04 RE
S
FB06
+3V3
3B11 10
K
150R
3B00-22 7
+24V
2B04
-2
100p
27
36
43
+3V3
2B04
-3
100p
99-235/RSBB7C-A24/2D7000
65
21
+24V
10K3B22
FB41
TEMP-SENSOR
BLANKPROG
SPI-CS
PWM-CLOCK
SPI-DATA-RETURNSPI-DATA-INSPI-CLOCK
LATCH
PWM-CLOCK
BLANK
SPI-DATA-IN-BUF
PWM-R1
PWM-G1PWM-R1
PWM-G3PWM-R3PWM-R2
PWM-B2PWM-G2
DATA-SWITCH
TEMP-SENSOR
PWM-G4PWM-R4PWM-B4
PWM-R5PWM-G5PWM-B5
SPI-CLOCK-BUF
SPI-DATA-IN-BUF
SPI-DATA-RETURN
SPI-CS
DATA-SWITCH
LATCH
SPI-DATA-INSPI-DATA-OUT
PWM-CLOCK-BUF
SPI-CLOCK-BUFPROG
SPI-CLOCK-BUF
PWM-CLOCK-BUF
SPI-CLOCK
PWM-G1
PWM-B1
PWM-B1
PWM-B3
Circuit Diagrams and PWB Layouts EN 73Q552.1A LA 10.
2010-Apr-02 back to div. table
Everlight LED Common 2
18770_671_100212.eps100212
Everlight 15 LED Common 2AL1B AL1B
2009-11-272
2009-11-031
8204 000 9059AL 2K10 Everlight15 LED Common
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
3B57-3 C3
FC03 H311 12
A
B
C
7104 B67105 B5F
G
3B55-2 B33B55-3 A3
E
7200 F8
3B55-4 A3
7C20-2 F3
8
1 2
3B53-4 C73B55-1 C3
11 12
FC02 G3
3
3B57-2 D3
4
3C15-3 G43C15-4 G4
9 10
7102 B97103 B7
3C10 F4
7C20-1 E3
3B50 B7
D
9 10
7201 F97202 F10
7B51 C3
FB71 C3FB72 D3FC01 F3
3C11 F43C12 F4
C
D
E
H
2B50 C11
3C15-1 G43C15-2 G4
7100 B117101 B10
3C00-4 E3
7C22 G3FB70 B3
3 4
3B51 B7
7
3B52 B73B53-1 B7
5
3C00-1 G33C00-2 F33C00-3 F3
7B50-1 A37B50-2 B3
A
B
3B53-2 C73B53-3 C7
1
F
G
H
3C06-1 G33C06-2 H3
5 6
6 7 8
5
3
4 +24V
2
45
BC847BS(COL)7B50-2
7
10K
3B55
-4
3B57
-2
10K
221
43
99-235/RSBB7C-A24/2D7105
65
BC847BS(COL)
2
6
1
65
21
43
7B50-1
99-235/RSBB7C-A24/2D7100
65
21
43
1
43
710199-235/RSBB7C-A24/2D
99-235/RSBB7C-A24/2D
65
2
10K
3C06
-11
8
7200
1
43
+24V
99-235/RSBB7C-A24/2D7201
65
2
10K
3B55
-33
6
100n
2B50
4
FC01
7C20-2BC847BS(COL)
5
3
270R
3C101 2
270R
1 2
10K
3B55
-11
8
3C11
3B52
68R
21
43
710499-235/RSBB7C-A24/2D
65
3
2
FB71
7B51BC847BW
1
3B51
270R
270R
3B50
1K5
3B53-44 5
1K5
3B53-33 6
3B53-22 7
1 8
1K5
1K5
3B53-1
27
FC02
36
10K
3C06
-22
73C
00-3
10K
83C
00-2
10K
53C
00-1
10K
13C
00-4
10K
4
+24V
3 6
4 5
3C15-3
1K5
3C15-4
1K5
2
3C12
68R
BC847BW7C22
1
3
36
+24V
+24V
3B57
-3
10K
FB72
FB70
FC03
10K
3B55
-22
7
65
21
43
3
710399-235/RSBB7C-A24/2D
99-235/RSBB7C-A24/2D7202
65
21
4
1 8
2 7
3C15-1
1K5
3C15-2
1K5
2
6
1
+24V
+24V
BC847BS(COL)7C20-1
65
21
43
PWM-R2
PWM-G2
99-235/RSBB7C-A24/2D7102
PWM-B2
PWM-R3
PWM-G3
PWM-B3
Blue
Green
Red
EN 74Q552.1A LA 10.Circuit Diagrams and PWB Layouts
2010-Apr-02 back to div. table
10-6 AL1 820400090601 9 LED Everlight9 LED Everlight
18770_640_100212.eps100219
9 LED EverlightAL2A AL2A
8204 000 90603104 313 64191
9 LED Everlight AL 2K10
2009-11-031
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
51 6 7
3 8 9
A
B
C
4 8
7203 A3
2 10
421
3
B
C
D
10
1M84 A102D01 B6
7204 A4
D
9
5 6 7
A7205 A5
B003
100n
2D01
+3V3
+3V3
26 27+24V
22232425
3456789
13141516171819
2
2021
1
101112
FH12-25S-0.5SH(55)
1M84
43
+24V
99-135/RSGBB7C-A24/2D7205
65
21
5
21
43
720499-135/RSGBB7C-A24/2D
665
21
43
720399-135/RSGBB7C-A24/2D
B004
TEMP-SENSOR
BLANKPROG
LATCHSPI-CS
PWM-CLOCK-BUF
SPI-DATA-RETURNSPI-DATA-OUTSPI-CLOCK-BUF
Blue
Green
Red
Circuit Diagrams and PWB Layouts EN 75Q552.1A LA 10.
2010-Apr-02 back to div. table
9 LED Everlight
18770_641_100212.eps100212
9 LED EverlightAL2B AL2B
2009-11-031
8204 000 90603104 313 64191
9 LED Everlight AL 2K10
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
3D13-2 C12
FD03 D1FD04 D1
3D05-3 C13D05-4 C13D10 A123D11 B123D12 B123D13-1 B12
3D13-3 C123D13-4 C127300 B57301 B67302 B77303 B87304 B107305 B117D01-1 A27D01-2 B2
FD01 A1
4 5 6 7 8 9 10 12
7 8 9 10 11 12 13
1
7D02 C2
3
FD02 C1
4 5
13
A
B
C
D
11
6
A
B
C
D
2D10 C133D02-1 A13D02-2 A13D02-3 B13D02-4 B1
36
2
1 2 3
3D02
-3
K01K01
3D02
-22
7
1
43
+24V
730099-135/RSGBB7C-A24/2D
65
2
3D101 2
270R
+24V
68R
3D12
2
6
1
FD01
7D01-1BC847BS(COL)
3D02
-44
5
FD02
10K
1K5
3D13-33 6
FD04
4 5
FD03
3D13-4
1K5
7D01-2BC847BS(COL)
5
3
4
21
43
730599-135/RSGBB7C-A24/2D
6565
21
4343
99-135/RSGBB7C-A24/2D7304
99-135/RSGBB7C-A24/2D7301
65
21
1
3
2
18
BC847BW7D02
3D02
-1
10K
+24V
45
2D10
100n
36
3D05
-4
10K
10K
3D05
-3
1K5
3D13-11 8
270R
3D111 2
2 7
1
43
3D13-2
1K5
99-135/RSGBB7C-A24/2D
65
2
65
21
43
7303+24V
99-135/RSGBB7C-A24/2D7302
PWM-B4
PWM-R4
PWM-G4
EN 76Q552.1A LA 10.Circuit Diagrams and PWB Layouts
2010-Apr-02 back to div. table
10-7 AL1 820400090621 15 LED Everlight15 LED Everlight
18770_660_100212.eps100219
15 LED EverlightAL2A AL2A
8204 000 90623104 313 64211
15 LED Everlight AL 2K10
2009-11-271
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
A
B
C
D
A
B
C
765421
7205 A5
9 108
987643 10
3
1M84 A102D01 B67203 A37204 A4
FD18 C7
1 2 5
D
FD18
43
+24V
99-235/RSBB7C-A24/2D7205
65
2121
43
720499-235/RSBB7C-A24/2D
6565
21
43
720399-235/RSBB7C-A24/2D
B004 B005B003
100n
2D01
+3V3
+3V356789
26 27+24V
1819
2
202122232425
34
1
1011121314151617
1M84
TEMP-SENSOR
BLANKPROG
LATCHSPI-CS
PWM-CLOCK-BUF
SPI-DATA-RETURNSPI-DATA-OUTSPI-CLOCK-BUF
Blue
Green
Red
Circuit Diagrams and PWB Layouts EN 77Q552.1A LA 10.
2010-Apr-02 back to div. table
15 LED Everlight
18770_661_100212.eps100212
15 LED EverlightAL2B AL2B
2009-11-271
8204 000 90623104 313 64211
15 LED Everlight AL 2K10
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
BLUE
GREEN
RED
7305 B117400 F5
7403 F87404 F107405 F117D01-1 A2
F
G
H
FD06 H1
7301 B6
3D18-4 G127300 B5
7401 F67402 F7
9 10 11
3D03-4 G23D04-1 F23D04-2 G23D04-3 E2
12
FD04 F1FD05 G1
B
C
D
E
1 2 3 6 7 10 11 12 13
3D02-2 A13D02-3 B13D02-4 B13D03-3 H2
3D15 F12
3D04-4 F23D05-3 C1
13
A
3D11 B123D12 B123D13-1 B123D13-2 C12
7D01-2 B27D02 C27D03-1 E27D03-2 F2
FD02 C1FD03 D1
4 5
1 2
8 9
2D10 C132D11 H133D02-1 A1
3D16 F12
3D18-2 G123D18-3 G12
3D13-3 C123D13-4 C12
F
G
7302 B77303 B87304 B10
3D05-4 D13D10 B12
H
A
B
C
3 4 5 6
7D04 G2FD01 A1
D
E
FD02
7 8
3D17 F123D18-1 G12
45
FD01
3
3D04
-4
10K
99-235/RSBB7C-A24/2D
65
21
4
5
3
4
7403
3D13-22 7
BC847BS(COL)7D01-2
1K5
3 6
100n
2D10
4 5
3D13-3
1K5
45
1K5
3D13-4
43
3D02
-4
10K
740099-235/RSBB7C-A24/2D
65
213
4
+24V+24V
7D03-2BC847BS(COL)
5
3D11
68R
3D18-2
1K5
2 7
RES
65
21
43
18
99-235/RSBB7C-A24/2D7305
1
43
10K
3D04
-1
730199-235/RSBB7C-A24/2D
65
2
7D02BC847BW
1
3
2
10K
3D02
-11
8
10K
3D03
-44
5
65
21
43
45
99-235/RSBB7C-A24/2D7401
10K
3D05
-4
65
21
43
99-235/RSBB7C-A24/2D7300
+24V
RES
68R
3D16
68R
3D15
3D10
68R
5
21
43
730499-235/RSBB7C-A24/2D
6
36
+24V
3D03
-3
10K
FD04
+24V
FD06
10K
36
1 8
3D05
-3
3D13-1
1K5
3D18-4
1K5
4 57D04
1
3
2
2
6
1
BC847BW
7303
65
21
43
BC847BS(COL)7D01-1
1
43
99-235/RSBB7C-A24/2D730299-235/RSBB7C-A24/2D
65
2
7D03-1BC847BS(COL)
2
6
1
10K
3D02
-33
6
2D11
100n
65
21
43
1
43
740599-235/RSBB7C-A24/2D99-235/RSBB7C-A24/2D
7404
65
2
1K5
3D18-33 6
FD05 1K5
3D18-11 827
FD03
63D
04-2
10K
10K
3D04
-33
99-235/RSBB7C-A24/2D7402
65
21
43
3D12
68R
68R
3D17
+24V
+24V+24V
27
PWM-R4
PWM-G4
PWM-B5
3D02
-2
10K
PWM-B4
PWM-G5
PWM-R5
EN 78Q552.1A LA 10.Circuit Diagrams and PWB Layouts
2010-Apr-02 back to div. table
10-8 AL1 3104313 - 64201, 64191, 64211Layout AmbiLight Everlight
18770_672_100216.eps100325
AmbiLight Everlight
1M83 1M842B
00
2B01
2B02
2B03
2B04
2B08
2B09
2B10
2B112B17
2B20
2B50
2C15
3004 3B
00
3B01
3B02
3B03
3B07
3B11
3B13
3B18
3B21 3B223B
30 3B31
3B34
3B35
3B36
3B37
3B39
3B50
3B51
3B52
3B53 3B55
3B57
3C00
3C063C10
3C11
3C123C157000 7001 7002 7003 7004 7005 7100 7101 7102 7103 7104 7105 7200 7201 7202 7203 7204 72057B06
7B077B207B23
7B25
7B267B30
7B50
7B51
7C20
7C22B00
1
B00
2
B00
3
B00
7
FB01
FB03
FB04
FB05 FB06
FB
07
FB08 FB10
FB11FB12
FB13
FB15FB16FB20
FB30 FB31
FB32
FB35FB40FB41FB70
FB71FB72
FC01
FC02 FC03
1M83 1M84
2B00
2B01
2B02
2B03
2B04
2B08
2B09
2B10
2B112B17
2B20
2B502D01
2D10
3004 3B
00
3B01
3B02
3B03
3B07
3B11
3B13
3B18
3B21 3B223B
30 3B31
3B34
3B35
3B36
3B37
3B39
3B50
3B51
3B52
3B53 3B55
3B57
3C00
3C063C10
3C11
3C123C15
3D023D05 3D10
3D11 3D12
3D13
7000 7001 7002 7003 7004 7005 7100 7101 7102 7103 7104 7105 7200 7201 7202 7203 7204 7205 7300 7301 7302 7303 7304 73057B06
7B077B207B23
7B25
7B26
7B307B50
7B51
7C20
7C22 7D01 7D
02
B00
1
B00
2
B00
3
B00
4
B00
7FB01
FB03
FB04
FB05 FB06
FB07
FB08 FB10
FB11FB12
FB13
FB15FB16FB20
FB30 FB31
FB32
FB35FB40FB41FB70
FB71FB72
FC01
FC02 FC03
FD01 FD02
FD03
FD04
1M83 1M84
2B00
2B01
2B02
2B03
2B04
2B08
2B09
2B10
2B112B17
2B20
2B50 2D01 2D10
2D11
3004 3B
00
3B01
3B02
3B03
3B07
3B11
3B13
3B18
3B21 3B223B
30 3B31
3B34
3B35
3B36
3B37
3B39
3B50
3B51
3B52
3B53 3B55
3B57
3C00
3C063C10
3C11
3C123C15
3D02 3D03
3D043D05 3D10
3D11
3D12
3D13 3D15
3D16
3D17
3D18
7000 7001 7002 7003 7004 7005 7100 7101 7102 7103 7104 7105 7200 7201 7202 7203 7204 7205 7300 7301 7302 7303 7304 7305 7400 7401 7402 7403 7404 74057B06
7B077B207B23
7B25
7B267B30
7B50
7B51
7C20
7C22 7D01 7D
02
7D03
7D04
B00
1
B00
2
B00
3
B00
4
B00
5
B00
7
FB01
FB03
FB04
FB05 FB06
FB
07
FB08 FB10
FB11FB
12
FB13
FB15FB16FB20
FB30 FB31
FB32
FB35FB40FB41FB70
FB71FB72
FC01
FC02 FC03
FD01 FD02
FD03
FD04
FD05
FD06
FD18
3104 313 6419.1
3104 313 6421.1
3104 313 6420.1
18 LED
24 LED
30 LED
Circuit Diagrams and PWB Layouts EN 79Q552.1A LA 10.
2010-Apr-02 back to div. table
10-9 B01 820400089943 Tuner, HDMI & CI Common Interface
18770_500_100118.eps100218
Common InterfaceB01A B01A
2009-10-223
8204 000 8994TUNER, HDMI & CI
G3
12
3EN23EN1
G3
12
3EN23EN1
G3
12
3EN23EN1
G3
12
3EN23EN1
G3
12
3EN23EN1
G3
12
3EN23EN1
+T
3F04-4 C4
2F01 A2
C
101P00-B G102F00 A6
IF04 B9
3F09-1 B93F08-4 B9
7F02 D5
51
D
3F04-1 C4
4
3F09-2 B9
2 3
2F04 E6
3F05-4 C4
3F09-3 B9
3F03-2 A4
IF02 A5
3F05-1 C4
3F04-2 C43F04-3 C4
11
3F08-3 B9
IF08 D9
2
3F09-4 B9
3F11-1 D9
7F03 E5
2F02 B6
7F05 I5
3F07-4 A9
E
F
3F08-2 A9
IF03 A4
G
IF06 C5
B
A
H
8
3F07-3 A9
2F06 H6
3F11-4 D9
3F02 A43F03-1 A4
7F01 B5
H
7
B
3F12 C9
3F11-3 D9
IF07 C5
3F07-2 A93F07-1 A9
8
D
3F10-1 C9
3F08-1 A9
I
9
2F03 D6
3 1P00-A D10
11
15-BIT ADDRESS
3F11-2 C9
3F01 A2
2F05 G6
CONTROL
I
7F04 G5
3F10-3 C93F10-4 C9
3F06 A9
C
A
E
4
8-BIT DATA
61
TRANSPORT STREAM FROM CAM
IF05 C4
3F10-2 C9
3F05-3 C4
7F00 A5
F
G
76
3F05-2 C4
IF01 A4
109
5
3F08-2
10K2 7
3F05-1 100R1 8
100R3 6
4 5
3F04-3
3F10-4
10K
100n
2F06
4 5
RES
3 6
3F08-4
10K
10K
3F08-3
10K4 53F11-4
3F09-3
10K3 6
100R1 83F04-1
IF02
+3V3
+3V3
131211
1
10
19
20
56789
18
17161514
74LVC245A7F01
2
34
18
3F04-4 4 5
3F11-1
10K
4 5
100R
10K
3F09-4
14131211
1
10
19
20
3456789
18
171615
74LVC245A7F03
2
3 6 100R3F05-3
1 8
3F12
10K
3F03-1
100R
20
17161514131211
1
10
19
2
3456789
18
7F0474LVC245A
IF07
1 810K
3F10-1
IF03
100n
2F04 RES
2 7
100R3F03-2
RES
100n
2F02
+3V3
+5VCA
3F02
100R
IF06
1211
1
10
19
20
56789
18
1716151413
7F0074LVC245A
2
34
REF EMC HOLE1X01
REF EMC HOLE1X04
2 7 100R3F04-2
4 5
+3V3
4 5
3F07-4
10K
100R3F05-4
10K
3F11-33 6
IF05
RES2F03
100n
IF04
16VCC1 17VPP1 18
WE|P 15
33WP|IOIS16
IF01
4D5D6 5D7 6
GND1 1
34GND26970
OE 9
RDY|BSY
A8A9 11
CE1 7
D0 30D1 31D2 32
D3 2D4 3
A15 20
A16 19
A2 27
A3 26
A4 25
A5 24
A6 23
A7 22
12
A0 29
A1 28
A10 8
A11 10
A12 21
A13 13A14 14
10074595-050MLF
ROW_A1P00-A
3F06 100K
10K
3F10-33 6
+3V3
2 7
+3V3
+5VCA
3F05-2 100R
+5V
+5VCA
10K
3F08-11 8
2F05
100n
1 8
RES
RE
S
3F09-1
10K
16V
22u2F
01
72
61REG
58RESET
51VCC2
52VPP2
43VS1
57VS2
59WAIT
64D8
65D9
35GND3
68GND4
60INPACK
44IORD
45IOWR
71
CD2
42CE2
66D10
37D11
38D12
39D13
40D14
41D15
A21
53A22
54A23
55A24
56A25
63BVD1|STSCHG 62BVD2|SPKR
36CD1
67
46A17
47A18
48A19
49A20
50
11
1
10
19
20
1P00-BROW_B
10074595-050MLF
6789
18
171615141312
74LVC245A7F05
2
345
2 73F10-2
10K
IF08
3 63F07-3
10K
RES
+3V3
2 7
2F00
100n
3F11-2
10K+3V3
+3V3
10K
3F07-11 8
2 710K
3F09-2
2 710K
3F07-20R4
3F01
131211
1
10
19
2056789
18
17161514
7F0274LVC245A
2
34
+5VCA
CA-RDY
CA-D00
CA-D01CA-D02CA-D03CA-D04CA-D05CA-D06CA-D07
CA-DATADIR
CA-DATAENn
MOVAL
MOSTRT
MDO0
MDO1
MDO2
MDO3
MDO4
MDO5
MDO6
MDO7
CA-WAITn
CA-INPACKn
CA-WP
CA-VS1n
CA-WEnCA-OEn
CA-CE2nCA-CE1n
CA-REGn
CA-MOCLK
CA-MOVALCA-MOSTRT
CA-MDO0
CA-MDO1CA-MDO2CA-MDO3CA-MDO4
CA-MDO6CA-MDO5
CA-MDO7
CA-RST
CA-CD1n
CA-CD2n
CA-DATAENn
CA-DATADIR
CA-ADDENn
MOCLK
XIO-D07XIO-D06XIO-D05XIO-D04XIO-D03XIO-D02XIO-D01
XIO-D00
CA-ADDENn
CA-WAITnXIO-D15XIO-D14XIO-WEnXIO-OEnXIO-D08XIO-D09
XIO-D11
XIO-D10CA-IOWRnCA-IORDn
CA-A03CA-A04CA-A05CA-A06CA-A07
XIO-A00
XIO-A01XIO-A02XIO-A03XIO-A04XIO-A05XIO-A06XIO-A07
CA-ADDENn
CA-A08
CA-A09CA-A10CA-A11CA-A12CA-A13CA-A14
XIO-A08
XIO-A09XIO-A10XIO-A11XIO-A12XIO-A13XIO-A14
CA-ADDENn
CA-D07CA-D06CA-D05CA-D04
MOCLK
MOVALMOSTRT
CA-D03
MDO0
MDO1MDO2MDO3MDO4MDO5MDO6MDO7
CA-A00
CA-A01CA-A02
CA-CE2nMDO7MDO6MDO5MDO4MDO3CA-CD1n
CA-WPCA-D02CA-D01CA-D00CA-A00CA-A01CA-A02CA-A03CA-A04CA-A05CA-A06CA-A07CA-A12CA-MICLKCA-MIVAL
CA-RDYCA-WEnCA-A14CA-A13CA-A08CA-A09CA-A11CA-OEnCA-A10CA-CE1n
CA-CD2nMDO2MDO1MDO0MOSTRTMOVALCA-REGnCA-INPACKnCA-WAITnCA-RSTMOCLKCA-MDI7CA-MDI6CA-MDI5CA-MDI4
CA-MDI3CA-MDI2CA-MDI1CA-MDI0CA-MISTRTCA-IOWRnCA-IORDnCA-VS1n
EN 80Q552.1A LA 10.Circuit Diagrams and PWB Layouts
2010-Apr-02 back to div. table
Flash
18770_501_100118.eps100118
FlashB01B B01B
2009-10-223
8204 000 8994TUNER, HDMI & CI
WE
BRWP
VCC
VSS
IO
NC
01234567
CLEALECERE
3
C
3F21-1 C12F21 A3IF23 D3
2
3F22-1 C2
3F22-2 C13F21-3 C1
42
3F20-1 B1
C
IF21 C3
3F21-2 C23F21-4 C2
A
7F20 B3
1
D
B
D
1
3F22-3 C2
43F20-4 C2
A
IF22 D3
B
3F23 C2
3F22-4 C2
32F20 A3
3F24 D23F19 D2
3F20-2 B2
IF21
3F20-3 B1
4 5
3F23 10K
3F20-4 100R
2F21
100n
+3V3
2 7 100R3F20-2
2 7
2 7
3F22-2 100R
+3V
3
100R3F21-2100R3F21-3 3 6
3F21-1 100R1 8
1 83F20-1 100R
IF23
6
3F24
2K2
100R3F20-3 3
+3V3
+3V3
100n
2F20
3F19
10K
4 5 100R3F22-4
1114
8
7
12 37
13 361819
3940454647
3
48
456
10
2425262728
2
33343538
41424344
1
1520212223
179
16
29303132
3 6
4Gx16[FLASH]Φ
NAND04GW3B2DN6F7F20
4 5
100R3F22-3
8
3F21-4 100R
3F22-1 100R1
IF22
NAND-CE1n
NAND-RDY1n
XIO-D01XIO-D00
XIO-D03XIO-D02
XIO-D05XIO-D04
XIO-D07XIO-D06
NAND-ALENAND-CLE
XIO-OEnXIO-WEnNAND-WPn
Circuit Diagrams and PWB Layouts EN 81Q552.1A LA 10.
2010-Apr-02 back to div. table
USB Hub
18770_502_100118.eps100118
USB HubB01C B01C
2009-10-223
8204 000 8994TUNER, HDMI & CI
VDD_3V3CR PLLFILT
OSC1
OSC3
OSC2
VIAGND_HS
USBUP
NC
VBUS_DET
RESET
DM
XTALOUT
DP
RBIAS
TEST
+T
+T
B
3
2F29 A4
6
2F31 A5
IF40 C2IF41 C2IF42 C2
2F34 B12F35 B2
IF32 C1
FF33 C9FF34 C7
IF37 C5IF39 D2
IF45 D9
5
3F34-4 D8
7 8
A
4
FF30 E8FF31 E9FF32 E9
C
FF36 D7
2F30 A4
SIDE USB TOP
2F32 A5
3F32 C83F34-1 C8
1 2
IF31 C1
1 2
FF35 C7
IF35 B5IF36 C5
3F26-4 B83F28 B23F30 C2
1P07 B91P08 D92F25 A2
IF43 A3IF44 A3
9
3F26-1 A8
IF33 B2IF34 B2
5 6 7
SIDE USB BOTTOM
FF37 D7FF38 E9
3F31-4 D2
FF40 A8IF30 C2
9F26 B8
2F33 A5
3F35 B1
9F20 B7
3 4
8 9
A
B
D
E
1F24 E91F25 B1
3F34-2 C83F34-3 D8
E
3F25 A8
3F26-2 A83F26-3 A8
3F31-2 C23F31-3 C2
C
D
FF39 E8
3F36 D67F25 B2
2F27 A22F28 A4
9F21 B79F25 B8
2F26 A2
1u0
2F27
2336
38 39 40 41
33XTALIN|CLKIN
322
USBDP_DN1|PRT_DIS_P1
4USBDP_DN2|PRT_DIS_P2
7USBDP_DN3|PRT_DIS_P3
31
27
5 10 2915
SCL|SMBCLK|CFG_SEL0
22SDA|SMBDATA|NON_REM1
28SUSP_IND|LOCAL_PWR|NON_REM0
11
1USBDM_DN1|PRT_DIS_M1
3USBDM_DN2|PRT_DIS_M2
6USBDM_DN3|PRT_DIS_M3
30
89
2021
13
17
19
34
35
26
24
12BC_EN1|PWRTPWR1
16BC_EN2|PWRTPWR2
18BC_EN3|PWRTPWR3
14
37
25HS_IND|CFG_SEL1
ΦUSB HUB
USB2513B-AEZG7F25
100K
3F34-33 6
FF35
FF39
IF44
4 5
IF37
100K
3F26-4
FF40
100K
3 6
1
3F26-3
100K
3F34-1
FF36
3 6
IF33
10K
3F31-3
3F26-1
100K
1
IF35
3F34-2
100K
2 7
3F36
10K
9F20
2F34
10p
100n
2F30
FF32
+5V
2F33
100n
4 5
+5V-USB1
3F34-4
100K
0R4
3F32
IF36 FF34
IF32
+5V-USB2
+3V3
100n
2F32
1P08
1234
5 6
292303-4
IF42
FF38
FF33
+3V3
+5V-USB1
IF43
10K
3F35
2 7
IF31
100K
3F26-2
3F31-2
10K
2 7
FF31
3F25 0R
4
2F31
100n
24
1 3
2F28
1u0
24M
1F25
IF45
+3V3
100n
FF30
2F29
9F25
2F25
100n
9F21
+5V-USB2
100n
2F26
+3V3
4 5
FF37
3F31-4
10K
1M0
3F28
IF34
10p
2F35
IF39
IF30
5 6
1234
IF41
1P07
292303-4
12K
3F30
+5V
9F26
12345
67
+5V
502382-0570
1F24
IF40
USB-DP1
USB-DP
USB-DM1
USB-DM
RESET-USBn
USB-OC3n
USB-OC2n
USB-OC1n
USB-DM3USB-DP3
USB-DM2
USB-DP2
USB-DP2
USB-DM2
USB-OC1n
USB-OC2n
USB-OC3n
USB-DM1
USB-DM2
USB-DM3
USB-DP1
USB-DP2
USB-DP3USB-DMUSB-DP
EN 82Q552.1A LA 10.Circuit Diagrams and PWB Layouts
2010-Apr-02 back to div. table
SD Card
18770_503_100118.eps100118
SD CardB01D B01D
2009-10-223
8204 000 8994TUNER, HDMI & CI
+T
4
1
C
D
1 2 3
2 3 4
A
D
A
B
47K
2 7
B
C
2 73F41-2
100R
3F44-11 8
3F44-2
100R
3F43-33 6
1 8100R 3F43-1
100R
2F40
22u
16V
IF47
RES
IF46
10K
3F45
FF46
FF45
12
+3V3 +3V3-SD
1939115-1
1P09-2
1011
FF50
FF47
3F42-3
47K
3 6
2 7
3F41-11 8
47K
3F42-2
3 6
47K
3 6
3F41-3
47K
3F44-3
100R
+3V3-SD
3F40
0R4
FF42
FF44
FF41
14
FF43
123456789
13
1939115-1
1P09-1
FF49
FF483F43-2
100R
2 7
+3V3
47K
3F42-11 847K
3F41-44 5
SDIO-CLK
SDIO-DAT3
SDIO-CMD
SDIO-CLK
SDIO-DAT0
SDIO-DAT1
SDIO-DAT2
SDIO-CDn
SDIO-WP
SDIO-DAT3
SDIO-CMD
SDIO-DAT0
SDIO-DAT1
SDIO-DAT2
SDIO-CDn
SDIO-WP
1P09-1 C4
3F44-3 C33F45 C1
1D 2-24F3
4D 2-90P1
3F42-3 D13F43-1 C3
2F40 A23F40 A23F41-1 C13F41-2 C13F41-3 C1
FF47 C3FF48 C3
FF50 D3IF46 D1IF47 B1
FF41 C3FF42 C3FF43 C3FF44 D3
3F41-4 C13F42-1 C1
3F43-3 C33F44-1 C33F44-2 C3
3F43-2 C3
FF45 A2FF46 C4
FF49 C3
Circuit Diagrams and PWB Layouts EN 83Q552.1A LA 10.
2010-Apr-02 back to div. table
PNX85500 Control
18770_504_100118.eps100118
PNX85500 ControlB01E B01E
2009-10-223
8204 000 8994TUNER, HDMI & CI
D
C
S
W
HOLD
VSS
Q
VCC
SCLADR
012 SDA
WC
IF53 B3IF54 C3
DEBUG / RS232 INTERFACE
SCL
FOR
FF29 C4FF55 E3FF56 E3
SHIFTED
UP
FF66 F4IF50 B3IF51 B1IF52 B3
DEBUG
3F63 E53F64 F53F65 F5
IF55 C6IF56 C7IF57 C7IF58 D2IF59 E1IF61 C4IF62 C4
7F54-2 C77F58 D19CH0 C7FF04 C4
DEBUG ONLY
SDA
USE ONLY
1F52 D8
FF57 E2FF58 C7FF61 D4FF62 D7FF63 E4FF64 F7FF65 F4
3F58 E13F59 E33F60 E33F62 D5
A
B
C
D
E
F
A
3F66 B73F67 B63F68 C73F69 D77F52 B27F53 B77F54-1 C7
D
E
F
1F51 F8
LEVEL
MAIN NVM
B
C
2F52 B12F53 D62F58 D23F51 B13F52 B33F53 C63F54 D7
1 2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8 9
3F54
FF66
RE
S1K
0
FF57
IF50
2F52
100n
IF55
RE
S
5
3
4
IF56BC847BPN(COL)
7F54-2 RES
FF62
1F51
12345
67
10K
3F58
RES
9CH0
IF51
IF57
100R3F62
3F64
100R
FF61
+5V
+3V3-STANDBY
7
2
1
84
3
Φ512K
FLASH
M25P05-AVMN67F52
6
5
RE
S3F
68
47K
FF58
100R
3F59
IF61
10K
RE
S
3F69
FF04
PDTA114EURES7F53
IF59
+3V3
FF64
100R
3F60
10K
3F51
123
4 5
1F52
+3V3
IF52
+3V3
RES
+3V3-STANDBY
100n
2F58
IF54
RES
2
6
1
FF65
BC847BPN(COL)7F54-1
23
6
5
84
7
7F58
EEPROM
Φ(8K×8)
1
+3V3
3F53
10K
IF53
3F66
10K
+3V3-STANDBY
RE
S
RE
S
3F67
10K
2F53
1u0
RE
S
+3V3-STANDBY
FF63 3F63
FF56
FF55
100R
3F52
10K
IF58
FF29
3F65
100R
IF62
BOOST-PWM
BACKLIGHT-BOOST
SDM
SPI-PROG
RESET-STBYnSPI-PROG
SDA-UP-MIPS
SCL-UP-MIPS
SCL-SSB
SDA-SSB
TXD-UP
RXD-UP
PNX-SPI-CLK
PNX-SPI-SDO
PNX-SPI-CSBn
PNX-SPI-SDI
PNX-SPI-WPn
EN 84Q552.1A LA 10.Circuit Diagrams and PWB Layouts
2010-Apr-02 back to div. table
HDMI & CI
18770_505_100118.eps100118
HDMI & CIB01F B01F
2009-10-223
8204 000 8994TUNER, HDMI & CI
AGC CONTROL
IO2IGNDO1
GND
B
C
D
E
1F75 B51T01 A12F59 B12F60 B1
1 2 3 4 5 6 7 8 9 10
1 2 3 4 5 6 7 8 9 10
A
B
C
D
E
A
2F61 B1
2F62 B102F63 C92F64 C92F65 B102F66 C10
2F70 B102F71 A72F72 A92F73 A92F74 B6
2F75 B82F76 B92F77 B92F78 B62F79 B8
2F80 B92F81 B12F82 B92F84 C12F85 C4
2F86 D12F88 E52F90 C62F91 D62F92 C7
2F93 C22F94 D73F71 C73F72 C73F75 D2
3F76 C23F77 C43F78 C73F79-1 B83F79-4 B8
3F80 C93F81 C93F82 B105F66 C105F70 D6
5F71 B95F72 E45F73 C55F74 B105F76 B10
6F72 C77F70 D87F75 A69F00 A69F01 A6
9F02 A89F03 A89F04 B39F05 C49F06 C4
9F71 E4AF70 B3AF71 B3AF72 B9AF73 B9
FF00 B2FF01 C4FF71 A1FF74 B1FF75 B2
FF76 B1FF81 C1FF82 C2IF10 A5IF11 A5
IF12 C9IF13 C9IF14 C9IF15 C9IF16 B10
IF72 C5IF73 B6IF74 B8IF75 B6
9F04
IF76 B8
IF77 B6IF78 B8IF79 C5IF80 B8IF81 B6
IF82 C4IF86 C5IF87 C2IF88 D2IF89 D5
IF90 D7
2F77
22p
22p
2F66
RF_
IO
4TU
N
IF11
IF_O
UT1
10
IF_O
UT2
11
13
1415
16
12N
C
3R
F_A
GC
1
1T01TX31XX
TUNER4M
HZ_
RE
F92
B+_
LNA
B+_
TUN
85I2
C_A
DR
6I2
C_S
CL
I2C
_SD
A7
FF81
10n
2F71
680n
5F66
1K0
3F72
BA
591
6F72
820n
5F74
2F64
10n
IF13
IF81
IF90
3F79-1
220R
1
100n
2F93
3F75
47R
10n
2F92
220R
3F80
3F82
820R
220R
3F81
IF86
GN
D2
5
INPUT12
INPUT23
OUTPUT1 7
OUTPUT2 6
VAGC4
VC
C1
UPC3221GV-E17F75
GN
D1
8
RES
IF74
30R
5F72
IF73
2F81
4n7
RE
S
IF79
9F06
IF75
47R
3F76
IF14
FF76 10n
2F79
+5V-TUN
FF71
47n
2F85
RES
2F91
10n
2F84
15p
2F65
15p
IF16
10n
2F90
IF80
220R
3F79-44
1p0
2F82
FF01
9F02
3K3
3F78
10n
RE
S
+5V-TUN-PIN
2F94
9F01
2F78
10n
5F70
470n
IF89
AF70
2F59
4u7
RE
S
9F71
IF82
IF15
4u7
2F61
AF73
100n
2F60
4K7
3F77
9F03
15p
2F72
2F80
15p
9F05
FF75
10n
2F74
9F00
+5V-TUN-PIN
15p
2F86
2F73
1p0
FF00
IF76
+5V
-TU
N-P
IN
4K7
3F71
5F73
ATB2012
23
14
IF78
12
45
36M17
1F75
X7251X
3
AF72
10p
2F62
5F76
330n
IF77
2F76
2p2
RE
S
IF72
IF10
2F88
22u
2F63
10n
5F71
680n
PDTC114EU7F70
IF87
IF12
IF88
2F75
10n
1p0
2F70
FF74
FF82
AF71
+5V-TUN-PIN
SELECT-SAW
IF-AGC
TUN-IF-N
TUN-IF-P
PNX-IF-P
PNX-IF-N
SDA-TUNER
SCL-TUNER
TUN-IF-N
TUN-P7
IF-AGC
IF+
IF-PNX-IF-AGC
TUN-P6
TUN-P7
TUN-P1TUN-IF-P
TUN-P6
Circuit Diagrams and PWB Layouts EN 85Q552.1A LA 10.
2010-Apr-02 back to div. table
Toshiba Supply
18770_506_100118.eps100118
Toshiba SupplyB01G B01G
2009-10-223
8204 000 8994TUNER, HDMI & CI
COM
OUTIN
D
A
C
D
1
5FA3 B25FA4 B3A
FFA2 C2FFAF B2
B
2FA2 C1
7FA3 B2
1 2 3
2 3
B
C
2FA3 C22FA4 C3
30R
5FA
4
5FA
3
30R
2FA
4
10u
100n
2FA
3FFAF
1
3 2
FFA2
7FA3LD1117DT12
+3V3
2FA
2
100n
+1V2-BRA-DR1
+1V2-BRA-VDDC
Not yet implementedNot yet implemented
EN 86Q552.1A LA 10.Circuit Diagrams and PWB Layouts
2010-Apr-02 back to div. table
HDMI
18770_507_100118.eps100118
HDMIB01H B01H
2009-10-223
8204 000 8994TUNER, HDMI & CI
3FBF-1 C4 3FBF-2 C4 FFB6 C2
4
4
A
B
FFB3 C2
C
1
FFB4 C2
2
FFB1 C2 FFB2 C2 FFB5 C1
HDMI CONNECTOR SIDE
1
A
2 3
B
3
FFB2
C
1P05 B1
2 7
DIN-5V
3FBF-2
47K
47K
3FB
F-1
18
DIN-5V
DIN-5V
456789
20212223
111213141516171819
23
1P05
1
10
FFB1
FFB5
FFB6
FFB3FFB4
DRX0+
DRX0-
DRX-DDC-SCLDRX-DDC-SDA
DRX2+
DRXC+
DRXC-PCEC-HDMI
DRX-DDC-SCLDRX-DDC-SDA
DRX-HOTPLUG
DRX2-DRX1+
DRX1-
Circuit Diagrams and PWB Layouts EN 87Q552.1A LA 10.
2010-Apr-02 back to div. table
VGA
18770_508_100118.eps100118
VGAB01I B01I
2009-10-223
8204 000 8994TUNER, HDMI & CI
9FC6 D6
3FC3 C6
C
FFC3 C4FFC4 C3
FFC6 D2FFC7 D4FFC8 D4
6FC2 B56FC3 C56FC4 C5
3FC7 C66FC1 B5
6
FFC5 C4
8
CONNECTOR
FFC1 A4
9FC1 D6
6FC6 E56FC7 E56FC8 F5
3FC5 A6
E9FC3 E69FC4 E69FC5 C6
6FC5 D5
A
C
E
A
B2FC7 E4
D
3FC1 D3
FFC2 B4
9FC2 E6
VGA
FFC9 E4
5 7
3FC2 E3
9
3FC4 D6
2
3FC6 B6
4 5 7
2FC5 D4
1FC5 D4
F
9
B
3
D
F
2FC4 C4
8
2FC6 E4
61
1FC6 F4
1E05 B242
3
1FC1 B41FC2 B41FC3 C41FC4 C4
1
2FC8 F4
2FC1 B42FC2 B42FC3 C4
9FC5
FFC3
2FC
1
100p
2FC
2
100p
RES
10K
3FC1
RE
S
12V
CD
S4C
12G
TA
6FC
3
1FC
6
RES3FC2
10K
3FC
4
4K7
2FC
6
47p
RES
9FC21F
C1
FFC4
18R
3FC6
FFC1
789
1617
1112131415
23456
1216-00D-15S-1EF
1
10
6FC
7
CD
S4C
12G
TA
12V
1E05
FFC8
FFC6
12V
CD
S4C
12G
TA
6FC
2R
ES
2FC
5
47p
1FC
5
6FC
4R
ES
12V
CD
S4C
12G
TA
100p
2FC
3
12V6F
C5
CD
S4C
12G
TA
RE
S
FFC7
47p
2FC
42F
C8
47p
1FC
2
RES
9FC4
FFC2
9FC3
9FC6
1FC
3
3FC7
18R
12V
CD
S4C
12G
TA
6FC
6
4K7
3FC
3
47p
2FC
7
12V
CD
S4C
12G
TA
6FC
8
1FC
4
FFC5
12V
CD
S4C
12G
TA
6FC
1R
ES
9FC1
FFC9
3FC5
18R
VGA-SCL-EDID
VGA-SDA-EDID
VGA-SDA-EDID-HDMI
VGA-SCL-EDID-HDMI
+5V-VGA
R-VGA
G-VGA
B-VGA
H-SYNC-VGA
V-SYNC-VGA
EN 88Q552.1A LA 10.Circuit Diagrams and PWB Layouts
2010-Apr-02 back to div. table
Temp Sensor + Headphone
18770_509_100118.eps100118
Temp Sensor + HeadphoneB01J B01J
2009-10-223
8204 000 8994TUNER, HDMI & CI
C
3 4 5 7
2 3 4
2FD1 A42FDC D5
8 9
A
B
C
1 2
E
A
B
7FD1 B3
1328 D61329 C61FD2 D41FD3 D5
6FD1 B36FD2 D4
IFD2 B3IFD3 B4
2FDD D53FD1 A3
IFD4 B3IFD5 B4
3FDG-2 D4
3FD3 B3
6
3FD6 C43FD7 C43FDG-1 D4
1
9FD1 A49FD2 A49FD5 C5
IFD1 B4
5 6 7 8
D
E
3FD4 B2
6FD3 D5
9
FFDA D5FFDB D5FFDC D6
D
IFD4
3FD2 B5
1FD
3
IFD5
2FD
1
12V
CD
S4C
12G
TA
6FD
2
100n
3FD
2 1K0R
ES
9FD
5
9FD
1
9FD
2
FFDB
FFDA6F
D3
CD
S4C
12G
TA
12V
IFD2
RES 1K0
3FD
1
1K0
27
RE
S
3FD
G-2
1K0
3FD
6
IFD3
1n0
2FD
D
IFD1
1FD
2
18
+3V3
FFDC
1K0
3FD
G-1
6FD
1
LTS
T-C
190K
GK
T
1328
MSJ-035-29D PPO (PHT)
2
13
RES
A25
4G
ND
OS3
SCL2
SDA1
7FD1
+V
S8
A07
6A1
LM75BDP
2FD
C
1n0
RE
S3F
D7 1K
0
3FD3
100R
5
3FD4
100R
123
4
AMP1AMP2
502382-0370
1329
SDA-SSB
SCL-SSB
Circuit Diagrams and PWB Layouts EN 89Q552.1A LA 10.
2010-Apr-02 back to div. table
Tuner Brazil
18770_510_100118.eps100118
Tuner BrazilB01K B01K
2009-10-223
8204 000 8994TUNER, HDMI & CI
OUTIN
INH BP
COM
X
XSEL
ADI_AI
ADQ_AI
AD_VREF
TSMD
TN
SLADRS
VSS
DR
2VD
D
DR
1VD
DVDDSA
D_D
VD
D
AD
_AV
DD
PLL
VD
D VDDC
PBVAL
RERR
RLOCK
RSEORF
SBYTE
SLOCK
SRCK
SRDT
STSFLG1
AGCCNTI
AGCCNTR
STSFLG0
SYRSTN
01
SCLSDA
FIL
AD
_AV
SS
AD
_DV
SS
PLL
VS
S
I
O
01
PN
PN
PN
AD_VREF
DTCLK
DTMB
S_INFO
01
AGCI
CKI
SCLSDA
BFE5 E4
7FE3 C11
9F28 E8
2FH6 E3
7FE0 D4
3FE8 F33FE9 F33FG2-1 F6
5FE4 B7
IF18 D4IF27 E7
3FG6-3 E73FG6-4 D7
5FE0 A3
FF03 C12IF17 D4
IF67 B4IF68 B5
IF48 C12IF49 F4
DFF1 E6
IF65 B4IF66 B5
DFF2 F6
2FG6 D32FG7 E32FG8 E3
IF29 F4
5FE9 C115FG0 E11
IF64 A5
BFE4 E4
2FH8 E7
DFE6 D6DFE7 D6
BFE1 E4
2FH7 E3
BFE3 E4
5FG2 E11
BFE2 E4
2FF1 A72FF2 B62FF3 B6
3FG2-2 F7
2FF9 C72FG0 C6
5FE3 B3
5FE5 B35FE7 C11
IF28 E7
3FG7 E7
IF69 C6
IF63 A4
2FG1 C72FG2 C12FG3 C22FG4 D3
2FG9 E3
9F27-1 E8
9F27-4 D8
2FH5 D6
2FE4 A6
3FE5 E73FE6 F3
DFE8 D6
2FE5 A62FE6 B32FE8 C32FF0 A6
2FF4 B6
3FG4-1 F7
DFE9 E6
3FG6-2 E7
2FF8 C6
5FE8 C7
B
D
B
2FH2 D11
9F27-2 D8
2FH4 D12
1 2
3FE7 F3
126
73
2FF5 B6
3FG4-2 F6
2FF7 C6
11 13
A
C
9 10
G
H
A
2FE3 A6
F
H
2FH3 D12
G
1FE0 C2
D
EE
F
10 114 5
C
8 9
61 2
3
4 5
7
2FF6 B7
13
9F27-22 7
128
2FE0 A3
18p
9F27-44 5
2FG
3
LD3985M257FE3
4
2
1
3
5
IF29
3FG4-2
4K7
2FH
3
10n
30R
5FE8
AGND
5FE3
30R
100n2FG8
2FH5
FF03
1n5
IF63
2FH
2
1u0
IF17
BFE2
BFE4
AGND
9F28
AGND
AGND
100n
2FE
3
IF68
IF65
IF64
IF67
100n
2FG
0
10K3FE6
100n
2FF
3
10K
2FE
4
100n
2 7
3FG2-12F
F7
3FG6-2 33R
100n
2FF
1
1u0
2FH6 100n
18K
3FE5
DFE9
DFE7
30R
5FG2
2FF
2
100n
2FE
0
1u0
2FF
0
100n
BFE1
2FG4 10n
2FF
8
100n
2FF
9
1u0
AGND
3FE9 100R100R3FE8
1 8
AGND
9F27-1
IF49
30R
5FE4
AGND
DFF1
24
1 3
100n
2FF
5
1FE0
25M4
BFE5
BFE3
2FG7 100n
IF69
AGND
3FE7 10K
IF66
1u0
2FG
1
2FH
8
10n
IF18
30R
5FE9
IF28
57 62
19
18
32
13 35 49 64
4 15 33 37 44 47 50
42
8
1214
141
16 36 56 6355
59
4546
65
52
61
60
51
38
34 48 4339
40
21
58
20
17
53
54
23
32
31
26
2524
9
10
7
11
ΦTC90517FG
7FE0
2930
2728
22AGND
10K3FG2-2
3FG6-3 33R3 6
4 53FG6-4 33R
1u0
2FE
8
AGND
10n2FG6
100n2FH7
30R
5FE0
1u0
2FH
4
3FG7 33R
IF48
1u0
2FF
6
IF27
DFF2
DFE6
4K73FG4-1
30R
5FE5
AGND
18p
2FG
2
AGND
2FE
6
1u0
30R
5FG0100n2FG9
30R
DFE8
5FE7
100n
2FE
52F
F4
100n
TS-DVBS-DATA
TS-DVBS-VALID
TS-FE-SOP
TS-DVBS-SOP
TS-FE-CLOCK
TS-DVBS-CLOCK
+1V2-BRA-VDDC
+1V2-BRA-DR1
+3V3-BRA-FLT +3V
3-B
RA
-FLT
+3V3-BRA-FLT
+3V3-BRA-FLT
RESET-SYSTEMn
IF+
+2V5-BRA+5V
+3V3 +3V3-BRA
+2V5-BRA
+3V3-BRA
+2V5-BRA
SCL-SSBSDA-SSB
IF-
TS-FE-DATA
IF-AGC
TS-FE-VALID
Not yet implementedNot yet implemented
EN 90Q552.1A LA 10.Circuit Diagrams and PWB Layouts
2010-Apr-02 back to div. table
10-10 B02 820400089506 PNX85500PNX NandFlash - Conditional Access
18770_511_100118.eps100218
PNX NandFlash - Conditional AccessB02A B02A
2009-12-076
8204 000 8950PNX85500
MDI
MCLK
MDO
TNR_SER1
VS
CD
CA
DATAERR
MICLKMIVAL
SOP
01234567
12
12
VPPEN
01234567
ADD_EN
DATA_DIR
DATA_EN
I
O
MISTRT
MIVAL
MOSTRT
MOVAL
OOB_EN
RDY
RST
VCCEN
NAND
XIO_A
XIO_D
XIO
NAND
070809101112131415
OE_WE_
CLK_BURST
WP_RDY1RDY2CE2_CE1_
00010203040506
CLE
00010203040506070809101112131415
ALE
3 4 5 6 7
1
G
3S02-4 E3
3S01-1 E23S01-2 E33S01-3 E23S01-4 E33S02-1 E3
14
1 21018
*
13 14
G
2 3 4 5 6
H
3S02-2 E23S02-3 E2
7 8 9 10 11 12 13
A
B
C
D
E
2 9 11
F
H
A
B
C
D
F
3S1S G7
3S03 F33S04-1 F33S04-2 F33S15 B63S1R F7
3S1T G7
3S29 H77S00-11 E37S00-5 A49S00 F59S08 C5IS00 C5
E
IS25 C3IS26 B6
3S1U G73S23 G73S24 G73S28 G7
IS26
10K
3S15
470R3S23RES
J23
J24
K23K24
T21T23T22R23R22
M24M25M26L21
N24
N25
L22
L23
J21
L24
L26
P22P23P24P25P26N21N22
N26M21M22M23
J22
K21K22
K25
K26
N23
L25
P21
7S00-11PNX85500
VIDEO_STREAM
3S02-33633R
33R
3S01-2 27
+3V3
3S1R
560R
560R
3S1S
3S1T
560R
183S04-1
33R
560R
3S1U
3S29
470R
RES
470R
3S28
9S00
1833R
3S01-1
10R
27
3S03
45
33R
3S04-2
3S02-4
33R
E23E24E25E26D24
B22C22
D25D26C24D23C23B23A22E22F24F25F26
H24H25H26G21G22G23G24G25G26F22F23
D21
C21
F21A20
A21
J25J26H21H22H23
7S00-5PNX85500
FLASH
B21
D22
E21
7 3S02-2
33R2
IS00
9S08
18 3S02-1
33R
RES3S24
470R
3633R
3S01-3
IS25
1X06EMC HOLE
45 3S01-4
33R
TS-FE-ERR
CA-CD1n
TS-FE-DATA
TS-FE-CLOCK
INPACK
TS-FE-VALID
TS-FE-SOP
TS-FE-SOP
TS-FE-VALID
TS-FE-CLOCK
TS-FE-DATA
INPACK
CA-MDI3CA-MDI4CA-MDI5CA-MDI6CA-MDI7
CA-MISTRT
CA-MIVAL
CA-MOCLK
CA-DATAENn
CA-DATADIR
CA-ADDENn
CA-RDY
CA-RST
NAND-ALE
NAND-CE1n
NAND-CLE
NAND-RDY1n
TS-FE-DATA
NAND-WPn
XIO-A07XIO-A06XIO-A05XIO-A04XIO-A03XIO-A02XIO-A01XIO-A00
CA-VS1n
CA-CD2n
TS-FE-VALIDTS-FE-SOP
TS-FE-CLOCK
CA-MOVAL
CA-MOSTRT
CA-MDO7CA-MDO6CA-MDO5CA-MDO4CA-MDO3CA-MDO2CA-MDO1CA-MDO0CA-MDI0
CA-MDI1CA-MDI2
XIO-D10XIO-D09XIO-D08XIO-D07XIO-D06
XIO-D04XIO-D03XIO-D02XIO-D01XIO-D00
XIO-A15
XIO-A13XIO-A14
XIO-A12XIO-A11XIO-A10XIO-A09XIO-A08
CA-MOCLK
XIO-D05
CA-MICLK
XIO-WEnXIO-OEn
XIO-D15XIO-D14
XIO-D11
Circuit Diagrams and PWB Layouts EN 91Q552.1A LA 10.
2010-Apr-02 back to div. table
PNX SDRAM
18770_512_100118.eps100118
PNX SDRAMB02B B02B
2009-12-076
8204 000 8950PNX85500
1
3
01234567891011121314151617181920212223242526272829
0
1
RASB
CASBCKECSBODT
PCAL
0123456789
1011121314
NP
NP
3031
012
2DM
DQ
BA
A
CLK
DQS0
NP
DQS1
NP
DQS2
NP
DQS3
VREF
M0
WEB
2
3S6P E103S6Q E107S00-8 B6FS01 D3FS02 D2IS42 E8
2S24 E72S25 E73S06 D33S07 D33S0V F83S20 D23S22 D23S30 C73S33 C8
8 9 10 11
A
B
C
D
E
A
B
11
1 2 3 4 5 6
1 2 3 4 5 6 7 8 9
F
7
C
D
E
F
2S12 D42S17 E72S20 E7
10
2S12
100u
2.0V
3S22
180R
1%
3S0V
261R
FS02
1%
3S3310R
1%18
0R3S07
DDR2-VREF-CTRL2
2S25
100p
M1M5
A2V1
H3
B2E2E3
D3D4
R1R2
T3T4
M4
P5N3V3
C3
R4V5
B4F1C1E1F4
P2U2P3
F2
N1U1P1T1V4R5U5
T5
F3C2
E5C5A4G5B3F5U3
H1H2G1
K3K4
N5N4
L5
D1D5R3
J4M2K5
K1G4L3G3L2H5L1J5
MEMORY J1J3
J2M3
7S00-8PNX85500
3S20 1%
180R
2S17
100n
10R3S30
DDR2-VREF-CTRL3
IS42
3S6Q
10K
+1V8
2S24
100p
10K
3S6P
DDR2-VREF-CTRL2
FS01
3S06
180R
1%
2S20
100n
DDR2-VREF-CTRL3
DDR2-CLK_NDDR2-CLK_P
DDR2-ODT
DDR2-A10DDR2-A11DDR2-A12
DDR2-A0
DDR2-CKE
DDR2-DQS0_NDDR2-DQS0_P
DDR2-A1DDR2-A2DDR2-A3DDR2-A4DDR2-A5DDR2-A6DDR2-A7DDR2-A8DDR2-A9
DDR2-CKEDDR2-CS
DDR2-CAS
DDR2-DQS3_NDDR2-DQS3_P
DDR2-DQS2_NDDR2-DQS2_P
DDR2-DQS1_NDDR2-DQS1_P
DDR2-D11DDR2-D10
DDR2-D1DDR2-D0
DDR2-BA1DDR2-BA0
DDR2-A14DDR2-A13
DDR2-ODT
DDR2-WEDDR2-RAS
DDR2-D2
DDR2-D18DDR2-D19DDR2-D17DDR2-D16DDR2-D15DDR2-D14DDR2-D13DDR2-D12
DDR2-D25DDR2-D26DDR2-D30DDR2-D24DDR2-D21DDR2-D20DDR2-D23DDR2-D22
DDR2-D7
DDR2-D6DDR2-D5DDR2-D4
DDR2-D29DDR2-D27
DDR2-D3
DDR2-D31DDR2-D28
DDR2-BA2
DDR2-DQM3DDR2-DQM2DDR2-DQM1DDR2-DQM0
DDR2-D9DDR2-D8
EN 92Q552.1A LA 10.Circuit Diagrams and PWB Layouts
2010-Apr-02 back to div. table
PNX Digital Video In
18770_513_100118.eps100118
PNX Digital Video InB02C B02C
2009-12-076
8204 000 8950PNX85500
RX0_A
RX1_A
PN
RX2_A
RXC_APN
DDC_A
PN
PN
HOT_PLUG_A
SDASCL
RREF
A
IS10 E7
7 11 12 13 14
14
3 4 5 6
9
D
E
F
G
H
8 9 10
10 11 12 13
IS01 E6
1 2
5 6 7 8
D
E
F
G
H
B
C
I
2S2E F53S0W E57S00-6 D6
RES
1 2 3 4
I
A
B
C
2S2E
10u
12K
3S0W
IS10
+3V3
V26V25
W26W25
Y26Y25
T24
W24
T26T25
U26U25
HDMI_DVPNX85500
7S00-6
IS01
DDCA-SCLDDCA-SDA
HDMIA-RX0+HDMIA-RX0-
HDMIA-RX1+HDMIA-RX1-
HDMIA-RX2+HDMIA-RX2-
HDMIA-RXC-HDMIA-RXC+
Circuit Diagrams and PWB Layouts EN 93Q552.1A LA 10.
2010-Apr-02 back to div. table
PNX Audio
18770_514_100118.eps100118
PNX AudioB02D B02D
2009-12-076
8204 000 8950PNX85500
OUT IN
INHBP
COM
&
&
AIN1
LR
AIN2
LR
AIN3
LR
AIN4
LR
AIN5
VR_AADC
ADAC
ADACL
PN
ADACR
I2S_OUT
I2S_OUT_SD
SPDIF_OUT
POSNEG
VREF_AADC
VCOM_AADC
SPDIF_IN1
4321
2
NP
1
3456
WSSCK
OSCLK
LR
&&
2S2K F122S2L D4
6 11 12
F
10
2S36 C6
13
G
H
9
3 4 52
2S3Q G52S41 C62S42 C63S0Z A11
2S2R B72S2S B92S2T B82S2V B32S2W B3
C
D
H
7 8
I
2S2G C122S2H D122S2J G12
9
3S17-3 C33S17-4 C33S18-1 G73S18-2 G8
2S38 E92S39 E92S3A E82S3B E82S3C E8
10 11 122 14
1
2S3M H9
3S51 C63S53-1 A63S53-2 B63S53-3 B6
3S10 D43S11 F53S12-1 B23S12-2 B23S12-3 B2
2S2Y C32S2Z B32S30 C3
E
F
G
I
A
B
C
D
E
3S16-2 B33S16-3 B33S16-4 C3
3S17-2 D3
IS06 G11IS07 E11
3S18-3 G83S19 H53S25 H93S32 G123S34 G11
2S3D E82S3E E32S3F E2
13
8765431
3S3G-2 D83S3G-3 C83S3G-4 D7
2S3L H8
3S3U D8
7S05-4 B127S08 B87S09-1 G67S09-2 H6
3S53-4 B63S6L F123S6M H87S00-2 C57S05-1 E12
3S12-4 C23S13-1 C23S13-2 D2
2S31 C3
3S17-1 C3
3S37 F113S38 B13
IS0R C2IS0V C2IS12 B8IS13 B9IS19 D3
3S36-1 C123S36-2 B113S36-3 D11
2S3G E3
14
A
B
3S3F E43S3G-1 C7
IS1N C7IS1S D7IS44 H9
3S3H D7
7S05-3 C12
IS1B D4IS1D G5
7S05-2 G12
7S09-3 H77S09-4 I79S06 E4DBS8 E4FS03 B12FS08 B7IS02 B11IS03 C11
3S13-3 C2
2S32 D32S33 C32S34 B9
IS1E H5
IS1G G7IS1K H9IS1L F5
IS1A D3
3S39 C13
3S36-4 D12
2S3H E32S3J B112S3K G6
3S13-4 C23S14 B93S16-1 B3
IS0R
+2V5-AUDIO
+3V3-ARC
1n0
2S3D
3S53-2
100R
4 5
10K
3S16-4
1n0
2S3C
22K
3S12-227
DBS8
IS1A
100R3S10
3 6
IS1B
18
3S16-3
10K
3S12-1
22K
LM3247S05-412
1314
4
11
+24V-AUDIO-VDD
IS13
2S34
100n
4R7
IS03
3S51
2S3A
1n0
IS19
100n
2S3Q
2S31
1u0
3S13-1
22K1 8
3S53-3
3S11
100R
1R0
5
67
4
11
+3V3-ARC
+3V3
LM3247S05-2
3S17-210K
27
22K
3S14
3S3U
33R
IS0V
3S6M
180R
FS08
100n
2S3K
2S3G
100n
+3V3
63S3G-3
33R
3
1u0
2S42
3S53-1
2S2V
1u0
IS1N
100R
10u
2S3H
+3V3
1u0
2S2W
22K
3S32
10
98
4
11
LM3247S05-3
1u0
2S2Y
1n0
2S38
+24V-AUDIO-POWER
2S2K
47p
2S32
2 7
1u0
3S3G-2
33R
3S3H
33R
2S3E
100n
FS03
IS1E
220R
3S18
-33
6
2
1
3
5
LD3985M257S08
4
3S0Z
8
IS1D
4R7
10K
3S17-11
IS06
3S36-1
10K
18
3S17-44 5
IS12
10K
IS44
2S2S
10u
+24V-AUDIO-VDD
RE
S
22K
3S6L3S37
10K
3S3F
56R
4 5
10K3S17-3
36
22K
3S12-4
+3V3
68R
3S25
10u
2S3F
2S2L
1u0
2S33
10K
3S19
1u0
3 63S12-3
22K
8
2S3J
220n
3S16-1
10K
1
2S2Z
1u0
IS1L
47p
2S2J2S
2T
47p
2S2H
100n
10K3S16-2
27
3S18
-2
220R
27
+3V3-ARC
7S09-174LVC00APW
1
2
714
3
4 5
IS02
22K
3S13-4
2S41
100u
4V
1112
13
71474LVC00APW
7S09-4
3
21
4
11
LM3247S05-1
2S36
1u0
IS1S
714
6
100n
2S3M
74LVC00APW7S09-2
4
5
+24V-AUDIO-VDD
1n0
2S39
3S3G-1
33R
1 8
+3V3-ARC
3S18-1
220R
1 8IS1G
AB9
2S2G
47p
AE1AF2AE3AF3
AD2
AE5
AF5
AC8
AD8
AB8
AF10
AD10AC10
AE9AF9
AD9AC9
AF84DA8EA
AD1
AD7AE7AF7AD6AE6AF6
AB7AC7
AB6AC6
AE10
5
PNX855007S00-2
AUDIO
3S3G-4
33R
4
3S34
10K
3S39
100R
3 63S36-3
10K
IS1K
+2V5
9S06
10K
3S36-22 7
7S09-374LVC00APW
9
10
714
8
6
IS072S3B
1n0
3S13-3
22K
3
+3V3
+24V-AUDIO-VDD
2S30
1u0
3S38
100R
27
2S3L
100n
22K
3S13-2
+3V3
3S53-4
100R
45
2S2R
10u
10K
3S36-4
AUDIO-OUT-L
AUDIO-OUT-R
SPDIF-OUT-PNX
+AUDIO-L
-AUDIO-R
AUDIO-IN1-L
AUDIO-IN1-R
ADAC(2)
ADAC(3)
ADAC(1)
ADAC(4)
SPDIF-OUT
eHDMI+SEL-HDMI-ARC
ADAC(1)
ADAC(2)
ADAC(5)
AUDIO-IN4-L
AUDIO-IN4-R
AUDIO-IN3-L
AUDIO-IN3-R
AUDIO-IN2-L
AUDIO-IN2-R
ADAC(5)
ADAC(6)
ADAC(6)
SPDIF-OUT-PNX
EN 94Q552.1A LA 10.Circuit Diagrams and PWB Layouts
2010-Apr-02 back to div. table
PNX Mips
18770_515_100118.eps100118
PNX MipsB02E B02E
2009-12-076
8204 000 8950PNX85500
USB
1
2
3
4
RREFDPDN
CLK_54_OUT
BL_PWM
RESET_SYS
TDITDOTCKTMS
TRSTN
SCLSDA
SCLSDA
SCLSDA
SCLSDA
ETHRXD
SDIODAT
ETH
TXD
TXCLK
0123
TXENTXER
COLCRSMDC
MDIO012SDCDSDWP
RXCLK
0123
RXDVRXER
CC_DAT3CLKCMD
-BUSCTRLFIL
I 2 CINP
3S64 C1
DS52 B2FS10 B2FS11 B2FS2W F9FS2Y F9
3S65 E113S66 E113S67 E113S68 E113S69 A9
A
B
12 13
USE ONLY
3S61 B63S62 B1
9S13 F8
IS04 B2IS05 A2IS08 F8IS09 F8IS40 C6
7 8
FOR FACTORY
RES
3S82 B13S83 C1
7S01 E89S10 F89S11 F89S12 F8
9
H
1F10 A12
G
H
A
B
C
D
FS44 A12FS49 A12FS50 A12FS51 B12FS52 B12FS53 B12FS57 B12FS64 C2
3S6H-3 B93S6H-4 B93S6J C53S6K B93S72 C6
1 2 3
IS4Z B4IS50 G12
3S84 C17S00-3 A47S00-4 G12
3S56 A53S57 A63S58 A53S5W B63S5Y B5
10
C
D
E
F
3 4 5 6 7 8
E
F
G
FS31 F8
3S6B A93S6C B83S6D B93S6E B83S6F B93S6G B83S6H-1 B83S6H-2 B9
4 5 6
3S80 B13S81 B1
14
2S89 D83S00 B53S21 B13S26 C53S27 C63S40 A13S45 A13S55 C3
11 12 13 14
1 2 9 10 11
3S5Z B63S60 B5
3S6A A8
IS08
+3V3-STANDBY
FS51
+3V3
+3V310K
3S84
3S83
10K
10K
3S82 RES+3V3
3S45
10K
3S6C 4K7
3S67
4K712
3S64
10K
3S66
4K712
AB26
AA24AA25
R26R25R24
C26
A25
A24
A23
C25
B26
B25
B24
AA23
AB25
GPIO_10U23
GPIO_11
Y23GPIO_2
Y24GPIO_3
W21GPIO_4
W22GPIO_5
W23GPIO_6
V22GPIO_7
AE4
PNX855007S00-3
CONTROL
AD5
AC5
Y21GPIO_0
Y22GPIO_1
V23
IS05
2S89
FS2Y
100n
IS50
1 23S58
100R
1 2
FS31
3S5Z100R
3S00
33R
4K7
3S69
+3V3
3S55
5K6
FS2W
9S12
1 2 3S57100R
FS44
FS64
3S6A 4K7
10K3S6H-33 6
23S56
100R1
3S6B3S40
10K
4K7
10K
3S62
3S27
10K
FS53
3S6J
10K
10K3S80
+3V3
3S8110K
1 2
IS40
3S61100R
3S5Y
100R1 2
123S65
4K7
+3V3
FS10
2K23S6D
V6
AB2AA5AB3W2
W1W6W5W4W3U6
AA3
Y5Y6AB4AC1
AC2Y4
AA2
AA1AA4AB1
PNX855007S00-4
ETHERNET
AC3Y2Y3Y1
12
+3V3
3S68
4K7
1 2
+3V3
+3V33S60
100R
345678
910
+3V3
1F10
BM08B-SRSS-TBT
12
FS57
IS4Z
+3V3
10K
10K
3S26
3S6K
FS11
DS52
1 2
+3V3
3S5W100R
4K73S6F
+3V3IS04
IS09
3S6E 2K2
3S6G 4K7
9S13
3S21
10K 1 8
VSS
3S6H-110K
5SC0
8SC1
4LCS1 SD0
7SD12 SDA
3
VDD
6
7S01PCA9540B
10K3S6H-44 5
3S6H-210K2 7
+3V3
3S72
47R
9S11
FS49
+3V3
FS52
9S10
+3V3
FS50
BACKLIGHT-PWM
TXD2-MIPSRXD2-MIPS
EJTAG-TDO-PNX85500
EJTAG-TDI-PNX85500EJTAG-TCK-PNX85500
BOOST-PWM
RXD1-MIPS
TXD1-MIPSPXCLK54
USB-DM
GPIO1 GPIO1BOOTMODE
BOOTMODE
SELECT-SAW
SELECT-SAWPNX-SPI-CS-AMBIn
PNX-SPI-CS-BLn
SCL-BL
SCL-DISP
SDA-SET
SDA-DISP
SDA-BL
RESET-SYSTEMn
EJTAG-TMS-PNX85500EJTAG-TRSTn-PNX85500
EJTAG-TCK-PNX85500EJTAG-TDO-PNX85500EJTAG-TDI-PNX85500
EJTAG-DETECTn
EJTAG-TRSTn-PNX85500EJTAG-TMS-PNX85500
SDA-TUNERSCL-TUNER
SCL-DISP
SCL-BL
SCL-SET SDA-DISP
SDA-BLSDA-SET
SCL-DISP
SCL-BL
SDA-DISP
SDA-BL
SCL-SET
ETH-CRSETH-MDC
ETH-TXERETH-COL
SDA-UP-MIPSSCL-UP-MIPS
SDA-SETSCL-SET
SDA-SSBSCL-SSB
SDA-TUNERSCL-TUNER
SDA-UP-MIPSSCL-UP-MIPS
SDA-SETSCL-SET
SDA-SSBSCL-SSB
ETH-RXD(3)
ETH-RXDVETH-RXER
SDIO-DAT3SDIO-CLKSDIO-CMDSDIO-DAT0SDIO-DAT1SDIO-DAT2SDIO-CDnSDIO-WP
ETH-TXCLK
ETH-TXD(0)ETH-TXD(1)ETH-TXD(2)ETH-TXD(3)ETH-TXEN
BOOST-PWM
RXD1-MIPSTXD1-MIPSRXD2-MIPSTXD2-MIPSPNX-SPI-CS-AMBInPNX-SPI-CS-BLn
EJTAG-TCK-PNX85500
EJTAG-TDI-PNX85500EJTAG-TDO-PNX85500
EJTAG-TMS-PNX85500EJTAG-TRSTn-PNX85500
USB-DP
ETH-MDIO
ETH-RXCLK
ETH-RXD(0)ETH-RXD(1)ETH-RXD(2)
Circuit Diagrams and PWB Layouts EN 95Q552.1A LA 10.
2010-Apr-02 back to div. table
PNX Video Out - LVDS
18770_516_100118.eps100118
PNX Video Out - LVDSB02F B02F
2009-12-076
8204 000 8950PNX85500
LOUT1
A
NP
B
CLK
NP
C
NP
D
NP
E
LOUT2
NP
A
NP
B
NP
CLK
NP
C
NP
D
NP
E
LOUT3
A
NP
B
CLK
NP
C
NP
D
NP
E
NP
NP
LOUT4
A
NP
B
CLK
NP
C
NP
D
NP
E
NP
NP
NP
NP
7S00-7 C8
D
G
A
2
F
3 91
D
4
13
E
14
C
B
9 122
10
F
13
6
51 7
G
1211
B
A
6 11 14
5 87
8
C
10
E
4
3
D19
D14E14
E15D15
E17D17
D16E16
D18E18
E19
E7
E8D8
E10D10
D9E9
D11E11
E12D12
B15
C17B17
A16B16
A18B18
C19B19
D7
C10B10
A9B9
A11B11
C12B12
A14B14
C15
PNX855007S00-7
LVDSA7B7
C8B8
PX1A-
PX1D+PX1D-
PX1CLK+PX1CLK-
PX1C+PX1C-
PX1B+PX1B-
PX1A+
PX2CLK+PX2CLK-
PX2C+PX2C-
PX2B+PX2B-
PX2A+PX2A-
PX1E+PX1E-
PX3C-
PX3B+PX3B-
PX3A+PX3A-
PX2E+PX2E-
PX2D+PX2D-
PX4A+PX4A-
PX3E+PX3E-
PX3D+PX3D-
PX3CLK+PX3CLK-
PX3C+
PX4E+PX4E-
PX4D+PX4D-
PX4CLK+PX4CLK-
PX4C+PX4C-
PX4B+PX4B-
EN 96Q552.1A LA 10.Circuit Diagrams and PWB Layouts
2010-Apr-02 back to div. table
PNX Stand-by Controller
18770_517_100118.eps100118
PNX Stand-by ControllerB02G B02G
2009-12-076
8204 000 8950PNX85500
MC
PWM
SPI
P0
P1
P2
P3
P5
P6
345
0123
45
VD
D_X
TA
L
VD
DA
_AD
C2V
5
VD
DA
_1V
1_D
CS
01237
01234567
012
7
VS
S_X
TA
L
XTAL_IN
XTAL_OUT
RESET_IN
EA
ALE
PSEN
SDASCL
01
SDOSDI
CLKCSB
0123456
2 3
C
5
3S2H D7
D
E
F
G
7
1
2S13 B6
3S41 D123S42 C11
2S4E E2
H
A
B
3S43 C11
2S4F B9
2 3 4
3S1C C1
2S37 B52S4D C3
13
1
3S2F D73S2G D7
3S2A D2
3S2K D7
4 5 6
3S2V F11
E
F
G
H
C
D
2S11 B5
B
3S3Y D9
3S44 C11
2S4G B92S4K G103S1B C2
3S6V C11
6 7 8 9 12
3S1L E2
FS0Z G11FS45 G9IS20 B6IS2U G10
3S2L D103S2M E103S2S E10
8 9 10 11
1S02 B82S10 B6
A
3S3T D1
IS3F C10
3S6W D12
3S46 D103S47 E103S49 E10
9S0D G9
3S1D C23S1E C13S1F C23S1G D2
10 11
3S1K D1
DS50 B8
5S04 B67S00-9 B6
3S1P D11
3S3Q C2
3S3L C23S3M C13S3N C23S3P C1
12 13
IS2V D7IS2Z D7IS3B A6
7S20 G10
3S3W E9
3S3R D23S3S D1
9S0E G99S24 B6
3S1H D13S1J D2
IS3D C10IS3E C10
10p
2S4G
RES 3S4710K
10K3S3P
100R3S2K+3V3-STANDBY
3S2S
RES
10K RES
10K
3S2A
RES3S3N10K
2S4E
100n
10K
3S1L
10K3S1C RES
10K
3S44
IS3B
RE
S
9S0D
3S4210K
3S2H 100R
10K3S3YRES
100R3S2G
9S0E
2S4D1n0
RES 3S3S10K
IS3D
DS50
1
+1V
1
+3V3-STANDBY
3
3S2LRES10K
54M
1
+3V3-STANDBY
1S02
3S4610KRES
10K
3S1G
3S2V
12
FS0Z
10K
+3V3-STANDBY 3S1B
10K
AF25AE23
AA
17
AF
26
AC
17A
D17
AE17
AF17
AE24
AF22AE22
AC26
AD26AC25
AA26
AC24AC23
AF24AF23
AC21AD21
AE21AF21AA22AB22AC22AD22
AD23AE26AE25
AE19AF19AA20AB20
AC20AD20AE20AF20AA21AB21
AB23
AB24
AB17AA18AD18AE18AF18AA19AB19AC19
AD19
7S00-9PNX85500
STANDBY
IS2U
10K3S3W4K7
3S2MRES
RES3S1K
10K
2S4F
10p
4
NC
OUTP1
NCP303LSN287S20
5CD
3
GND
INP2
3S6W
RES
+3V3-STANDBY
4K73S3T10K
3S3M10K
3S2F 100R
100n
2S11
IS2Z
1u0
2S37
3S1H10K
4K73S49
100n
IS2V
2S4K
PO
L
10K
3S41
IS3E
IS20
10K3S1E RES
10K
3S1PRES
9S24
RE
S
3S1D27K
3S1J
100K
RES
RES
3S6V
4K7
3S3L
10K
+3V3-STANDBY
5S04
30R
3S1F
10K
RE
S
1FS45
100n
2S10
+3V3-STANDBY
2S13 1u0
IS3F
10K
3S43
RES3S3Q10K
LCD-PWR-ONnLCD-PWR-ONn
RESET-AVPIP
SPI-PROG
RESET-AVPIP
RES10K3S3R
RESET-ETHERNETnRESET-USBnRESET-DVBS
AUDIO-MUTE-UPRESET-AUDIO
SEL-HDMI-ARCRESET-ETHERNETn
RESET-USBnRESET-DVBS
CTRL-DISP
SPI-PROG
SDA-UP-MIPSSCL-UP-MIPS
FAN-CTRL1FAN-CTRL2POWER-OK
ENABLE-3V3n
AV1-STATUSAV2-STATUS
RESET-STBYn
PNX-SPI-WPn
DETECT2
RESET-STBYn
SEL-HDMI-ARC
CTRL-DISP
AUDIO-MUTE-UPRESET-AUDIO
TACHOCEC-HDMI
BACKLIGHT-PWM-ANA-DISPSDM
RXD-UPTXD-UP
RESET-SYSTEMn
KEYBOARD
SDA-UP-MIPSSCL-UP-MIPS
LED1LED2
PSEN
ALE
EA
LED1
LED2
PSEN
ALE
EA
EJTAG-DETECTnLAMP-ONSTANDBY
RCTACHOCEC-HDMIBACKLIGHT-PWM-ANA-DISPSDM
EJTAG-DETECTnLAMP-ONSTANDBYFAN-CTRL1FAN-CTRL2POWER-OKENABLE-3V3n
RXD-UPTXD-UPDETECT2
RESET-SYSTEMnAV2-BLKAV1-BLK
PNX-SPI-CLKPNX-SPI-CSBn
PNX-SPI-SDIPNX-SPI-SDO
KEYBOARDLIGHT-SENSOR
RC
Circuit Diagrams and PWB Layouts EN 97Q552.1A LA 10.
2010-Apr-02 back to div. table
PNX Power
18770_518_100118.eps100118
PNX PowerB02H B02H
2009-12-076
8204 000 8950PNX85500
VDDA_2V5
HDMI_VDDA_3V3_TERM
VDDA_2V5_LVDS_BG
VDDA_2V5_USB
VDDA_2V5_VADC
VDDA_2V5_VDAC
VDDA_3V3_USB
VDD_1V1
VDD_1V8
HDMI_VDDA_1V1
HDMI_VDDA_2V5
VDD_2V5
VDD_2V5_LVDS
VDD_3V3
VDD_3V3_SBY
VDDA_1V2
VS
SA
_US
B
VS
SA
_2V
5_LV
DS
_BG
VS
SA
_1V
1_LV
DS
_PLL
HD
MI_
AG
ND
VDD_1V1_DDR
VDDA_2V5_DCS
VDDA_2V5_ADAC
VDDA_2V5_AADC
VDDA_1V1_LVDS_PLL
VSSA
VSS
VSS
VSS
D
E
2S28 B3
1 2 3 4 13 14
1 2 3 4 5 6 7 8 9 10
F
G
H
I
2S21 F62S23 B62S26 A62S27 B3
E
F
G
H
I
A
B
C
5 6 7 8 9 10 11 12
2S29 C62S43 B22S45 F112S46 F112S4M B122S4N C112S4P C112S4Q B32S4R B42S4S F52S4T H112S4U D112S4V D112S4W D11
11 12 13 14
A
B
C
D
2S4Z E112S50 E112S51 E92S52 E92S53 H112S55 G112S56 G112S57 G112S58 H112S59 I112S5A A112S5B A112S5C B112S5D B112S5G-1 B42S5G-2 B4
2S5H-2 B52S5H-3 B52S5H-4 B52S5J-1 C52S5J-2 C52S5J-3 C52S5J-4 C52S5K-1 C42S5K-2 C42S5K-3 C4
2S5K-4 C52S5M G112S5P F52S60 A62S61 A62S62 A7
2S4Y D11
2S64 A72S65 A72S66 A72S67 A82S68 A82S6A A112S6B A112S6C C112S6D B112S6E B112S6F C112S6G C112S6H H112S6K H112S6L I112S6M I11
2S5G-3 B42S5G-4 B52S5H-1 B5
5S81 A125S82 A125S83 D125S84 E125S85 C125S87 F125S88 G125S89 H125S90 H125S92 I125S93 B125S94 F55S95 E107S00-10 B67S00-12 C1IS3K D10
2S63 A7
IS3L D10IS3Q A10IS3S A10IS58 I10c000 E13c001 B5
2S6N C112S6P C122SHW I115S80 A12
27
2S4Q
22u
2S5J
-2
100n
30R
5S88
100n
2S63
27
+1V1
2S5G
-2
100n
5
2S51
100n
100n
2S5H
-44
2S57
10u
2S68
100n
2S66
100n
100n
2S4U
2S65
100n
IS3L
+2V5
10u
2S58
100n
2S28
100n
2S67
c000
47u
2S23
100n
2S64
2S29
100u
2.0V
2S56
1u0
2S53
10u
+2V5-AUDIO
C13
R20
5S81
30R
C16C18
W20P20M20K20
V7Y8
Y19Y18
A13
A5
A6
B5
B6
N6N7
C7C9
C11C14
C6
D6
E6
F6
G6
F7
G7
L7 R6
R7
U7
Y7W7F9G9
AB5H20F11G11F13
J7
L6
R15R17U9U11U13
AC4
U15U17J6AA6
L15L17N9N11N13
AD3
N15N17R9R11R13
F19G19J9J11J13
AE2
J15J17L9L11L13
T20
Y13
Y10
R21
AF1
G13F15G15F17G17
U21
U22
B13
AA15Y15
AA13
Y12
AA9
AA7
Y17
D13
VDD
PNX855007S00-10
U24
V24
V20V21
U20
2S4S
10u RES
RE
S
2S5B 10
u
5S93
30R
12
30R
5S92
100n
2S6C
2S21
1u0
IS3S
+1V2
2S27
100n
5S89
30R
+2V5-AUDIO
10u
2S5A
12
RE
S
5S85
2S6G
100n
18
30R
100n
2S5K
-1
100n
2S6A
12
2S4Z
100n
IS3Q
2S4N
100n
100n
2S45
2
100n
2S5P
1
+3V3
+2V5
+2V5-LVDS
RE
S10
u
2S5D
5S84
+3V3
30R4
52S
5J-4
100n
2S55
100n
45
30R
5S82
2S5K
-4
100n
100n
2S5K
-22
7
12
+1V12S
61
100n
2S6B
100n
12
2S4W
100n
100n
2S6M
+1V1
1u0
2S59
5S90
30R
1u0
2S4Y
RE
S
27
5S83
30R
12
2S5H
-2
100n
+2V5
2S6K
100n
2S4P
10u
100n
2S5C
2
IS3K
2
5S94
30R
100n
2S6E
1
2S62
100n
100n
2S5H
-11
8
2S52
10u
6.3V
+2V5
+1V1
100n
2S60
100n
12
AA
16A
A8
Y11
Y14
Y16 Y9
2S6H
T7U4
V10V12V14V16V18
V2
A3
Y20
A8P6P7
T10T12T14T16T18
A26
T2T6
M6
M7N2
N20P10P12P14A19P16P18
P4
K2
K6
K7
L20 L4
M10
M12
A17
M14
M16
M18H4
H6
H7
J20
K10
K12
A15
K14
K16
K18
F20F8G10G12
G14
G16
A12
G18 G2
G20 G8
D2D20E13E20E4F10
A10
F12F14F16F18
7S00-12PNX85500
VSS
A1
B1B20C20C4
100n
2S6L
12
8
5S95
30R
100n
2S5J
-11
100n
2S43
100n
2S5G
-11
8
100n
2S6F
12
12
100n
2S6N
47u
2S26
2S6D
100n
12
+2V5-LVDS
5S87
30R
36
36
2S5G
-3
100n
100n
2S5H
-3
2S4M
220u
6.3V
+2V5
+3V3
22u
2S4R
100n
2SH
W
10u
2S50
100n
2S5M
30R
5S80
+3V3-STANDBY
2S4V
10u
IS58
10u
2S6P
100n
2S5K
-33
6
36
2S46
100n
2S5J
-3
100n
+1V8
5
POL
2S4T
100n
2S5G
-4
100n
4
c001
+2V5
SENSE+1V1
SENSE+1V2
EN 98Q552.1A LA 10.Circuit Diagrams and PWB Layouts
2010-Apr-02 back to div. table
PNX Analog Video
18770_519_100118.eps100118
PNX Analog VideoB02I B02I
2009-12-076
8204 000 8950 PNX85500
CVBS_Y7C7
6
INOUTSCLSDA
ANALOG_VIDEO
AV1
VGA
ATV_CVBS_Y3C3
CVBS1_OUTCVBS2_OUT
RESREF
REF
TUNERVGA_EDID
VSYNC
CURREF
12345
IF_AGCRF_AGC
PN
AGND
CVBS_Y1RBG
SYNCIN1Y_G1PR_R_C1PB_B1
CVBS_Y2SYNCIN2Y_G2PR_R_C2PB_B2
RGBHSYNC_IN
2S7N D62S7P D6
VGA
B
2S14 D12
F
2S16 D12
C
E
2S8G E6
F
G
H
YPBPR1
*
3S08 B113S09 C11
EU:
3
134
2S77 F12
3
3S4W F63S50 H6
2S7L C6
6 7 8
EU:
I
A
D
3S52 H6
2S7M C6
3S59 A63S5B A11
Connectivity
2S15 D12
2S18 D122S19 D12
13
2S85 H6
B
2S87 A62S8A A11
E
1 5
AP:
3S5T-3 I53S5T-4 I113S5V-1 I5
3S05 A11
IS5H E9IS5J E9
2
2S78 G122S7E G6
2S7J A62S7K B6
5
3S4T D6
2S7H B6
IS5D E9
3S54 I6
AP:
= TCON ONLY
EU:
14
A
C
D
2S7U F62S84 G6
3S5T-1 I5
2S86 H6
3S5V-4 I12
IS5G E9
3S75 E123S76 F12
BS15 F9BS17 F10
9S14 I39S15 I3
6 7
41 2
3S4P D63S4R D6
BS13 E9
3S4U F6
**
AP:
3S5V-2 I123S5V-3 I5
-
G
H
I
21119
3S5L E63S5S E9
3S5T-2 I11
EU:
YPBPR2
SCART1
AP:
VGA
7S00-1 D8
3S4J A6
IS4W C10
8 9 10 11 12
2S22 A11
14
2S75 F112S76 F11
BS09 F9BS10 F10
IS11 F13
IS5C D9
9S17 A13
3S5E B11
IS5E E9
SCART2
10
2S7Q E62S7R F6
YPBPR1
IS5F E9
3S4G G6
2S40 B11
3S4K C63S4L B6
+CVBS
IS4V B10
56R
3S05
2S22
22n
BS13
IS4V
3S50
56R
56R
3S4P
3S59
47R
100R
3S5V
-22
7
9S14
22n
2S14
IS5H
560R
3S5E
27
45
100R
3S5T
-2
100R
3S5T
-4
AF12AE12
AC18AF4
AE15
AE14
9S17
AB13AB12AA12AA10
AB10
AB11
AF16
AD24AD25
AF15
AF14
AD11
AD16
AB18 AD12
AD15
AD14
AC15
AC14AC16AB16
AD13AE13
AC13
AE16
AF13
AC11
AA11
AF11AE11
AB15
AB14
7S00-1PNX85500
AA
14
AC12
IS5DIS5F
3S4U
56R
IS5E
22n
2S8A
3S5T-33 6
2S86
22n
100R
22n
2S7U
2S7K22n
IS5C
9S15
IS11
22n
2S18
3S4L
56R
22n
2S16
56R
3S4G
2S84
22n
IS5G
3S5B
47R
22n
2S7P
100R
3 6
BS15
3S5V-3
3S5L
47R
2S7E
22n
2S76
10n
BS10
22n
2S7J
3S09
8K2
IS4W56R
3S4K
47K
3S75
22n
2S85
2S87
22n
56R
3S4W
56R
3S4J
3S4R
56R
10n
2S7Q
BS17
3S76
47K
3S5T-11 8
100R
2S40
47p
22n
2S8G
2S78
10n
10n
2S752S7R
22n
22n
2S7H
BS09
22n
56R
3S4T
2S7N
100R
3S5V-11 8
22n
2S15
10n
2S77
IS5J3S
54
56R
3S08
560R
3S5S10K
22n
2S7L
100R
3S5V
-44
5
22n
2S19
2S7M
10n
56R
3S52
VGA-SCL-EDID-TCON
VGA-SDA-EDID-TCON
VGA-SDA-EDID
C-SVHS
Y-SVHS
YPBPR1-SYNCIN1
AV4-Y
AV4-PR
AV4-PB
R-VGA
B-VGA
YPBPR2-SYNCIN2
CVBS-MON-OUT1
PNX-IF-AGC
PNX-IF-N
PNX-IF-P
PNX-RF-AGC
V-SYNC-VGA
H-SYNC-VGA
VGA-SCL-EDID
AV1-CVBS
AV1-G
AV3-Y
AV3-PR
AV3-PB
AV1-B
AV1-R
G-VGA
AV2-CVBS
Circuit Diagrams and PWB Layouts EN 99Q552.1A LA 10.
2010-Apr-02 back to div. table
10-11 B03 820400089514 CLASS DAudio
18770_520_100118.eps100218
AudioB03A B03A
2009-10-224
8204 000 8951CLASS D
VIA VIA
VIA
VIA
VCLAMP
MUTE
IN
BSL
SD
R
AVCC
L
BSR
GND_HS
L
PGNDAGND L R
L
OUT
R
BYPASS
1
R
0
PVCC
GAIN
7D15 B3
ID29 C5ID30 C5ID31 C6
7D11-2 D37D13-1 E17D13-2 E2
ID32 C6ID33 F4ID34 D3
3D14-4 B73D15-1 E23D15-2 E3
2D19 B62D20 B5
3D15-4 D5
MAINS SWITCH DETECT
ID10 C7ID11 A4
ID19 C5ID27 B6ID28 B6
6 7
7D15 C3CD10 D5
ID35 D3ID36 E2
FD03 B1FD05 E8
FD06 E8FD07 F4FD14 A5
ID37 D4ID38 D5ID39 E2
2D11 C82D12 C82D13 F82D14 E82D16 C42D17 C4
2D01 F72D02 F4
2D21 D8
3D16 A55D01 C7
5D04 C85D05 C85D07 A65D08 A66D01 E3
ID12 A5ID13 E3ID14 B3ID15 B3ID18 C5
1 2 3 4 5
2 3 9
3D04 E2
FD01 B1FD02 F8
3D06-3 F33D06-4 F33D09 A33D10-1 D83D10-2 D8
ID05 C8ID06 C8ID07 C8ID08 C8ID09 C7
C
D
1D38 E91D50 E81D52 F8
C
D
E
2D22 B82D23 B4
5D02 C75D03 E7
2D27 D82D28 B22D29 B23D01-1 D33D01-2 D3
7D03-1 A57D03-2 F57D10-1 B67D10-2 E57D11-1 D2
2D09 C72D10 C7
8 9
1
A
B
3D06-1 F43D06-2 F4
4 5 6 7 8
3D10-3 D73D10-4 D73D14-1 B83D14-2 B83D14-3 B7
E
5
3
4
F
A
B
F
1735 E8
2D24 B42D26 B8
2D03 E32D05 A52D06 A52D07 B52D08 B6
3D01-4 E23D02 B33D02 C33D02 B43D02 C4
BC847BS(COL)7D11-2
2D03
100p
+AVCC
BZX384-C
6D01
3D14
-4
22K
54
72
22K
3D14
-2
GND-AUDIO
GND-AUDIO
2D16
1u0
7D13-1BC847BS(COL)
2
6
1
+24V-AUDIO-POWER
7D13-2BC847BS(COL)
5
3
4
220n
2D10
2D22
220n
22K
3D10
-18
1
5D07
220R
ID31
3 10 12
615
2
11
17
25
522
4
23 24 13 14
1
8 919 20
21
16
7
18
7D10-1TPA3120D2PWP
CLASS-DΦ
AUDIO AMP
2D23
47n
220R
5D08
5D03
220R
ID08ID18
72
2
6
1
3D01-2
47K
7D11-1BC847BS(COL)
ID30
GND-AUDIO
2829
30 31 32 3334
VIA26
353637
38394027
ID37
TPA3120D2PWP7D10-2
FD06123
10n
2D13
6 1
1D38
1735446-3
BC847BS(COL)7D03-1
2
ID27
2D08
220n
2D11
220u25V
4K7
3D15-1 81
ID32
2D06
220n
FD14
CD10
ID29
45
ID11
ID13
3D15
-4
4K7
ID09
GND-AUDIO
22K
3D10
-45
4
ID33
45
220n
2D07
8
3D01
-4
47K
47K
3D01
-11
GND-AUDIO
ID05
1735
1735446-4
1234
8 1
ID07
GND-AUDIO
3D06-1
100K
220R
5D04
100K
3D06-33 6
ID06
ID38
GND-AUDIO
10u
2D02
1D50
V_N
OM
81
1u0
2D17
3D14
-1
22K
27
1u0
2D28
3D15-2
4K7
5D05
220R 25V 220u
2D12
2D20
220u
35V
72
22u
5D01
3D10
-2
22K
GND-AUDIO
3D04
2K2
+24V-AUDIO-POWER
GND-AUDIO
5
3
4
FD01
7D03-2BC847BS(COL)
FD02
5D02
2D05
10u
35V
22u
63
GND-AUDIO
GND-AUDIO
3D14
-3
22K
2D14
10n
FD05
ID36
ID34
2D19
220u
35V
+3V3-STANDBY
ID14
ID35
ID10
3
4
GND-AUDIO
220n
2D21
1
BC847BS(COL)7D15-25
BC847BS(COL)7D15-12
6
1u0
2D29
3D02-2
4K7
7 2
ID39
3D10
-3
22K
63
22K
3D16
1D52
V_N
OM
GND-AUDIO
6 3
+3V3-STANDBY
18
4K7
3D02-3
45
3D02
-1
4K7
4K7
3D02
-4
+A
VC
C
ID19
3D06-2
100K7 2
2D26
220n
ID12
3D09
4R7
10n
2D01
FD03
GND-AUDIO
ID28
GND-AUDIO
+3V3-STANDBY
GND-AUDIO
FD07
47n
2D24
4 5
GND-AUDIO
GND-AUDIO
3D06-4
100K
2D27
220n
GND-AUDIO
ID15
2D09
220n
LEFT-SPEAKER
RIGHT-SPEAKER
A-PLOP
AUDIO-MUTE-UP
+AUDIO-L
-AUDIO-R
MAINS-OK
A-STBY
DETECT2
LEFT-SPEAKER
RIGHT-SPEAKER
LEFT-SPEAKER
RIGHT-SPEAKER
EN 100Q552.1A LA 10.Circuit Diagrams and PWB Layouts
2010-Apr-02 back to div. table
DC/DC
18770_521_100118.eps100118
DC/DCB03B B03B
2009-10-224
8204 000 8951DC/DC
2VFB
12
TRIP
DRVL
12
DRVH
12
SW
12
PGND
12
TEST
12
VREG5V5FILT
12
VIN
GND
VBST
12
EN
12
VO
1
15
E
F
G
H
2U00 D22U01 E32U02 D4
8 9 10 11 12
2U04 F42U05 F42U06 F12U07 H3
2U08 G92U09 F9
1 14
11 12 13 14
2U03 E2
12V/1V1 CONVERSION
7
A
B
C
D
13
1 2 3 4 5
RES
2U19 B12
2U20 B142U21 C62U22 D8
15
A
B
C
2 3 4 5 6
3U05 E43U08 G23U09 H33U10 H3
12V/1V8 CONVERSION
2U10 F102U11 F9
2U12 F112U13 F12
6 7 8 9 10
3U20 F113U21 G133U22 G2
3U23-1 C9
2U23 B5
2U24 B52U25 B122U29 G14
D
E
F
G
H
5U01 E10
5U02 B135U03 A136U00 E8
IU08 D4IU09 C6
9F 81UI6B 01UI7U00 F1
7U01 D87U02-1 B67U02-2 C67U03 E3
7U04 E8CU00 H7
2U14 E142U15 C10
2U16 C102U17 C92U18 D9
IU05 D3IU06 D3
IU21 H9IU22 B13IU23 C9
IU24 E3IU25 F4
FU06 E8IU01 F3IU02 F3IU03 F1
7D 21UI3G 40UIIU13 D7IU14 E8
IU11 C6
3U23-2 C93U23-3 C93U23-4 C8
3U24-1 F93U24-2 F9
3U00 F1
3U01 F13U02 F23U03 F33U04 D3 IU15 C9
IU16 E5IU17 F9
3U24-3 F93U24-4 F8
3U27 D53U28 D55U00 C10
IU07 D4 IU19 G10
IU20 G9
FU00 G13FU01 E14
FU02 B9FU03 C14FU04 F4FU05 B9
3U11 B63U14 D73U17 G103U18 G10
3U19 G9
3R3
3U05
FU05
22K
3U02
IU14
+1V1
45
GND-SIG
47R
3U23
-4
2U09
1n0
2U12
47u 2U
14
100u
2.0V
RE
S
10u
2U19
47R
3U24
-4
22u
2U16
IU24
1u0
2U20
2U21
220p
IU03
+1V1
3U17
330R
1%
1n0
2U18
10u
2U00
IU09
+1V8
IU16
IU07
IU25
GND-SIG
10u
2U24
1n0
2U11
GND-SIG
+1V8
18
2U02
100n
+12V
3U23
-1
47R
IU23
GND-SIG
IU19
GND-SIG
5U02
30R
IU20
GND-SIG
3U24
-3
47R
1%
GND-SIG
1K03U
09
RE
S
2U03
1n0
GND-SIG
FU02
FU06
IU21
100p2U
08
3U23
-3
47R
36
RE
S
IU10
GND-SIG
IU05
+3V3-STANDBY
10u
2U23
RE
S2U
29
100n
IU11
IU18
IU06
3U24
-1
47R
3U20
10R
BC847BW
13
2
RE
S
GND-SIG
GND-SIG
7U00
FU00
IU13
GND-SIG
RE
S10
0p
2U07
IU15
IU02
100n
2U01
1K0
3U18
2u0
1%
5U01
IU08
2U10
1u0
7 84
1 2 3
2U04
10u
SI4778DY7U01
5 6
100R 1%
22u
2U13
1%
3U21
3U08
330R
1 2 3
3U22
1K0 1%
7U04SI4778DY
5 6 7 84
27
47R
3U23
-2
3U03
22K
IU01
3U04
3R3 3U
14
3R3
47R
3U24
-2
6U00
ST
PS
2L30
A
2U25
10u
220p
2U22
+1V1
47u
2U15
IU04
5K6
3U19
20
49
19
13
717
2116
18
211
58
112
2314
310
6
2215
24
7U03TPS53126PW
2U05
1u0
3U01 10
K
5 6
4
3
10K
7U02-2SI4952DY
3U00
GND-SIG
CU00
1
22K
3U10
SI4952DY7U02-1
7 82
3u6
IU12
5U00
3U27
10R
3R3
3U11
+1V8
IU22
FU04 IU17
3U28
10R
2U17
1n0
RES
FU01
5U03
30R
FU03
2U06
100n
ENABLE-1V8
SENSE+1V1
Circuit Diagrams and PWB Layouts EN 101Q552.1A LA 10.
2010-Apr-02 back to div. table
DC/DC
18770_522_100118.eps100118
DC/DCB03C B03C
2009-10-224
8204 000 8951DC/DC
9U42 B4FU07 C3FU48 C1FU49 C1
3U67 D23U68 B33U69 B33U70 B4
FU72 F4
IU56 C3IU57 F6IU61 E4
7U42 B57U43 B37U48-1 C67U48-2 E69U41 B5
IU48 E4IU49 E3IU50 F4IU51 F3IU52 F5IU55 D3
FU50 C1FU51 C1FU52 C3FU53 C2FU54 C2
IU62 F4IU63 F3IU64 C6
FU63 E1FU64 F1FU65 F1FU66 F1FU67 F1FU68 F1
2U68 E1
3U71 D33U72 F33U73 F33U74 A43U75 A4
FU73 E5FU74 D1IU40 E5IU41 D5IU43 B5IU44 B5IU45 B4IU47 B4
3U84 D26U40 E37U40-1 F47U40-2 E47U41-1 F47U41-2 F5
4 5 6 7 8 9
A
B
C
D
∗FU55 C1FU56 D1FU57 D1FU58 E1FU59 E1FU60 E1FU61 E1FU62 E1
3U63 F53U64 C23U65 D23U66 D2
2U42 C22U43 D22U44 D32U45 D32U46 D32U47 E12U48 F12U49 F12U50 F12U51 D1
2U71 D52U72 D13U41 B53U42 C33U43 C3
3U76 F23U80 F43U81 C33U82 C53U83-1 D63U83-2 E53U83-3 E53U83-4 C5
3U60-4 F53U61 E53U62-1 F43U62-2 E33U62-3 E43U62-4 E3
1 2 3
E
F
A
Boptionally 1M99 is a 9 pin connector
∗
C
D
1M99 C11U40 E22U41 B1
1 2 3 4 5
2U52 D12U53 D22U54 F22U55 F3
3U44 C33U45 C33U53 B63U56 D33U59 B63U60-1 F53U60-2 F43U60-3 E5
6 7 8 9
E
F
1M95 E1
23456789
FU61
1-1735446-1
1
1011
+24V-AUDIO-POWER
1M95
10n
2U54
3U71
100R
3U84
RES100R
2U43
10n
IU44
2U42
1u0
IU48
BC847BS(COL)
5
3
4
+3V3-STANDBY
7U41-2
IU57
IU61
3U42
100R
FU07FU54
RE
S
2U48
100p
FU56
1K0
3U72
2U53
1n0
RES
3U56
10K
BC847BW7U42
RES1K0
3U82
FU59 FU73
IU50
IU51
+3V3-STANDBY
34
IU62
BC857BS(COL)7U48-2
5+3V3-STANDBY
10K
3U70
2
61
8 1
+3V3-STANDBY
7U48-1BC857BS(COL)
3U60-1
22K
2U49
RE
S10
0p
10n
2U46
3U66
GND-AUDIO
RES 100R
7U43BC847BW
FU63
3456789
1M99
1-1735446-2
1
101112
2
45
10K
3U62
-4
RE
S10
K
3U74
81
FU48
100K
3U83
-1
9U42RES
FU50R
ES
2U55
1u0
RES
IU49
10K
3U59
+3V3
+12V
FU64
100p
RE
S
IU45
RE
S
2U72
3 6
3U75 10
K
100K
3U83-3
RE
S
FU65
10K
3U69
IU40
10K
3U53
FU60
2U68
1u0
6
1
FU55
7U40-1BC847BPN(COL)
2
2U45
1n0
27
3U68
10K
3U83-2
100K
IU64
2U71
100n
FU72
FU67
2U51
18
RE
S10
0p
10K
3U62-1
2U41
100p
RES
FU52
FU49
100R
3U43
IU43
10n
2U50
+3V3
IU52
IU63
+3V3-STANDBY
+12VD
100R
3U45
100p
2U44
3U73
53
4
3K3
7U40-2BC847BPN(COL)
FU68
FU53
100R RES
3U67
IU56
10K
3U61
RE
S
10K
3U81
3U44
100R
IU47
FU513U
62-2
10K
27
4 5
+5V
3U83-4
100K
6U40
BZ
X38
4-C
6V2
RES
3U41
10K
RE
S1K
0
3U65
3U64
1K0
+3V3
BC847BS(COL) 2
6
1
2U47
10n
45
7U41-1
3U60
-4
22K
FU58
FU62
10K
3U63
RE
S
+3V3
IU41
FU74
3U60-3
22K
3 6
3U62
-3
10K
36
100p
2U52
RE
S
3U76
100R
FU57
9U41
3U60
-27
2
FU66 22K
4K7
3U80
IU55
T 32V3.0A
1U40
ENABLE-3V3-5V
BL-SPI-CSn
BL-SPI-SDO
BL-SPI-CLK
BACKLIGHT-PWM_BL-VS
BACKLIGHT-BOOST
BACKLIGHT-PWM-ANA-DISP
STANDBY
MAINS-OK
LED2
LED1
POWER-OK
ENABLE-3V3n
DETECT2
ENABLE-1V8
LAMP-ON
LED-1
LED1
LED-2
LED2
EN 102Q552.1A LA 10.Circuit Diagrams and PWB Layouts
2010-Apr-02 back to div. table
DC/DC
18770_523_100118.eps100118
DC/DCB03D B03D
2009-10-224
8204 000 8951DC/DC
COM
OUTIN
NCNC
A
REF
K
OUTIN
INH BP
COM
C
D
E
2UA1 A42UA2 B5
RESERVED
1 2 3 4 5 6 7 8 9
1 2 3 4 5 6
D
9
A
E
F
A
B
∗
2UA5 B62UA6 B72UA7 D42UA8 D52UA9 D52UB0 C72UB1 D62UB2 D72UB3 F62UB4 F62UB5 F82UB6 F82UB7 F72UB8 D2
F
2UA0 A5
3U15-1 C83U15-2 C8
2UA3 B52UA4 A7
3U16-1 C93U16-2 C93U16-3 D93U16-4 D93U25-1 E33U25-2 E33U25-3 E23U25-4 E23U26-1 F33U26-2 F33U26-3 F33U26-4 F33U29-1 E33U29-2 E33U29-3 E33U29-4 F33UA0 A23UA1 A33UA2 B3
7 8
3UA5 A63UA6 B5
B
C ∗
∗
∗
3UA9 D53UB0 D63UB1 E63UB2 E6
3UB3 F63UB4 F53UB5 F5
3U12 C33U13 C3
3UB6-3 C23UB6-4 C2
3U15-3 D83U15-4 D8
RESERVED
NOT FOR 5000 SERIES
* 3UB7-3 D23UB7-4 C25UA0 E87U06-1 F27U06-2 F17UA0 B27UA1-1 A57UA1-2 C57UA2 A67UA3 C6
3UA3 B43UA4 A4
7UA6 C37UA7-1 C3
3UA7 B63UA8 B5
CUA0 B9FUA0 A2FUA1 A7FUA2 D5FUA3 D7FUA4 B9IU26 C3IU29 E2IU30 F3
3UB6-1 C23UB6-2 C2
IUA3 A6IUA4 A6
3UB7-1 D33UB7-2 D2
IUA7 C4IUA8 D5IUA9 B6
7UA4 E57UA5 E8
IUB0 F6IUB1 E8
7UA7-2 D27UC0 A8
IUB2 C2IUB3 C3
3U15-33 6
IUB4 D3IUB5 C2IUB6 B3
IUA1 A4IUA2 B5
IUA5 C6IUA6 E5
470R
1 8
100R
RES3U26-1
3UA7
1K0
3
4
IU29
IU30RES
BC847BS(COL)7U06-2 5 7U06-1
BC847BS(COL)2
6
1
3U25-4
RES
4 5
RES
+3V3
100K
1%33
0R
3U12
330p2U
A2
3UB5
100K
IUA8
IUB1
5 3
12
4
7UA4TS431AILT
+5V5-TUN
IU26
FUA1
FUA33U16-4
100R
4 5
7UA7-2BC847BS(COL)
5
3
4
RES
+2V5-REF
330p
2UB4
2UB
8
22u
IUA1
2 7
+12V
IUA9
470R
3U26-2 RES
3UB0
22R
2
6
1BC847BS(COL)
7UA7-1
2
1 3
2UB
0
1u0
LF25ABDT7UC0
2 7
+3V3
+5V
1 8
100R
3U15-2
100R
3U15-1
PHD38N02LT7UA3
BC817-25W7UA6
3UA
4
+3V3
+2V5-LVDS
1K0
2UA
6
1u0
3UB1
IUA5
1K0
8
CUA0
3UB
7-1
470R
1
3UB6-1
1K01 8
+12V
+12V
FUA2
IUB6
3UA1
3K3
1%
1n02U
A3
30R
5UA0
RES
470R
3 6
3U29-2
470R
2 7
3U29-3
RES1 8
RES
3U26-33 6
470R
3U29-1
470R
RES
IUA4 1u0
2UA
4
3
21
84
27
7UA1-1LM833
3UB
7-2 47
0R
6
2UB
5
100n
RES
3U25-3
100K
3
100K3U
25-1
RE
S
81
3U25
-2
100K
27
3UA
6
1K0
RE
S
+2V5-REF
4 5
2UB
2
1u0
470R
3UB7-4
22K
3UA
8
3UA
9
+5V-TUN
+1V2
1K0
3U15-44 5
+5V
FUA0
100R
RE
S
+5V5-TUN
1u0
2UB
1
RES4 5
+12V
IUB5
470R
3U26-4
+3V3
1
3
5
1u0
2UB
7
LDS3985M507UA5
4
2
3UB6-3
1K03 6
IUB0
2UA
8
330p
+1V8
IUA3
3UA
0
2K2
1u0
2UA
5
A
3
1
K
2
R
+2V5
7UA0TS2431
3UB
3
4K7
+12V
2UA
9
1n0
6
+5V-TUN
3U16-3
100R
3
3U16-1
100R
1 8
4 5
+3V3
RES3U29-4
470R
3UA2
3K3
1%
IUB3IUB2
2UB
6
1u0
330R
3U13
5
67
84
1% 7UA1-2LM833
2UA
7
100n
22n
2UB3
+2V5-REF
+5V
100n
2UA0
4 5
IUA6
1K0
3UB6-4
3UA
3
47K
IUB4
IUA2
FUA4
IUA7
470R
3UB
7-3
36
3U16-2
100R
2 7
2UA
1
100n 22R
3UA5 1
33UB4
1K0
7UA2PHD38N02LT
2
3UB6-22 71K0
ENABLE-1V8
4K7
3UB
2
SENSE+1V2
Circuit Diagrams and PWB Layouts EN 103Q552.1A LA 10.
2010-Apr-02 back to div. table
DC/DC
18770_524_100118.eps100118
DC/DCB03E B03E
2009-10-224
8204 000 8951DC/DC
GND
VIN
HSPA
INH
SYNC
SW
VFB
A
SW
COM
OUTIN
GND
VIN
HSPA
INH
SYNC
SW
VFB
A
SW
COM
OUTIN
VIA
VIA
5UD0 A25UD1 A55UD2 C55UD3 C26UD0 A66UD1 E47U05-1 B77U05-2 D77UD0-1 A47UD0-2 B47UD1-1 C47UD1-2 D4
IU28 D8IUD0 A2IUD1 C2
3UD2 B63UD3 D53UD4 D5
8
1 2
(∗∗)
8
A
B
C
D
3UD5 D5
NOT FOR 5000 SERIES
IUD2 D5IUD3 A5IUD4 C5IUD5 E4IUD6 B6IUD7 A5
2UE1 D52UE2 D62UE3 D6
∗
F
2U27 B82U28 D82UD0 A22UD1 A2
7UD2 E57UD3 F5FUD2 C5FUD3 A7IU27 B8
∗
2 3 4 5 6 7
3 4 5 6 7
2UD6 B62UD7 B62UD8 C22UD9 C22UE0 C3
C
D
E
∗
2UD4 B5
(∗)
2UD2 A32UD3 B3
2UE4 D62UE5 E42UE6 E62UE7 F42UE8 F52UE9 B83U06 B83U07 D83UD0 B53UD1 B5
A
B
1
FOR 5000 SERIES ONLYE
F
100n
2U28
RE
S
2UD5 B5
+5V
+1V1
16V
220u2U
D6
16V
22u2U
E6
2UE
4
220u
16V
IUD210
0n
2UE
5
IUD4
IUD1
2UD
4
IUD3
22u
35
1 6
4 9
2
8
7
7UD0-1ST1S10PH
1n0
2UD
3
+12VR
ES
10u
2UD
0
10u
2UD
9
+12V
6UD0
SS36
4n7
2UE
1
3UD3 100K
1%
IUD7
RES
5
3
4
BC847BS(COL)
7U05-2
33K
3UD
1
1%
+3V3
22u
2UE
2
FUD2
30R
5UD3
S1D
6UD1
1
3 2
7UD2LD1117DT25
2UE
7
100n
+5V
RE
S
22u2U
E9
3u6
5UD2
3UD
4
1M0
2UE
8
22u
16V
IUD5
3U07
RE
S
120K
3UD2
10K
1%
+1V1
3UD
5
33K
3U06
10K
RE
SR
ES
2U27
100n
+2V5
1415
2UD
8
10u
7UD0-2
10
11
12
13
7UD1-2ST1S10PH
10
11
12
13
1415
ST1S10PH
+5V5-TUN
10u
2UD
2
2UD
1
10u
2UD
5
22u
IUD6
2UE
3
22u
30R
1
3 2
5UD0
+3V3
7UD3LD1117DT33
4n7
2UD7
5UD1
3u6
IU28
2
6
1
IU27BC847BS(COL)7U05-1
RES
FUD3
6
2UE
0
10u
4 9
2
8
7
35
1
1%
ST1S10PH7UD1-1
3UD
0
68K
IUD0
ENABLE-3V3-5V
ENABLE-3V3-5V
EN 104Q552.1A LA 10.Circuit Diagrams and PWB Layouts
2010-Apr-02 back to div. table
Temp Sensor + AmbiLight
18770_525_100118.eps100118
Temp Sensor + AmbiLightB03F B03F
2009-10-224
8204 000 8951DC/DC
5UM1 A3
E
A
4
IUM0 A4
D
B
1
C
D
1UM0 A4
FUM0 A5
2 7
B
A
5 62 3
E
C
5UM0 A3
1 5 6
7
3 4
FUM01UM0
1.0A+3V3
63VT
+5VRES
5UM0
30R
IUM0
30R
5UM1V-AMBI
Circuit Diagrams and PWB Layouts EN 105Q552.1A LA 10.
2010-Apr-02 back to div. table
Fan Control
18770_526_100118.eps100118
Fan-ControlB03G B03G
2009-10-224
8204 000 8951DC/DC
3US7 A43US9 B67US1-1 A57US1-2 B5
3US4-1 A43US4-2 D43US4-3 C43US4-4 C53US5-1 B63US5-2 A63US5-3 A53US5-4 B53US6 C6
4
1 2 3 4 5 6
A
7 8 9
1
E
F
2US3 A73US2 A33US3 B3
76532
IUS9 B6IUT1 A4IUT2 B4
8 9
A
B
C
D
IUS7 B7IUS8 B6
7US1-3 C57US1-4 D57US2 A67US3 B69US0 D4IUS0 D5IUS3 A5IUS4 B5IUS5 C5IUS6 A6
+3V3
+3V3
B
C
D
E
F
10K
2S
U33
SU3
10K
+12V
2US
3
100n
IUS5
+12V
10K
3US
4-3
36
3US7
1K0IUS3
45
+12V
+12V
1
3US
4-4
10K
3US
5-1
10K
8
IUS7
+12V
7US2BC807-25W
6 3
27
10K
3US5-3
3US
5-2
10K
3US
9
22R
3
12
RE
S
9US
0
7US1-2LM339P11
1013
9
814
3
12
IUT2
LM339P7US1-1
IUT1
5 4
27
10K
3US5-4
10K
3US
4-2
3US
6
47R
+12V
BC807-25W7US3
IUS9
+3V3
+12V
12
IUS8
LM339P7US1-3
5
42
3
IUS6
+12V
7
61
312
7US1-4LM339P
3US
4-1
18
IUS0
+12V
10K
TACHO
FAN-CTRL1
FAN-CTRL2
IUS4
FAN-DRV
TACH02
TACH01
EN 106Q552.1A LA 10.Circuit Diagrams and PWB Layouts
2010-Apr-02 back to div. table
Vdisp Switch
18770_527_100118.eps100118
VDisp-SwitchB03H B03H
2009-10-224
8204 000 8951DC/DC / CLASS D
2
4
4 5
IUU4 C6
7UU0 B4
9UU0-4 A4
D
51
IUU2 C5
2UU1 C4
3UU2 D6
9UU1-1 A4
VDISP-SWITCH
3UU3-4 C7
D
9UU0-2 A4
9UU1-4 A4
9UU1-2 A4
E
3UU3-3 C6
9UU1-3 A4
2UU0 C63
3UU0-3 C2
3UU3-1 C4
FUU0 A5
9UU0-3 A4
3UU0-2 C4
7
3
A
BB
IUU5 C7
7UU1 B57UU2-1 C3
IUU1 C4
A
1
E
C
IUU0 C3
IUU3 C6
6
C
7UU3 C69UU0-1 A4
7
3UU3-2 C5
2
6
7UU2-2 C3
3UU0-1 C4
IUU2
IUU6 D6
3UU1 C4
2UU1
FUU0
+VDISP-INT
1u0
2
7UU3BC847BW
RES
13
+3V3
2UU
0
100n
47R
3UU15
3
4
+3V3-STANDBY
6
1
PUMD127UU2-2
7UU2-1PUMD12
236
9UU1-1RES
1 8
3UU0-3
47K
RES9UU1-22 7
9UU1-3RES
3 6
RES9UU0-44 5
7
9UU0-3RES
3 6
1
RES9UU0-22
2
3UU
0-1
47K
8
3UU0-27
8 1
IUU0
47K
5
3UU3-1
47K RES
3UU3-4
47K RES
4
47K
3UU3-3
RES
6 3
3UU3-2
RES
2 7
9UU0-1RES
1 8
47K
+12VD
SI4835DDY
+3V3
7UU0
RES
4K7
3UU2
RES
RES9UU1-44 5
IUU6
IUU1
SI3441BDV
IUU3
7UU1
IUU5IUU4
LCD-PWR-ONn
Circuit Diagrams and PWB Layouts EN 107Q552.1A LA 10.
2010-Apr-02 back to div. table
10-12 B04 820400089524 Analog I/OAnalogue Externals A
18770_528_100118.eps100218
Analogue Externals AB04A B04A
2009-10-224
8204 000 8952CLASS D
FE83 G4FE84 G4FE85 G5FEA0 A7FEA1 B7
IEC0 A7IEC1 A6IEC2 B7
* EU
IE54 E1IE55 F1IE56 E9IE57 F9IE59 E8
RES
RES
FE60 A12FE61 B12FE62 B12FE63 D12FE64 D12
IE60 E6IE61 E6IE62 H10IE67 A8IE68 B8IE70 E7IE89 D7IE90 D7IE91 G6IE92 G7IE93 H7IE94 H6IE96 G6
7E09-2 G109E01 D69E02 D79E05 F49E06 G4
RES
9E07 F4
FEC8 B13IE05 D10IE08 E5IE13 D6IE14 F5IE16 F5IE17 G5IE18 E3IE20 B10IE21 C10
IE22 B2IE23 C2IE48 G2IE51 G10IE52 H2IE53 D1
6E22 E36E23 D36E24 D116E26 F36E28 F3
* EU
AP
FE66 E12FE67 E12FE68 D12FE70 A5FE71 B4FE72 C4FE73 E4FE74 E4FE75 E4FE76 G12FE77 H12FE78 H12FE79 F13FE80 E4FE81 F4FE82 F4
3EB6-4 G63EB9-1 H63EB9-2 I133EB9-3 I133EB9-4 I6
(AV1)
9E08 F49E09 G49E10 F49E50 D19E51 D29E52 E19E53 E29E54 F19E55 F2BEC0 D10BEC1 E10BEC2 F10BEC3 D2BEC4 E2BEC5 F2FE55 D9
3E78 F23E79 F23E80 C103E82 D103E83 E10
RES
RES
6E29 H36E30 I36E31 I116E32 I36E34 E116E35 F116E36 G116E37 H117E01-1 A67E01-2 B67E04 H67E05 G67E06-1 E77E06-2 E67E09-1 H2
3E37-2 G133E37-3 H133E37-4 A33E39 H103E43 H2
* EU
SCART2
AP
* EU
5E73 D25E74 E25E76 F25E77 D105E78 E105E79 F105E80 E86E01 A36E02 E116E03 B36E07 C36E08 B116E09 D36E10 A116E12 C116E14 C11
2E99 E82EA4 A72EA5 B72EB1 D62EB3 E73E07-1 C3
3E84 E103E85 F103E86 F103EA1 D63EA2 D63EA7-1 A73EA7-2 H133EA7-3 H133EA7-4 B73EB1 E63EB3 E63EB6-1 G63EB6-2 H133EB6-3 H13
2E75 H42E76 I42E77 G122E78 I122E79 D1
AP2E80 D22E81 E72E82 C12
3E44 G23E45 G73E48 G73E49 I73E52 H73E61 G113E62 H23E63-1 A113E63-2 I133E63-3 I133E63-4 B113E73 G103E74 D23E75 D23E76 E23E77 E2
2E12 F42E13 G112E14 F42E15 D42E16 D12
SCART1
3E07-2 H133E07-3 H133E07-4 B33E11-1 B113E11-2 I133E11-3 I133E11-4 C113E16 D113E17 E103E18 E73E19 E73E24 C73E25 C133E31 E33E32 E33E37-1 C3
G
H
I
A
B
1E24 I111E25 I41E26 G111E27 H111E31 B4
2E83 F12E84 F22E85 F12E86 F22E87 A42E88 B42E89 D92E90 C42E91 D42E92 D102E93 E102E94 E92E95 F102E96 F92E97 E82E98 E8
4 5 6 7 8
2E17 E122E18 E42E19 F122E24 G22E29 A102E30 B102E31 C102E32 C102E33 E122E41 H122E44 I42E50 A122E51 B122E70 C122E73 H72E74 F7
1E01-2 H51E02 C131E12 D41E18 F41E19 F41E22 H41E23 I4
RES
1E45 A111E46 B111E47 C111E48 C111E49 D111E52 F111E53 C41E54 D41E55 E41E56 E111E57 E111EP2 F132E01 A32E04 D32E06 B32E10 C3
C
D
E
F
(AV2)
9 10 11 12 13
A
B
C
D
E
F
G
H
I
1E00 A41E01-1 D51 2 3 4 5 6 7 8 9 10 11 12 13
1 2 3
RE
S6E
01
CD
S4C
12G
TA
12V
45
2 7
3EB
9-4
470R
1K0
3E07-2
IEC1
3E25
10K
2
6
1PUMH7
7E01-1
p001p001
2E88
2E90
6E30
CD
S4C
12G
TA
12V
RE
S
IE54
1u8
5E76
CD
S4C
12G
TA
12V
RE
S
3E84
18R6E22
1u0 16V
2EA5
3E78 18R
150p
2E93
1R0
+3V3
FEC8
3EA
2
5E73
1u8
100p
2E91
3E73
4K7
9E09
2E01
100p
6E08
CD
S4C
12G
TA
12V
RE
S
330R
3EB
31
2
IE94
IEC0
2E14
100p
1E19
IE68
1K04 5
3E11-41E
12
12
IE90
18K
3E19
FE74
1E24
23
18R
3E79
MRC-021V-29 PC
MT
1E01-2
22
9E55
3EB6-1
470R
1 8
6E24
CD
S4C
12G
TA
12V
RE
S
2E30
100p
IE05
IE48
BEC3
18R
3E75
2E75
100p
IE13
RE
S
7
FE78
3EA7-2
470R2
3E31
12K
RE
S6E
07
CD
S4C
12G
TA
12V
2E84
150p
470R
3EB9-11 8
IE53 150p
2E92
3E85 18R
75R
3E43
1K0
3E07-1
1 8
3E63-4
4 5100R
1E56
18R3E76
IE22
FE81
FE638
9
FE68
18
19
2
20
21
3
4
5
6
7
1
10
11
12
13
14
15
16
17
1E02
MTJ-505H-01 NI LF
789
FE64
1
101112
23456
IEC2
1EP2
FE735E78
1u8
100p
2E15
150p
2E85
IE93
RES
IE89
68R
3E49
1E45
2E24
100n
BEC0
BC847BPN(COL)
7E06-2
5
3
4
3E32
4K7
3E07-3
1K03 6
FE83
5
3
4PUMH7
7E09-2
1X02REF EMC HOLE
IE60
1E31
FE76
1E55
RE
S6E
23
CD
S4C
12G
TA
12V
RE
S
CD
S4C
12G
TA
12V
6E10
2E41
100p
150p
2E96
2E29
100p
150p
2E89
3E77
18R
1E57
9E10
3
4
1E22
PUMH7
7E01-2
5
RE
S6E
28
CD
S4C
12G
TA
12V
2E19
100p
IE23
9E06
RE
S
FE72
12
6E37
CD
S4C
12G
TA
12V
3E18
39K
3E80 18R
+3V3
470R
3EA7-3
3 6
3E82
100p
2E06
18R
6E31
CD
S4C
12G
TA
12V
RE
S
18R
FE55
3E86
9E01
2E95
150p
1E49
2E18
100p
12V
CD
S4C
12G
TA
6E12
RE
S
IE18
IE55
1E48
IE59
7E04BC847BW
1u8
5E79
10u
1E53
5E80
150p
2E86
2E32
12V
CD
S4C
12G
TA
6E26
RE
S
100p
2E31
100p
9E52
2E17
100p
5
68R
3E45
3E07-4
1K04
1E27
FE80
1E54
1E18
2E74
100n
3E11-1
1 81K0
150p
2E79
FE84
5p6
3E48
68R
RES
2E99
9E51
2E83
150p
RE
S
1 2
6E36
CD
S4C
12G
TA
12V
9E50
3EB1
820R
100p
2E50
470R
3EA7-1
18
+5V
100p
2E70
IE21
2E04
100p
+5V
IE52
FE71
BEC4
2E97
39p
7E05BC847BW
BEC2
FE61
FE75
FE70
IE51
IE62
150p
IE92
6
2E94
3E37-3
100R3
3E17
4K7
3E44
4K7
CD
S4C
12G
TA
6E29
12V
RE
S
RE
S
FE60
100p
2E77
9E05
FE79
FE67
150p
2E80
2 7
2E73 100n
470R
3EB6-2
100R
3E37-1
1 8
FE85
9E02
2EA4
1u0 16V
1E26
2 7100R
3E63-2
100R
3E37-2
2 7
9E08
IE91
+3V3
9E07
2E98
18p
2E16
100p
1E52
2E78
100p
FE77
RE
S
1E47
IE20
BEC5
2E13
BEC1
16V
100n
IE14
IE08
+5V
18R
2K2
3E24
3E74
6
7
8
9
FE66
16
17
18
19
2
20
21
3
4
5
MRC-021V-29 PC
1E01-1
1
10
11
12
13
14
15
FEA0
IE57
18R3E83
FE62
3E11-3
3 6
3E52
68R
1K0
1E25
1u0
2EB
3IE61
2E81
2u2
RE
S
FE82
27R
3E62
6E35
CD
S4C
12G
TA
12V
3EA7-4
470R 45
45
3E16 12K
6
470R
3EB
6-4
3E63-3
100R3
2 7
3E11-2
1K0
6E34
CD
S4C
12G
TA
12V
RE
S6E
14
CD
S4C
12G
TA
12V
RE
S
1E46
12V
RE
S
IE96
3 6
CD
S4C
12G
TA
6E32
3EB9-3
470R
9E54
2E82
100p
RE
S
3E39
27R
12V
CD
S4C
12G
TA
6E03
2E87
100p
PUMH77E09-1 2
6
1
IE67
2E44
100p
IE17
IE16
1E00
2E51
100p
3EA
1
1K0
IE56
75R
3E61
6
1
5E77
1u8
7E06-1
BC847BPN(COL)
2
100p
2E10
100p
2E33
1E23
9E53
100p
2E12
3EB6-3
470R
3 6
6E02
CD
S4C
12G
TA
12V
RE
S
3E63-1
100R1 8
RE
S
100p
2E76
5E74
1u8
3EB9-22 7
IE70
470R
12V
CD
S4C
12G
TA
6E09
RE
S
100n
2EB
1
FEA1
3E37-4
100R4 5
RESET-AVPIP
CVBS-MON-OUT1
CVBS-OUT-SC1
A-PLOP
YPBPR2-SYNCIN2
AV2-BLK
AV4-Y
AV4-PR
AV4-PB
AV1-G
YPBPR1-SYNCIN1
YPBPR1-PB
YPBPR1-PR
AP-SCART-OUT-R
AUDIO-OUT-R
AP-SCART-OUT-L
AUDIO-OUT-L
AV1-B
AUDIO-IN1-L
AP-SCART-OUT-L
AUDIO-IN1-R
AP-SCART-OUT-R
AV1-R
AV2-CVBS
CVBS-OUT-SC1
AV1-STATUS
AUDIO-IN2-R
AP-SCART-OUT-L
AUDIO-IN2-L
AV1-CVBS
AV1-BLK
AV2-STATUS
AP-SCART-OUT-R
EN 108Q552.1A LA 10.Circuit Diagrams and PWB Layouts
2010-Apr-02 back to div. table
Analogue Externals B
18770_529_100118.eps100118
Analogue Externals BB04B B04B
2009-10-224
8204 000 8952ANALOG I/O
SVHS IN
4 5 6 7
EU
1 2 3 4
C
D
E
F
9 10 11 12
G
H
I
1E03 B3
C
D
E
F
1E08-3 D31E09 F31E28 B41E29 D4
AP
1E43 B41E44 B101E75 H51E76 I5
B
5 6 7 8
1E04 C31E07 A121E08-1 B31E08-2 E3
2E27 B42E35 F62E36 F42E37 G4
1E37 F41E38 G41E39 C41E42 E4
EU
YPBPR AUDIO
2E68 C42E71 E5
3E21 F53E87 B63E88 B63E89 B6
1 2 3
6E06 D56E15 H56E16 I56E19 F5
8 9 10 11 12 13 14
VGA ( OR DVI ) AUDIO
YPBPR
13 14
A
B
6E51 B46E52 C49E04 B5
G
H
I
A
BE21 H6BE22 I4
2E72 D53E14 H63E15 H63E20 G5
FE42 C4FE43 D4FE44 H5FE45 H5
FE51 B4FE54 B4FE59 B10IE09 F6
1ECB I42E20 H42E21 I42E22 B9
IE71 B6IE72 B7IE73 B7IE74 B6IE75 B7IE76 C6IE77 C7
2E38 G62E39 D42E40 E42E67 B4
FE01 F4FE02 F5FE03 G5FE41 B12
3E90 C63E96 E53E97 D55E06 B9
FE46 I4FE48 C4FE49 E4FE50 D4
6E20 G56E38 E56E40 B56E46 B11
IE10 G6IE15 B9IE29 E6IE31 D6
EU
SPDIF out
9E29 B59E57 B59E58 C5BE20 H6
2E37
1n0
1E29
IE74
6E38
CD
S4C
12G
TA
12V
RE
S
FE43
100p
2E39
CD
S4C
12G
TA
6E46
RE
S
FE02
12V
3E88
27R
IE31
18R
3E87
FE48
100p
2E35
3E90
18R
IE75
FE42
2E72
100p
FE59
1E28
YKB11-0946V2
1
1E07CON_JACK
2
3
4
756
FE51
1ECBMDC-066H-A LF
1
FE03
1K0
3E96
FE41
IE29
IE77
1E08-2
WHITE
YKC21-5598
3
4
9E57
YKC21-5598
1
21E08-1
YELLOW
3E89
18R
12V
RE
S
CD
S4C
12G
TA
6E40
9E58
12V
RE
S
IE72
FE50
6E51
CD
S4C
12G
TA
100p
IE09
2E68
100p
2E71
5E06
30R
1E08-3
RED
YKC21-5598
5
6
IE71
12V
RE
S
CD
S4C
12G
TA
6E06
100p
2E27
1K0
3E21
10p
2E22
1E39
2E38
100p
1
2
1E44
MTJ-032-21B-41 NI FE
1E03
1E43
1K0
3E97
IE15
1E42
2E40
100p
BE22
FE54
BE21
BE20
IE73
45
78
V_N
OM
1E38
1E09
MSJ-035-10A B AG PPO
1
2
3
FE44
12V
CD
S4C
12G
TA
6E20
9E29
1E75
IE10
FE01
IE76
RE
S
12V
CD
S4C
12G
TA
6E16
1E76
100p
2E67
9E04
FE49
3E20
1K0
6E19
CD
S4C
12G
TA
12V
1E37
V_N
OM
6E52
CD
S4C
12G
TA
12V
FE45
RE
S
1n0
2E36
FE46
18R
3E14
2E20
100p
6E15
CD
S4C
12G
TA
12V
RE
S
2
3E15
27R
1E04
MTJ-032-21B-41 NI FE
1
100p
2E21
YPBPR1-PR
YPBPR1-PB
YPBPR1-SYNCIN1
C-SVHS
Y-SVHS
SPDIF-OUT
AV3-PR
AV3-Y
AV2-CVBS
AV3-PB
AUDIO-IN4-L
AUDIO-IN4-R
AUDIO-IN3-R
AUDIO-IN3-L
Circuit Diagrams and PWB Layouts EN 109Q552.1A LA 10.
2010-Apr-02 back to div. table
Ethernet + Service
18770_530_100118.eps100118
Ethernet + ServiceB04C B04C
2009-10-224
8204 000 8952ANALOG I/O
VDDCLKIN
XTAL
RXD<0:3>
MODE
CRS_DVMODE2
INTTXER
TXD
RX
PN
TX
RXD40
RXCLK
PHYAD
1
INTSEL
LED
PN
TXCLK
RXDV
1
RXER
REGOFF
2
CRS
RBIAS
CR 1A 2A IO
TXEN
01234
MDCMDIO
VSS
12
RST
01RMIISELPHYAD2
COL
VIA
3E66 (RES)
MODE(0) = 1
BE02 G6
PHYADD(2) = 0FE28 G6
IE33 B3IE38 B4
IE49 A10IE50 A9IE63 C6IE64 C6
FE58 A11IE06 B4
FE29 G6FE30 G6
INTERRUPT FUNCTION
FE33 I5FE34 H6FE56 A11FE57 A11
6E47 G26E48 G3
7E10-1 B4
IE07 A3IE26 C2IE32 B3
PHYADD(1) = 13E65 (RES)
INTERRUPT FUNCTION
Resistor
MII mode selected
IE39 D5
BE01 G6
7E10-2 E49E42 D59E43 C3BE00 G6
3E65 D63E66 B2
BE03 H6FE27 G6
3E69 C2
PHYADD(1) = 0
Internal 1.2V reg. disabled
3E70 C1
3E95-1 F33E95-2 F3
FE31 H6FE32 I5
3E98 F55E08 A36E43 A96E44 A10
3E30 B33E33 B2
6E49 G46E50 G5
3E40 D5
ENABLED ON
3E70 (RES)
3E64 (RES)
RMII mode selected
3E53-2 A93E53-3 A103E53-4 A93E64 C6
D
E
3E67 B23E68 D6
H
MODE(2) = 0
CONFIGURATION RESISTOR SETTINGS
Internal 1.2V reg. enabled
3E71 C33E72 D6
2E62 A32E63 A3
3E95-3 F43E95-4 F4
3E22-2 F33E22-3 F23E22-4 F23E26 F5
13 14
3E34 D63E35 D6
C
UART
POP
3E69 (RES)
PHYADD(0) = 1
E
F
3E51 E13E53-1 A10
I
A
B
C
13 14
F
G
3
PHYADD(2) = 1
MODE(2) = 1
2E60 H5
5 6
2E66 A33E22-1 F2
9 10 11 12
2E55 B32E56 H2
A
B
3E67 (RES)
MODE(1) = 0
3E72
MODE(1) = 1
SERVICE
1 2
D
10 11
G
H
nINT/TXER/TXD4 SIGNAL
1 2
5 6 7 8 9
DISABLED ON
MODE(0) = 0
PHYADD(0) = 0
1N00 G7
4
EMPTY
nINT/TXER/TXD4 SIGNAL
3E71 (RES)
2E57 H22E58 H3
7 8
I
1E06 A131E70 B31E85 A111E86 A11
2E48 B52E49 B52E52 B32E53 B42E54 B3
3 4
2E59 H4
ETHERNET CONNECTOR
CONNECTOR
12
3E68 (RES)
100n
2E52
NU
P13
01M
L3 6E48
3E66
10K
RE
S
5E08
30R
RE
S
9E43
2E48
10u
+3V3
IE07
100R
36
IE63
3E22
-3
15p
2E56
IE32
1E86
RE
S
2 7
18
47R
3E53-2
100R
3E95
-1
+3V3
RES
10K3E64
3E53-3
47R
36
100R
45
3E95
-4
BE03
IE39
3E53-4
47R
4 5
3E22
-1
18
+3V3-ET-ANA
100R
3E7010K
+3V3
RES
FE31
+3V3-ET-ANA
NU
P13
01M
L3 6E49
+3V3R
ES
3E95
-2
100R
27
FE58
FE57
+3V3
2E66
100n
100n
2E49
IE38
22n
2E60
IE64
9E42
+3V3
RE
S2E
57
15p
FE34
27
RE
S6E
50
NU
P13
01M
L3
45
3E22
-2
100R
3E22
-4
100R
15p
2E58
RE
S
IE49
3E26
22R
BE02
+3V3
100n
2E63
FE28
10K3E68
BE01
RES
6E43
BZ
X38
4-C
5V1
2E54
10p
10K
3E67
RE
S
2E62
10u
4n7
2E53
FE56
3E51 1K5
FE30
2
13
IE26
YKB21-5157V
1E06
10K3E35 +3V3RES
+3V3-ET-ANA
FE33
IE33
3E3410K
FE32
3E7210K
1E85
3E98
22R
3E33
10K
10K
16 12
33
54
RES
3E65
20
22232425
21
2829
27
19
7
111098
26
13
3031
15
1418
3
2
1716
32
LAN8710A-EZK7E10-1
RE
S
FE27
2E59
15p
25M
1E70NX3225GA
RE
S6E
47
NU
P13
01M
L3
BZ
X38
4-C
5V1
6E44
18
IE06
47R
3E53-1
IE50
3E40
12K
1 1%
RES10K3E69
10K3E71
36
RES
78
100R
3E95
-3
1N00
1551151-1
123456
37
3E30
1M0
7E10-2LAN8710A-EZK
3435
36
2E55
10p
BE00
FE29
ETH-RXN
ETH-RXCLK
ETH-RXER
ETH-RXDV
ETH-TXPETH-TXNETH-RXP
RXD1-MIPS
TXD1-MIPS
ETH-CRS
ETH-TXCLK
ETH-REGOFF
ETH-INTSEL
ETH-RXD(2)ETH-RXD(3)
ETH-RXD(0)ETH-RXD(1)
ETH-TXD(2)
ETH-TXEN
ETH-TXNETH-TXP
ETH-INTSEL
ETH-REGOFF
ETH-TXD(3)
ETH-COL
ETH-TXER
ETH-MDCETH-MDIO
RESET-ETHERNETnETH-RXNETH-RXP
ETH-TXD(0)ETH-TXD(1)
EN 110Q552.1A LA 10.Circuit Diagrams and PWB Layouts
2010-Apr-02 back to div. table
HDMI
18770_531_100118.eps100118
HDMIB04D B04D
2009-10-224
8204 000 8952 HDMI
CEC_A
(CBUS) HPD2R2PWR5V
DSDA2DSCL2
DSCL3DSDA3
R3PWR5V(CBUS) HPD3
(CBUS) HPD0R0PWR5V
DSDA0DSCL0
NP
DSCL1DSDA1
R1PWR5V(CBUS) HPD1
VCC33
SB
VC
C33
MIC
OM
_VC
C33
EPAD
R3XC
NP
R3X0
NP
R3X1
NP
R3X2
TX2
NP
TX1
NP
TX0
NP
TXC
VIA
R4PWR5V
DSCL4DSDA4
CEC_D
NP
TPWR_CI2CA
RSVDL
CSDACSCL
INT
NP
R0X1
NP
R0X2
NP
R1XC
NP
R1X0
NP
R1X1
NP
R1X2
NP
R2XC
NP
R2X0
NP
R2X1
NP
R2X2
NP
R0XC
NP
R0X0
C
D
2EC0 A9
FEC0 A9FEC1 B2
3ECA-2 D43ECA-3 F4
FEC4 B2
E
3ECE H33ECF I3
F
7 8
3ECG I33ECH A10
D
FECC D2
3ECU-2 I83ECU-4 I8
5EC3 A116EC1 H3
2ECU I32ECV A9
IE42 B8IE43 D8
5EC0 A85EC2 F7
A
B
11 12
FECY E10FECZ I3
2EC1 A8
IE12 D10
FECJ F2
IE44 E8IE45 F8
13 144 5 6 7
2EC2 A10
2ECQ F8
FEC2 B2FEC3 A10
3ECA-4 F43ECD G3
A
3EC1-1 B4
5 6
FEC6 B2FEC7 A10
9EC3 E11
FECB A10
IE66 I7
3ECJ D103ECK D11
G
H
1
C
3ECN-3 E83ECN-4 F8
B
3ECP-3 B10
I
3
3ECN-2 D8
2ECP E8
FECW H9
IE11 I3
FECE D2
E
F
HDMI CONNECTOR 2
2EC3 B102EC6 B92EC7 B92EC8 B9
3EC1-3 B43EC3 E10
3ECA-1 D4
3E23 F4
FEC5 B2
FECA F3
7E02 G37EC0 G3
G
H
I
3ECP-1 B10
13
2
3ECN-1 B8
FECP F2FECR E10
3ECL E11
FECK F2
FECD D2
8 9 10
3EC5 E10
HDMI CONNECTOR 1
2ECW B10
IE65 I7
IEC5 G3
HDMI CONNECTOR 3SII9187A = 0xB2
FECM F2
2 3 4 14
1
3ECF
9
3ECM-4 B8
12
FECG D2
FECL F2
IEC4 G3
IEC6 G4
2ECC G82ECM B82ECN D8
I2C Address 1P04 A2
NON-INSTAPORT
INSTAPORT
9187A
9287B
9EC2 C119EC0 G4
4X 3K3
4X 100K
7EC1 B9
100K
3K3
7EC1 3ECN
10 11
3ECM-1 F83ECM-2 E83ECM-3 D8
1P02 E21P03 C2
FECF D2
FECN F2
IEC7 H3
3ECF
100K
10p
2EC
C
CIN-5V
FECP
FEC4
22K
3EC
E
FEC3
10R
3ECM-33 6
+5V-EDID
IE45
+3V3-HDMI
IE43
9EC2
RES
10K
3ECU-44 5
2EC
2
1u0
FEC1
IEC4
2 73ECM-2
10R
IE44
2ECN1u0
10R
3ECM-11 8
FECK
81
FECD
3EC
1-1
47K
CIN-5VFECN
IEC5
RES
4K7
3ECK
3EC5 100R
100K3ECN-44 5
MICOM-VCC33
+3V3-STANDBY
2ECU
1u0
9EC3RES
FECC
RES3ECJ
4K7
220u
2EC
1R
ES
16V
BC847BW7E02RES
FECF
3EC
H
10K
212223
1819
23456789
20
1
1011121314151617
1P02
3EC3 100R
FECZIE66
30R
5EC0
22KRES
3E23
89
20212223
3EC
G
4R7
16171819
234567
1P03
1
101112131415
+3V3
VGA-SCL-EDID-HDMI
3 63ECN-3 100K
FEC7
2 7
100n
2EC
7
100K3ECN-2
AIN-5V
BIN-5V
MICOM-VCC33
+3V3-STANDBY
+3V3
+5V-VGA
FECM
2EC
V
10u
+5V-EDID
5EC2
30R
1u0 2ECP
FECB
3ECP-1 10K
18
IE11
3ECD
100R
FECR
2EC
6
FEC6
100n
10K
3ECP-3
36
RES
VGA-SDA-EDID-HDMI
3ECL
4K7
2ECQ1u0
BIN-5V
36
47K
3EC
1-3
FECW
+3V3
36
FECL
47K
3EC
A-3
FECY
FECG
BAT54
6EC1
RES5EC3
30R
89
7576777879808182
62
9 27 64
74
838485868788
28
38
55
6160
5958
5756
63
2122
2324
2526
1920
49
10
2
42
1314
1516
1718
1112
46
6566
36
34
56
78
1
47
73
52
37
32
6768
6970
7172
53
30
34
40
44
48
29
33
39
43
7EC1
31
35
41
45
50
51
54
SII9287B
2ECM
CIN-5V
FECJ
1u0
AIN-5V
2EC
3
100n
IE12
IE65
9EC0
DIN-5V
FECA
FEC2
FECE
AIN-5V
7EC0BC847BW
4 5
8
3ECM-4
10R
3EC
A-1
47K
1
IEC7
FEC5
100n
2EC
8
IEC6
+3V356789
20212223
1213141516171819
234
1P04
1
1011
47K
3EC
A-2
72
10u
2EC
W
AIN-5V
RE
S
3ECU-2
10K
2 7
CIN-5V
54
BIN-5V
FEC0
3EC
A-4
47K
100n
2EC
0
BIN-5V
1 8
+5V
3ECN-1 100K IE42
DDCA-SCL
eHDMI+
ARC-eHDMI+
DDCA-SDA
BRX-DDC-SDA
ARX-DDC-SDA
CRX-HOTPLUG
DRX-HOTPLUGCRX-DDC-SDA
BRX-DDC-SCL
SDA-SSB
CEC-HDMI
PCEC-HDMI
CRX-DDC-SCLCRX-DDC-SDA
ARX-DDC-SCLARX-DDC-SDA
ARX-HOTPLUG
BRX-HOTPLUG
DRX-DDC-SCLDRX-DDC-SDA
SCL-SSB
HDMIA-RX2-
HDMIA-RXC+
HDMIA-RX0+
HDMIA-RX1+
HDMIA-RX2+
BRX-DDC-SCLBRX-DDC-SDA
DRX1-
DRX2+DRX2-
DRXC+DRXC-
HDMIA-RXC-
HDMIA-RX0-
HDMIA-RX1-
CRX0-
CRX1+CRX1-
CRX2+CRX2-
CRXC+CRXC-
DRX0+DRX0-
DRX1+
BRX0+BRX0-
BRX1+BRX1-
BRX2+BRX2-
BRXC+BRXC-
CRX0+
ARX0+ARX0-
ARX1+ARX1-
ARX2+ARX2-
ARXC+ARXC-
ARX1+
ARX1-ARX0+
ARX0-
ARX-DDC-SCL
CRX-DDC-SCL
PCEC-HDMI CEC-HDMI
ARX2+
ARXC+
ARXC-PCEC-HDMI
ARX-DDC-SCLARX-DDC-SDA
ARX-HOTPLUG
ARX2-
BRX2+
BRXC+
BRXC-PCEC-HDMI
BRX-DDC-SCLBRX-DDC-SDA
BRX-HOTPLUG
BRX2-BRX1+
BRX1-BRX0+
BRX0-
CRX2+
CRXC+
CRXC-PCEC-HDMI
ARC-eHDMI+CRX-DDC-SCLCRX-DDC-SDA
CRX-HOTPLUG
CRX2-CRX1+
CRX1-CRX0+
CRX0-
Circuit Diagrams and PWB Layouts EN 111Q552.1A LA 10.
2010-Apr-02 back to div. table
Headphone
18770_532_100119.eps100119
HeadphoneB04E B04E
2009-10-224
8204 000 8952AUDIO
VIAGND_HS
VOIN-
VDD
1
SHUTDOWN
BYPASS
2
GND
2
1
2EE0 C52EE1 D5
2EE4 E32EE5 D5
7 8
2 3 6 7
B
C
FF
A
2EE2 E42EE3 E2
D
E
2EE6 E62EE7 E6
3EE0-4 E33EE1-1 C5
1 2 3 4 5 6 9
1 4 5
3EE2-1 D73EE2-2 E7
7EE0-1 B57EE0-2 B6
8 9
A
7EE1 D4
D
E
FE35 E7FE36 E7
B
C
FEE0 B4IEE0 E2IEE1 E2IEE2 E2IEE3 E3IEE4 E3
3EE0-1 E33EE0-3 F3
IEE5 F3IEE6 E4
3EE1-2 D83EE1-3 D8
IEE7 E6IEE8 E6
2EE0
3EE1-4 D5
3EE2-3 E73EE2-4 E7
2EE5
47p
3 6
47p
10K
3EE0-3
FEE0
2EE
1
100n
1 8
4 5
3EE2-1
33R
3EE2-4
33R
IEE3
IEE4
6
5
8
1011
1
7
TPA6111A2DGN7EE1
AMPLIFIERΦ
3
4 9
2IEE1
IEE6
1 8
IEE7
IEE5
3EE1-1
22K
4 5
22K
3EE1-4
IEE25 4
IEE8
1
3EE0-4
10K
3EE0-1
10K
82EE3
1u0
1u0
2EE4
4
+3V3
PUMD127EE0-25
3
4V 100u
2EE7
22K
3EE
1-2
27
4V 100u
2EE6
6
1PUMD127EE0-12
1u0
2EE2
+3V3-STANDBY
IEE0 FE36
3 6FE35
2 7
3EE2-3
33R
3EE2-2
33R
36
3EE
1-3
22K
AMP1
AMP2
ADAC(4)
ADAC(3)
A-PLOP
RESET-AUDIO
A-PLOP
A-STBY
EN 112Q552.1A LA 10.Circuit Diagrams and PWB Layouts
2010-Apr-02 back to div. table
10-13 B05 820400089535 DDRDDR
18770_534_100119.eps100218
DDRB05A B05A
2009-12-075
8204 000 8953DDR 4
4567
2
0
VSSDLVSS
123
CSRAS
NU|RDQS
CKE
DQS
ODT
1
012345678910111213
NC
VDDQ
DQA
CK
VSSQ
BA
CASWE
0
DM|RDQS
VREFVDDLVDD
4567
2
0
VSSDLVSS
123
CSRAS
NU|RDQS
CKE
DQS
ODT
1
012345678910111213
NC
VDDQ
DQA
CK
VSSQ
BA
CASWE
0
DM|RDQS
VREFVDDLVDD
4567
2
0
VSSDLVSS
123
CSRAS
NU|RDQS
CKE
DQS
ODT
1
012345678910111213
NC
VDDQ
DQA
CK
VSSQ
BA
CASWE
0
DM|RDQS
VREFVDDLVDD
4567
2
0
VSSDLVSS
123
CSRAS
NU|RDQS
CKE
DQS
ODT
1
012345678910111213
NC
VDDQ
DQA
CK
VSSQ
BA
CASWE
0
DM|RDQS
VREFVDDLVDD
3B03 D93B04-1 C123B04-2 B13
3B18 H133B19 H123B20 H13B21 I1
3B08-1 G73B08-2 G63B08-3 G7
3B25 I33B26 I93B27 C13B28 C1
AT T-POINT
7B03 B10
3B11-2 G133B11-3 G123B11-4 G13
2B47 H123B00-1 C63B00-2 B7
3B12 C73B13 C63B14 C133B15 C12
3B05-2 C13
3B16 H73B17 H7
3B07-1 G63B07-2 G73B07-3 G73B07-4 G6
2B36 A62B37 A112B38 F6
3B08-4 G63B09 H93B10-1 G123B10-2 G13
3B22 B13B23 D33B24 D9
7B00 G47B01 G107B02 B4
2B46 H6
2B17 A112B18 F22B19 F3
3B00-3 B73B00-4 C63B01 C3
3B02-1 C7
3B04-3 B123B04-4 C123B05-1 C13
2B28 F8
3B05-3 B123B05-4 C133B06 H3
2B32 F92B33 F92B34 F102B35 F11
B
C
D
2B39 F112B40 A22B41 B82B42 F2
FB00 H1
3B10-4 G123B11-1 G12
2B13 B92B14 B92B15 B92B16 B10
3
2B20 F32B21 F32B22 F32B23 F3
3B02-3 C73B02-4 B6
2B27 F8
2B29 F92B30 F92B31 F9
11 12 13
A
6 7 8
E
F
G
H
3B10-3 G12
2B44 C62B45 C12
2B12 B9
4 5 6 7
3B02-2 B6
2B25 F42B26 F6
C
8
D
2B04 A32B05 A32B06 A4
2B10 B8
I
2B00 A22B01 A32B02 A32B03 A3
2B11 B9
9 10 11 12
2B43 F8
A
B
1 2 3 4 5
I
1
13
2
2B24 F4
9 10
E
F
G
H
2B07 A42B08 A62B09 B8
DDR2-VREF-DDR
3B22
240R2 73B02-2
33R
3B17
33R33R
3B19
3B11-3 3 6
B8
D2
D8
F3
33R
C7
C9
E2
A3
E3 J1 K9
E7
A7
B2
A2
F9
F7
A1
E9
L1 H9
E1
A9
C1
C3
C2D7D3D1D9B1B9
B7A8
L3L7
K3
G2G3G1
G7
E8
F2F8
G8
B3
C8
H2K7L2L8
H7J2J8J3J7K2K8
EDE1108AGBG-1J-F7B02
SDRAMΦ
H8H3
J1 K9
E7
A7
B2
B8
D2
D8
F3
H9
E1
A9
C1
C3
C7
C9
E2
A3
E3
B1B9
B7A8
L3L7
A2
F9
F7
A1
E9
L1
F2F8
G8
B3
C8C2D7D3D1D9
J8J3J7K2K8K3
G2G3G1
G7
E8
ΦH8H3
H2K7L2L8
H7J2
D2
D8
F3
EDE1108AGBG-1J-F7B03
SDRAM
C7
C9
E2
A3
E3 J1 K9
E7
A7
B2
B8
F9
F7
A1
E9
L1 H9
E1
A9
C1
C3
C2D7D3D1D9B1B9
B7A8
L3L7
A2G2G3G1
G7
E8
F2F8
G8
B3
C8
K7L2L8
H7J2J8J3J7K2K8K3
EDE1108AGBG-1J-F7B00
SDRAMΦ
H8H3
H2
2p22B47 RES
2B462p2RES
100n
2B24
100n
2B30
33R
3B24
3B26
33R33R
3B25
33R
3B23
2B11
100n2B
04
100n
RES2B452p2
RES 2p22B44
RES
+1V8
+1V8
3B09240R
D2
D8
F3
C7
C9
E2
A3
E3 J1 K9
E7
A7
B2
B8
A2
F9
F7
A1
E9
L1 H9
E1
A9
C1
C3
D7D3D1D9B1B9
B7A8
L3L7
G2G3G1
G7
E8
F2F8
G8
B3
C8C2
K7L2L8
H7J2J8J3J7K2K8K3
SDRAM
7B01
ΦH8H3
H23B16
EDE1108AGBG-1J-F
33R
+1V8
4 533R
3B02-4
100n
1 8
2B22
3B02-133R
240R
+1V8
RES3B01
2B17
100n
33R1 83B00-1
100n
2B29
3B07-2
33R2 7
3B13
33R
2B18
100n
100n
2B08
33R3 6
2B31
100n
3B00-3
4 5
100n
2B15
33R3B11-4
3B21
180R
1%
2B26
100n
2B06
100n
100p
2B37
100n
2B02
1 833R
3B04-1
100n
2B28
33R3B00-4 4 5
100n
2B07
2B01
100n
2B12
100n
2B43
47u47
u
2B42
100n
1 8
2B09
3 6
33R3B05-1
33R3B04-3
3B08-33 633R
3B1233R
3B07-433R
4 5
83B10-133R
1
1%18
0R3B20
2B14
100n
100n
2B13
2 7 3B05-233R
2B21
100n
3 6
DDR2-VREF-DDR
3B05-333R
3B1833R
2B05
100n
2B25
100n
2B40
47u
47u
2B41
2B33
1 8
100n
3B11-1 33R
2B36
100p
2 7
2B35
3B00-2
33R
100n
RES240R
3B06
2B39
100p10
0p2B
38
3 6 3B07-333R
3B08-11 8
3B10-4 4 533R
33R
240R3B03
4 5
RES
3B04-433R
3B07-1 1 8
2B32
33R
100n
2 7
3 63B11-233R
4 5
33R3B10-3
3B08-433R
100n
2B10
2 73B10-2
33R
100n
2B34
33R3B14
2B23
5
100n
3B05-433R
4
DDR2-VREF-DDR
100n
DDR2-VREF-DDR
2B27
3B08-2 2 7
2B16
100n
33R
100n
2B03
3 633R3B02-3
3B15
33R
100n
2B00
DDR2-VREF-DDR
2B20
100n
+1V8
3B04-22 733R
2B19
100n
FB00
3B28
240R
DDR2-CLK_N
DDR2-CLK_N
DDR2-CLK_P
DDR2-CLK_P
240R
3B27
DDR2-ODT
DDR2-A14
DDR2-DQM0
DDR2-ODT
DDR2-DQM1
DDR2-ODT
DDR2-BA2DDR2-BA1DDR2-BA0
DDR2-CLK_P
DDR2-A12DDR2-A11DDR2-A10DDR2-A9DDR2-A8DDR2-A7DDR2-A6DDR2-A5DDR2-A4DDR2-A3DDR2-A2DDR2-A1DDR2-A0
DDR2-DQM2
DDR2-ODT
DDR2-DQM3
DDR2-CSDDR2-CKE
DDR2-CASDDR2-A14
DDR2-CLK_N
DDR2-A13DDR2-A13DDR2-A12DDR2-A11DDR2-A10
DDR2-A1DDR2-A0
DDR2-WE
DDR2-RAS
DDR2-BA2DDR2-BA1DDR2-BA0
DDR2-A9DDR2-A8DDR2-A7DDR2-A6DDR2-A5DDR2-A4DDR2-A3DDR2-A2
DDR2-CS
DDR2-CLK_NDDR2-CKE
DDR2-CLK_P
DDR2-CAS
DDR2-CAS
DDR2-BA2DDR2-BA1DDR2-BA0
DDR2-A9DDR2-A8DDR2-A7DDR2-A6DDR2-A5DDR2-A4DDR2-A3DDR2-A2
DDR2-A14
DDR2-A13DDR2-A12DDR2-A11DDR2-A10
DDR2-A1DDR2-A0
DDR2-WE
DDR2-RAS
DDR2-A1DDR2-A0
DDR2-WE
DDR2-RASDDR2-CS
DDR2-CLK_NDDR2-CKE
DDR2-CLK_P
DDR2-A5DDR2-A4DDR2-A3DDR2-A2
DDR2-A14
DDR2-A13DDR2-A12DDR2-A11DDR2-A10
DDR2-CAS
DDR2-BA2DDR2-BA1DDR2-BA0
DDR2-A9DDR2-A8DDR2-A7DDR2-A6
DDR2-WE
DDR2-RASDDR2-CS
DDR2-CLK_NDDR2-CKE
DDR2-CLK_P
DDR2-D27DDR2-D26
DDR2-D10DDR2-D11
DDR2-D19DDR2-D18
DDR2-CLK_N
DDR2-CLK_P
DDR2-DQS2_PDDR2-DQS2_N
DDR2-D24DDR2-D25
DDR2-D28DDR2-D29DDR2-D30DDR2-D31
DDR2-DQS3_PDDR2-DQS3_N
DDR2-DQS1_PDDR2-DQS1_N
DDR2-D16DDR2-D17
DDR2-D20DDR2-D21DDR2-D22DDR2-D23
DDR2-DQS0_PDDR2-DQS0_N
DDR2-D8DDR2-D9
DDR2-D12DDR2-D13DDR2-D14DDR2-D15
DDR2-D0DDR2-D1DDR2-D3DDR2-D2DDR2-D4DDR2-D5DDR2-D6DDR2-D7
Circuit Diagrams and PWB Layouts EN 113Q552.1A LA 10.
2010-Apr-02 back to div. table
10-14 B06 820400089572 LVDS Non DVBSDisplay Interfacing - VDisp
18770_565_100125.eps100218
Display Interfacing - VDispB06A B06A
2009-10-222
8204 000 8957LVDS Non DVBS
8
5
1G00 C4
6
6
4
2G43 C4
D
2G44 C3
1
5
C
3
D
5G01 C3
2
F
B IG11 C5
7
A
3G28 C5
6G00 C6FG0H C5
E
21 3
A1G03 B4
5G02 C3
7
C
8
B
4
F
E
FG0H
RES
5G02
30R
RES30R
5G01
2G43
100n
LTST-C190KGKT
+VDISP
6G003G28
2K2
RE
S
2G44
22u
T
+VDISP-INT
IG11
RES1G00
3.0A32V
T 32V3.0A
1G03
EN 114Q552.1A LA 10.Circuit Diagrams and PWB Layouts
2010-Apr-02 back to div. table
Video Out - LVDS
18770_566_100125.eps100125
Video Out - LVDSB06B B06B
2009-10-222
8204 000 8957LVDS Non DVBS
FG25 E9FG26 E9
FG18 F4FG19 F4
FG29 E9FG2A E9FG2B E9FG2C E9FG2D F9FG2E D9
FG1E E4FG1F E4FG1G E4
FG2G C9
FG1A F4
FG2P F11FG2R D11
FG1U F9
FG2K D9FG2L D10FG2M D10FG2N G11
3G33 C9
FG1P F4FG1Q F4FG1R F9
3G37 D99G0G G11
FG1S F9FG1T F9
TO DISPLAY
FG1V F9
FG28 E9
9G0K-1 C49G0K-2 C49G0K-3 C4
FG1W F9FG1Y D9
FG12 F4FG13 F4FG14 F4
FG23 E9FG24 E9
2G7A C10
FG15 F4FG16 F4FG17 F4
2G95 D42G96 D4
FG1B F4
FG1C D4FG1D D4
2G98 D4
FG1L E4FG1M E4FG1N E4
FG2H C9FG2J D5
3G31 D83G32 C8
G
3G34 B93G35 C93G36 D8
C
D
FG2F D9
FG27 E9
FG1Z D9FG20 D9FG21 D9FG22 E9
2G78 C102G79 C10
1
2G92 C42G93 C42G94 D4
TO DISPLAY
8
2G97 D4
12
2G99 D43G2W C8
FG1H E4FG1J E4FG1K E4
E
F
2G75 C10
H
A
B
2 6
9G0K-4 C4FG04 D8FG11 E4
12 13
2 3 4 5 6 7 9 10 11
1G51 G11
13
A
3G2Y C83G2Z D83G30 D9
2G28 E112G29 E11
2G25 C112G26 C112G27 C11
5431 7 8
RES
2G76 C102G77 C10
FG30 D5FG31 D5
1G50 G5
E
F
G
H
1X05 G12G24 C10
B
C
D
FG32 D5FG33 D5FG34 C11
9 10 11
FG22
RE
S2G
7810
0p
FG1E
RES10p 2G93
FG30
FG2M
FG04
FG28
FG2P
FG1H
3G2W100R
RES3G30100R
100R
3G31
RES
FG1A
RESRES
2G9810p10p 2G97
FG1J
FG2D
FG1M
4546 4748 4950
FG1G
41
56789
42
51
4344
30313233343536373839
4
40
212223242526272829
3
111213141516171819
2
20
1G50
FI-RE41S-HF
1
10
FG21
RES 9G0G
EMC HOLE1X05
FG1N
FG1S
FG24
FG26
FG2K
FG1F
RES
2G9610p FG2F
FG16
10p
2G75
RES2G9210p
FG2A
FG1R
RE
S
10K
3G34
FG2H
FG1Z
RES 3G32
RES
100R
2G9910p
FG31
FG20
36
FG13
9G0K
-3
10K
FG1B
RE
S3G
35
FG23
FG1Y
FG2C
2G76
10p
FG2J
FG1T
RE
S10
p2G
26
FG29
FG25
2G2810p
RE
S10
p2G
24
RE
S
10p 2G95
2G27
10p
2G77
RE
S
RES
18
100p
9G0K
-1
+VDISP
2G7A
100p
RE
S
FG27
FG1D
100R3G2Y
FG1K
9G0K
-22
7
FG1U
FG32
FG1W
FG2G
FG19
FG2L
3G36
100R
+3V3
RES
FG33
RE
S10
p2G
25
3G2ZRES
FG2E
100R
FG34
2G9410pRES
10p 2G29
FG1V
FG17
FG14
FG15
FG18
FG1C
FG1Q
RE
S10
0p2G
79
FG2B
FG2N
45
9G0K
-4
FG1P
FG12
5960
FG1L
89
52
61
5354 5556 5758
4546474849
5
5051
67
343536373839
4
4041424344
2526272829
3
30313233
1516171819
2
2021222324
1G51
FI-RE51S-HF
1
1011121314
3G33
10K
+VDISP
RE
S
FG2RRES100R3G37
FG11
PX1CLK-PX1CLK+
PX1D-PX1D+
BACKLIGHT-BOOSTBACKLIGHT-PWM-ANA-DISP
PX2A-PX2A+
PX1A-PX1A+PX1B-PX1B+PX1C-PX1C+
PX4D-
PX4E-PX4E+
PX1E-PX1E+
PX4CLK+
PX4C-PX4C+
PX4B-PX4B+
PX4A-PX4A+
PX4D+
PX3D+
PX3CLK-PX3CLK+
PX3C-PX3C+
PX3A-PX3A+
PX4CLK-
CTRL-DISP
CTRL-DISP
PX3B-PX3B+
PX3E+PX3E-
PX3D-
PX2C+PX2C-
SCL-DISPSDA-DISP
BACKLIGHT-PWM_BL-VS
CTRL-DISP
PX2CLK-PX2CLK+
PX2D-PX2D+PX2E-PX2E+
PX2B-PX2B+
Circuit Diagrams and PWB Layouts EN 115Q552.1A LA 10.
2010-Apr-02 back to div. table
AmbiLight CPLD
18770_567_100125.eps100125
AmbiLight CPLDB06C B06C
2009-10-222
8204 000 8957LVDS Non DVBS
TMSTDOTDITCK
GND
VCCINT VCCIO
A
B
C
D
E
F
G
2G13 F7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A
H
1G35 G21G36 G21G37 B13
2G10 F32G11 F32G12 F3
B
C
D
E
F
G
H
2G14 F82G15 F8
2G16 F82G17 F82G18 F9
2G19 F92GA0 B32GA1 B4
2GA2 B42GA3 B32GA4 G3
2GA5 B33G10-1 E63G10-2 E7
DEBUG ONLY
3G10-3 E63G10-4 E73G11-1 E6
3G11-2 E33G11-4 E43G12 E6
3G13 E73G14 E43G15 E2
3GA1 E63GA2-1 G3
DEBUG ONLY
3GA2-2 G3
3GA2-3 G33GA2-4 G33GA5-1 B12
3GA5-2 B123GA5-3 B123GA5-4 B12
3GA6-1 F133GA6-2 F133GA6-3 F12
3GA6-4 F125GA0 A35GA1 B2
6GA0 F126GA1 F126GA2 F13
6GA3 F137GA0 D57GA1-1 D13
7GA1-2 D137GA2-1 E127GA2-2 E12
9GA0 H59GA1 D7FGA0 A5
FGA1 B4FGA2 G3FGA3 G5
FGA4 G4FGA5 G5FGA6 G4
IGA0 C11IGA1 C11IGA2 C11
IGA3 C11
100R3GA5-1 1 8
123456
6
1G37
SD51022
3GA2-3 100R3
IGA0
7GA1-25
3
4
5
3
4
VINT
BC847BS(COL)
1
7GA2-2BC847BS(COL)
BC847BS(COL)7GA2-12
6
330R
3GA
6-1
18
45
VINT
3GA
6-4
330R
VIO
+3V3
3GA147R
9GA1
10p
2G19
RE
S
2G18 10
p
10p
2G17
RE
S
RE
S
3G10-2 100R2 7
1 8
100R4 5
100R3G10-1
8 1 3G10-4
2 7
3G11-1 100R
100R3G11-2
RE
S2G
14 10p
10p
2G10
RE
S
10R3G123G13
3 6
100R
100R3G10-3
LTS
T-C
190K
GK
T
6GA
3
+3V3
3G15
10K
2GA
2
100n
FGA3
FGA0
100n
RE
S
2GA
4
2G13 10
p
30R
5GA0
RE
S
1u0
+3V3
2GA
0
100n
2GA
1
FGA2
3G11-4 100R4 5
FGA4456
7 8
1G35123
FGA5
FGA6
30R
5GA1
RE
S
RE
S2G
16 10p
4 5
10p
2G15
100R3GA2-4
10p
2G12
RE
S
RE
S2G
11 10p
3G14 100R
+3V3
6GA
0
LTS
T-C
190K
GK
T
LTS
T-C
190K
GK
T
6GA
2
3GA5-2100R
2 73 6
35 26
100R3GA5-3
21
IXO4_2222
IXO4_2323
IXO4_2727
IXO4_2828
1192410
15
16
IXO3_1818
IXO3_55
IXO3_66
IXO3_77
IXO3_88
IXO4_1919
IXO4_2020
IXO4_21
33IXO2_34|GTS2
34IXO2_36|GTS1
36
IXO2_3737
IXO2_3838
IXO3_12 12
IXO3_1313
IXO3_1414
IXO3_16
41
IXO1_4242
IXO1_43|GCK143
IXO1_44|GCK244
IXO2_2929
IXO2_3030
IXO2_3131
IXO2_3232
IXO2_33|GSR
4 17 25
IXO1_1|GCK31
IXO1_22
IXO1_33
IXO1_3939
IXO1_4040
IXO1_41
XC9572XL-10VQG44C01007GA0
Φ
9GA0
FGA1
100R3GA2-2 2 7
7GA1-1BC847BS(COL)
2
6
1
123456
SD51022
1G363GA2-1 100R1 8
+3V3
100n
2GA
5
6
IGA3
330R
3GA
6-3
3
3GA
6-2
330R
27
+3V3
1u0
2GA
3
VIO+3V3
IGA1
IGA2
+3V3
LTS
T-C
190K
GK
T
6GA
1
4 5
+3V3
3GA5-4100R
CPLED1
AMBI-PWM-CLK_B2AMBI-SPI-CS-OUTn_R2-R
AMBI-SPI-CS-OUTn_R2AMBI-LATCH1_G2
AMBI-BLANK_R1AMBI-SPI-CS-EXTLAMPSn
AMBI-SPI-CLK-OUTAMBI-SPI-SDI-OUT_G1
AMBI-SPI-SDO-OUTAMBI-LATCH2_DIS
AMBI-PROG_B1
AMBI-TEMP
GTS2GTS1GCK3
GSR
PXCLK54
BACKLIGHT-PWM
BACKLIGHT-PWM_BL-VS
CPLED2
CPLED3
GCK2
GTS2
GTS1
GCK3
GSR
PNX-SPI-CSBn
CPLED1
AMBI-SPI-CLK-OUT-RAMBI-SPI-SDI-OUT_G1-R
AMBI-SPI-SDO-OUT-R
SV-LB_MWP-THGILKCABMWP-THGILKCAB
GCK3
PNX-SPI-CS-AMBInPNX-SPI-CS-BLnPNX-SPI-SDOPNX-SPI-SDIPNX-SPI-CLK
GCK2
GSRGTS2GTS1
CPLED3CPLED2
BL-SPI-SDOBL-SPI-SDI
BL-SPI-CSn
BL-SPI-CLK
EN 116Q552.1A LA 10.Circuit Diagrams and PWB Layouts
2010-Apr-02 back to div. table
SPI-Buffer
18770_568_100125.eps100125
SPI-BufferB06D B06D
2009-10-222
8204 000 8957LVDS Non DVBS
G3
12
3EN23EN1
3GE3 B43GE4 B37GE0 B3
* Buffer
IGE0 B3IGE1 D2
B
2GE0 A23GE0-1 B43GE0-3 B43GE1-3 B43GE1-4 B33GE2 A4
9GE0-1 C39GE0-2 C39GE0-3 D39GE1 C39GE2 D3
3 4
7GE1 A4
C
D
A
* Direct
5 6
1 2 3 4 5 6
C
D
**5 4
A
B
*
9GE3 D3
1 2
*9GE0-4
9GE2
9GE3
9GE0-36 3
IGE0
1 8
3 6
47R
3GE0-147R
3GE0-3
10K
3GE
2 7GE1PDTC114EU
1514131211
1
10
19
20
2
3456789
18
1716
7GE074LVC245A
47R3GE3
RES
9GE1
9GE0-27 2
IGE1
47R3GE1-4
RES5 4
47R
RES6 3
3GE4
+3V3
47R3GE1-3
100n
2GE
0
+3V3
BL-SPI-SDI
PNX-SPI-CLK BL-SPI-CLK
BL-SPI-SDO
PNX-SPI-CS-BLn BL-SPI-CSn
PNX-SPI-SDI
PNX-SPI-SDI
PNX-SPI-CS-AMBIn AMBI-SPI-CS-OUTn_R2-R
BL-SPI-CLK
AMBI-SPI-CLK-OUT-R
PNX-SPI-CLK
PNX-SPI-SDO
AMBI-SPI-SDI-OUT_G1-R
BL-SPI-SDO
AMBI-SPI-SDO-OUT-R
BL-SPI-SDI
PNX-SPI-SDO
PNX-SPI-CSBn
Circuit Diagrams and PWB Layouts EN 117Q552.1A LA 10.
2010-Apr-02 back to div. table
10-15 B09 820400089812 Non DVBS Con.Non DVBS Connector Board
18770_569_100125.eps100218
Non DVBS Connector BoardB09A B09A
2009-10-222
8204 000 8981Non DVBS
CONNECTOR BOARD
FT71 A4FT72 A5FT73 A4FT74 A4FT75 A5FT76 B4FT77 B5FT78 B4FT79 B4
TO
HOTEL TV
FT92 B9FT93 B9FT94 B9FT95 C7
SENSOR
FT57 E8
FT96 E4FT97 E4FT98 E5FT99 F5IT73 A7IT74 B7IT75 B7IT78 F4
3T88-2 E73T88-4 F73T90 D33T91 D43T92 E43T93 E35T53 F3
5T54 F39T50 E7
FT80 B5FT81 B5FT82 B5FT87 A7FT88 B9FT89 B9FT90 B9FT91 B9
*
LED PANEL
2T92 F73T70 B23T71 E73T74 A63T75 A73T76 A73T77 B73T78 B73T79 C7
FT58 E8FT59 F7FT60 E8FT61 E8FT64 E7FT68 D3FT69 E3FT70 A5
3T88-1 D7
1M71 E51T85 F41T86 B42T70 B32T76 A72T77 A72T78 B72T79 B72T80 B7
FC83 B4FT50 C7FT51 C7FT52 D8FT53 D8FT54 D8FT55 D8FT56 E8
2T89 D72T90 E72T91 F7
1M20 B9
3T80 D43T81 E43T82 E43T83 E43T84 C73T85 C73T86 D73T87 F7
TEMPERATURE
1M59 A5
9
1 2 3 4 5 6 7 8
2T81 B92T82 C72T83 E42T84 E42T85 F52T86 C72T87 D72T88 D7
9
A
B
C
D
E
F
A
B
C
D
E
F
1F53 D91M09 C5
FT71
1 2 3 4 5 6 7 8
FT97
3T86
100R
100R
3T82
FC83
2T83
100p
T 63V2.0A
1T86
FT59
4 5
100R
3T88-4
FT94
FT77
2T89
10p
2T76
100p
FT56
2T87
10p
2T70
100n
10p
2T90
FT80
+3V3
* RES
10K
3T93
+3V3
FT90
FT78
100p
2T77
3T92
FT76
* RES
100R
* RES
100R
3T9110K
3T90
678
* RES
12345
FT51
1M20
FT64
FT81
+3V3
100p
2T80
3T88-18 1
100R
RES
FT53
30R
5T54
FT87
FT72
FT98
+5V
FT57
FT54
2T81
FT68
FT91
100n
100R
3T76
100R
3T87
2T79
100p
FT61
FT74
3T88-2
100R
2 7
FT92
3T84
100R
FT96
T63
V1.
0A
1T85
3T75
100R
16
FT75
1314
23456789
15
1F53
502386-1470
1
101112
V-AMBI
FT52
10p
2T91
FT99
+3V3
2T85
1u0
FT89
100p
FT602T84
9T50
100R
3T71
FT95
3T70
100R
FT70
10p
2T88
FT79
+24V
IT75
FT88
+12V
2T92
10p
IT74
10R
3T79
100R
RES 3T83
100R
RES
FT55
3T81
100p
2T82
IT73
FT50
502382-0470
1234
56
1M09
56789
FT93
19
2
202122232425
34
1
101112131415161718
FH12-25S-0.5SH(55)
1M59
IT78
FT58
REF EMC HOLE1X03
100K
3T74
3T77
100R
FT73
100R
3T78
10p
2T86
1735446-4
1M71
1234
RES
5T53
30R
FT82
100R
3T85
V-AMBI
FT69
3T80
+24V
100R
2T78
100p
FAN-CTRL1
FAN-CTRL2
FAN-DRV
+3V3-STANDBY
BL-SPI-SDO
BL-SPI-SDI
BACKLIGHT-PWM_BL-VS
BL-SPI-CSn
AMBI-SPI-CS-OUTn_R2
AMBI-LATCH2_DISAMBI-SPI-CS-EXTLAMPSn
BACKLIGHT-PWM-ANA-DISP
SDA-BL
SCL-BL
BL-SPI-CLK
LED-2
LED-1
KEYBOARD
SCL-BL
TACH02
TACH01
SDA-BL
AMBI-TEMP
RC
LIGHT-SENSOR
AMBI-SPI-CLK-OUTAMBI-SPI-SDO-OUTAMBI-SPI-SDI-OUT_G1
AMBI-PWM-CLK_B2
AMBI-LATCH1_G2
AMBI-PROG_B1AMBI-BLANK_R1
EN 118Q552.1A LA 10.Circuit Diagrams and PWB Layouts
2010-Apr-02 back to div. table
10-16 310431363643 SSB LayoutOverview top side
18770_580_100216.eps100219
1328
1329
1735
1D38
1D50
1D52
1E00
1E01
1E02 1E031E04
1E05
1E06
1E07
1E08
1E091E12 1E18 1E19
1E22
1E23
1E24
1E25
1E26 1E27
1E28
1E29
1E31
1E37
1E38
1E39
1E421E
43
1E44
1E45
1E46
1E47
1E48
1E49 1E52
1E53
1E54 1E55
1E56
1E57
1E70
1E75
1E76
1E85
1E86
1ECB1EP2
1F10
1F24
1F25
1F51
1F52
1F53
1F75
1FC11FC21FC3 1FC4
1FC
5
1FC6
1FD
2
1FD3
1G351G36
1G37
1G501G51
1M09
1M20 1M591M711M
951M
99
1N00
1P00
1P021P031P04
1P05
1P07
1P08
1P09
1S02
1T01
1T851T86
1UM
0
2B44
2B45
2B46
2B47
2D052D06
2D07
2D08
2D09
2D10
2D11
2D12
2D16
2D19
2D20
2E01
2E04
2E06
2E10
2E12
2E13
2E14
2E15
2E16
2E17
2E18
2E19
2E202E21
2E22
2E24
2E27
2E29 2E30
2E31
2E32
2E33
2E35
2E36
2E37 2E38
2E39
2E40
2E41
2E44
2E48
2E49
2E50
2E51
2E54
2E55
2E56
2E57
2E58
2E59
2E60
2E62
2E63
2E66
2E67
2E68
2E70
2E71
2E72
2E73
2E74
2E75 2E76
2E77
2E78
2E79
2E80
2E81
2E82
2E83
2E84 2E
85
2E86
2E87
2E88
2E89
2E90
2E91
2E92
2E93
2E94
2E95
2E96
2E97
2E98
2E99
2EB1
2EB
3
2EC1
2ECC
2ECM
2ECN
2EC
P
2ECU
2EE
0
2EE1
2EE22EE3
2EE
4
2EE
52EE
6
2EE
7
2F01
2F29
2F32
2F33
2F342F35
2F40
2F58
2F60
2F81
2F86
2F88
2F902F
91
2F92
2F93
2F94
2FC
1
2FC
2
2FC
3
2FC
4
2FC
5
2FC
6
2FC
7
2FC8
2G10
2G11
2G12
2G132G14
2G15
2G16
2G17
2G18
2G19
2G24
2G25
2G26
2G27
2G28
2G29
2G75
2G762G77
2G78 2G79
2G7A
2G96
2G97
2G98
2G99
2GA
4
2S2R
2S2S
2S2T
2S2V
2S2W
2S2Y
2S2Z
2S30
2S31
2S32
2S33
2S34
2S41
2S4D
2S4E
2S4F
2S4G
2S4M
2S772S78
2S7E
2S7H
2S7J
2S7K
2S7L
2S7M
2S7N
2S7P
2S7Q
2S7R
2S7U
2S87
2S8G
2T70
2T76
2T77
2T78
2T79
2T80
2T81
2T82
2T83
2T84
2T85
2U09
2U11
2U15
2U16
2U17 2U18
2U19
2U20
2U23
2U24
2U25
2U27
2U28
2U41
2U42
2U43
2U44
2U45
2U46
2U48
2U49
2U51
2U52
2U53
2U72
2UD0
2UD1
2UD2
2UD
3
2UD
4
2UD
5
2UD6
2UD7
2UD
82U
D9
2UE
0
2UE
1
2UE
2
2UE
3
2UE4
2UE
62UE8
2UE
9
2US
3
2UU
0
2UU1
3B00
3B02
3B04
3B05
3B07
3B08
3B10
3B11
3B123B13
3B143B15
3B163B17
3B183B19
3B23
3B24
3B25
3B26
3E07
3E11
3E14
3E15
3E163E17
3E183E19
3E20
3E21
3E22
3E24
3E25
3E26
3E30
3E313E32
3E33
3E35
3E37
3E39
3E40
3E43
3E44
3E45
3E48
3E49
3E52
3E53
3E61
3E62
3E63
3E64
3E653E66
3E693E70
3E71
3E72
3E73
3E74
3E75 3E76
3E77
3E78
3E79
3E80
3E82
3E83
3E84
3E85
3E86
3E87
3E88
3E89
3E90
3E95
3E96
3E97
3E98
3EA
1
3EA2
3EB
1
3EB
3
3EB6
3EB9
3EC3
3EC5
3EC
F
3EC
G
3ECM
3ECN
3ECP
3EE
03E
E1
3EE2
3F26
3F28
3F31
3F36
3F58
3F59
3F60
3F623F63
3F64
3F65
3F71
3F72
3F75
3F78
3FC
1
3FC2
3FC
33F
C4
3FC
5
3FC
6
3FC
7
3G103G11 3G12
3G13
3G14
3G15
3G28
3GA
1
3GA
5
3S00
3S01
3S02
3S03
3S04
3S123S13
3S14
3S1B
3S1C
3S1E
3S1J3S1K
3S1L
3S21
3S233S
24
3S26
3S27
3S28
3S29
3S2A
3S2M
3S3F
3S3G3S3H
3S3L
3S3M
3S3N
3S3Q
3S3R
3S3S
3S3T
3S3U
3S3W
3S3Y
3S42
3S433S44
3S4G
3S4J
3S4K
3S4L
3S4P
3S4R
3S4T
3S4U
3S4W
3S50
3S52
3S53
3S54
3S59
3S5L
3S62
3S6H
3S6J
3S6K
3S803S81
3S833S84
3T70
3T74
3T75
3T76
3T77
3T78
3T79
3T80
3T81
3T82
3T83
3T90
3T91
3T92
3T93
3U06 3U
07
3U23
3U24
3U26
3U29
3U42
3U43
3U44
3U45
3U56
3U64
3U65
3U66
3U67
3U71
3U81
3U84
3UD0
3UD1
3UD2
3UD
33U
D4
3UD
5
3US2
3US3
3US4
3US5
3US6
3US7
3US
9
3UU
0
3UU1
3UU2
3UU
3
5D01
5D02
5D04
5D05
5D07
5D08
5E06
5E08
5E73 5E74
5E76
5E77
5E78 5E795E80
5EC2
5F70
5F72
5F73
5T53
5T54
5U00
5U01
5U02
5U03
5UD
0
5UD
1
5UD
25U
D3
5UM
0
5UM1
6E01
6E02
6E03
6E06
6E07
6E08
6E09
6E10
6E12
6E14
6E156E16
6E19
6E20
6E22
6E23
6E24
6E26
6E28
6E29
6E30
6E31
6E32
6E34
6E35
6E36
6E37
6E38
6E40
6E436E44
6E46
6E51
6E52
6EC1
6F72
6FC1
6FC2
6FC3
6FC4
6FC5
6FC6
6FC7
6FC8
6FD
26F
D3
6G00
6GA0
6GA1
6GA2
6GA3
6U00
6UD
0
7B00
7B01
7B02
7B03
7D10
7E01
7E04
7E05
7E06
7E09
7E10
7EC1
7EE0
7EE1
7F20
7F25
7F58
7F70
7GA0 7GA
1
7GA2
7S00
7S08
7U01
7U02
7U04
7U05
7UD
0
7UD
1
7US
1
7US
2
7US
3
7UU0
7UU
1
7UU2
7UU3
9E01
9E02
9E04
9E05
9E06
9E07
9E08 9E099E10
9E29
9E429E43
9E50
9E51
9E52
9E53
9E54
9E55
9E579E58
9EC3
9F00
9F01
9F04
9F05
9F06
9F27
9F28
9F71
9FC
3
9FC
4
9FC
5
9FC6
9G0K
9GA
0
9S00
9S06
9S149S15
9US0
9UU0 9UU1
BE00
BE
01
BE02
BE03
BE20BE21BE22
BE
C0
BE
C1
BEC2BEC3 B
EC
4
BE
C5
BS
09B
S10
BS
13
BS
15
CD
10
DB
S8
DS50
IE07
IE09
IE10
IE11
IE39
IE42
IEE3
IEE4
IEE5
IEE6
IF61
IF62
IF86
IF89
IG11
IGA0
IGA1IGA2
IGA3
IS13
IT74IT75
IU15
IU17
IU18
IU23
IU57
IUD0IUD1 IUD2
IUD
4
IUS3
IUS4
IUS5
IUS6
IUS
9
IUT1
IUT
2
3104 313 6364.3
Circuit Diagrams and PWB Layouts EN 119Q552.1A LA 10.
2010-Apr-02 back to div. table
Overview bottom side
1FE
0
1G00
1G03
1U40
2B00
2B012B02
2B03
2B04
2B05
2B06
2B07
2B08
2B09
2B10
2B112B
12
2B13
2B14
2B15
2B16
2B17
2B182B192B
20
2B21
2B222B23
2B24
2B25
2B26
2B27
2B282B
29
2B30
2B31
2B322B33 2B342B35
2B36
2B37
2B38
2B39
2B40
2B41
2B42
2B43
2D01
2D02
2D03
2D13
2D14
2D17
2D21
2D22
2D23
2D24
2D26
2D27
2D28
2D29
2E522E53
2EA4
2EA5
2EC
0
2EC
2 2EC3
2EC
6
2EC
7
2EC8
2ECQ
2EC
V
2EC
W
2F00
2F02
2F03
2F04
2F05
2F06
2F20
2F21
2F25
2F26
2F27
2F28
2F30
2F31
2F52
2F53
2F59
2F61
2F62
2F632F64
2F652F
66
2F70
2F71
2F72
2F73
2F74
2F75
2F76
2F77
2F78
2F79
2F80
2F82
2F84
2F85
2FA
2
2FA3
2FA
4
2FD1
2FDC
2FDD
2FE0
2FE
3
2FE4
2FE
5
2FE6
2FE8
2FF0
2FF1
2FF
2
2FF
3
2FF
4
2FF52FF6
2FF
7
2FF8
2FF
9
2FG
02F
G1
2FG
22F
G3
2FG4
2FG62FG7
2FG8
2FG9
2FH
2
2FH3
2FH
4
2FH5
2FH6
2FH7
2FH8
2G43
2G44
2G92
2G93
2G94
2G95
2GA
0
2GA1
2GA2
2GA
3
2GA
52G
E0
2S10
2S11
2S12
2S13
2S14
2S15
2S16
2S17
2S18
2S19
2S20
2S21
2S22
2S23
2S24
2S25
2S26
2S27
2S28
2S292S
2E
2S2G
2S2H
2S2J
2S2K
2S2L
2S36
2S37
2S38
2S39
2S3A
2S3B
2S3C
2S3D
2S3E
2S3F
2S3G
2S3H
2S3J
2S3K
2S3L
2S3M
2S3Q
2S40
2S42
2S43
2S45
2S46
2S4K
2S4N
2S4P
2S4Q2S
4R
2S4S
2S4T
2S4U
2S4V
2S4W
2S4Y
2S4Z
2S50
2S51
2S52
2S53
2S55
2S56
2S57
2S582S
59
2S5A
2S5B
2S5C2S
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3104 313 6364.318770_581_100216.eps
100216
EN 120Q552.1A LA 11.Styling Sheets
2010-Apr-02 back to div. table
11. Styling Sheets
11-1 Matisse 32" - 46"
0004
0024
0260
0029
0010
0021
0010
0018
Pos Nbr Description Remarks
0004 Front Cabinet
0010 Rear Cover (with left & right diffuser)
0018 Leading edge cover
0021 I/O bracket side
0024 I/O bracket bottom
0029 Switch bracket
0162 Mid High Speaker Interface bracket 32" Not displayed. For screen size 32" only
0189 Front Cabinet Locking Bracket 40" Not displayed. For screen size 40" only
0260 Stand
1085 Remote Control Not displayed
1114 Keyboard assy
5213 Loudspeaker assy (left & right)
18770_803_100216.eps100401
MATISSE 32"- 46"
FOR ELECTRICAL PARTS SEE WIRING DIAGRAM CHAPTER 9