CMPE 421 Advanced Computer Architecture

Supplementary material for Pipelining

PART1

2

3

30 40 20 30 40 20 30 40 20 30 40 20

6 PM 7 8 9 10 11 Midnight

Time

Pipelining Lessons: Laundry Machine example

Slow Way

• If each load is done sequentially it takes 6 hours

4Pipelined laundry takes 3.5 hours

Pipelining Lessons: Laundry Machine example

Quick way 6 PM 7 8 9

Time

30 40 40 40 40 20

5

Single Cycle Datapath

6

AL

U

Pipeline Divisions

• Divide datapath into steps 1 cycle each• Instructions range from 3-5 stages in MIPS pipeline

Regs

Regs

DataMemory

Instr.Memory

IFInstruction

Fetch

ID/RFRegister

Fetch

EXExecution

MEM.Memory

WBWriteback

PC

7

Revised: Single Cycle Datapath

8

Multicycle Datapath/Control

Shiftleft 2

PCMux

0

1

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Instruction[15– 11]

Mux

0

1

Mux

0

1

4

Instruction[15– 0]

Signextend

3216

Instruction[25– 21]

Instruction[20– 16]

Instruction[15– 0]

Instructionregister

ALUcontrol

ALUresult

ALUZero

Memorydata

register

A

B

IorD

MemRead

MemWrite

MemtoReg

PCWriteCond

PCWrite

IRWrite

ALUOp

ALUSrcB

ALUSrcA

RegDst

PCSource

RegWriteControl

Outputs

Op[5–0]

Instruction[31-26]

Instruction [5– 0]

Mux

0

2

Jumpaddress [31-0]Instruction [25– 0] 26 28

Shiftleft 2

PC [31-28]

1

1 Mux

0

3

2

Mux

0

1ALUOut

Memory

MemData

Writedata

Address

write controlwrite control

write control

9

Pipeline Datapath

10

Load Datapath: Stage 1

A

11

Load Datapath: Stage 2

B

12

Load Datapath: Stage 3

13

Load Datapath: Stage 4

A

14

Load Datapath: Stage 5

B

15

Store Datapath: Stage 3

16

Store Datapath: Stage 4

17

Store Datapath: Stage 5

18

Corrected Pipelined datapath for lw