cmos testing-2 - duke electrical and computer...
TRANSCRIPT
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ECE 261 James Morizio 1
CMOS Testing-2• Design and test• Design for testability (DFT)
– Scan design
• Built-in self-test• IDDQ testing
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ECE 261 James Morizio 2
Design and Test Flow: Old View• Test was merely an afterthought
Specification
DesignDesignerrors
Fabrication
Testing
Randomdefects
Synthesis, full-customsimulation, verification,test generation
Accept Reject
Pass Fail
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Design and Test Flow: New ViewDesign and test are tightly coupled
Specification
Design fortestability
Designerrors
Fabrication
Testing
Randomdefects
Accept Reject
Pass Fail
Processimprovements
Designimprovements
Diagnosis
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Testing Sequential CircuitsDifficult problem-internal states cannot be directly controlled and observedLong test sequences are necessarySolution: Scan design-simplify to combinational circuit testing
Combinationallogic
Registers
Primaryinputs
Primaryoutputs
(controllable) (observable)
State outputs(not observable)State inputs
(not controllable)
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Design for Test
• Design the chip to increase observability and controllability
• If each register could be observed and controlled, test problem reduces to testing combinational logic between registers.
• Better yet, logic blocks could enter test mode where they generate test patterns and report the results automatically.
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Scan DesignMake all flip-flops directly controllable and observable by adding multiplexersPopular design-for-test (DFT) technique-circuit is now combinational for testing purposes
Combinationallogic
Primaryinputs
Primaryoutputs
Scan in
Scan out
Scan cells
State inputsState outputs(controllable)(observable)
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Scan Design• Convert each flip-flop to a scan register
– Only costs one extra multiplexer
• Normal mode: flip-flops behave as usual• Scan mode: flip-flops behave as shift register
• Contents of flopscan be scannedout and new values scannedin
Flo
p
QD
CLK
SI
SCAN
scan out
scan-in
inputs outputs
Flo
pF
lop
Flo
pF
lop
Flo
pF
lop
Flo
pF
lop
Flo
pF
lop
Flo
pF
lop
LogicCloud
LogicCloud
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Scan Cell Design0
1D Q
Scan in(Test data)
Data(Functional)
N/T
N/T = 1: Test mode
N/T = 0: Normal mode
Scanin
ClockD0 D1 D2 D3
Scanout
N/TQ0 Q1 Q2 Q3Clock
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ECE 261 James Morizio 9
Scannable Flip-flops
0
1 Flo
pCLK
D
SI
SCAN
Q
Dφ
φ
φ
φ
X
Q
Qφ
φ
φ
φ
(a)
(b)
SCAN
SI
Dφ
φ
X
Q
Qφ
φ
φ
φ
SI
φs
φs(c)
φ
φd
φd
φd
φs
SCAN
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ECE 261 James Morizio 10
Scan Design• Separate input and output 4-bit scan registers• Test sequence: {01100, 11011}, first 4 bits are for flip-flops
Combinational circuitCombinational circuit
Scan chain/Scan path
Test data
Test responses
01101101
10
Controllableprimaryinput
N/T
N/T
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Steps in Scan Testing• N/T = 1: Scan in test pattern, hold appropriate bit
pattern on controllable primary inputs• N/T = 0: Apply test pattern to combinational circuit• N/T=1: Scan out test responses• Scan provides complete controllability and
observability• Testing time? How many cycles? How to test scan
registers?
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Long Scan Chains
Test vectors need to be translated to scan format
Nor
mal
dat
a
Scan chainTest data
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Built-in Self-test
• Built-in self-test lets blocks test themselves– Generate pseudo-random inputs to comb. logic– Combine outputs into a syndrome– With high probability, block is fault-free if it produces
the expected syndrome
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Built-in Self Testing (BIST)
On-chip test generator and response monitor
Testgenerator
(TGC)
Testgenerator
(TGC)
(CUT)
Control
InputsOutputs
Error
0
1
Responsemonitor
(RM)
Responsemonitor
(RM)
Circuitunder test
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BIST: Advantages• Lower cost due to elimination of external tester
• Sematech’s projection: 500 MHz tester (400 pins) will cost $50M in 2010, 90% of on-chip testing will be done using BIST
• In-system, at-system, high-quality testing• Faster fault detection, ease of diagnosis• Overcomes pin limitations and related interfacing problems• Reduces maintenance and repair costs at system level
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BIST: IssuesTest strategy (random, exhaustive, deterministic)Circuit partitioningTest pattern generation
Exhaustive: countersRandom: Linear-feedback shift registers (LFSRs)Deterministic: ROM, other methods?
Response analysisTest control and scheduling
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BIST Logic Circuits
Test patterns
• Linear-feedback shift-register (LFSR)
• Multiple-input signature register (MISR) Test responses
Signature
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BIST Pattern Generation• Linear Feedback Shift Register
– Shift register with input taken from XOR of state– Pseudo-Random Sequence Generator
Flo
p
Flo
p
Flo
pQ[0] Q[1] Q[2]
CLK
D D D
7654321
1110QStep
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BIST Pattern Generation• Linear Feedback Shift Register
– Shift register with input taken from XOR of state– Pseudo-Random Sequence Generator
Flo
p
Flo
p
Flo
pQ[0] Q[1] Q[2]
CLK
D D D
765432
11011110QStep
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ECE 261 James Morizio 20
PRSG• Linear Feedback Shift Register
– Shift register with input taken from XOR of state– Pseudo-Random Sequence Generator
Flo
p
Flo
p
Flo
pQ[0] Q[1] Q[2]
CLK
D D D
76543
101211011110QStep
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PRSG• Linear Feedback Shift Register
– Shift register with input taken from XOR of state– Pseudo-Random Sequence Generator
Flo
p
Flo
p
Flo
pQ[0] Q[1] Q[2]
CLK
D D D
7654
0103101211011110QStep
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PRSG• Linear Feedback Shift Register
– Shift register with input taken from XOR of state– Pseudo-Random Sequence Generator
Flo
p
Flo
p
Flo
pQ[0] Q[1] Q[2]
CLK
D D D
765
10040103101211011110QStep
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PRSG• Linear Feedback Shift Register
– Shift register with input taken from XOR of state– Pseudo-Random Sequence Generator
Flo
p
Flo
p
Flo
pQ[0] Q[1] Q[2]
CLK
D D D
76
001510040103101211011110QStep
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PRSG
• Linear Feedback Shift Register– Shift register with input taken from XOR of state– Pseudo-Random Sequence Generator
Flo
p
Flo
p
Flo
pQ[0] Q[1] Q[2]
CLK
D D D
70116001510040103101211011110QStep
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PRSG
• Linear Feedback Shift Register– Shift register with input taken from XOR of state– Pseudo-Random Sequence Generator
Flo
p
Flo
p
Flo
pQ[0] Q[1] Q[2]
CLK
D D D
111 (repeats)70116001510040103101211011110QStep
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BILBO• Built-in Logic Block Observer
– Combine scan with PRSG & signature analysis
MODE C[1] C[0]Scan 0 0Test 0 1Reset 1 0Normal 1 1
Flo
p
Flo
p
Flo
p
1
0
D[0] D[1] D[2]
Q[0]Q[1]
Q[2] / SOSI
C[1]C[0]
PRSGLogicCloud
SignatureAnalyzer
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Boundary Scan
• Testing boards is also difficult– Need to verify solder joints are good
• Drive a pin to 0, then to 1• Check that all connected pins get the values
• Through-hold boards used “bed of nails”• SMT and BGA boards cannot easily contact pins• Build capability of observing and controlling pins
into each chip to make board test easier
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Boundary Scan Example
Serial Data In
Serial Data Out
Package Interconnect
IO pad and Boundary ScanCell
CHIP A
CHIP B CHIP C
CHIP D
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Boundary Scan InterfaceIEEE 1149.1 JTAG standard
• Boundary scan is accessed through five pins– TCK: test clock– TMS: test mode select– TDI: test data in– TDO: test data out– TRST*: test reset (optional)
• Chips with internal scan chains can access the chains through boundary scan for unified test strategy.
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BIST in IndustryEarly days: AT&T (Lucent) incorporated BIST in hundreds of commercial chips
Intel: 80386, Pentium, Pentium ProHardware overhead typically 15% of self-tested portion (around 5% for entire chip, e.g. 6% for the Pentium Pro)Regular embedded arrays (RAMs, PLAs) almost always tested using BIST: DEC Alpha, PowerPCBIST for irregular logic not so widespread
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IDDQ Testing• Based on current measurements, not voltage
– IDDQ = IDD quiescent
• In CMOS technology, quiescent current is very low
• Testing idea: check for faults by detecting current spikes– Advantage: Massive observability, good for detecting shorts– Disadvantage: slow, leakage current closer to quiescent current for
deep submicron