clp preliminary datasheet - esamicroelectronics.esa.int/components/d17-clp-preliminary... · 2017....
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CLP-TN-C-007-SABC
Iss.1 Rev.1
26/08/2016
Page : 1/360
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Category: 4 Class: 2
Prepared by: M. Ruiz
26/08/16
Checked by:
CLP Team Feron J-B
30/08/16
Duthoit S.
30/08/16
Lapierre S.
31/08/16
Chapeaux T.
31/08/16
Botero D. 31/08/16
Approved by:
P. Lenelle
07/09/16
Authorised by:
M. Ruiz
08/09/16
CLP PROGRAM
CLP Preliminary Datasheet
CLP-TN-C-007-SABC
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Issued by : SABCA Contractual : Yes (X) No () Date : 26/08/2016
Customer : Contract Number:
TITLE : CLP Preliminary Datasheet AUTHOR: Marco Ruiz AUTHOR'S ABSTRACT: This document presents the CLP Preliminary Datasheet
TOTAL NUMBER OF PAGES: 360 - Number of Annexes : n/a
File Identification : CLP-TN-C-007-SABCLARi1r1.docx
Distribution Key Words
Internal External processor, motor, ASIC, real-time Dept. N° Cop. Names Dept./Company N° Cop. Names
Document’s signatories ESA/ESTEC 1 R. Weigand
CLP Team 1 L. Van Hilten
K. Vekemans 1 P. Parisis
1 D. Torette
TE = Transfert électronique
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ISSUE / REVISION STATUS
Date Iss./ Rev. N°
Brief Description of Change Mod.
N° ECP/PM
N°
Config. Control
Approval
09/06/2016 1/0 First Issue (based on DOORS “CLP Requirements
specification” module baseline 5.1 and DOORS ‘CLP
User manual” module baseline 1.0 )
LF-PDR-18: statement suggesting to make RGPx scrubbing by SW has been added
08/08/2016 1/1 RID BR640: Use rule added in case of sticky mode configuration during boot.
RID BR629: Forbidden READSEL on ADCIF_CS[x] with SELADC[x] disabled.
$7.1.1: Clarified that NaN, infinite and denormalised values are managed when floating point operations are executed
RID RW-PDR-44 and RID RW-PDR-46: Consistent conventions for registers names, pin names
RID BR202: Clarified that after each Boot Tentative or SWRST, "Clock and Reset Control" registers should be manually re-initialised.
RID BR778: Clarified that tracing CPU activity while this one is reset is forbidden.
RID BR764: Removed register M1553_EVENTEN.
RID BR369: Provided list of forbidden combination of instructions leading to conflict in destination registers (simultaneous write)
RID PM-PDR-03: Added behavior of the CLP execution float in case of abnormal calculation.
Correct Instruction Set descriptions.
RW-PDR-21: Added CRC clock gating and reset control; Replaced Assembler by Assembly when necessary.
RW-PDR-47: Uniformized format of Register definitions for XML Golden source extraction.
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Date Iss./ Rev. N°
Brief Description of Change Mod.
N° ECP/PM
N°
Config. Control
Approval
Renamed section §31 from Annex to APB registers description.
RW-PDR-48: Replace “IO” by “IO standard” in the
pinout section.
Update reset values for FPU register, RMEM and ROUTAPB to 32-bits values.
§ 28.7 Corrected Typo MAC address in section 28.7
§ 31.1.16 For GPIO_MEM8_CONF replaced binary number notation 000000000x by explicit numbers 0000000000b and 0000000001b.
§ 31.1.16 Removed “Note: During the Boot, if the boot source is the MEM8, it is mandatory that the user set BRST to 08h and MEM8SEL to ‘1’” (not mandatory anymore).
RID BR669: Added IEEE-754 compliance matrix
§28.4: Added additional description for address tracer when Masked instruction with RMEM.
RID BR756: Replaced “highly advised” sentence with “mandatory”.
RID-PDR-003: Improved description of division by Zero.
RID-PDR-009: Clarified that limit of the Code size corresponds to the RAM size
RW-PDR-44: Added naming and text conventions in whole text (cfr §5.1)
Fixed missing cross-references. Harmonised §4 to make it more user-friendly to users.
§27.1 Added reference to GPIO registers in IOMUX description.
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TABLE OF CONTENTS
1 INTRODUCTION ........................................................................................................................ 18
2 DOCUMENTS AND ACRONYMS ................................................................................................. 18
2.1 APPLICABLE DOCUMENTS ............................................................................................................... 18 2.2 REFERENCES ................................................................................................................................ 19 2.3 ACRONYMS ................................................................................................................................. 19
3 THE CLP IN A GLANCE… ............................................................................................................. 21
4 THE CONTROL LOOP PROCESSOR .............................................................................................. 23
4.1 FUNCTIONAL DIAGRAM ............................................................................................................ 23 4.2 SUMMARY ............................................................................................................................... 24
5 CONVENTIONS AND DEFINTIONS .............................................................................................. 27
5.1 TEXT FORMATTING ................................................................................................................... 27 5.2 CONTENT ................................................................................................................................. 27
6 DEVICE ..................................................................................................................................... 30
6.1 PINOUT .................................................................................................................................... 30 6.2 CHARACTERISTICS .................................................................................................................... 35
6.2.1 RECOMMENDED OPERATING CONDITIONS ....................................................................................... 35 6.2.2 ABSOLUTE MAXIMUM RATINGS ..................................................................................................... 35 6.2.3 AC CHARACTERISTICS ................................................................................................................... 35 6.2.4 DC CHARACTERISTICS ................................................................................................................... 44 6.2.5 ENVIRONMENTAL REQUIREMENTS .................................................................................................. 47
6.3 PACKAGE ................................................................................................................................. 47 6.4 QUALITY FLOW ......................................................................................................................... 47
7 CENTRAL PROCESSING UNIT (CPU) ............................................................................................ 48
7.1 ARCHITECTURE ............................................................................................................................ 48 7.1.1 IEEE-754 IMPLEMENTATION ......................................................................................................... 49 7.1.2 CONDITION CODES .................................................................................................................. 50 7.1.3 INTEGER FORMAT ................................................................................................................... 51 7.1.4 REGISTER FILES ............................................................................................................................ 52 7.1.5 SU UNIT ..................................................................................................................................... 54 7.1.6 INSTRUCTION SET ........................................................................................................................ 64 7.1.7 APB AND PROGRAM MEMORY MANAGEMENT .................................................................................. 82
7.2 DIRECT MEMORY ACCESS (DMA) .................................................................................................... 90 7.3 ON-CHIP COMMUNICATION ..................................................................................................... 92
7.3.1 OVERVIEW.................................................................................................................................. 92
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7.3.2 ADDRESS ALLOCATION ............................................................................................................ 94 7.3.3 APB MODE SWITCH ................................................................................................................. 95 7.3.4 PERIPHERAL ADDRESS PARTITIONING..................................................................................... 96 7.3.5 SPECIAL BEHAVIOURS ............................................................................................................. 96 7.3.6 APB ADDRESS MAPPING .......................................................................................................... 96
7.4 FAULT TOLERANCE ................................................................................................................... 98 7.4.1 CPU .......................................................................................................................................... 98 7.4.2 APB BUS AND WP/AL BITS ..................................................................................................... 106 7.4.3 EDAC MANAGEMENT ............................................................................................................ 107 7.4.4 MONITORING FUNCTIONS ........................................................................................................... 108
8 SPI .......................................................................................................................................... 109
8.1 OVERVIEW .............................................................................................................................. 109 8.1.1 CONVENTIONS ...................................................................................................................... 109 8.1.2 4-WIRE EXCHANGES ................................................................................................................... 110 8.1.3 3-WIRE MODE CASES .................................................................................................................. 112 8.1.4 RECEIVE AND TRANSMIT QUEUES.................................................................................................. 112 8.1.5 CLOCK GENERATION (MASTER MODE) .......................................................................................... 113 8.1.6 AUTOMATED PERIODIC TRANSFERS (MASTER MODE) ...................................................................... 113 8.1.7 CCS/CDOL (MASTER MODE) ..................................................................................................... 114 8.1.8 SPECIFIC CASES (MASTER MODE) ................................................................................................. 115
8.2 I/O SIGNALS ............................................................................................................................ 117 8.3 APB INTERFACE ....................................................................................................................... 118
9 UART ...................................................................................................................................... 120
9.1 OVERVIEW .............................................................................................................................. 120 9.2 BEHAVIOUR ............................................................................................................................ 120 9.3 I/O SIGNALS ............................................................................................................................ 122 9.4 APB INTERFACE ....................................................................................................................... 123
10 INTERCOM RAM ...................................................................................................................... 124
10.1 OVERVIEW .............................................................................................................................. 124 10.2 I/O SIGNALS ............................................................................................................................ 124 10.3 APB INTERFACE ....................................................................................................................... 124
11 CRC ......................................................................................................................................... 125
11.1 OVERVIEW .............................................................................................................................. 125 11.2 I/O SIGNALS ............................................................................................................................ 126 11.3 APB REGISTERS........................................................................................................................ 126
12 GPIO AND MEM8 INTERFACE ................................................................................................... 127
12.1 OVERVIEW .............................................................................................................................. 127
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12.2 BEHAVIOUR ............................................................................................................................ 127 12.2.1 MEM8 (8-BIT PARALLEL INTERFACE) ................................................................................... 129
12.3 I/O SIGNALS ............................................................................................................................ 132 12.4 APB INTERFACE ....................................................................................................................... 132
13 PWM ...................................................................................................................................... 133
13.1 OVERVIEW .............................................................................................................................. 133 13.1.1 ENABLE/DISABLE ................................................................................................................. 133 13.1.2 PWM FREQUENCY ............................................................................................................... 134
13.2 I/O SIGNALS ............................................................................................................................ 137 13.3 APB INTERFACE ....................................................................................................................... 137
14 TIMERS ................................................................................................................................... 138
14.1 OVERVIEW .............................................................................................................................. 138 14.1.1 PRESCALERS ........................................................................................................................ 138 14.1.2 TIMERS ................................................................................................................................ 139
14.2 I/O SIGNALS ............................................................................................................................ 139 14.3 APB INTERFACE ....................................................................................................................... 140
15 ADC PARALLEL INTERFACE ....................................................................................................... 141
15.1 OVERVIEW .............................................................................................................................. 141 15.1.1 ACQUISITION PHASE ........................................................................................................... 142 15.1.2 READ SEQUENCE PHASE ...................................................................................................... 143
15.2 I/O SIGNALS .............................................................................................................................. 146 15.3 APB REGISTERS........................................................................................................................ 147
16 AWG ....................................................................................................................................... 148
16.1 OVERVIEW .............................................................................................................................. 148 16.2 IO SIGNALS .............................................................................................................................. 150 16.3 APB INTERFACE ....................................................................................................................... 150
17 MMU AND MIL-STD-1553 RT,SPACEWIRES/RMAP AND CAN ..................................................... 151
17.1 OVERVIEW .............................................................................................................................. 151 17.2 MMU ...................................................................................................................................... 152
17.2.1 MEMORY PROTECTION ....................................................................................................... 152 17.2.2 APB INTERFACE ................................................................................................................... 153
17.3 MANAGEMENT OF INTERACTIONS BETWEEN THE XCHGRAMS AND ITS INTERFACES .................. 154 17.3.1 MIL-STD-1553 RT ................................................................................................................. 154 17.3.2 SPACEWIRE/RMAP .............................................................................................................. 161 17.3.3 CAN...................................................................................................................................... 168
17.4 IO SIGNALS .............................................................................................................................. 170
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18 MIL-STD-1553 RT ..................................................................................................................... 171
18.1 OVERVIEW .............................................................................................................................. 171 18.1.1 COMPLIANCE TO MIL-STD-1553 STANDARD ............................................................................... 171 18.1.2 COMPLIANCE TO ECSS-E-ST-50-13C STANDARD ......................................................................... 171 18.1.3 INTERACTION WITH XCHGRAMS, MMU AND SOFTWARE ................................................... 172
18.2 IO SIGNALS .............................................................................................................................. 173 18.3 APB INTERFACE ....................................................................................................................... 173
19 CAN ........................................................................................................................................ 174
19.1 OVERVIEW .............................................................................................................................. 174 19.1.1 INTERACTION WITH XCHGRAMS, MMU AND SOFTWARE ................................................... 174
19.2 APB INTERFACE ....................................................................................................................... 174
20 SPACEWIRE/RMAP .................................................................................................................. 175
20.1 OVERVIEW .............................................................................................................................. 175 20.2 ECSS-E-ST-50-12C COMPLIANCE ................................................................................................... 175 20.3 I/O SIGNALS .............................................................................................................................. 179 20.4 APB INTERFACE ....................................................................................................................... 179 20.5 INTERACTION WITH XCHGRAMS, MMU AND SOFTWARE ........................................................... 180
21 IOMUX .................................................................................................................................... 181
21.1 OVERVIEW .............................................................................................................................. 181 21.2 APB INTERFACE ....................................................................................................................... 187
22 CLOCK AND RESET CONTROL ................................................................................................... 188
22.1 OVERVIEW .............................................................................................................................. 188 22.2 APB REGISTERS........................................................................................................................ 188
23 PROGRAM RAM ...................................................................................................................... 189
23.1 OVERVIEW .............................................................................................................................. 189 23.2 I/O SIGNALS ............................................................................................................................ 189 23.3 APB INTERFACE ....................................................................................................................... 189
24 XCHG RAM .............................................................................................................................. 190
24.1 OVERVIEW .............................................................................................................................. 190 24.2 I/O SIGNALS ............................................................................................................................ 190 24.3 APB INTERFACE ....................................................................................................................... 190
25 HW STATUS AND CONFIGURATION .......................................................................................... 191
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25.1 OVERVIEW .............................................................................................................................. 191 25.1.1 CPU HARDWARE STATUS .......................................................................................................... 191 25.1.2 BOOT DESCRIPTORS SELECTION .......................................................................................... 192 25.1.3 INTERFACE HARDWARE ENABLING ..................................................................................... 192
25.2 I/O SIGNALS ............................................................................................................................ 194 25.3 APB REGISTERS........................................................................................................................ 194
26 SCRUBBING MANAGEMENT..................................................................................................... 195
26.1 OVERVIEW .............................................................................................................................. 195 26.1.1 SCRUBBING PRINCIPLE ........................................................................................................ 195
26.2 APB REGISTERS .......................................................................................................................... 196
27 BOOT MANAGER ..................................................................................................................... 197
27.1 OVERVIEW .............................................................................................................................. 197 27.2 USER INTERACTION ................................................................................................................. 199
27.2.1 FIRST STEP ........................................................................................................................... 200 27.2.2 SECOND STEP ...................................................................................................................... 200
27.3 RESTART PROCEDURE .............................................................................................................. 202 27.4 BOOT_FRAME ......................................................................................................................... 203
27.4.1 MAPPING WITH SPACEWIRE/RMAP,CAN AND RTBT ........................................................... 204 27.4.2 MEM8 CASE ......................................................................................................................... 205
27.5 BOOT DESCRIPTOR TABLE ........................................................................................................ 205
28 REAL-TIME BACKGROUND TRACER .......................................................................................... 206
28.1 OVERVIEW .............................................................................................................................. 206 28.2 ETHERNET FRAME ................................................................................................................... 207
28.2.1 UDP PACKET STRUCTURE .......................................................................................................... 207 28.2.2 ETHERNET HEADER STRUCTURE .................................................................................................. 207 28.2.3 IPV4 HEADER STRUCTURE ......................................................................................................... 208 28.2.4 UDP HEADER STRUCTURE ......................................................................................................... 209 28.2.5 IP ADDRESS ............................................................................................................................ 209
28.3 RTBT FRAMES .......................................................................................................................... 210 28.3.1 HOST TO RTBT FRAME DEFINITION ............................................................................................ 210 28.3.2 RTBT TO HOST FRAME DEFINITION ............................................................................................ 211
28.4 TRACING CAPABILITIES ............................................................................................................ 213 28.4.1 VARIABLE TRACER ............................................................................................................... 214
28.5 RTBT STATE MACHINE ............................................................................................................. 215 28.5.1 IDLE STATE .............................................................................................................................. 217 28.5.2 CONFIGURATION TRACERS STATE ............................................................................................... 218 28.5.3 CODE UPLOAD STATE ............................................................................................................... 219
28.6 RTBT COMMANDS ................................................................................................................... 222 28.6.1 REPORT_STATUS COMMAND .............................................................................................. 222 28.6.2 SET_IP_ADDRESS COMMAND ............................................................................................. 223 28.6.3 REPORT_IP_ADDRESS COMMAND ...................................................................................... 223 28.6.4 GO_INTO_CONFIGURATION_TRACERS_STATE COMMAND ............................................... 224
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28.6.5 GO_INTO_UPLOAD_STATE COMMAND .............................................................................. 224 28.6.6 GO_INTO_CPU_RUN COMMAND ........................................................................................ 224 28.6.7 GO_INTO_IDLE_STATE COMMAND ..................................................................................... 225 28.6.8 EDAC_CORRUPT COMMAND .............................................................................................. 225 28.6.9 FLUSH_RTBT_BUFFER COMMAND ...................................................................................... 227 28.6.10 SET_VARIABLE_TRACER_TABLE COMMAND ..................................................................... 227 28.6.11 ADDRESS TRACER .............................................................................................................. 228 28.6.12 APB TRACER ....................................................................................................................... 230 28.6.13 AHB TRACER ...................................................................................................................... 231 28.6.14 EVENTS OCCURING IN CASE OF MIL-STD-1553 TRANSFERS .............................................. 232 28.6.15 EVENTS OCCURING IN CASE OF SPACEWIRE TRANSFERS .................................................. 232 28.6.16 EVENTS OCCURING IN CASE OF CAN TRANSFERS .............................................................. 232 28.6.17 VARIABLE TRACER ............................................................................................................. 233
28.7 NOTE TO THE USER .................................................................................................................. 234
29 I2C .......................................................................................................................................... 235
29.1 OVERVIEW .............................................................................................................................. 235 29.2 IO SIGNALS .............................................................................................................................. 235 29.3 APB REGISTERS........................................................................................................................ 236
30 JTAG INTERFACE ...................................................................................................................... 237
31 APB REGISTERS DESCRIPTION .................................................................................................. 238
31.1 GENERAL-PURPOSE INPUTS OUTPUTS ...................................................................................... 238 31.1.1 GPIO_MODE15TO0 (CONFIGURATION REGISTER) ..................................................................... 238 31.1.2 GPIO_MODE31TO16 (CONFIGURATION REGISTER) ................................................................... 240 31.1.3 GPIO_MODE47TO32 (CONFIGURATION REGISTER) ................................................................... 242 31.1.4 GPIO_MODE63TO48 (CONFIGURATION REGISTER) ................................................................... 243 31.1.5 GPIO_MODE79TO64 (CONFIGURATION REGISTER) ................................................................... 244 31.1.6 GPIO_MODE95TO80 (CONFIGURATION REGISTER) ................................................................... 245 31.1.7 GPIO_OZ15TO0 (CONFIGURATION REGISTER) ........................................................................... 246 31.1.8 GPIO_OZ31TO16 (CONFIGURATION REGISTER) ......................................................................... 247 31.1.9 GPIO_OZ47TO32 (CONFIGURATION REGISTER) ......................................................................... 249 31.1.10 GPIO_OZ63TO48 (CONFIGURATION REGISTER) ....................................................................... 251 31.1.11 GPIO_OZ79TO64 (CONFIGURATION REGISTER) ....................................................................... 252 31.1.12 GPIO_OZ95TO80 (CONFIGURATION REGISTER) ....................................................................... 254 31.1.13 GPIO_INVAL31TO0 (DATA REGISTER) ................................................................................... 256 31.1.14 GPIO_INVAL63TO32 (DATA REGISTER) ................................................................................. 257 31.1.15 GPIO_INVAL95TO64 (DATA REGISTER) ................................................................................. 257 31.1.16 GPIO_MEM8CONF (CONTROL REGISTER) .............................................................................. 258 31.1.17 GPIO_MEM8ADD (DATA REGISTER)...................................................................................... 259 31.1.18 GPIO_MEM8RDATA (DATA REGISTER).................................................................................. 259 31.1.19 GPIO_MEM8WDATA (DATA REGISTER) ................................................................................ 260 31.1.20 GPIO_MEM8STAT (STATUS REGISTER) .................................................................................. 260
31.2 ADC INTERFACE ....................................................................................................................... 261 31.2.1 ADCIF_TIMSEL (CONFIGURATION REGISTER) ............................................................................. 261
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31.2.2 ADCIF_ACQSEL (CONFIGURATION REGISTER) ............................................................................ 261 31.2.3 ADCIF_READSEL5TO0 (CONFIGURATION REGISTER) .................................................................. 262 31.2.4 ADCIF_READSEL11TO6 (CONFIGURATION REGISTER) ................................................................ 263 31.2.5 ADCIF_WAVFSEL (CONFIGURATION REGISTER) ......................................................................... 264 31.2.6 ADCIF_REG0 TO ADCIF_REG11 (DATA REGISTER) ................................................................... 265
31.3 UART ...................................................................................................................................... 265 31.3.1 UART0_DATA8_RCV, … , UART3_DATA8_RCV (8-BIT WORD FIFO RECEIVE) (DATA
REGISTER) ............................................................................................................................................ 265 31.3.2 UART0_DATA8_TSM, … , UART3_DATA8_TSM (8-BIT WORD FIFO TRANSMIT) (DATA
REGISTER) ............................................................................................................................................ 266 31.3.3 UART0_LCR, … , UART3_LCR (LINE CONTROL REGISTER) (CONTROL REGISTER) ............................ 266 31.3.4 UART0_LSR, … , UART3_LSR (LINE STATUS REGISTER) (STATUS REGISTER) .................................. 267 31.3.5 UART0_FCR, … , UART3_FCR (FIFO CONTROL REGISTER) (CONTROL REGISTER) ........................... 269 31.3.6 UART0_DR, … , UART3_DR (DIVISOR REGISTER) (CONTROL REGISTER) ........................................ 269 31.3.7 UART0_DATA32_RCV, … , UART3_DATA32_RCV (32-BIT WORD FIFO RECEIVE) (DATA
REGISTER) ............................................................................................................................................ 270 31.3.8 UART0_DATA32_TSM, … , UART3_DATA32_TSM (32-BIT WORD FIFO TRANSMIT) (DATA
REGISTER) ............................................................................................................................................ 270 31.4 CRC ......................................................................................................................................... 271
31.4.1 CRC0_POL, CRC1_POL (CONFIGURATION REGISTER) ................................................................. 271 31.4.2 CRC0_CFG, CRC1_CFG (CONFIGURATION REGISTER) ................................................................. 272 31.4.3 CRC0_DATA_IN, CRC1_DATA_IN (DATA REGISTER) ................................................................ 272 31.4.4 CRC0_DATA_OUT, CRC1_DATA_OUT (DATA REGISTER) ......................................................... 273 31.4.5 CRC0_STAT, CRC1_STAT (STATUS REGISTER) .......................................................................... 274
31.5 SPI .......................................................................................................................................... 274 31.5.1 SPI0_CAPAREG, SPI1_CAPAREG (CONTROL REGISTER) ............................................................ 274 31.5.2 SPI0_MODREG, SPI1_MODREG (CONTROL REGISTER) ............................................................ 275 31.5.3 SPI0_EVTREG, SPI1_EVTREG (CONTROL REGISTER) ................................................................. 279 31.5.4 SPI0_MASKREG, SPI1_MASKREG (CONTROL REGISTER) .......................................................... 281 31.5.5 SPI0_CMDREG, SPI1_CMDREG (CONTROL REGISTER) ............................................................. 282 31.5.6 SPI0_TRSREG, SPI1_TRSREG (DATA REGISTER) ....................................................................... 282 31.5.7 SPI0_RCVREG, SPI1_RCVREG (DATA REGISTER) ...................................................................... 283 31.5.8 SPI0_SLVSELREG, SPI1_SLVSELREG (CONTROL REGISTER) ....................................................... 284 31.5.9 SPI0_AUTSLVSEL, SPI1_AUTSLVSEL (CONTROL REGISTER) ....................................................... 284 31.5.10 SPI0_AMCONFREG, SPI1_AMCONFREG (CONTROL REGISTER) .............................................. 285 31.5.11 SPI0_AMPERREG, SPI1_AMPERREG (CONTROL REGISTER) .................................................... 287 31.5.12 SPI0_AMMSKREG AND SPI1_AMMSKREG (CONTROL REGISTER) ............................................ 287 31.5.13 SPI0_AMTRSREG AND SPI1_AMTRSREG (DATA REGISTER) .................................................... 288 31.5.14 SPI0_AMRCVREG, SPI1_AMRCVREG (DATA REGISTER) ........................................................ 289 31.5.15 SPI0_CCS_CDOL, SPI1_CCS_CDOL (DATA REGISTER) ............................................................ 290
31.6 I2C .......................................................................................................................................... 290 31.6.1 I2C_MCKPRE (CONFIGURATION REGISTER) ............................................................................... 290 31.6.2 I2C_MCTRL (CONFIGURATION REGISTER) .................................................................................. 291 31.6.3 I2C_MTRREG (DATA REGISTER) .............................................................................................. 292 31.6.4 I2C_MRECREG (DATA REGISTER) ............................................................................................ 292 31.6.5 I2C_MCOM (CONTROL REGISTER) ............................................................................................ 293 31.6.6 I2C_MSTAT (STATUS REGISTER) .............................................................................................. 294 31.6.7 I2C_SADD (CONFIGURATION REGISTER) .................................................................................... 295
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31.6.8 I2C_SCTRL (CONTROL REGISTER) ............................................................................................. 296 31.6.9 I2C_SSTAT (STATUS REGISTER) ................................................................................................ 297 31.6.10 I2C_SMASK (CONTROL REGISTER) .......................................................................................... 298 31.6.11 I2C_SRECREG (DATA REGISTER) ............................................................................................ 298 31.6.12 I2C_STRREG (DATA REGISTER) .............................................................................................. 299
31.7 INTERCOM RAM ...................................................................................................................... 299 31.7.1 INCOMRAM_ADD0 TO INCOMRAM_ADD511(DATA REGISTER).............................................. 299
31.8 PWM ...................................................................................................................................... 300 31.8.1 PWM0_CONF, ..., PWM23_CONF (CONFIGURATION REGISTER) ............................................... 300 31.8.2 PWM0_T1T2, ..., PWM23_T1T2 (DATA REGISTER) ................................................................. 301
31.9 TIMERS ................................................................................................................................... 302 31.9.1 TIM_STRTFRZ (CONTROL REGISTERS) ....................................................................................... 302 31.9.2 TIM_CLR (CONTROL REGISTER) ................................................................................................ 303 31.9.3 TIM_PRESC0 AND TIM_PRESC1 (CONTROL REGISTER) .............................................................. 304 31.9.4 TIM_COMPREG0 TO TIM_COMPREG9 (DATA REGISTER) ........................................................ 304 31.9.5 TIM_CAPTREG0 TO TIM_CAPTREG9 (DATA REGISTER) ............................................................ 305 31.9.6 TIM_CTRLREG0 TO TIM_CTRLREG9 (CONTROL REGISTER) ....................................................... 305
31.10 IOMUX .................................................................................................................................... 306 31.10.1 IOMUX_PIN7TO0,.., IOMUX_PIN105TO104 (CONFIGURATION REGISTER) .............................. 306
31.11 BOOT MANAGER ..................................................................................................................... 308 31.11.1 BD0, BD1, BD2 AND BD3 (CONFIGURATION REGISTER) ............................................................. 308
31.12 CLOCK AND RESET CONTROL .................................................................................................... 309 31.12.1 CLOCKCTRL (CONTROL REGISTER) .......................................................................................... 309 31.12.2 RESETCTRL (CONTROL REGISTER) .......................................................................................... 310
31.13 PROGRAM RAM ...................................................................................................................... 311 31.13.1 PRAM_ADD0 TO PRAM_ADD32767(DATA REGISTER) ........................................................... 311
31.14 XCHGRAM ............................................................................................................................... 311 31.14.1 XCHGRAM_ADD0 TO XCHGRAM_ADD8191 (DATA REGISTER) .............................................. 311
31.15 AWG ....................................................................................................................................... 312 31.15.1 AWG0_CONF, AWG1_CONF (CONFIGURATION REGISTER) ..................................................... 312 31.15.2 AWG0_WFD0, ..., AWG0_WFD3, AWG1_WFD0,...AWG1_WFD3 (CONFIGURATION
REGISTER) 313 31.15.3 AWG0_STAT, AWG1_STAT (STATUS REGISTER) .................................................................... 314 31.15.4 AWG0_PT0, … , AWG0_PT63, AWG1_PT0, … , AWG1_PT63 (DATA REGISTER) .................... 315
31.16 SCRUBBING MANAGEMENT ..................................................................................................... 316 31.16.1 CPU0_SCR_ADDR, CPU1_SCR_ADDR, ICOM0_SCR_ADDR, ICOM1_SCR_ADDR, XCHG0_SCR_ADDR, XCHG1_SCR_ADDR (CONTROL REGISTER) ............................................................. 316 31.16.2 CPU0_SCR_CTRL, CPU1_SCR_CTRL, ICOM0_SCR_CTRL, ICOM1_SCR_CTRL, XCHG0_SCR_CTRL, XCHG1_SCR_CTRL (CONTROL REGISTER) ................................................................ 316
31.17 MMU ...................................................................................................................................... 317 31.17.1 MMU_PROT0_SPW0, MMU_PROT0_SPW1,MMU_PROT0_1553RT, MMU_PROT0_CAN (CONFIGURATION REGISTER) ................................................................................... 317 31.17.2 MMU_PROT1_SPW0, MMU_PROT1_SPW1, MMU_PROT1_1553RT, MMU_PROT1_CAN (CONFIGURATION REGISTER) ................................................................................... 318 31.17.3 MMU_STAT (STATUS REGISTER) ............................................................................................ 319
31.18 CAN ........................................................................................................................................ 320 31.18.1 CAN_CONF (CONFIGURATION REGISTER) ................................................................................ 320 31.18.2 CAN_STAT (STATUS REGISTER) .............................................................................................. 322
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31.18.3 CAN_CTRL (CONTROL REGISTER) ........................................................................................... 324 31.18.4 CAN_SYNC (CONTROL REGISTER) ........................................................................................... 325 31.18.5 CAN_SYMF (CONTROL REGISTER) ........................................................................................... 325 31.18.6 CAN_TRCR (CONTROL REGISTER) ........................................................................................... 326 31.18.7 CAN_TRAR (CONTROL REGISTER) ........................................................................................... 327 31.18.8 CAN_TRSIZE (CONTROL REGISTER) ........................................................................................ 327 31.18.9 CAN_TRWRREG (DATA REGISTER) ....................................................................................... 328 31.18.10 CAN_TRRDREG (DATA REGISTER) ....................................................................................... 329 31.18.11 CAN_RCCR (CONTROL REGISTER) ......................................................................................... 331 31.18.12 CAN_RCAR (DATA REGISTER) .............................................................................................. 332 31.18.13 CAN_RCSIZE (DATA REGISTER) ............................................................................................ 332 31.18.14 CAN_RCWRREG (DATA REGISTER) ..................................................................................... 333 31.18.15 CAN_RCRDREG (DATA REGISTER) ...................................................................................... 334 31.18.16 CAN_RCMR (CONTROL REGISTER) ...................................................................................... 335 31.18.17 CAN_CODR (CONTROL REGISTER) ........................................................................................ 335
31.19 MIL-STD-1553 RT ..................................................................................................................... 336 31.19.1 M1553_EVENTREG (CONTROL REGISTER) ............................................................................. 336 31.19.2 M1553_HWCONF (STATUS/CONTROL REGISTER).................................................................... 337 31.19.3 M1553_STATREG (STATUS REGISTER) ................................................................................... 338 31.19.4 M1553_CONFREG (CONTROL REGISTER) ............................................................................... 338 31.19.5 M1553_BUSSTAT (STATUS REGISTER) ................................................................................... 340 31.19.6 M1553_SWRDSREG (STATUS REGISTER) ............................................................................... 341 31.19.7 M1553_SYNCREG (STATUS REGISTER) .................................................................................. 341 31.19.8 M1553_SUBADDTAB (CONTROL REGISTER) ........................................................................... 342 31.19.9 M1553_MCREG (CONTROL REGISTER) ................................................................................... 343
31.20 SPACEWIRE/RMAP .................................................................................................................. 345 31.20.1 SPW0_CTRL, SPW1_CTRL (CONTROL REGISTER) .................................................................... 345 31.20.2 SPW0_STAT, SPW1_STAT (STATUS REGISTER) ...................................................................... 347 31.20.3 SPW0_NOD_ADD, SPW1_NOD_ADD (CONTROL REGISTER) .................................................. 348 31.20.4 SPW0_CLK_DIV, SPW1_CLK_DIV (CONTROL REGISTER) ........................................................ 349 31.20.5 SPW0_DST_KEY, SPW1_DST_KEY (CONTROL REGISTER) ....................................................... 350 31.20.6 SPW0_TIM, SPW1_TIM (CONTROL REGISTER) ....................................................................... 350 31.20.7 SPW0_DMA_CTRL, SPW1_DMA_CTRL (CONTROL REGISTER) ............................................... 351 31.20.8 SPW0_DMA_LEN, SPW1_DMA_LEN (DATA REGISTER) ........................................................ 352 31.20.9 SPW0_DMA_TADD, SPW1_DMA_TADD (DATA REGISTER) .................................................. 353 31.20.10 SPW0_DMA_RADD, SPW1_DMA_RADD (CONTROL REGISTER) ........................................... 353 31.20.11 SPW0_DMA_ADD, SPW1_DMA_ADD (DATA REGISTER) .................................................... 354
31.21 IEEE-754 COMPLIANCE ................................................................................................................ 355
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TABLE OF FIGURES
Figure 1: MIL-STD-1553 RT bus out timings .......................................................................................... 36 Figure 2: MIL-STD-1553 RT bus in timings ............................................................................................ 37 Figure 3: Spacewire H/L data out timings ............................................................................................. 40 Figure 4: Spacewire H/L data in timings ............................................................................................... 41 Figure 5: RTBT_MDC/RTBT_MDIO read operation ............................................................................... 42 Figure 6: RTBT_MDC/RTBT_MDIO write operation .............................................................................. 42 Figure 7: PHY 2-bit nibble write timings ............................................................................................... 43 Figure 8: PHY 2-bit nibble read timings ................................................................................................ 44 Figure 9: CLP pipeline architecture ....................................................................................................... 48 Figure 10: DMA descriptor values ......................................................................................................... 91 Figure 11: CPUs and APB busses architecture ...................................................................................... 92 Figure 12: SPI 4-wire mode (CPHA=0) ................................................................................................. 110 Figure 13: SPI 4-wire mode (CPHA=1) ................................................................................................. 111 Figure 14: UART byte frame ................................................................................................................ 121 Figure 15: MEM8-read case(no burst) ................................................................................................ 129 Figure 16: MEM8-read case burst ....................................................................................................... 130 Figure 17: MEM8-write case (no burst) .............................................................................................. 131 Figure 18: MEM8-write case (burst) ................................................................................................... 131 Figure 19: PWM double edge mode ................................................................................................... 134 Figure 20: PWM single edge complementary mode........................................................................... 135 Figure 21: PWM single edge independent mode ............................................................................... 136 Figure 22: ADC interface architecture ................................................................................................ 141 Figure 23: ADC acquisition and reading sequence ............................................................................. 142 Figure 24: ADC interface acquisition phase ........................................................................................ 143 Figure 25: ADC interface read phase - mode 0 ................................................................................... 144 Figure 26: ADC interface read phase - mode 1 ................................................................................... 145 Figure 27: AWG waveform .................................................................................................................. 149 Figure 28: Boot manager architecture ................................................................................................ 198 Figure 29: Boot manager state machine ............................................................................................. 199 Figure 30: RTBT state machine ........................................................................................................... 215
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TABLE OF TABLES Table 1: CLP pinout ............................................................................................................................... 34 Table 2: recommended operating conditions....................................................................................... 35 Table 3: absolute operating conditions ................................................................................................ 35 Table 4: MIL-STD-1553 timings ............................................................................................................. 37 Table 5: I2C timings ............................................................................................................................... 38 Table 6: SpaceWire timings ................................................................................................................... 42 Table 7: Clocls timings ........................................................................................................................... 44 Table 8: I2C DC characteristics .............................................................................................................. 45 Table 9: Radiation characteristics ......................................................................................................... 47 Table 10: IEEE-754 Illegal values conversion table ............................................................................... 49 Table 11: Condition codes ..................................................................................................................... 50 Table 12: A/B unit register structure .................................................................................................... 53 Table 13: RFLAGA description ............................................................................................................... 55 Table 14: RFLAGB description ............................................................................................................... 56 Table 15: RFLAGSU description ............................................................................................................. 56 Table 16: RSTATG1 description ............................................................................................................. 57 Table 17: RSTATG2 description ............................................................................................................. 58 Table 18: RSTATCNT1 description ......................................................................................................... 58 Table 19: RSTATCNTA description......................................................................................................... 58 Table 20: RSTATCNTB description ......................................................................................................... 58 Table 21: RSTATCNTSU description ...................................................................................................... 59 Table 22: RSTATCNT2 description ......................................................................................................... 59 Table 23: RSTATCNT3 description ......................................................................................................... 59 Table 24: RSTATCNT4 description ......................................................................................................... 60 Table 25: RCONF description ................................................................................................................ 61 Table 26: RSWREST description ............................................................................................................ 61 Table 27: SU unit register structure ...................................................................................................... 63 Table 28: Instruction field #2 description ............................................................................................. 64 Table 29: Instruction field #3 description ............................................................................................. 64 Table 30: Instruction field #4 description ............................................................................................. 65 Table 31: WP/AL table .......................................................................................................................... 94 Table 32: WP/AL definition ................................................................................................................... 95 Table 33: APB address table.................................................................................................................. 97 Table 34: forbidden instructions combinations .................................................................................. 106 Table 35: SPI IO table .......................................................................................................................... 117 Table 36: SPI0 APB registers ............................................................................................................... 118 Table 37: SPI1 APB registers ............................................................................................................... 119 Table 38: UART I/O signals .................................................................................................................. 122 Table 39: UART APB registers ............................................................................................................. 123 Table 40: Intercom RAM APB registers ............................................................................................... 124 Table 41: CRC APB registers ................................................................................................................ 126 Table 42: GPIO/MEM I/O signals ........................................................................................................ 132 Table 43: GPIO/MEM8 APB registers .................................................................................................. 132 Table 44: PWM I/O signals .................................................................................................................. 137 Table 45: PWM APB registers ............................................................................................................. 137 Table 46: Timers I/O signals ................................................................................................................ 140
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Table 47: Timers APB registers ........................................................................................................... 140 Table 48: ADC interface I/O signals ..................................................................................................... 146 Table 49: ADC interface APB registers ................................................................................................ 147 Table 50: AWG I/O signals................................................................................................................... 150 Table 51: AWG APB registers .............................................................................................................. 150 Table 52: MMU APB registers ............................................................................................................. 153 Table 53: MIL-STD-1553 subaddress table description ...................................................................... 155 Table 54: MIL-STD-1553 subaddress control word ............................................................................. 156 Table 55: MIL-STD-1553 Tx/Rx descriptor table ................................................................................. 157 Table 56: MIL-STD-1553 Control word description............................................................................. 158 Table 57: Spacewire 1st transmit descriptor description ................................................................... 163 Table 58: Spacewire 2nd transmit descriptor description .................................................................. 164 Table 59: Spacewire 3rd transmit descriptor description .................................................................. 164 Table 60: Spacewire 4th transmit descriptor description ................................................................... 165 Table 61: Spacewire 1st receive descriptor description ..................................................................... 166 Table 62: Spacewire 2nd receive descriptor description ................................................................... 166 Table 63: CAN messages mapping in XCHGRAM ................................................................................ 169 Table 64: CAN messages fields details ................................................................................................ 170 Table 65: MIL-STD-1553 I/O signals .................................................................................................... 173 Table 66: MIL-STD-1553 APB registers................................................................................................ 173 Table 67: CAN APB registers ............................................................................................................... 174 Table 68: Spacewire/RMAP write command description ................................................................... 176 Table 69: Spacewire/RMAP read command description .................................................................... 177 Table 70: Spacewire/RMAP read-modify-write command description .............................................. 178 Table 71: Spacewire I/O signals .......................................................................................................... 179 Table 72: Spacewire0 APB registers .................................................................................................... 179 Table 73: Spacewire1 APB registers .................................................................................................... 180 Table 74: IOMUX table ........................................................................................................................ 186 Table 75: IOMUX APB registers ........................................................................................................... 187 Table 76: IOMUX I/O signals ............................................................................................................... 187 Table 77: clock and reset control APB registers ................................................................................. 188 Table 78: Program RAM APB registers ................................................................................................ 189 Table 79: XCHGRAM APB registers ..................................................................................................... 190 Table 80: CPU_STAT description ......................................................................................................... 191 Table 81: BDINIT_SEL[2:0] description ............................................................................................... 192 Table 82: IF_CONFIG description ........................................................................................................ 192 Table 83: HW status and configuration I/O signals............................................................................. 194 Table 84: Scrubbing APB registers ...................................................................................................... 196 Table 85: BOOT_FRAME description ................................................................................................... 203 Table 86: Spacewire, CAN and RTBT mapping with RTBT ................................................................... 204 Table 87: Boot descriptors APB registers ............................................................................................ 205 Table 88: RTBT UDP packet ................................................................................................................. 207 Table 89: RTBT Ethernet packet .......................................................................................................... 207 Table 90: RTBT IPv4 header ................................................................................................................ 208 Table 91: RTBT UDP header structure ................................................................................................ 209 Table 92: Host to RTBT frame ............................................................................................................. 211 Table 93: RTBT to Host frame ............................................................................................................. 212 Table 94: Destination port used in RTBT to Host frame ..................................................................... 213
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Table 95: Host to RTBT commands ..................................................................................................... 217 Table 96: RTBT CPU0 Address trace content ...................................................................................... 228 Table 97: RTBT CPU1 Address trace content ...................................................................................... 229 Table 98: RTBT APB0 trace content .................................................................................................... 230 Table 99: RTBT APB1 trace content .................................................................................................... 230 Table 100: RTBT AHB trace content .................................................................................................... 231 Table 101: RTBT CPU0 A unit variable tracer content ........................................................................ 233 Table 102: RTBT CPU1 A unit variable tracer content ........................................................................ 233 Table 103: RTBT CPU0 B unit variable tracer content ........................................................................ 233 Table 104: RTBT CPU1 B unit variable tracer content ........................................................................ 233 Table 105: RTBT CPU0 SU unit variable tracer content ...................................................................... 233 Table 106: RTBT CPU1 SU unit variable tracer content ...................................................................... 234 Table 107: I2C I/O signals .................................................................................................................... 235 Table 108: I2C APB registers ............................................................................................................... 236
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1 INTRODUCTION
This document is the CLP preliminary datasheet.
The CLP microprocessor is a radiation hardened processor tailored to control hard real time loops . It
is an evolution of the existing HBRISC2 processor previously developed with ESTEC support in the
frame of the GSTP2 program. The HBRISC2 microprocessor is the core of the electronic control unit
of the Thrust Vector Control systems developed by SABCA for the four stages of the VEGA launcher,
as well as for the Flap Control System of the Intermediate eXperimental Vehicle, both programs
being led by ESA. The primary goal is to provide an attractive and powerful ESA ASSP solution for the
control processor of next launchers applications and a number of ESA satellites applications such as
ELSA (European Levitated Spherical Actuator).
2 DOCUMENTS AND ACRONYMS
2.1 APPLICABLE DOCUMENTS
[AD 1] 4000107720-13-NL-LvH GSTP Contract – Control Loop Processor (Phase 1)
[AD 2] ECSS-Q-ST-60-02C Space Product Assurance, ASIC and FPGA development
[AD 3] CLP-TN-C-001-SABC CLP Requirements Specification
[AD 4] SPB-CLP-UM-001 SDE Preliminary User Manual
[AD 5] I2C Specification version 2.1 January 2000
[AD 6] ISO/IEC IEEE Std 802.3-2002 Ethernet Communication Standards
[AD 7] ECSS-E-ST-50-13C Space Engineering - Interface and communication protocol for MIL-STD-1553B data bus onboard spacecraft
[AD 8] ANSI/IEEE Std 754-2008 IEEE Standard for Floating-Point Arithmetic
[AD 9] MIL-STD-1553 rev B +chg notice 1 to 4 Aircraft Internal Time Division Command/Response Multiplex Data Bus
[AD 10] ESCC Generic Specification 9000 Integrated Circuits, Monolithic, Hermetically sealed
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[AD 11] ECSS-E-ST-50-12C Space Engineering, SpaceWire – Links, nodes, routers and networks
[AD 12] IEEE Std 1149.7-2009 IEEE Standard for Reduced-Pin and Enhanced-
Functionality Test Access Port and Boundary-Scan Architecture
[AD 13] ISO 11898-1:2003 Road Vehicles, Controller area network (CAN),
Part 1: Data link layer and physical signaling [AD 14] ECSS-E-ST-50-52C SpaceWire - Remote memory access protocol [AD 15] TIA-EIA-644-A Electrical Characteristics Of Low Voltage
Differential Signaling (LVDS) Interface Circuits [AD 16] ARM IHI 0011A AMBA TM specification Rev 2.0 issue A
2.2 REFERENCES
[RD 1] CLP-VP-C-001-SABC CLP Verification Plan [RD 2] CLP-VCD-C-001-SABC CLP Verification Control Document [RD 3] CLP-COP-C-001-SABC CLP Control Plan
[RD 4] CLP-DVP-C-001-SABC CLP Develoment Plan
[RD 5] CLP-JF-C-001-SABC CLP Feasibility and Risk Analysis
[RD 6] CLP-TN-S-008-SABC SW Library User Manual
2.3 ACRONYMS
A5ME Ariane 5 Midlife Evolution
ADC Analog to Digital Converter
AOCS Attitude and Orbital Control Systems
AWG Arbitrary Waveform Generator
BIST Built In Self Test
CLP Control Loop Processor
CPU Central Processing Unit
CSMA/CD Carrier Sense Multiple Access / Collision Detection
DRY Design Requirements Directives
DRD Document Requirements Description
DSP Digital Signal Processor
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EDAC Error Detection And Correction
EEPROM Electrically Erasable Programmable Read Only Memory
EGPIO Extended GPIO
EMOx Extended Multiplexor Output
ESWTB Evolved SoftWare Test Bench
FIFO First In First Out
FPGA Field Programmable Gate Array
GPIO General Purpose Inputs Outputs
GSTP General Support Technology Program
HBRISC Hardened Bi Reduced Instruction Set Computer
HSSL High Speed Serial Link
I2C Inter Integrated Circuit
ITAR International Traffic in Arms Regulation
JTAG Joint Test Action Group
KLOC Kilo Lines Of Code
LSB Least Significant Bit
LVDS Low Voltage Differential Signalling
LVDT Linear Variable Differential Transformer
MAC Media Access Controller
MOQ Minimum Order Quantity
MPW Multi Project Wafer
MSB Most Significant Bit
NC Not Connected
PWM Pulse Width Modulation
QML Qualified Manufacturer List
RT Remote Terminal
SEL Signal Event Latch-up
SEU Single Event Upset
SIMD Single Instruction Multiple Data
SPI Serial Peripheral Interface
SRAM Static Random Access Memory
SW SoftWare
TDF Transient Delay Fault
TID Total Ionizing Dose
TMR Triple Modular Redundancy
TVC Thrust Vector Control
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3 THE CLP IN A GLANCE…
DUAL CORE ARCHITECTURE FEATURING Fully uninterruptible and deterministic behaviour
IEEE-754 single precision data format
16-bit/32-bit integer operations
50 MHz external clock
Real-time and non-intrusive debugging
DMA
BENCHMARK/PERFORMANCE
Two Field-Oriented Control Loops @ 10kHz with CPU load <50%
Up to 200 MFLOPS/100 MIPS peak performance
EXTENSIVE ON-CHIP PERIPHERALS
2x SPI (master or slave, master driving up to 12 slaves)
1x I2C (master or slave)
4x UART
96x GPIO
24x PWM (complementary, twice more in independent mode)
10x Timers
1x ADC Interface
2x AWG (parallel interface)
2x Spacewire (+RMAP)
1x CAN
1x MIL-STD-1553 (Remote Terminal)
1x MMU
2x XCHG RAM
COMPONENT
Package: CQFP-256 (TBC)
Technology: CMOS UMC 65 nm (TBC)
Library: ESA/IMEC DARE (TBC)
TAILORED FOR HARD-REAL TIME AND/OR SIGNAL PROCESSING SPACE APPLICATIONS
Mechanisms and Actuator Control
AOCS systems
Robotics
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COMPLETE SOFTWARE DEVELOPMENT ENVIRONEMENT (Q3 2017)
Cycle-accurate ISS SystemC model (available)
Programmable at system-level (Simulink or C)
Automated binary code generation
Eclipse-based GUI
Tracer/uploader (beta version available)
Unit Test Manager (beta version available)
Simulink Macro Library for enhanced performance (beta version available)
C-compiler and linker
Assembler (beta version available)
KEY FEATURES FOR THE USER
System
Application design performed directly in Simulink – The same model is used for simulations and code generation.
Simple and deterministic code generation, facilitating proof of real-time constraints.
Direct cross-checking and representativity with Simulink reference model
Allows migration towards smart actuator architecture (micro packaging technologies)
Electronics
Single-chip integrated solution
Minimized glue logic, reducing board space (~30-50%) w.r.t. convential COTS solutions)
Easier manufacturing management.
Reliability
Enhanced reliability (due to highly integrated system)
Conventional QFP package
Easy manufacturing management.
Allows migration towards smart actuator architecture (via dedicated micro packaging
technologies)
Software
Limited SW activity due to the Simulink “push-button” approach
Typical CPU load (current loop @ 10 kHz, vector control, 2 actuators) = 40%
No useless code required for debugging
Easy software design validation
Static register allocation
Simulink library qualified at unit level
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SW tools suite allowing easy code generationAssociated software in line with ECSS requirementsStatic register allocation
Simulink library qualified at unit level
SW tools suite allowing easy code generation
4 THE CONTROL LOOP PROCESSOR
4.1 FUNCTIONAL DIAGRAM
UDP/IP
CLP
PWM
(x24)
GPIO
(x96)
TIMERS
(x10)
SPI
(x2)
I2C
ADC IF
UART
(x4)
CRC
INTER
RAM
C
P
U
1REAL-TIME
BACKGROU
ND
TRACER
REGISTERS
FILE
IEEE-
754
32-bit
FPU/IU
REGISTERS
FILE
A UNIT
B UNIT
SU UNIT
EDAC
REGISTERS
FILE
IEEE-
754
32-bit
FPU/IU
EDAC
16-bit
IU
DMA REGS
SPACEWI
RE
#1
MIL-STD-
1553
RT
SPACEWI
RE
#2
CAN
PERIPHERALS
AWG
APB MASTER
C
P
U
2
PROGRAM/DATA
MEMORY
EDAC
CPU PIPELINE MANAGEMENT
CORE
1
XCHG
RAM
CORE
2
XCHG
RAM
AM
BA
AH
B
M M M
AMBA AHB
AMBA APB CORE 1
AMBA APB CORE 2
BOOT
MANAG
ER
EDAC
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
M
MMU
CO
NFIG
S
S
S
S
IOMUX
CONFIG
MS
S
M
BO
OT
CO
NF
IG
M
DMA REGS
ED
AC
DMA
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4.2 SUMMARY
The Control Loop Processor is made of two CPUs (drawn in blue and red) and a number of
peripherals (surrounded by an orange box).
Each CPU is based on a RISC architecture and cache-free topology to provide a fully deterministic
behaviour. No interruptions are foreseen. It is made of three arithmetic units. Two of them are
floating-point units, called A and B, and the last one is a 16-bit integer unit, called SU. The A and B
units integrate the IEEE-754 format in single precision. 16-bit Integer operation are also possible as
well as 32-bit operations. A large number of operations is proposed thus making each CPU well-
suited for algorithms implementation. In particular, SIMD instructions are available to parallelize
computations. The CLP target speed is 50 MHz thus providing up to 200 MFLOPs peak performance
when the 4 FPUs are fully occupied.
Each CPU contains a 32kx39 program memory, called PRAM, which is also available for data through
the APB bus controlled by the CPU.
Each CPU integrated 2x512 general-purpose registers in floating-point units and 32 general-purpose
registers in the SU unit. A stack pointer is also available with an on-chip integration of stacks (using
general-purpose registers). A number of status registers are available to constantly report events
occurring in the CPU but also in the CLP.
Each CPU has access to an eXCHanGe RAM (XCHGRAM). Both XCHGRAM memories are 8kx39-bit
wide.
Each CPU contains a Direct Memory Access controller (DMA). This unit allows to off-load the
software from transfers occurring between the CPU registers and any APB peripherals. The
descriptors are under software control and stored in the XCHG RAMs. The DMA is triggered with one
of the CLP timers.
Two on-chip busses, based on the APB AMBA standard, are available. Each CPU has its own bus to
interact with peripherals and has the master role. Each peripheral is thus exclusively slave. An
allocation and write protection mechanism is integrated to the on-chip busses and defines at boot
time which APB register or segment is allocated to which CPU. When the software is running, this
configuration is static thus ensuring a deterministic communication between the CPUs and the
peripherals. Any abnormal access is detected and reported in a dedicated counter.
10 on-chip timers are available for use by the CPUs or most of the various on-chip peripherals. These
timers constitute the nerve of the CLP as they allow to synchronise the software running on the
CPUs with the used peripherals. These timers also ease the structuring of the software in time-slots
which is the recommended way of using the CLP
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A SPI interface is included and divided in two separate units that can be programmed in either
master or slave mode. In master mode, each unit can drive up to 12 slaves. The data acquisition can
be either sequential or made in parallel. This interface is particularly interesting when working with
serial off-chip ADCs.
A PWM interface is integrated allowing to drive up to 2x24 signals. Each output has its complement
thus easing the generation of signals intended for power electronics. The dead time is
programmable and several modes of functioning are available.
Two AWG are available to automatically generate any arbitrary waveform. The generated signals are
12-bit wide to easily drive any external DAC. The typical use of these AWG is either performing
sensors excitation or some sort of analog reporting.
A parallel ADC interface is included to allow interacting with any off-chip parallel interface. The
polarity and timings are fully programmable. Up to 4 off-chip devices can be addressed and 16
samples transferred per acquisition (which is triggered by one of the CLP timers). The ADC interface
is autonomous.
Four UARTs are included to interface any off-chip device with the CLP. The baud rate is
programmable and either 8-bit or 32-bit modes are available.
The communication between the two CPUs is made through an INTERCOM RAM. This memory is
512x39-bit wide.
The CLP also integrates one I2C interface to interact with upcoming space devices which make use of
this standard
Two CRC units are available to perform any data integrity check. The polynomial is defined by default
but is fully programmable.
96 GPIOs are available either in the conventional mode (input, output or input/outputs) or in a
MEM8 mode allowing to automatically interact with an external 8-bit memory. These GPIOs are
multiplexed with other interfaces in the IOMUX pins.
A Spacewire-RMAP, MIL-STD-1553 RT and CAN interfaces are included to support most space
applications needs. All these interfaces comply with their respective standards and interact with the
software through two XCHG RAMS. A MMU performs the routing from/to these XCHGRAMs from/to
the mentioned interfaces. The MMU can be programmed by the software through descriptors. An
allocation mechanism is also foreseen to filter data handled by a given interface.
The software is debugged and validated through the RTBT link. This interface is based on the 100
Mbits/s Ethernet/UDP standard and allows to perform real-time tracing of CPUs registers, APBs
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traffic, MMU interactions and PRAMs activity. The RTBT is not intrusive and does not need
instrumentation code thus making it suitable for applications forbidding useless code.
The CLP is fault-tolerant against any SEU occurring in its whole memory space. EDAC management is
integrated to perform “on-the-fly” correction in case of read and an on-chip write-back correction to
avoid errors accumulation. A scrubbing unit is also foreseen with a programmable refresh rate and
correction address range. The fault tolerance also applies to any abnormal event occurring inside the
CLP such as a deadlock condition in the ADC interface, an allocation violation detected by the MMU,
a saturation condition occurring in an arithmetic unit or illegal operand detection. Dedicated
saturating counters are included for each possible event.
Finally, a boot manager is integrated and provides a robust boot and restart mechanism through 4
boot descriptors. 5 boot sources can be programmed (RMAPx2, CAN, MEM8 or RTBT) to
automatically upload these boot descriptors and then boot the whole CLP according to the content
of these ones. Whenever a boot tentative fails, the boot manager automatically reboots the CLP
from the next boot descriptor. These boot descriptors allow the boot from the same boot sources.
The boot descriptor can be protected but also made available to the software.
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5 CONVENTIONS AND DEFINTIONS
5.1 TEXT FORMATTING
UPPERCASE BOLD words are used to identify CLP I/O (e.g. GPIO[0],PWM_TIMER[5]…), CPU (e.g.
RGP1, RSTATCNT1,…) registers or APB registers (M1553_HWCONF,…). IOMUX pins do not use the
convention to make the document easier to read.
UPPERCASE (and non bolded) words are used to identify CLP resources (e.g. A unit, SPI, DMA,…), CLP
instructions (e.g. WRITEAPB,…) register fields (e.g. RNDF,…), well-known acronyms (e.g. LSB,…) or
specifc acronyms defined in §5.2 (e.g. IMM9,…)
Underlined words or sentences highlight a specific feature of the CLP
Italic text identifies user directives that are mandatory to correctly make use of the CLP.
[x] is used to identify xth bit of a given vector
[x:y] is used to identify a x to y range in a given vector (x>y)
5.2 CONTENT
The data will be represented in the following way:
the MSB will be located on the left and numbered N-1, where N is the data width.
the LSB will be located on the right and numbered 0
‘b’ at the end of a data indicates that the value is in binary base.
‘h’ at the end of a data indicates that the value is in hexadecimal base.
If the value is not ended by ‘b’ and ‘h’, the value should be considered in decimal base.
A big endian representation will be used
The CLP is a dual-core processor that contains a number of interfaces that are implemented with
VHDL core-IPs provided by 3rd-party provider(s). The specification will use the term
CPU to refer to each core
IP to refer to these interfaces based on existing core-IPs
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The CLP integrates 16-bit integer operations inside the 32-bit floating point units. The integer
operations made on:
the 16 LSBs will be named low-bits operations
the 16 MSBs will be named high-bits operations
The CLP instruction set foresees the use of two type of immediate (see definition below) values:
IMM9 will refer to 9-bit immediate value that is inside the 32-bit instruction (i.e. in one of the operand fields)
IMM32 will refer to the 32-bit immediate value or literal that is used in transfers operations
imm0 will be used to refer to the IMM9 value that is equal to 0 (coded "11000000000" in the associated instruction field)
The numbering of items will start from 0 up to N-1. For example:
the CPU: CPU0 and CPU1
the XCHG RAM: XCHGRAM0 and XCHGRAM1
the PRAM: PRAM0 (linked to CPU0) and PRAM1 (linked to CPU1)
the Spacewire: Spacewire0 and Spacewire1
A bus (i.e. a collection of bits belonging to a same function) having width N will be named [N-1:0 .
The following acronyms and notations are used:
a = computational unit A
b = computational unit B
ab = A and B, or A in parallel with B
su = special unit
( ) = content of
= becomes
OR = bitwise Boolean or
XOR = bitwise Boolean xor
AND = bitwise Boolean and
NOT = one's complement (unary)
r = register
u.r = register r in unit u (u=a, b, ab, SU)
r.f = 32-bit IEEE-754 floating-point value represented in r register
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r.l = low 16-bits of 32-bit (a orBcase) or 16-bit (su case) r register ,
r.h = high 16-bits of 32-bit r register (note: h does not exist in SU)
u.r.p = p part of r in u where u =a, b, ab or SU and p=f ,l or h
ind() = "indirect" address operation; returns value located at address hold by argument
o2a() = "offset to absolute" address conversion; returns the real RGPx address mapped to
ROFFy argument
is_zero() = returns '1' if argument is equal to IEEE-754 zero (i.e. +0.0 or -0.0), '0' otherwise
f_mask()= returns predefined boolean operation according to argument value;
used for calculation of mask bit via COND instruction
sign() = returns '1' if argument is strictly negative, '0' otherwise
; = separator for concurrent operations made on the same clock cycle
( e.g. op1;op2 denotes op1 and op2 made in parallel)
INSTRUCTION CYCLE: Time required by one CPU to load one instruction from its program memory
to the instruction register
CLOCK CYCLE: The period of the clock feeding one CPU (i.e the PLL output or an external
clock if the PLL is bypassed)
INSTRUCTION: Operation(s) executed by one CPU during a predefined number of clock
cycles (typically one), as a consequence of the reading of one line of the
program memory (located in the on-chip SRAM).
IMMEDIATE DATA: Data that is part of the code under execution and that is accessed via the
nominal fetch flow.
Notes:
1 instruction cycle equals one clock cycle
only the term clock cycle will be used in this document
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6 DEVICE
6.1 PINOUT
The CLP device has 150 functional inputs and outputs. Due to the high number of interfaces, an IO standard multiplexing architecture is made available to the user allowing most of the interfaces to share a common IO standard cell called IOMUX. Up to 106 programmable IOMUX are foreseen and the user needs to program each IOMUX during boot time. Dedicated APB registers are available for that purpose. When the CPUs are running, no modification of IOMUX configuration is possible. Each IOMUX can be routed to 2 predefined interfaces or one GPIO pin, which its turn can be programmed in input or output according to dedicated GPIO control registers available on the APB. By default and after the reset state, each IOMUX is routed to each GPIO The table below provides the pinout of the CLP.
The 1st column gives the CLP IO standard name.
The 2nd column gives the type of IO standard (I=input; O=output; Z=high impedance;LVDS).
The 3rd column gives the width.
The 4th column gives a short description.
The 5th column the CLP pin (i.e. after the IOMUX allocation).
The 6th column mentions if a pull-up (PU) or pull-down (PD) is foreseen and the value of the resistor (in Ohms)
The 7th column provides the output current drive strength (for outputs only)
The 8th column gives an indication of the toggle rate
The 9th column mentions to which CLP function the IO belongs
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IO NAME IO standard
WIDTH DESCRIPTION PIN NAME PU/PD DRIVE STRENGTH
TOGGLE RATE
CLP FUNCTION
CLOCK I 1 CLP Clock CLOCK TBD N/A 50 MHz SYSTEM
PLL_BYPASS I 1 CLP PLL bypass control PLL_BYPASS TBD N/A static SYSTEM
PLL_LOCK O 1 CLP PLL locked signal PLL_LOCK TBD N/A static SYSTEM
RESET_BAR I 1 CLP Reset bar RESET_BAR TBD N/A static SYSTEM
M1553_RTADDR[4:0 I 5 1553 RT Address IOMUX[83:79] TBD N/A static MIL-STD-1553
M1553_RTADDRP I 1 1553 RT Address parity bit IOMUX[84] TBD N/A static MIL-STD-1553
M1553_RTADDRERR O 1 1553 RT Address error IOMUX[51] TBD 1 mA static MIL-STD-1553
M1553_BUSAINEN O 1 1553 RT Bus A input enable IOMUX[56] TBD 1 mA 1 MHz MIL-STD-1553
M1553_BUSAINP I 1 1553 RT Bus A positive input IOMUX[52] TBD N/A 1 MHz MIL-STD-1553
M1553_BUSAINN I 1 1553 RT Bus A negative input IOMUX[53] TBD N/A 1 MHz MIL-STD-1553
M1553_BUSBINEN O 1 1553 RT Bus B input enable IOMUX[60] TBD 1 mA 1 MHz MIL-STD-1553
M1553_BUSBINP I 1 1553 RT Bus B positive input IOMUX[54] TBD N/A 1 MHz MIL-STD-1553
M1553_BUSBINN I 1 1553 RT Bus B negative input IOMUX[55] TBD N/A 1 MHz MIL-STD-1553
M1553_BUSAOUTIN O 1 1553 RT Bus A output inhibit IOMUX[57] TBD 1 mA 1 MHz MIL-STD-1553
M1553_BUSAOUTP O 1 1553 RT Bus A positive output IOMUX[58] TBD 1 mA 1 MHz MIL-STD-1553
M1553_BUSAOUTN O 1 1553 RT Bus A negative output IOMUX[59] TBD 1 mA 1 MHz MIL-STD-1553
M1553_BUSBOUTIN O 1 1553 RT Bus B output inhibit IOMUX[61] TBD 1 mA 1 MHz MIL-STD-1553
M1553_BUSBOUTP O 1 1553 RT Bus B positive output IOMUX[62] TBD 1 mA 1 MHz MIL-STD-1553
M1553_BUSBOUTN O 1 1553 RT Bus B negative output IOMUX[63] TBD 1 mA 1 MHz MIL-STD-1553
M1553_CLK I 1 1553 Clock M1553_CLK TBD N/A 10 MHz MIL-STD-1553
SPW_DIN0H LVDS 1 Spacewire#0 Data In High SPW_DIN1H TBD N/A 200 MHz SPACEWIRE
SPW_DIN0L LVDS 1 Spacewire#0 Data In Low SPW_DIN1L TBD N/A 200 MHz SPACEWIRE
SPW_SIN0H LVDS 1 Spacewire#0 Strobe In High SPW_SIN1H TBD N/A 200 MHz SPACEWIRE
SPW_SIN0L LVDS 1 Spacewire#0 Strobe In Low SPW_SIN1L TBD N/A 200 MHz SPACEWIRE
SPW_DOUT0H LVDS 1 Spacewire#0 Data Out High SPW_DOUT1H TBD N/A 200 MHz SPACEWIRE
SPW_DOUT0L LVDS 1 Spacewire#0 Data Out Low SPW_DOUT1L TBD N/A 200 MHz SPACEWIRE
SPW_SOUT0H LVDS 1 Spacewire#0 Strobe Out High SPW_SOUT1H TBD N/A 200 MHz SPACEWIRE
SPW_SOUT0L LVDS 1 Spacewire#0 Strobe Out Low SPW_SOUT1L TBD N/A 200 MHz SPACEWIRE
SPW_DIN1H LVDS 1 Spacewire#1 Data In High SPW_DIN2H TBD N/A 200 MHz SPACEWIRE
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IO NAME IO standard
WIDTH DESCRIPTION PIN NAME PU/PD DRIVE STRENGTH
TOGGLE RATE
CLP FUNCTION
SPW_DIN1L LVDS 1 Spacewire#1 Data In Low SPW_DIN2L TBD N/A 200 MHz SPACEWIRE
SPW_SIN1H LVDS 1 Spacewire#1 Strobe In High SPW_SIN2H TBD N/A 200 MHz SPACEWIRE
SPW_SIN1L LVDS 1 Spacewire#1 Strobe In Low SPW_SIN2L TBD N/A 200 MHz SPACEWIRE
SPW_DOUT1H LVDS 1 Spacewire#1 Data Out High SPW_DOUT2H TBD N/A 200 MHz SPACEWIRE
SPW_DOUT1L LVDS 1 Spacewire#1 Data Out Low SPW_DOUT2L TBD N/A 200 MHz SPACEWIRE
SPW_SOUT1H LVDS 1 Spacewire#1 Strobe Out High SPW_SOUT2H TBD N/A 200 MHz SPACEWIRE
SPW_SOUT1L LVDS 1 Spacewire#1 Strobe Out Low SPW_SOUT2L TBD N/A 200 MHz SPACEWIRE
I2C_SDA I/O/Z 1 I2C Serial Data IOMUX[72] TBD 10 mA 400 kHz I2C
I2C_SCL I/O/Z 1 I2C Serial Clock IOMUX[73] TBD 10 mA 400 kHz I2C
CAN_TX O/Z 1 CAN Transmit In IOMUX[66] TBD 10 mA 1 MHz CAN
CAN_RX O 1 CAN Receive In IOMUX[67] TBD 10 mA 1 MHz CAN
CAN_SEL O 1 CAN Transceiver selection IOMUX[68] TBD 10 mA 1 MHz CAN
UART_TX0 O 1 UART#0 Transmit In IOMUX[67] TBD 10 mA 1 MHz UART
UART_RX0 I 1 UART#0 Receive In IOMUX[66] TBD N/A 1 MHz UART
UART_TX1 O 1 UART#1 Transmit In IOMUX[69] TBD 10 mA 1 MHz UART
UART_RX1 I 1 UART#1 Receive In IOMUX[68] TBD N/A 1 MHz UART
UART_TX2 O 1 UART#2 Transmit In IOMUX[71] TBD 10 mA 1 MHz UART
UART_RX2 I 1 UART#2 Receive In IOMUX[70] TBD N/A 1 MHz UART
UART_TX3 O 1 UART#3 Transmit In IOMUX[73] TBD 10 mA 1 MHz UART
UART_RX3 I 1 UART#3 Receive In IOMUX[72] TBD N/A 1 MHz UART
RTBT_RXDV I 1 RTBT Data valid RTBT_RXDV TBD N/A 25 MHz RTBT
RTBT_RXER I 1 PHY Error RTBT _RXER TBD N/A 25 MHz RTBT
RTBT_COL I 1 PHY Collision RTBT _COL TBD N/A 25 MHz RTBT
RTBT_CRS I 1 PHY Carrier Sense RTBT _CRS TBD N/A 25 MHz RTBT
RTBT_RXD[3:0 I 4 PHY Receiver Data RTBT _RXD[3:0 TBD N/A 25 MHz RTBT
RTBT_RX_CLK I 1 PHY Receive Clock RTBT _RX_CLK TBD N/A 25 MHz RTBT
RTBT_TXEN O 1 PHY Transmit Enable RTBT _TXEN TBD 10 mA 25 MHz RTBT
RTBT_TXER O 1 PHY Transmit Error RTBT _TXER TBD 10 mA 25 MHz RTBT
RTBT_TXD[3:0 O 4 PHY Transmit Data RTBT _TXD[3:0 TBD 10 mA 25 MHz RTBT
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IO NAME IO standard
WIDTH DESCRIPTION PIN NAME PU/PD DRIVE STRENGTH
TOGGLE RATE
CLP FUNCTION
RTBT_TX_CLK I 1 PHY Transmit Clock RTBT _TX_CLK TBD N/A 25 MHz RTBT
RTBT_MDIO I/O/Z 1 PHY Management Data Input Output RTBT _MDIO TBD 10 mA 25 MHz RTBT
RTBT_MDC O 1 PHY Management Clock RTBT _MDC TBD 10 mA 25 MHz RTBT
RTBT_MDEN O 1 PHY Management Data RTBT _MDEN TBD 10 mA 25 MHz RTBT
GPIO[95:0 I/O/Z 106 GPIO input/output IOMUX[95:0] TBD 10 mA 1 MHz GPIO
PWM_TIMERS[23:0 O 48 PWM Timers output IOMUX[47:0] TBD 5 mA 10 kHz PWM
ADCIF_SOC O 1 ADC Start of convert IOMUX[70] TBD 5 mA 1 kHz ADC INTERFACE
ADCIF_EOCB[3:0 I 4 ADC End of conversion bar IOMUX[78:75] TBD N/A 1 kHz ADC INTERFACE
ADCIF_CS[3:0 O 4 ADC Chip Select IOMUX[82:79] TBD 5 mA 1 kHz ADC INTERFACE
ADCIF_RC O 1 ADC Read/Convert IOMUX[83] TBD 5 mA 1 kHz ADC INTERFACE
ADCIF_MUXSEL[3:0 O 4 ADC multiplexor selection IOMUX[87:84] TBD 5 mA 1 kHz ADC INTERFACE
ADCIF_DATABUS[15:0 I/Z 16 ADC data bidirectional bus IOMUX[103:88] TBD 5 mA 1 kHz ADC INTERFACE
SPI0_CLK I/O/Z 1 SPI Serial Clock Out or In IOMUX[74] TBD 10 mA 1 MHz SPI
SPI0_MOSI I/O/Z 1 SPI Master Out Slave In IOMUX[75] TBD 10 mA 10 kHz SPI
SPI0_CSI I 1 SPI Chip Select In IOMUX[76] TBD N/A 10 kHz SPI
SPI0_GCSO/GMISO I/O 1 SPI General Chip Select Out/SPI Master In Slave Out
IOMUX[77] TBD 10 mA 10 kHz SPI
SPI0_CSO/MISO[11:0] O 12 SPI Chip Select Out/SPI Master In Slave Out
IOMUX[89:78] TBD 10 mA 10 kHz SPI
SPI1_CLK I/O/Z 1 SPI Serial Clock Out or In IOMUX[90] TBD 10 mA 1 MHz SPI
SPI1_MOSI I/O/Z 1 SPI Master Out Slave In IOMUX[91] TBD 10 mA 10 kHz SPI
SPI1_CSI I 1 SPI Chip Select In IOMUX[92] TBD N/A 10 kHz SPI
SPI1_GCSO/GMISO I/O 1 SPI General Chip Select Out/SPI Master In Slave Out
IOMUX[93] TBD 10 mA 10 kHz SPI
SPI1_CSO/MISO[11:0] O 12 SPI Chip Select Out/SPI Master In Slave Out
IOMUX[105:94] TBD 10 mA 10 kHz SPI
DAC0_OUT[11:0] O 12 AWG#0 Output IOMUX[35:24] TBD 10 mA 1 MHz AWG
DAC1_OUT[11:0] O 12 AWG #1 Output IOMUX[47:36] TBD 10 mA 1 MHz AWG
DAC0_EN O 1 DAC0 Enable output IOMUX[64] TBD 10 mA 1 MHz AWG
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IO NAME IO standard
WIDTH DESCRIPTION PIN NAME PU/PD DRIVE STRENGTH
TOGGLE RATE
CLP FUNCTION
DAC1_EN O 1 DAC1 Enable output IOMUX[65] TBD 10 mA 1 MHz AWG
CPU_STAT[5:0 O 6 CPU Status Code CPU_STAT[5:0 TBD 5 mA static STATUS AND CONFIG
BDINIT_SEL [2:0 I 3 Boot descriptors initialisation selection
BDINIT_SEL [2:0 TBD N/A static STATUS AND CONFIG
BDINIT_SELP I 1 Boot descriptors selection parity bit BOOT_SELP TBD N/A static STATUS AND CONFIG
IF_CONFIG [5:0 I 6 Interfaces activation configuration IF_CONFIG [5:0 TBD N/A static STATUS AND CONFIG
WDOG_OUT O 1 Watchdog output IOMUX[50] TBD 5 mA 20 MHz STATUS AND CONFIG
MEM8_DATA[7:0] I/O 8 8-bit external memory data bus IOMUX[47:40] TBD N/A 1 MHz MEM8
MEM8_ADDR[18:0] O 19 8-bit external memory address bus IOMUX[38:20] TBD 5 mA 1 MHz MEM8
MEM8_CSB O 1 8-bit external memory chip select bar
IOMUX[48] TBD 5 mA 1 MHz MEM8
MEM8_OEB O 1 8-bit external memory output enable bar
IOMUX[49] TBD 5 mA 1 MHz MEM8
MEM8_RWB O 1 8-bit external memory read write bar
IOMUX[39] TBD 5 mA 1 MHz MEM8
TEST_SE I 1 Test pin (scan path enable) TEST_SE TBD N/A 10 MHz TEST
TEST_SCLK I 1 Test pin (scan path clock) TEST_SCLK TBD N/A 10 MHz TEST
JTAG_TMS I 1 JTAG Test Mode Select JTAG_TMS TBD N/A 10 MHz JTAG
JTAG_TRST I 1 JTAG Test Reset JTAG_TRST TBD N/A 10 MHz JTAG
JTAG_TDI I 1 JTAG Test Data In JTAG_TDI TBD N/A 10 MHz JTAG
JTAG_TDO O 1 JTAG Test Data Out JTAG_TDO TBD 10 mA 10 MHz JTAG
JTAG_CLK I 1 JTAG Clock JTAG_CLK TBD N/A 10 MHz JTAG
Table 1: CLP pinout
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6.2 CHARACTERISTICS
6.2.1 RECOMMENDED OPERATING CONDITIONS
CHARACTERISTIC MIN MAX UNIT
Supply IO standard voltage
(VDD)
3 3.6 V
Supply core voltage (VCC) 1.65 1.95 V
Input voltage 0 VDD V
Output voltage 0.4V VDD-0.4 V
Consumption 3 W
Operating temperature -55 +125 °C
Table 2: recommended operating conditions
6.2.2 ABSOLUTE MAXIMUM RATINGS
CHARACTERISTIC MIN MAX UNIT
Supply IO standard voltage (VDD)
-0.5 3.75 V
Supply core voltage (VCC)
-0.5 1.8 V
Input voltage -0.3 VDD+0.3 V
Junction temperature -55 +135 °C
Storage temperature -60 +150 °C
Table 3: absolute operating conditions
6.2.3 AC CHARACTERISTICS
The "max" timings are based on the following test conditions:
Ambient temperature= +125°C
VCC (core voltage) = 1.65 V
VDD (IO standard voltage) = 3.0 V
Output loads = 400 pF
"Logic 1" voltage threshold = 70% of VDD
"Logic 0" voltage threshold = 30% of VDD
The "min" timings are based on the following test conditions:
Ambient temperature= -55°C
VCC (core voltage) = 1.95 V
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VDD (IO standard voltage) = 3.6 V
Output loads = 400 pF
"Logic 1" voltage threshold = 70% of VDD
"Logic 0" voltage threshold = 30% of VDD
6.2.3.1 MIL-STD-1553
The timings related to M1553_BUSAOUTP/M1553_BUSBOUTP and M1553_BUSAOUTN/
M1553_BUSBOUTN are compatible with the following timings
Tx1
M1553_BUSxOUTP
M1553_BUSxOUTN
Tx2
Figure 1: MIL-STD-1553 RT bus out timings
The timings related to M1553_BUSAINP/ M1553_BUSBINP and M1553_BUSAINN/
M1553_BUSBINN are compatible with the following timings
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Tx3
M1553_BUSxINP
M1553_BUSxINN
Tx4
Figure 2: MIL-STD-1553 RT bus in timings
Parameter Description Min Max unit
Tx1 skew between M1553_BUSAOUTP/ M1553_BUSBOUTP and M1553_BUSAOUTN/ M1553_BUSBOUTN
-25 +25 ns
Tx2 zero crossing distortion T -25 T+25 ns (T=500, 1000, 1500 or 2000)
Tx3 delay between M1553_BUSAINP/ M1553_BUSBINP and M1553_BUSAINN/ M1553_BUSBINN
-200 +200 ns
Tx4 zero crossing stability T -150 T+150 ns (T=500, 1000, 1500 or 2000)
Table 4: MIL-STD-1553 timings
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6.2.3.2 I2C
The CLP have the following IO timing characteristics for the I2C interface in standard mode and Fast-Mode
Parameter Symbol Standard-Mode (Min)
Standard-Mode (Max)
Fast-Mode (Min)
Fast-Mode (Max)
Unit
SCL clock frequency fSCL 0 100 0 400 kHz
Hold time (repeated) START condition. After this period, the first clock pulse is generated
tHD;STA 4.0 - 0.6 - us
LOW period of the SCL clock tLOW 4.7 - 1.3 - us
HIGH period of the SCL clock tHIGH 4.0 -
0.6 - us
Set-up time for a repeated START condition
tSU;STA 4.7 - 0.6 -
us
Data hold time: for CBUS compatible masters (see NOTE, Section 10.1.3) for I2C-bus devices
tHD;DAT 5.0 0(2)
- 3.45(3)
- 0(2)
- 0.9(3)
us
Data set-up time tSU;DAT 250 - 100(4) - us
Rise time of both SDA and SCL signals tr - 1000 20 + 0.1Cb(5) - us
Fall time of both SDA and SCL signals tf - 300 20 + 0.1Cb(5) - us
Set-up time for STOP condition tSU;STO 4.0 - 0.6 - us
Bus free time between a STOP and START condition
tBUF 4.7 - 1.3 - us
Capacitive load for each bus line Cb - 400 - 400 pF
Noise margin at the LOW level for each connected device (including hysteresis)
VnL 0.1VDD - 0.1VDD - V
Noise margin at the HIGH level for each connected device (including hysteresis)
VnH 0.2VDD - 0.2VDD - V
Table 5: I2C timings
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(1) All values referred to VIHmin and VILmax levels (see Table 4).
(2) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.
(3) The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
(4) A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT (cfr(3))250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released.
(5) Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times according to Table 6 are allowed.
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6.2.3.3 SPACEWIRE
The timings related to the SpaceWire output signals SPW_DOUT1H, SPW_DOUT1L, SPW_SOUT1H
and SPW_SOUT1L have the following timings
Tskdh
SPW_DOUTxH
SPW_DOUTxL
SPW_SOUTxH
SPW_SOUTxL
Tskdl
CLOCK
(derived from CLP
clock )
Tsksh
Tsksl
Tspock
Tjdh
Tjdl
Tjsh
Tjsl
Figure 3: Spacewire H/L data out timings
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The timings related to the SpaceWire input signals SPW_DIN1H, SPW_DIN1L, SPW_SIN1H and
SPW_SIN1L have the following timings
Tstdh
SPW_DINxH
SPW_DINxL
CLOCK
(output of
XOR( SPW_DINx,
SPW_SINx )
Tspick
Thdh
Tstdl Tstdl
Figure 4: Spacewire H/L data in timings
PARAMETER MIN MIN TYP MAX
Tspcock Internal spacewire clock 10 200 MHz
Tskdh SPW_DOUTxH skew 2 ns
Tjdh SPW_DOUTxH jitter 1 ns
Tskdl SPW_DOUTxL skew 2 ns
Tjdl SPW_DOUTxL jitter 1 ns
Tsksl SPW_SOUTxH skew 2 ns
Tjsl SPW_SOUTxH jitter 1 ns
Tsksl SPW_SOUTxL skew 2 ns
Tjsl SPW_SOUTxL jitter 1 ns
Tspick Generated Spacewire clock 200 MHz
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Tstdh Setup time from SPWW_DINHx 2 ns
Thdh Hold time from SPWW_DINHx 1 ns
Tstdl Setup time from SPWW_DINLx 2 ns
Thdl Hold time from SPWW_DINLx 1 ns
Table 6: SpaceWire timings
6.2.3.4 ETHERNET (REAL-TIME BACKGROUND TRACER)
6.2.3.4.1 PHY INTERFACE
The RTBT of the CLP performs a MDC/MDIO read operation to the external PHY component according to the following diagram
0 1 1 0 0 1 1 0 0 0 0 0 0 0 Z 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0Z Z
Idle StartOpcode
(Read)
PHY Address
(PHYAD = 0Ch)
Register Address
(00h=BMCR)TA Register Data Idle
ZZ
MDIO
(PHY)
ZZ
MDIO
(CLP)
MDC
Figure 5: RTBT_MDC/RTBT_MDIO read operation
The RTBT of the CLP performs a RTBT_MDC/RTBT_MDIO write operation to the external PHY component according to the following diagram
0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Z Z
Idle StartOpcode
(Write)
PHY Address
(PHYAD = 0Ch)
Register Address
(00h=BMCR)TA Register Data Idle
Z
Z
MDIO
(CLP)
MDC
Figure 6: RTBT_MDC/RTBT_MDIO write operation
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6.2.3.4.2 RMII (REDUCED MEDIA INDEPENDENT INTERFACE)
The Reduced Media Independent Interface (RMII) is a synchronous 2-bit wide data interface that
connects the PHY component to the Ethernet MAC of the RTBT. It consists of the following signals:
PHY_TXD[1:0] and PHY_RXD[1:0],
transmit and receive valid signals PHY_TXEN and PHY_RXDV,
error signal PHY_RXER
transmit/receive clocks PHY_RX_CLK/ PHY_TX_CLK
The CLP write a 2-bit nibble to the external PHY component according to the f ollowing diagram
PHY_CLK
PHY_TXD[1:0]
PHY_TX_EN
Valid
nibble
Figure 7: PHY 2-bit nibble write timings
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The CLP read 2-bit nibbles to the external PHY component according to the following diagram
PHY_CLK
PHY_RXD[1:0]
PHY_RX_DV
Valid
nibble
Figure 8: PHY 2-bit nibble read timings
6.2.3.4.3 CLOCKS
Parameter Min Typ Max unit
CLOCK frequency 50 MHz
CLOCK duty cycle 20 50 80 %
M1553_CLK frequency 10 MHz
PHY_CLK frequency 50 MHz
JTAG_CLK frequency 10 MHz
Table 7: Clocls timings
6.2.3.5 OTHER
Timings for ADC interface, PWM timers, excitation PWM, software real time counter and SPI are
provided in the diagrams of corresponding paragraphs.
Timings for other pins are not critical (GPIO, PWM,…) will be provided during future releases
6.2.4 DC CHARACTERISTICS
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6.2.4.1 I2C
The CLP has the following IO characteristics for the I2C interface in standard mode and Fast-Mode
Parameter Symbol Standard-Mode (Min)
Standard-Mode (Max)
Fast-Mode (Min)
Fast-Mode (Max)
Unit
LOW level input voltage: fixed input levels VDD-related input levels
VIL -0.5 -0.5
1.5 0.3VDD
n/a -0.5
n/a 0.3VDD(1)
V V
HIGH level input voltage: fixed input levels VDD-related input levels
VIH 3.0 0.7VDD
(2) (2)
n/a 0.7VDD(1)
n/a (2)
V V
Hysteresis of Schmitt trigger inputs: VDD > 2 V VDD < 2 V
Vhys n/a n/a
n/a n/a
0.05VDD 0.1VDD
- -
V V
LOW level output voltage (open drain or open collector) at 3 mA sink current: VDD > 2 V VDD < 2 V
VOL1 VOL3
0 n/a
0.4 n/a
0 0
0.4 0.2VDD
V V
Output fall time from VIHmin to VILmax with a bus capacitance from 10 pF to 400 pF
tof
-
250(4)
20 + 0.1Cb(3)
250(4)
ns
Pulse width of spikes which must be suppressed by the input filter
tSP n/a n/a 0 50 ns
Input current each I/O pin with an input voltage between 0.1VDD and 0.9VDDmax
Ii -10 10 -10(5) 10(5) µA
Capacitance for each I/O pin Ci - 10 - 10 pF
Table 8: I2C DC characteristics
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(1) Devices that use non-standard supply voltages which do not conform to the intended I2C-bus system levels must relate their input levels to the VDD voltage to which the pull-up resistors Rp are connected.
(2) Maximum VIH = VDDmax + 0.5 V.
(3) Cb = capacitance of one bus line in pF.
(4) The maximum tf for the SDA and SCL bus lines quoted in Table 5 (300 ns) is longer than the specified maximum tof for the output stages (250 ns). This allows series protection resistors (Rs) to be connected between the SDA/SCL pins and the SDA/SCL bus lines as shown in Fig.36 without exceeding the maximum specified tf.
(5) I/O pins of Fast-mode devices must not obstruct the SDA and SCL lines if VDD is switched off.
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6.2.5 ENVIRONMENTAL REQUIREMENTS
6.2.5.1 RADIATION
Parameter Min Typ Max unit
TID (*) 150 kRad
Latchup LET threshold 70 Mev*cm2/mg
SEU LET threshold (**) Mev*cm2/mg
Table 9: Radiation characteristics
(*) tested up to 300 kRad
(**) to be determined in future releases
6.3 PACKAGE
The CLP is packaged in a ceramic and hermetic top-brazed QFP 256-pins package
6.4 QUALITY FLOW
The CLP is manufactured according to ESA ESCC-9000 standard.
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7 CENTRAL PROCESSING UNIT (CPU)
7.1 ARCHITECTURE
Each CPU is made of:
two identical floating point units called A and B that also support integer operations
one integer unit called "Special Unit" (SU).
The CLP has two identical Central Processing Units, called CPU, which are compliant with IEEE-754
single-precision formation. Such implementation is however restricted to the 32-bits binary format
mainly to have a similar approach than the ADSP-21020 device from Analog Devices.
One CPU works with three pipeline stages - Fetch, Decode and Execute - as depicted in the diagram
below
INSTRUCTION
SEQUENCER
INSTRUCTION
DECODER
ARITHMETIC
UNIT(S)
INS
TR
UC
TIO
N
RE
GIS
TE
R
CO
MM
AN
DS
RE
GIS
TE
RS
SO
UR
CE
RE
GIS
TE
R(S
)
DE
ST
INA
TIO
N
RE
GIS
TE
R(S
)
PR
OG
RA
M
ME
MO
RY
1 clock cycle 1 clock cycle 1or several clock cycles
FETCH DECODE EXECUTE
Figure 9: CLP pipeline architecture
Each CPU stage is executed in one clock cycle except the execute stage which needs one or several
clock cycles depending on either the instruction being executed or the transfer being executed.
The CPU has a SIMD architecture. The execution of instructions can be made, in either A, B, SU or
simultaneously on A and B units
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7.1.1 IEEE-754 IMPLEMENTATION
The CLP data format is based on a subset of the IEEE-754 standard (cfr [AD8]. The compliance with
respect to the IEEE-754 standard is provided in section 31.21. The following floating point operations
are supported by the CPU:
Addition
Subtraction
Multiplication
Division (performs y/x operation)
Conversion from floating point to integer
Conversion from integer to floating point
Compare
The only IEEE-754 format that is supported by the CLP is the single-precision (32-bit) binary format.
There are two rounding strategies for floating operations available: the “rounding-to-nearest
(roundTiesToEven)” and the “rounding-to-zero”. The choice of rounding strategy is made through
the "RNDF” bit located in the RCONF register
When a floating-point arithmetic operation is executed, the floating-point units (A and B) never
generate any NaN, infinite or denormalized number. In addition, such values are read as illegal
values and are automatically converted to a known and valid value according to the following table:
ILLEGAL
OPERAND
CONVERTED VALUE
NaN 0 (the sign of the 0 is fixed by the NaN sign)
+ Infinite + Maxfloat
- Infinite - Maxfloat
denormalised 0 (the sign of the 0 is fixed by the denormalised value sign)
Table 10: IEEE-754 Illegal values conversion table
The detection of these illegal values is reported in a dedicated 2-bit counters located in RSTATCNTA
and/or RSTATCNTB. For a given instruction, one increment is independently made for each operand.
However, up to 3 increments of RSTATCNTA or RSTATCNTB may occur per instruction (two for each
operand and one for the result).
The floating-point units also integrate one saturation mechanism to Maxfloat (=greatest
representable floating-point value ) or Minfloat (=smallest representable floating-point value), if the
computed result goes out of bounds. In particular for division by Zero, in case of dividend different
than Zero (x/0), the result saturates to Maxfloat and in case of dividend equal to Zero (0/0), it
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saturates to 0 (as NaN has to be converted to 0). These events are also reported in the RSTATCNTA
and/or RSTATCNTB counter
Except for the division operation, it is possible to pipeline multiple-cycle floating point instructions
between them.
The CPU continues working even if an illegal value is encountered.
7.1.2 CONDITION CODES
The three units of each CPU provide the following conditions codes to provide the required support
for code structures involving decisions :
FLAG
NAME
DESCRIPTION
N indicating if the result is negative or positive
Z indicating if the result equals zero or not
C holding the carry-out generated when the adder/subtracter has been used, taking 2's
complement convention into account
O indicating that an overflow has occurred
Table 11: Condition codes
These conditions codes are maintained individually for floating-point operations, low-bits integer
operations and high-bits integer operations. These 4 condition codes are handled separately
depending on the type of operands that is involved.
In particular, for N flag, 3 different bits are handled (as a reminder u. denotes the CPU unit) :
u.N.l: set if the sign of the last integer low-bits operation is negative; cleared otherwise.
u.N.h: set if the sign of the last integer high-bits operation is negative; cleared otherwise.
u.N.f: set if the sign of the last floating-point operation is negative; cleared otherwise.
For Z flag, 3 different bits are handled:
u.Z.l: set if the last integer low-bits operation is equal to zero; cleared otherwise.
u.Z.h: set if the last integer high-bits operation is equal to zero; cleared otherwise.
u.Z.f: set if the last floating-point operation is equal to zero; cleared otherwise.
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For O flag, 2 different bits are handled:
u.O.l: set if the last integer low-bits operation has generated an overflow (taking the signed or unsigned representation into account); cleared otherwise.
u.O.h: set if the last integer high-bits operation has generated an overflow (taking the signed or unsigned representation into account); cleared otherwise.
For the C flag, only one bit is handled
u.C.l: set if the last integer low-bits result has produced a carry out (the signed or unsigned representation is not taken into account); cleared otherwise.
Note that overflow flag is managed only when integer operations are executed. Floating-point
operations include an automatic saturating arithmetic by design and do not manage the overflow
and carry-out flags.
The instruction set described in §7.1.6 indicates which flag(s) are updated.
7.1.3 INTEGER FORMAT
The integer data format is either signed or unsigned (selection is made at the instruction level).
The data is always either 16-bits or 32-bits wide.
When the data is 16-bits wide, it is represented:
when signed numbers are used, in 2's complement: (b15 b14 ... b0) where bit 15 is the sign bit, bit 14 has weight 2^14 and so on.
when unsigned numbers are used, as a positive number (b15 b14 ... b0) where bit 15 is the msb and has weight 2^15 , bit 14 has weight 2^14 and so on.
When the data is 32-bits wide, it is represented:
when signed numbers are used, in 2's complement: (b31 b30 ... b0) where bit 31 is the sign bit, bit 30 has weight 2^30 and so on.
when unsigned numbers are used, as a positive number (b31 b30 ... b0) where bit 31 is the msb and has 2^31 , bit 30 has weight 2^30 and so on.
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7.1.4 REGISTER FILES
7.1.4.1 GENERAL-PURPOSE REGISTERS
Each floating point unit has a register file made of 512 general-purpose registers. Each of these
registers is named RGP0 to RGP511 and is 32-bits wide.
7.1.4.2 OFFSET REGISTERS
Each floating point unit also has set of 512 offset registers which are “address-mapped” to the
various RGPx general-purpose registers according to the content of the stack pointer register RSPA
(for unit A) and RSPB (for unit B). Each of these offset register is also 32-bits wide and are named
ROFF0 to ROFF511.
When an instruction requests a read or write to an offset register ROFFx (x=0...511), the floating
point unit accesses the RGPy (y=0...511) general-purpose register according to the following
formula:
y=RSPA+x (for A unit) and/or y=RSPB+x (for B unit)
Whenever the formula determining the RGPy (y=0...511) overflows (i.e. a stack overflow occurs), a wrap-around occurs and the associated RSTATCNTA/RSTATCNTB counter incremented.
The CPU continues working even if a stack overflow is encountered, except if a software reset is programmed on stack overflow event in RSWREST register.
7.1.4.3 OFFSET REGISTERS
Each floating point unit has a set of 32 DMA registers. Each of these registers is named RD0 to RD31
and is 32-bits wide. These registers are used by the DMA of each unit to perform pre-programmed
read/ write transfers from/ to these registers to/from the APB memory space.
7.1.4.4 SPECIAL REGISTERS
Each floating-point unit has three special registers that are mapped to the ALU outputs are updated
according to the instruction that has been executed. The first one is the ROUTADD, which is 32-bits
wide and is targeted in most ALU instructions. The second one is the ROUTMUL, which is 32-bits
wide and is targeted in ALU instructions involving a multiplication. The second one is the ROUTDIV,
which is 32-bits wide and is targeted in ALU instructions involving a division. All these registers can
be written exclusively in the scope of ALU instructions
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7.1.4.5 SUMMARY TABLE
The CLP register structure in unit A and B (made of RGPX, ROFFx, RSRx,…) is presented below .
Table 12: A/B unit register structure
(*) these registers are written exclusively in the scope of corresponding ALU instructions
Address
(bin)
Address
(hex)
in
A and B
Register type Comment Reset
Value
00000000000 000 RGP0 General purpose
register
Unknown
00000000001 001 RGP1 General purpose
register
Unknown
.. .. .. General purpose
register
Unknown
00111111110 1FE RGP510 General purpose
register
Unknown
00111111111 1FF RGP511 General purpose
register
Unknown
01000000000 200 ROFF0 Offset register Unknown
.. .. .. Offset register Unknown
01111111110 3FE ROFF510 Offset register Unknown
01111111111 3FF ROFF511 Offset register Unknown
10000000000 400 RD0 Special register DMA register h00000000
10000000001 401 RD1 Special register DMA register h00000000
.. .. .. Special register DMA register h00000000
10000011110 41E RD30 Special register DMA register h00000000
10000011111 41F RD31 Special register DMA register h00000000
.. .. .. Not used Not used
10000100001 421 ROUTDIV(*) Special register Divider output register h00000000
10000100010 422 ROUTADD(*) Special register Adder (ALU) output
register
h00000000
10000100011 423 ... Not used Not used
10000100100 424 ROUTMUL(*) Special register Multiplier output
register
h00000000
.. … … Not used Not used
11000000000 600 N/A immediate Reserved, refers to
imm0
N/A
.... .... ... Reserved N/A
11111111111 7FF N/A immediate Reserved N/A
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7.1.5 SU UNIT
7.1.5.1 GENERAL-PURPOSE REGISTERS
The SU unit have a register file made of 32 general-purpose registers. Each of these registers is
named RGP0 to RGP31 and is 16-bits wide.
7.1.5.2 OFFSET REGISTERS
The SU unit have a set of 32 offset registers which is address-mapped to the various RGPx general-
purpose registers according to the content of the stack pointer register RSPSU. Each of these offset
register is 16-bits wide and named ROFF0 to ROFF31
When an instruction requests one read or write to an offset register ROFFx (x=0...31), the SU unit
access the RGPy (y=0...31) general-purpose register according to the following formula:
y=RSPSU+x (for SU unit)
Whenever the formula determining the RGPy (y=0...31) overflows (i.e. a stack overflow occurs), a
wrap-around is implemented and the associated RSTATCNTSU counter incremented.
7.1.5.3 SPECIAL REGISTERS
The SU unit has two special registers that are mapped to the ALU outputs and are updated according
to the instruction that has been executed. The first one is the ROUTADD, which is 16-bit wide and is
targeted in most ALU instructions. The second one is the ROUTMUL, which is 16-bit wide and is
targeted in ALU instructions involving a multiplication. All these registers can be written exclusively
in the scope of ALU instructions
The RPC register is 15-bit wide and holds the program counter value. It constantly points to the
instruction being fetched even when a transfer is occurring on the memory (i.e. a direct/indirect
branch or immediate load, cfr 7.1.7.3). Whenever a RPC read is requested by an instruction, the
value is aligned to the 15 LSBs (others bits are set to '0'). Whenever a RPC write is requested by an
instruction, only the 15 LSBs are taken into account (others bits remain to '0').
The RSPA and RSPB registers are 9-bit wide and hold the content of the stack pointer of units A and
B (respectively). Whenever an RSPA or RSPB read is requested by an instruction, the value is
interpreted as an unsigned positive value and is aligned to the 9 LSBs (others bits are set to '0').
Whenever a RSPA or RSPB write is requested by an instruction, only the 9 LSBs are taken into
account (others bits remain to '0') and the corresponding ROFFx mapping is updated two cycles after
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the instruction that updated RSPA/RSPB (i.e. the next cycle still takes the previous value into
account)
The RSPSU register is 5-bit wide and holds the content of the stack pointer of SU unit. Whenever an
RSPSU read is requested by an instruction, the value is interpreted as an unsigned positive value and
is aligned to the 5 LSBs (others bits are set to '0'). Whenever an RSPSU write is requested by an
instruction, only the 5 LSBs are taken into account (others bits remain to '0') and the corresponding
ROFFx mapping is updated two cycles after the instruction that updated RSPSU (i.e. the next cycle
still takes the previous value into account)
The RFLAGA register is 16-bit wide and holds the condition codes of A unit according to the following
definition:
BIT FLAG DESCRIPTION
others ‘0’ Unused
9 A.O.h O flag of last integer high-bits or 32-bits arithmetic operation executed in unit A
8 ‘0’ Unused
7 A.N.h N flag of last integer high-bits or 32-bits arithmetic operation executed in unit A
6 A.Z.h Z flag of last integer high-bits or 32-bits arithmetic operation executed in unit A
5 A.O.l O flag of last integer low-bits arithmetic operation executed in unit A
4 A.C.l C flag of last integer low-bits arithmetic operation executed in unit A
3 A.N.l N flag of last integer low-bits arithmetic operation executed in unit A
2 A.Z.l Z flag of last integer low-bits arithmetic operation executed in unit A
1 A.N.f N flag of last floating-point operation executed in unit A
0 A.Z.f Z flag of last floating-point operation executed in unit A
Table 13: RFLAGA description
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The RFLAGB register is 16-bit wide and holds the condition codes of B unit according to the following
definition:
BIT FLAG DESCRIPTION
others ‘0’ Unused
9 B.O.h O flag of last integer high-bits or 32-bits arithmetic operation executed in unit B
8 ‘0’ Unused
7 B.N.h N flag of last integer high-bits or 32-bits arithmetic operation executed in unit B
6 B.Z.h Z flag of last integer high-bits or 32-bits arithmetic operation executed in unit B
5 B.O.l O flag of last integer low-bits arithmetic operation executed in unit B
4 B.C.l C flag of last integer low-bits arithmetic operation executed in unit B
3 B.N.l N flag of last integer low-bits arithmetic operation executed in unit B
2 B.Z.l Z flag of last integer low-bits arithmetic operation executed in unit B
1 B.N.f N flag of last floating-point operation executed in unit B
0 B.Z.f Z flag of last floating-point operation executed in unit B
Table 14: RFLAGB description
The RFLAGSU register is 16-bit wide and holds the condition codes of SU unit according to the
following definition:
BIT FLAG DESCRIPTION
others ‘0’ Unused
5 SU.O.l O flag of last integer arithmetic operation executed in unit SU
4 SU.C.l C flag of last integer arithmetic operation executed in unit SU
3 SU.N.l N flag of last integer arithmetic operation executed in unit SU
2 SU.Z.l Z flag of last integer arithmetic operation executed in unit SU
1 ‘0’ Unused
0 ‘0’ Unused
Table 15: RFLAGSU description
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The RSTATG1 register is 16-bit wide and holds general CLP status information according to the
following definition:
BIT DESCRIPTION
others ‘0’ - Unused
7 The PLL lock status (mapped to PLL_LOCK pin)
'0' = unlocked
'1' = locked
6-3 the CLP identifier, unique for a given VHDL code release (0001=release 1.0; etc...)
2-0 The boot source (mapped to read value on BDINIT_SEL[2:0]
000 = SPW0
001 = SPW1
010 = MEM8
011 = CAN
others = RTBT
Table 16: RSTATG1 description The RSTATG2 register is 16-bit wide. It is used to indentify any CLP variant (tunable via VHDL source code) and holds the architectural description of the CLP according to the following definition:
BIT DESCRIPTION
15 UART selection ('0 '= not present; '1'=all functions are present)
14 INTERCOM RAM selection ('0 '= not present; '1'=all functions are present)
13 CRC selection ('0' = not present; '1'=at least one CRC is present)
12 ADC interface selection ('0' = not present; '1'=all functions are present)
11 I2C selection ('0' = not present; '1'=all functions are present)
10 SPI selection ('0'=not present; '1'=at least one SPI is present)
9 PWM selection ('0'=not present; '1'=all functions are present)
8 SPACEWIRE#1 selection ('0'=no present; '1'=all functions are present)
7 SPACEWIRE#0 selection ('0'=no present; '1'=all functions are present)
6 CAN selection ('0'=no present; '1'=all functions are present)
5 ‘0’
4 MIL-STD-1553 RT selection ('0'=no present; '1'=all functions are present)
3-2 Program memory size ('11'=32768x32;'10'=16384x32;'01'=8192x32;'00'=4096x32)
1 FPU count ('0'=1 FPU; '1'=2 FPU). If two CPU are present, the same number of FPU apply to
both
0 CPU count:
'0': 1 CPU
INTERCOM RAM is not present;
only one CRC unit is present (if CRC is selected)
'1': 2 CPUs
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BIT DESCRIPTION
INTERCOM RAM is present (if selected);
two CRC units are present (if CRC is selected)
Table 17: RSTATG2 description
The RSTATCNT1 register is 16-bit wide and holds the content of counters applicable to CPU in
general according to the following definition:
BIT DESCRIPTION
others ‘0’ - Unused
1-0 "illegal opcode detection" saturating counter
Table 18: RSTATCNT1 description
The RSTATCNTA register is 16-bit wide and holds the content of counters applicable to unit A
according to the following definition:
BIT DESCRIPTION
others ‘0’ - Unused
9-8 "illegal operand detection" saturating counter
7-6 "unsupported value (NaN,+/-infinite, overflow detected) detection" saturating counter
5-4 "non-normalised value detection" (denormalised, underflow detected) saturating
counter
3-2 "simultaneous write to a same register detection" saturating counter
1-0 "stack overflow detection" saturating counter
Table 19: RSTATCNTA description
The RSTATCNTB register is 16-bit wide and holds the content of counters applicable to unit B
according to the following definition:
BIT DESCRIPTION
others ‘0’ - Unused
9-8 "illegal operand detection" saturating counter
7-6 "unsupported value (NaN,+/-infinite, overflow detected) detection" saturating counter
5-4 "non-normalised value detection" (denormalised, underflow detected) saturating
counter
3-2 "simultaneous write to a same register detection" saturating counter
1-0 "stack overflow detection" saturating counter
Table 20: RSTATCNTB description
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The RSTATCNTSU register is 16-bit wide and holds the content of counters applicable to unit SU
according to the following definition:
BIT DESCRIPTION
others ‘0’ - Unused
9-8 "illegal operand detection" saturating counter
7-2 “000000” - Unused
1-0 "stack overflow detection" saturating counter
Table 21: RSTATCNTSU description
The RSTATCNT2 register is 16-bit wide and holds the content of counters according to the following
definition:
BIT DESCRIPTION
others ‘0’ - unused
11-10 APB Allocation/Write protection violation error saturating counter for the other CPU
9-8 APB Allocation/Write protection violation error saturating counter for this CPU
7-6 ADC I/F error saturating counter
5-4 MMU Address Access error saturating counter
3-2 Software restart saturating counter
1-0 Last successful Boot Descriptor (BD0=00b, BD1=01b, BD2=10b, BD3=11b)
Table 22: RSTATCNT2 description
The RSTATCNT3 register is 16-bit wide and holds the content of recoverable SEU-related information
according to the following definition:
BIT DESCRIPTION
others ‘0’
9-8 recoverable SEU saturating counter for Unit B File Register
7-6 recoverable SEU saturating counter for Unit A File Register
5-4 recoverable SEU saturating counter for XCHG RAM
3-2 recoverable SEU saturating counter for Program RAM
1-0 recoverable SEU saturating counter for INTERCOM RAM
Table 23: RSTATCNT3 description
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The RSTATCNT4 register is 16-bit wide and holds the content of unrecoverable errors related information (counter and source(s) stored in a FIFO fashion) according to the following definition:
BIT DESCRIPTION
15-13 unrecoverable SEU error source related to 2nd last event for other CPU
12-10 unrecoverable SEU error source related to last event for other CPU
001=INTERCOM RAM;
010=Program RAM;
011=XCHG RAM;
100=Unit A File Register;
101=Unit B File Register
9-8 unrecoverable SEU errors saturating counter for other CPU
7-5 unrecoverable SEU error source related to 2nd last event for this CPU
4-2 unrecoverable SEU error source related to last event for this CPU
001=INTERCOM RAM;
010=Program RAM;
011=XCHG RAM;
100=Unit A File Register;
101=Unit B File Register
1-0 unrecoverable SEU errors saturating counter for this CPU
Table 24: RSTATCNT4 description
When multiple unrecoverable SEU errors from different sources occur at the same cycle, the error
saturating counter is incremented by one.
When multiple unrecoverable SEU errors from different sources occur at the same cycle, only one
event is logged following this priority (first item having the highest priority) :
Program RAM (CPU side) > Unit B File Register > Unit A File Register > XCHG Ram > Program RAM
(APB side) > INTERCOM RAM
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The RCONF register is 16-bit wide and has the following definition:
BIT DESCRIPTION
others ‘0’
10 RNDI bit holding the selected integer rounding
'0' = round-to-zero (RTZ); '1' = round-to-nearest (RTN).
9 RNDF bit holding the selected IEEE-compliant rounding:
'0' = round-to-zero (RTZ); '1' = round-to-nearest (RTN).
8 FIXSAT bit selecting or not the integer saturation mode:
'0'=non-saturating ; '1'=saturating (*)
7-4 DMA synchronisation source:
0000=TIMER0,.....1001=TIMER9, others=TIMER9
3 DMA enable bit:
'0' = disabled; '1' = enabled.
2-0 "000"
Table 25: RCONF description
(*) if an operation gives a result that exceeds the signed or unsigned representation dynamic, the
result saturates to the greatest (signed positive or unsigned) or smallest (signed negative)
representable value.
The RSWREST register, dedicated to the software restart function, is 16-bit wide and have the following definition:
BIT DESCRIPTION
others ‘0’
13 Software restart GENERAL enable(='1')/disable(='0), applies to all bits below
12 restart on PLL unlock value (enable(='1')/disable(='0))
11 restart on ADC I/F error (enable(='1')/disable(='0))
10 restart on AHB/MMU error (enable(='1')/disable(='0))'
9 restart on MMU simultaneous access error (enable(='1')/disable(='0))
8 '0'
7-4 restart on Timer tick("0000"=TIMER0,"0001"=TIMER1,...,"1001"=TIMER9, others =
disabled)
3 restart on unrecoverable SEU (enable(='1')/disable(='0))
2 restart on SWRST instruction (enable(='1')/disable(='0))
1 restart on simultaneous write to same register (enable(='1')/disable(='0))
0 restart on offset register access overflow (enable(='1')/disable(='0))
Table 26: RSWREST description
Whenever several events are programmed inside RSWREST, an OR function is used between each of
them. The restart procedure is explained in section 27.3.
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7.1.5.4 SUMMARY TABLE
The CLP register structure in unit SU (made of RGPX, ROFFx,RSRx …) is presented in the table below.
Address
(bin)
Address
(hex)
in SU Register type Comment Reset
Value
00000000000 000 RGP0 General purpose register h0000
00000000001 001 RGP1 General purpose register h0000
.. .. .. General purpose register h0000
00000011110 01E RGP30 General purpose register h0000
00000011111 01F RGP31 General purpose register h0000
.. .. .. Not used Not used
01000000000 200 ROFF0 Offset register h0000
01000000001 201 ROFF1 Offset register h0000
.. .. .. Offset register h0000
01000011110 21E ROFF30 Offset register h0000
01000011111 21F ROFF31 Offset register h0000
.. .. .. Not used Not used
10000000001 401 RMEM(***) Special register Program memory 32-bit
output register
h00000000
10000000010 402 ROUTAPB (**) Special register APB 32-bit output register h00000000
.. .. ... Not used Not used
10000000100 404 RPC Special register Program counter h0000
10000000101 405 RSPA Special register Unit A Stack pointer h0000
10000000110 406 RSPB Special register Unit B Stack pointer h0000
10000000111 407 RSPSU Special register Unit SU Stack pointer h0000
... ... ... Not used Not used
10000100010 422 ROUTADD(*) Special register Adder (ALU) output register h0000
.. 423 .. Not used Not used
10000100100 424 ROUTMUL(*) Special register Mutliplier output register h0000
.. .. .. Not used Not used
10001000000 440 RCONF Special register configuration register h0000
10001000001 441 RFLAGA(**) Special register status register h0000
10001000010 442 RFLAGB(**) Special register status register h0000
10001000011 443 RFLAGSU(**) Special register status register h0000
10001000100 444 RSTATCNT1(**) Special register status register h0000
10001000101 445 RSTATCNTA(**) Special register status register h0000
10001000110 446 RSTATCNTB(**) Special register status register h0000
10001000111 447 RSTATCNTSU(**) Special register status register h0000
10001001000 448 RSTATCNT2(**) Special register status register h0000
10001001001 449 RSTATCNT3(**) Special register status register h0000
10001001010 44A RSTATCNT4(**) Special register status register h0000
10001001011 44B .. Not used Not used
10001001100 44C RSTATG1(**) Special register status register Cfr 7.1.5.3
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Table 27: SU unit register structure
(*) these registers are overwritten exclusively in the scope of corresponding ALU instructions
(**) read-only registers. Any instruction attempting to overwrite their content is not taken into
account
(***) this read-only register is read exclusively in the scope of transfers explained in section 7.1.7.2
(APB and program management).
All SU registers are 16-bits wide, except RMEM and ROUTAPB that are 32-bits wide. The reason is
that the address bus of the program memory is 15-bits wide, the APB memory space is 16-bits wide
and that the SU unit is mainly dedicated to address management. The RMEM receives data from the
program memory, which is 32 bits-wide, so this register needs 32 bits. The RMEM receives data
coming from the peripheral management unit and some data (floating-point values for instance)
passing by RMEM are 32-bits wide, so this register needs to have 32 bits.
When the contents of a 16-bits register are transferred to a 32 bits register, the data is moved to the
16 LSB of the 32 bits register. In the same logic, a mov from a 32 bits register to a 16 bits register will
move the 16 LSB of the 32 bits register to the destination.
10001001101 44D RSTATG2(**) Special register status register (for CLP light
identifier)
hFFDF
10001001110 44E RSWREST Special register control register h0000
.. .. .. Not used Not used
11000000000 600 N/A immediate Reserved, refers to imm0 N/A
.... .... immediate Reserved N/A
11111111111 7FF N/A immediate Reserved N/A
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7.1.6 INSTRUCTION SET
The instruction format is as followed:
XXXXXXXXXX XX XXXXXXXXXX XXXXXXXXXX
31 24 22 21 11 10 0
F#1 F#2 F#3 F#4
FIELD WIDTH DESCRIPTION
F#1 8-bits OPCODE
F#2 2-bits ACTIVITY
F#3 11-bits OPERAND#1
F#4 11-bits OPERAND#2
23
The field f#1 denote the 32-bit instruction opcode with a 8-bit binary code
The field f#2 denote the 32-bit instruction activity in line with the following binary code
SYMBOL CODE MEANING
SU 00 SU unit selected
A 01 A unit selected
B 10 B unit selected
AB 11 A and B units selected
Table 28: Instruction field #2 description
The field f#3 denote the 1st operand (if applicable) of the 32-bit instruction. The 2 MSBs (i.e. bits 21
and 20 in the instruction) indicate the type of operands as described below:
SYMBOL CODE MEANING
RGPx 00xxxxxxxxx
address of any RGP registers
ROFFx 01xxxxxxxxx address of any offset register
RSRx 10xxxxxxxxx address of any special register
IMM9 11LLLLLLLLL where LLLLLLLL is an immediate value coded as a 9-bit data
and whose interpretation (signed/unsigned) depends on the
executed instruction
Table 29: Instruction field #3 description
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The field f#4 denotes the 2nd operand (if applicable) of the 32-bit instruction. The 2 MSBs (i.e. bits
10 and 9 in the instruction) indicates the type of operands as described below:
SYMBOL CODE MEANING
RGPy 00xxxxxxxxx
address of any RGP registers
ROFFy 01xxxxxxxxx address of any offset register
RSRy 10xxxxxxxxx address of any special register
IMM9 11LLLLLLLLL where LLLLLLLL is an immediate value coded as a 9-bitdata
and whose interpretation (signed/unsigned) depends on the
executed instruction
Table 30: Instruction field #4 description
The following format will be used to described the CLP instruction set:
INSTRUCTION NAME OPCODE CONDITION CODES NUMBER OF CYCLES UNIT(s) OPERAND1 OPERAND2
EFFECT
DESCRIPTION
7.1.6.1 ALU INSTRUCTIONS
Note:
If a register/a condition code is not mentioned, it means it is not accepted/affected by the described instruction
RMEM can only be used in the scope of transfers (cfr 7.1.7)
FDIV 00000000 u.N.f,u.Z.f 10 cycles A/B/AB RGPx/ROFFx/RSRx RGPy/ROFFy/RSRy
u.routdiv = u.rx/u.ry
Compute a floating point division between contents of registers u.rx (dividend) and u.ry (divisor).
The rounding strategy selected in RNDF bit (cfr RCONF in §7.1.5.3) is taken into account.
Result is sent to u.routdiv.
If an overflow occurs, the result is saturated to its maximal value
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FADD 00000001 u.N.f,u.Z.f 2 cycles A/B/AB RGPx/ROFFx/RSRx RGPy/ROFFy/RSRy
u.ROUTADD = u.rx + u.ry
Perform a floating point addition between contents of registers u.rx and u.ry.
The rounding strategy selected in RNDF bit (cfr RCONF in §7.1.5.3) is taken into account.
Result is sent to u.ROUTADD.
The instruction can be pipelined with another instruction.
If an overflow occurs, the result is saturated to its maximal value
FSUB 00000010 u.N.f,u.Z.f 2 cycles A/B/AB RGPx/ROFFx/RSRx RGPy/ROFFy/RSRy
u.ROUTADD = u.rx - u.ry
Performs a floating point subtraction between contents of registers u.rx and u.ry.
The rounding strategy selected in RNDF bit (cfr RCONF in §7.1.5.3) is taken into account.
Result is sent to u.ROUTADD.
The instruction can be pipelined with another instruction.
If an overflow occurs, the result is saturated to its maximal value
FMUL 00000011 u.N.f,u.Z.f 2 cycles A/B/AB RGPx/ROFFx/RSRx RGPy/ROFFy/RSRy
u.ROUTMUL = u.rx * u.ry
Performs a floating point multiplication between contents of registers u.rx and u.ry.
The rounding strategy selected in RNDF bit (cfr RCONF in §7.1.5.3) is taken into account.
Result is sent to u.ROUTMUL.
The instruction can be pipelined with another instruction
If an overflow occurs, the result is saturated to its maximal value
FCOMP 00000100 u.N.f,u.Z.f 1 cycle A/B/AB RGPx/ROFFx/RSRx RGPy/ROFFy/RSRy
u.Z.f = is_zero(u.rx - u.ry); u.N.f = sign(u.rx - u.ry)
Performs a floating point comparison between rx and ry.
The result exclusively update the associated flags (other output registers remain untouched)
FTOINT 00000101 u.N.l, u.Z.l, u.O.l 1 cycle A/B/AB RGPx/ROFFx/RSRx Not interpreted
u.ROUTADD.l = int(u.rx)
The contents of the floating point register u.rx is successively read, interpreted according to IEEE-
754 32-bit floating point representation and converted to the closest 2's complement 16-bits signed
representation, according to RNDI bit (cfr RCONF in §7.1.5.3).
if u.rx exceeds the available 16-bit range, the flag u.O.l is set and the result unconditionally
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FTOINT saturates (FIXSAT bit is NOT taken into account).
The result is stored in the 16 LSB of u.ROUTADD
INTOF 00000110 u.N.f, u.Z.f 1 cycle A/B/AB RGPx/ROFFx/RSRx/IMM9 Not interpreted
u.ROUTADD = float (u.rx.l)
u.ROUTADD = float (IMM9)
The contents of the 16 LSB of u.rx or IMM9 is successively read, interpreted as a 2’s complement
signed value and converted according to IEEE-754 32-bit floating point representation.
When IMM9 is used for the operand, the 9 LSBs is extended to 16-bit and according to 2's
complement convention
The result is stored in u.ROUTADD.
LADDS 00001000 u.N.l, u.Z.l, u.O.l 1 cycle A/B/AB/SU RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy/IMM9
u.ROUTADD.l = u.rx.l + u.ry.l
u.ROUTADD.l = IMM9 + u.ry.l
u.ROUTADD.l = u.rx.l + IMM9
u.ROUTADD.l = IMM9 + IMM9
Performs an integer signed addition between operands.
When IMM9 is the operand, the 9 LSBs of the immediate value is used as data.
Data is interpreted in 2's complement. Result is sent to the 16 LSB of u.ROUTADD.
LADDU 00001001 u.Z.l, u.O.l, u.C.l 1 cycle A/B/AB/SU RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy/IMM9
u.ROUTADD.l = u.rx.l + u.ry.l
u.ROUTADD.l = IMM9 + u.ry.l
u.ROUTADD.l = u.rx.l + IMM9
u.ROUTADD.l = IMM9 + IMM9
Performs an integer unsigned addition between operands.
When IMM9 is the operand, the 9 LSBs of the immediate value is used as data.
Data is interpreted as 16-bit unsigned positive. Result is sent to the 16 LSB of u.ROUTADD.
HADDS 00001010 u.N.h, u.Z.h,
u.O.h
1 cycle A/B/AB RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy/IMM9
u.ROUTADD.h = u.rx.h + u.ry.h
u.ROUTADD.h = IMM9 + u.ry.h
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u.ROUTADD.h = u.rx.h + IMM9
u.ROUTADD.h = IMM9 + IMM9
Perform an integer signed addition between operands.
When IMM9 is the operand, the 9 LSBs of the immediate value is used as data.
Data is interpreted in 2's complement.
Result is sent to the 16 MSB of u.ROUTADD
HADDU 00001011 u.Z.h, u.O.h 1 cycle A/B/AB RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy/IMM9
u.ROUTADD.h = u.rx.h + u.ry.h
u.ROUTADD.h = IMM9 + u.ry.h
u.ROUTADD.h = u.rx.h + IMM9
u.ROUTADD.h = IMM9 + IMM9
Perform an integer unsigned addition between operands.
When IMM9 is the operand, the 9 LSBs of the immediate value is used as data.
Data is interpreted as 16-bit unsigned positive.
Result is sent to the 16 MSB of u.ROUTADD.
HADDS32 00001100 u.N.h, u.Z.h, u.O.h 1 cycle A/B/AB RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy/IMM9
u.ROUTADD = u.rx + u.ry
u.ROUTADD = IMM9 + u.ry
u.ROUTADD = u.rx + IMM9
u.ROUTADD = IMM9 + IMM9
Performs a 32-bit integer signed addition between operands.
When IMM9 is the operand, the 9 LSBs of the immediate value is used as data.
Data is interpreted in 2's complement and sign extended to 32-bits when IMM9 is the operand.
Result is sent to the 32-bits of u.ROUTADD.
HADDU32 00001101 u.Z.h, u.O.h 1 cycle A/B/AB RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy/IMM9
u.ROUTADD = u.rx + u.ry
u.ROUTADD = IMM9 + u.ry
u.ROUTADD = u.rx + IMM9
u.ROUTADD = IMM9 + IMM9
Performs a 32-bit integer unsigned addition between operands.
When IMM9 is the operand, the 9 LSBs of the immediate value is used as data.
Data is interpreted as 32-bit unsigned positive and filled with ‘0’ when IMM9 is the operand. Result
is sent to the 32-bits of u.ROUTADD.
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LSUBS 00010000 u.N.l, u.Z.l, u.O.l 1 cycle A/B/AB/SU RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy/IMM9
u.ROUTADD.l = u.rx.l - u.ry.l
u.ROUTADD.l = IMM9 - u.ry.l
u.ROUTADD.l = u.rx.l - IMM9
u.ROUTADD.l = IMM9 - IMM9
Perform an integer signed subtraction between operands.
When IMM9 is the operand, the 9 LSBs of the immediate value is used as data.
Data is interpreted in 2's complement. Result is sent to the 16 LSB of u.routadd.
LSUBU 00010001 u.Z.l, u.O.l, u.C.l 1 cycle A/B/AB/SU RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy/IMM9
u.ROUTADD.l = u.rx.l - u.ry.l
u.ROUTADD.l = IMM9 - u.ry.l
u.ROUTADD.l = u.rx.l - IMM9
u.ROUTADD.l = IMM9 - IMM9
Performs an integer unsigned subtraction between operands.
When IMM9 is the operand, the 9 LSBs of the immediate value is used as data.
Data is interpreted as 16-bit unsigned positive. Result is sent to the 16 LSB of u.ROUTADD.
HSUBS 00010010 u.N.h, u.Z.h, u.O.h 1 cycle A/B/AB RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy/IMM9
u.ROUTADD.h = u.rx.h - u.ry.h
u.ROUTADD.h = IMM9 - u.ry.h
u.ROUTADD.h = u.rx.h - IMM9
u.ROUTADD.h = IMM9 - IMM9
Perform an integer signed subtraction between operands.
When IMM9 is the operand, the 9 LSBs of the immediate value is used as data.
Data is interpreted in 2's complement. Result is sent to the 16 MSB of u.ROUTADD.
HSUBU 00010011 u.Z.h, u.O.h 1 cycle A/B/AB RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy/IMM9
u.ROUTADD.h = u.rx.h - u.ry.h
u.ROUTADD.h = IMM9 - u.ry.h
u.ROUTADD.h = u.rx.h - IMM9
u.ROUTADD.h = IMM9 - IMM9
Perform an integer unsigned subtraction between operands.
When IMM9 is the operand, the 9 LSBs of the immediate value is used as data.
Data is interpreted as 16-bit unsigned positive. Result is sent to the 16 MSB of u.ROUTADD.
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HSUBS32 00010100 u.N.h, u.Z.h, u.O.h 1 cycle A/B/AB RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy/IMM9
u.ROUTADD = u.rx - u.ry
u.ROUTADD = IMM9 - u.ry
u.ROUTADD = u.rx - IMM9
u.ROUTADD = IMM9 - IMM9
Performs a 32-bit integer signed subtraction between operands.
When IMM9 is the operand, the 9 LSBs of the immediate value is used as data.
Data is interpreted in 2's complement and sign extended to 32-bits when IMM9 is the operand.
Result is sent to the 32-bits of u.ROUTADD.
HSUBU32 00010101 u.Z.h, u.O.h 1 cycle A/B/AB RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy/IMM9
u.ROUTADD = u.rx - u.ry
u.ROUTADD = IMM9 - u.ry
u.ROUTADD = u.rx - IMM9
u.ROUTADD = IMM9 - IMM9
Performs a 32-bit integer unsigned subtraction between operands.
When IMM9 is the operand, the 9 LSBs of the immediate value is used as data.
Data is interpreted as 32-bit unsigned positive and filled with ‘0’ when IMM9 is the operand. Result
is sent to the 32-bits of u.ROUTADD.
LMULSL 00011000 u.N.l, u.Z.l, u.O.l 1 cycle A/B/AB/SU RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy/IMM9
u.ROUTMUL.l = u.rx.l * u.ry.l
u.ROUTMUL.l = IMM9 * u.ry.l
u.ROUTMUL.l = u.rx.l * IMM9
u.ROUTMUL.l = IMM9 * IMM9
Perform an integer signed multiplication between the 16 LSB of operands.
When IMM9 is the operand, the 9 LSBs of the immediate value is used as data.
Data is interpreted in 2's complement.
The 16 LSBs of the 32-bit result are sent to u.ROUTMUL.l
LMULSH 00011001 u.N.h, u.Z.h, u.O.h 1 cycle A/B/AB RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy/IMM9
u.ROUTMUL.h = u.rx.l * u.ry.l
u.ROUTMUL.h = IMM9 * u.ry.l
u.ROUTMUL.h = u.rx.l * IMM9
u.ROUTMUL.h = IMM9 * IMM9
Performs an integer signed multiplication between the 16 LSB of operands.
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When IMM9 is the operand, the 9 LSBs of the immediate value is used as data.
Data is interpreted in 2's complement.
The 16 MSBs of the 32-bit result is sent to u.ROUTMUL.h
LMULUL 00011010 u.Z.l, u.O.l 1 cycle A/B/AB/SU RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy/IMM9
u.ROUTMUL.l = u.rx.l * u.ry.l
u.ROUTMUL.l = IMM9 * u.ry.l
u.ROUTMUL.l = u.rx.l * IMM9
u.ROUTMUL.l = IMM9 * IMM9
Performs an integer unsigned multiplication between the 16 LSB of operands.
When IMM9 is the operand, the 9 LSBs of the immediate value is used as data.
Data is interpreted as 16-bit unsigned positive.
The 16 LSBs of the 32-bit result is sent to u.ROUTMUL.l
LMULUH 00011011 u.Z.h, u.O.h 1 cycle A/B/AB RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy/IMM9
u.ROUTMUL.h = u.rx.l * u.ry.l
u.ROUTMUL.h = IMM9 * u.ry.l
u.ROUTMUL.h = u.rx.l * IMM9
u.ROUTMUL.h = IMM9 * IMM9
Performs an integer unsigned multiplication between the 16 LSB of operands.
When IMM9 is the operand, the 9 LSBs of the immediate value is used as data.
Data is interpreted as 16-bit unsigned positive.
The 16 MSBs of the 32-bit result is sent to u.ROUTMUL.h
HMULSL 00011100 u.N.l, u.Z.l, u.O.l 1 cycle A/B/AB RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy/IMM9
u.ROUTMUL.l = u.rx.h * u.ry.h
u.ROUTMUL.l = IMM9 * u.ry.h
u.ROUTMUL.l = u.rx.h * IMM9
u.ROUTMUL.l = IMM9 * IMM9
Perform an integer signed multiplication between the 16 MSB of operands.
When IMM9 is the operand, the 9 LSBs of the immediate value is used as data.
Data is interpreted in 2's complement.
The 16 LSBs of the 32-bit result is sent to u.ROUTMUL.l
HMULSH 00011101 u.N.h, u.Z.h, u.O.h 1 cycle A/B/AB RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy/IMM9
u.ROUTMUL.h = u.rx.h * u.ry.h
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u.ROUTMUL.h = IMM9 * u.ry.h
u.ROUTMUL.h = u.rx.h * IMM9
u.ROUTMUL.h = IMM9 * IMM9
Perform an integer signed multiplication between the 16 MSB of operands.
When IMM9 is the operand, the 9 LSBs of the immediate value is used as data.
Data shall be interpreted in 2's complement.
The 16 MSBs of the 32-bit result is sent to u.ROUTMUL.h
HMULUL 00011110 u.Z.l, u.O.l 1 cycle A/B/AB RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy/IMM9
u.ROUTMUL.l = u.rx.h * u.ry.h
u.ROUTMUL.l = IMM9 * u.ry.h
u.ROUTMUL.l = u.rx.h * IMM9
u.ROUTMUL.l = IMM9 * IMM9
Performs an integer unsigned multiplication between the 16 MSB of operands.
When IMM9 is the operand, the 9 LSBs of the immediate value is used as data.
Data is interpreted as 16-bit unsigned positive.
The 16 LSBs of the 32-bit result is sent to u.ROUTMUL.l
HMULUH 00011111 u.Z.h, u.O.h 1 cycle A/B/AB RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy/IMM9
u.ROUTMUL.h = u.rx.h * u.ry.h
u.ROUTMUL.h = IMM9 * u.ry.h
u.ROUTMUL.h = u.rx.h * IMM9
u.ROUTMUL.h = IMM9 * IMM9
Perform an integer unsigned multiplication between the 16 MSB of operands.
When IMM9 is the operand, the 9 LSBs of the immediate value is used as data.
Data is interpreted as 16-bit unsigned positive.
The 16 MSBs of the 32-bit result is sent to u.ROUTMUL.h
LOR 00100000 u.N.l, u.Z.l 1 cycle A/B/AB/SU RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy/IMM9
u.ROUTADD.l = u.rx.l OR u.ry.l
u.ROUTADD.l = IMM9 OR u.ry.l
u.ROUTADD.l = u.rx.l OR IMM9
u.ROUTADD.l = IMM9 OR IMM9
Perform a logical OR operation between the 16 LSB of the operands.
When IMM9 is an operand, the associated 16-bits data is made of the 9 LSBs of the immediate
value, extended with '0'.
The result is sent to the 16 LSB of u.ROUTADD.
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HOR 00100001 u.N.h, u.Z.h 1 cycle A/B/AB RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy/IMM9
u.ROUTADD.h = u.rx.h OR u.ry.h
u.ROUTADD.h = IMM9 OR u.ry.h
u.ROUTADD.h = u.rx.h OR IMM9
u.ROUTADD.h = IMM9 OR IMM9
Perform a logical OR operation between the 16 MSB of the operands.
When IMM9 is an operand, the associated 16-bits data is made of the 9 LSBs of the immediate
value, extended with '0'.
The result is sent to the 16 MSB of u.ROUTADD.
LAND 00101000 u.N.l, u.Z.l 1 cycle A/B/AB/SU RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy/IMM9
u.ROUTADD.l = u.rx.l AND u.ry.l
u.ROUTADD.l = IMM9 AND u.ry.l
u.ROUTADD.l = u.rx.l AND IMM9
u.ROUTADD.l = IMM9 AND IMM9
Perform a logical AND operation between the 16 LSB of the operands.
When IMM9 is an operand, the associated 16-bits data is made of the 9 LSBs of the immediate
value, extended with '0'.
The result is sent to the 16 LSB of u.ROUTADD.
HAND 00101001 u.N.h, u.Z.h 1 cycle A/B/AB RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy/IMM9
u.ROUTADD.h = u.rx.h AND u.ry.h
u.ROUTADD.h = IMM9 AND u.ry.h
u.ROUTADD.h = u.rx.h AND IMM9
u.ROUTADD.h = IMM9 AND IMM9
Perform a logical AND operation between the 16 MSB of the operands.
When IMM9 is an operand, the associated 16-bits data is made of the 9 LSBs of the immediate
value, extended with '0'.
The result is sent to the 16 MSB of u.ROUTADD.
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LCOMPL 00110000 u.N.l, u.Z.l 1 cycle A/B/AB/SU RGPx/ROFFx/RSRx/IMM9 NOT INTERPRETED
u.ROUTADD.l = NOT u.rx.l
u.ROUTADD.l = NOT IMM9
Perform a logical NOT operation on the 16 LSB of u.rx.
When IMM9 is an operand, the associated 16-bits data is made of the 9 LSBs of the immediate
value, extended with '0'.
The result is sent to the 16 LSB of u.ROUTADD.
HCOMPL 00110001 u.N.h, u.Z.h 1 cycle A/B/AB RGPx/ROFFx/RSRx/IMM9 NOT INTERPRETED
u.ROUTADD.h = NOT u.rx.h
u.ROUTADD.h = NOT IMM9
Perform a logical NOT operation on the 16 MSB of u.rx.
When IMM9 is an operand, the associated 16-bits data is made of the 9 LSBs of the immediate
value, extended with '0'.
The result is sent to the 16 MSB of u.ROUTADD.
LCOMPL2 01000000 u.N.l, u.Z.l 1 cycle A/B/AB/SU RGPx/ROFFx/RSRx/IMM9 NOT INTERPRETED
u.ROUTADD.l = NOT u.rx.l + 1
u.ROUTADD.l = NOT IMM9 + 1
Perform an arithmetic inversion on the 16 LSB of u.rx.
When IMM9 is an operand, the associated 16-bits data is made of the 9 LSBs of the immediate
value, extended with '0'.
The result is sent to the 16 LSB of u.ROUTADD.
HCOMPL2 01000001 u.N.h, u.Z.h 1 cycle A/B/AB/SU RGPx/ROFFx/RSRx/IMM9 NOT INTERPRETED
u.ROUTADD.h = NOT u.rx.h + 1
u.ROUTADD.h = NOT IMM9 + 1
Perform an arithmetic inversion on the 16 MSB of u.rx.
When IMM9 is an operand, the associated 16-bits data is made of the 9 LSBs of the immediate
value, extended with '0'.
The result is sent to the 16 MSB of u.ROUTADD.
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SHIFTA 01001000 u.N.l, u.Z.l ,u.N.h,
u.Z.h 1 cycle A/B/AB/SU RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy/IMM9
u.ROUTADD = sha(u.rx, u.ry)
u.ROUTADD = sha(u.rx, IMM9)
u.ROUTADD = sha(IMM9, u.ry)
u.ROUTADD = sha(IMM9, IMM9)
Perform an arithmetic shift by N places on u.rx or IMM9.
When IMM9 is used for the left operand, the 9 LSBs is extended to 32-bit (if u=a or b) or 16-bits (if u=su) and
according to 2's complement convention
N ranges from -32 to 32 if u=a orBand from -16 to 16 if u=su
In case of right shift, arithmetic shift implies that filling is done with MSB
In case of left shift, arithmetic shift implies that filling is done with '0'
When u.ry.m is the right operand, the 7 LSBs (if u=a or b) or 6 LSBs(if u=su) is used to determine the shift
value N
When IMM9 is the right operand, the 7 LSBs (if u=a or b) or 6 LSBs(if u=su) is used to determine the shift value
N
N is interpreted as a 2's complement value from the extracted LSBs and is saturated to -32 to 32 (if u = a or b)
or -16 to 16 (if u=su) ) before being processed.
If N is positive, the shift is performed N places to the right
If N is negative, the shift is performed abs(N) places to the left
The 32-bit (if u=a or b) or 16-bit (if u=su) result is stored in u.ROUTADD.
SHIFTZERO 01001001 u.N.l, u.Z.l ,u.N.h, u.Z.h 1 cycle A/B/AB/SU RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy/IMM9
u.ROUTADD = shl(u.rx, u.ry)
u.ROUTADD = shl(u.rx, IMM9)
u.ROUTADD = shl(IMM9, u.ry)
u.ROUTADD = shl(IMM9, IMM9)
Perform a logical-0 shift by N places on u.rx or IMM9.
When IMM9 is used for the left operand, the 9 LSBs is extended to 32-bit (if u=a or b) or 16-bits (if u=su) and
according to 2's complement convention.
N ranges from -32 to 32 if u=a or B and from -16 to 16 if u=su
In case of right or left shift, logical-0 shift implies that filling is done with '0'
When u.ry.m is the right operand, the 7 LSBs (if u=a or b) or 6 LSBs (if u=su) is used to determine the shift
value N
When IMM9 is the right operand, the 7 LSBs (if u=a or b) or 6 LSBs (if u=su) is used to determine the shift
value
N is interpreted as a 2's complement value from the extracted LSBs and is saturated to -32 to 32 (if u = a or b)
or -16 to 16 (if u=su) ) before being processed
If N is positive, the shift is performed N places to the right
If N is negative, the shift is performed abs(N) places to the left
The 32-bit (if u=a or b) or 16-bit (if u=su) result is stored in u.ROUTADD.
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SHIFTONE 01001011 u.N.l, u.Z.l ,u.N.h, u.Z.h 1 cycle A/B/AB/SU RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy/IMM9
u.ROUTADD = shl(u.rx, u.ry)
u.ROUTADD = shl(u.rx, IMM9)
u.ROUTADD = shl(IMM9, u.ry)
u.ROUTADD = shl(IMM9, IMM9)
Perform a logical-1 shift by N places on u.rx or IMM9.
When IMM9 is used for the left operand, the 9 LSBs is extended to 32-bit (if u=a or b) or 16-bits (if u=su) and
according to 2's complement convention.
N ranges from -32 to 32 if u=a or B and from -16 to 16 if u=su
In case of right or left shift, logical-1 shift implies that filling is done with '1'
When u.ry.m is the right operand, the 7 LSBs (if u=a or b) or 6 LSBs(if u=su) is used to determine the shift
value N
When IMM9 is the right operand, the 7 LSBs (if u=a or b) or 6 LSBs(if u=su) is used to determine the shift value
N
N is interpreted as a 2's complement value from the extracted LSBs and is saturated to -32 to 32 (if u = a or b)
or -16 to 16 (if u=su) before being processed
If N is positive, the shift is performed N places to the right
If N is negative, the shift is performed abs(N) places to the left
The 32-bit (if u=a or b) or 16-bit (if u=su) result is stored in u.ROUTADD.
7.1.6.2 REGISTER TRANSFER AND NO REGISTER INSTRUCTIONS
The Register Transfer and No Register instructions is as followed
MOVATO 10000001 - 1 cycle A/B/AB/SU RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy
u.ry = a.rx
u.ry = IMM9
Performs a data transfer from a register in a unit to another unit.
Content of a.rx is copied to u.ry. If u.ry belongs to SU unit, data is truncated to its 16 LSB.
When IMM9 is used, the 9 LSBs of the immediate value is used as data. Data is interpreted in 2's
complement and extended to the 16 LSBs. The 16 MSBs are padded with '0'
MOVBTO 10000010 - 1 cycle A/B/AB/SU RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy
u.ry = b.rx
u.ry = IMM9
Performs a data transfer from a register in B unit to another unit.
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Contents of b.rx is copied to u.ry. If u.ry belongs to SU unit, data is truncated to its 16 LSB.
When IMM9 is used, the 9 LSBs of the immediate value is used as data. Data is interpreted in 2's
complement and extended to the 16 LSBs. The 16 MSBs are padded with '0'
MOVSUTO 10000011 - 1 cycle A/B/AB/SU RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy
u.ry= su.rx
u.ry = IMM9
Perform a data transfer from a register in SU unit to another unit.
if rx is not RMEM or ROUTAPB, contents of su.rx is copied to the 16 LSBs of u.ry and the 16 MSBs is
padded with '0'.
if rx is RMEM or ROUTAPB, the full 32-bit data is transferred to u.ry, except if destination register is
in su. In that case, the data will be truncated to the 16 LSBs.
When IMM9 is used, the 9 LSBs of the immediate value is used as data. Data is interpreted in 2's
complement and extended to the 16 LSBs. The 16 MSBs are padded with '0'.
MOV 10000100 - 1 cycle A/B/AB/SU RGPx/ROFFx/RSRx/IMM9 RGPy/ROFFy/RSRy
u.ry = u.rx
u.ry = IMM9
Performs a data transfer from a register of one unit to the same unit.
Contents of u.rx is copied to u.ry
if u.rx is RMEM or ROUTAPB, data is truncated to its 16 LSB.
When IMM9 is used, the 9 LSBs of the immediate value is used as data. Data is interpreted in 2's
complement and extended to the 16 LSBs. The 16 MSBs is padded with '0'.
MOVIND 10001000 - 2 cycles A/B/SU RGPx/ROFFx RGPy/ROFFy
u.ry = ind(u.rx)
Performs an indirect-addressing data transfer from a register of one unit to the same unit.
The first clock cycle read the 9 LSBs (if u=a or b) or 5 LSBs (if u=su) of the content of u.rx and
interpret it as a 9-bit (if u=a or b) or 5-bit (if u=su) absolute address value
On the second clock cycle, the RGPx register mapped to the corresponding 9-bit or 5-bit address is
copied to u.ry.
Note: on the second cycle, no instruction involving registers of the concerned unit should be
executed
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MOVOFF2ABS 10001100 - 1 cycle A/B/SU ROFFx RGPy/ROFFy/RSRy
u.ry = o2a(u.rx)
Performs the conversion of the offset address associated to u.rx into its absolute address and stores
the computed value into u.ry.
The operand is restricted to offset registers ROFFx.
The instruction is implemented by adding the content of the stack pointer of unit u with the offset
address of u.rx
SWAP 10001110 - 1 cycle A/B RGPx/ROFFx RGPy/ROFFy
b.ry = a.rx; a.rx = b.ry(if u=a)
a.ry = b.rx; b.rx = a.ry (if u=b)
Perform a simultaneous swap between registers belonging to a and B units
Contents of two registers (u.rx and u.ry) in units a and B is exchanged.
The activity code supports only two codes - 01 (a unit) or 10 (b unit) - specifying to which unit is
assigned register u.rx.
WRITEAPB 10100000 - 1 cycle A/B/SU RGPx/ROFFx RGPy/ROFFy/RSRy
APB address = u.rx; APB data= u.ry
Request a data write on the APB bus at address u.rx and with data u.ry
One cycle is needed to send the address and data to the APB master interface
The next clock cycle is dedicated to any other instruction except an APB transfer
The data write is completed 3 cycles after the execution of WRITEAPB
READAPB 10100001 - 1 cycle A/B/SU RGPx/ROFFx NOT INTERPRETED
APB address = u.rx
Request a data read on the APB bus at address u.rx.
One cycle is needed to send the address to the APB master interface
The next clock cycle can be dedicated to any other instruction except an APB transfer.
The read data is available 3 cycles after the execution of READAPB and is stored in SU register
ROUTAPB
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NOP 11000000 - 1 cycle SU NOT INTERPRETED NOT INTERPRETED
none
The nop instruction does nothing (as its name implies).
CONDOR 11000100 - 1 cycle SU IMM9 IMM9
mask = applies function [f_mask(first operand IMM9) OR f_mask (second operand IMM9)] between
condition codes of selected unit
Update the mask bit as the OR between boolean functions selected by values of IMM9 (11-bit
value) in field#3 and field#4
if set, mask prevents execution of next instruction (and associated immediate if applicable)
if not set, next instruction is executed normally.
Interpret the following boolean function according to IMM9x binary
IMM9 bits 10 to 9 are reserved
IMM9 bit 8 not used
IMM9 bits 7 to 6 select either SU ("00"), A ("01") or B ("10") unit.
IMM9 bits 5 to 4 select either f ("00" or "11"), h ("10") or l ("01") flags.
IMM9 bits 3 to 0 select the boolean function (f_mask) according to the table below.
Following table indicates for each operand the possible operations:
For each operand, if IMM9 value does not correspond to any operation given in the previous table,
boolean test is false.
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CONDOR IMM [3..0]
(binary)
Operation Boolean test IMM[5,4]=00 or 11
Boolean test IMM[5,4]=10
Boolean test IMM[5,4]=01
0000 True on Equal u.Z.f (if unit=A or B) false (otherwise)
u.Z.h u.Z.l
0001 True on Less or Equal u.Z.f OR u.N.f (if unit=A or B) false (otherwise)
u.Z.h OR (u.N.h XOR u.O.h) (*)
u.Z.l OR (u.N.l XOR u.O.l) (*)
0010 True on Less u.N.f (if unit=A or B) false (otherwise)
u.N.h XOR u.O.h (*) u.N.l XOR u.O.l (*)
0011 True on Less or Equal (Unsigned only)
false u.O.h OR u.Z.h (*) u.O.l OR u.Z.l (*)
0100 True on Carry out Set false false u.C.l
0101 True on Negative u.N.f(if unit=A or B) false (otherwise)
u.N.h u.N.l
0110 True on Overflow Set false u.O.h u.O.l
0111 True on Not Equal NOT (u.Z.f) (if unit=A or B) false (otherwise)
NOT (u.Z.h NOT (u.Z.l
1000 True on Greater NOT (u.Z.f OR u.N.f) (if unit=A or B) false (otherwise)
NOT (u.Z.h OR (u.N.h XOR u.O.h)) (*)
NOT (u.Z.l OR (u.N.l XOR u.O.l)) (*)
1001 True on Greater or Equal
NOT (u.N.f) (if unit=A or B) false (otherwise)
NOT (u.N.h XOR u.O.h) (*) NOT (u.N.l XOR u.O.l) (*)
1010 True on Greater (Unsigned only)
false NOT (u.O.h OR u.Z.h) (*) NOT (u.O.l OR u.Z.l) (*)
1011 True on Carry out Clear (Unsigned: Greater than or Equal)
false false NOT (u.C.l)
1100 True on Positive Not (u.N.f) (if unit=A or B) false (otherwise)
NOT (u.N.h) NOT (u.N.l)
1101 True on Overflow Clear false NOT (u.O.h) NOT (u.O.l)
1110 None: always false false false false
(*) if FIXSAT bit is set (saturating mode, (cfr CLRS-4562)), Overflow is not taken into account.
CONDAND 11000101 - 1 cycle SU IMM9 IMM9
mask = applies function [f_mask(first operand IMM9) AND f_mask (second operand IMM9)]
between condition codes of selected unit
Update the mask bit as the AND between boolean functions selected by values of IMM9 (11-bit
value) in field#3 and field#4
if set, mask prevents execution of next instruction (and associated immediate if applicable)
if not set, next instruction is executed normally.
Interpret the following boolean function according to IMM9x binary
IMM9 bits 10 to 9 are reserved
IMM9 bit 8 not used
IMM9 bits 7 to 6 select either SU ("00"), A ("01") or B ("10") unit.
IMM9 bits 5 to 4 select either f ("00" or "11"), h ("10") or l ("01") flags.
IMM9 bits 3 to 0 select the boolean function f_mask according to the table below.
The following table indicates for each operand the possible operations:
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CONDAND For each operand, if IMM9 value does not correspond to any operation given in the previous table,
boolean test is true. IMM [3..0]
(binary)
Operation Boolean test IMM[5,4]=00 or 11
Boolean test IMM[5,4]=10
Boolean test IMM[5,4]=01
0000 True on Equal u.Z.f (if unit=A or B) true (otherwise)
u.Z.h u.Z.l
0001 True on Less or Equal u.Z.f OR u.N.f (if unit=A or B) true (otherwise)
u.Z.h OR (u.N.h XOR u.O.h) (*)
u.Z.l OR (u.N.l XOR u.O.l) (*)
0010 True on Less u.N.f (if unit=A or B) true (otherwise)
u.N.h XOR u.O.h (*) u.N.l XOR u.O.l (*)
0011 True on Less or Equal (Unsigned only)
true u.O.h OR u.Z.h (*) u.O.l OR u.Z.l (*)
0100 True on Carry out Set true true u.C.l
0101 True on Negative u.N.f (if unit=A or B) true (otherwise)
u.N.h u.N.l
0110 True on Overflow Set True u.O.h u.O.l
0111 True on Not Equal NOT (u.Z.f) (if unit=A or B) true (otherwise)
NOT (u.Z.h NOT (u.Z.l
1000 True on Greater NOT (u.Z.f OR u.N.f) (if unit=A or B) true (otherwise)
NOT (u.Z.h OR (u.N.h XOR u.O.h)) (*)
NOT (u.Z.l OR (u.N.l XOR u.O.l)) (*)
1001 True on Greater or Equal
NOT (u.N.f) (if unit=A or B) true (otherwise)
NOT (u.N.h XOR u.O.h) (*) NOT (u.N.l XOR u.O.l) (*)
1010 True on Greater (Unsigned only)
true NOT ( u.O.h OR u.Z.h) (*) NOT (u.O.l OR u.Z.l) (*)
1011 True on Carry out Clear (Unsigned: Greater than or Equal)
true true NOT (u.C.l)
1100 True on Positive Not (u.N.f) (if unit=A or B) true (otherwise)
NOT (u.N.h) NOT (u.N.l)
1101 True on Overflow Clear true NOT (u.O.h) NOT (u.O.l)
1110 None: always true true true true
(*) if FIXSAT bit is set (saturating mode, (cfr CLRS-4562)), Overflow is not taken into account.
WAITIC 11100000 - variable SU IMM9 IMM9
Stop CPU normal operation until one of TIMERS output ticks equals '1'.
The selection of timer ticks is made through the 5 LSBs of the two immediate occupying field f#3
and #4.
Bits 4 to 0 of the immediate in field#3 respectively point to TIMER9, TIMER8,...,TIMER5
Bits 4 to 0 of the immediate in field#4 respectively point to TIMER4, TIMER3,...,TIMER0
To select a given timer, the bit must be set to '1'; otherwise, the timer tick is not taken into account
The unused bits of the two immediate are not interpreted.
Instruction that permits to synchronise the software with the hardware (PWM, ADC's start-of-
conversion…).
When instruction is executed, the CLP pipeline and the Program Counter is stalled.
When one of the selected TIMERS output ticks, the pipeline is restarted. The instruction following
the WAITIC and stalled in the decode stage is then executed.
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WAITIC Note:
The user must wait that multicycles instructions are finished before executing a WAITIC instruction if a fully predictable behaviour is needed.
The WAITIC instruction does not stall multicycle instructions, including APB accesses.
SWRST 11110000 - 1 cycle SU NOT INTERPRETED NOT INTERPRETED
Perform a software restart
Instruction that commands a software restart that is handled by the boot manager as described and
triggers the reloading of the 1st boot descriptor.
The instruction does not reset the CPU context: the restart procedure explained in section 27.3
apply
The execution can be enabled or disabled via the SU register RSWREST.
If SWRST is disabled, a nop instruction is executed instead.
7.1.7 APB AND PROGRAM MEMORY MANAGEMENT
7.1.7.1 OVERVIEW
Each CPU of the CLP has a program memory space and a data memory space. Both are organised
with a "Super-Harvard"-like architecture. Its data memory is located in the various register file
located in the A, B and SU units and is accessible via 2 dedicated ports which are directly controlled
by the two operand fields of a CLP instruction.
Its program memory is an on-chip SRAM whose address is managed by the RPC register and whose
data bus is connected to the RMEM register. The program memory may also be used to handle data
(despite its low performance compared to registers file).
The peripherals memory space is accessed through an APB bus which is controlled through
dedicated instructions (WRITEAPB and READAPB). The on-chip SRAM, which is used for the program
memory, is a dual-port memory. One port is connected to the CPU pipeline management (to
perform instruction fetches) and the other port is connected to the APB bus. The on-chip SRAM
consequently also allows its use as an external data memory (in addition to the file registers) without
interfering the program flow.
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7.1.7.2 THE IMMEDIATE READ
This transfer is used when a 32-bit immediate data (noted IMM32) has to be read from the program
memory. RMEM is the register to be used by an instruction to access this data. This register is also
exclusively intended for that purpose. The immediate read can be used to load a register or to
perform an "on-the-fly" operation with another operand.
The first case is called “Immediate operation” transfer
In that case we have an arithmetic operation with the "on-the-fly" operand sourced from RMEM.
The code template to use is the following
Lxx SU rsrc rmem
LL
x
Where:
Lxx: any arithmetic instruction with RMEM as a source.
LL: a 32-bit immediate (IMM32) holding the desired value
The effect is that Lxx instruction will be executed with value LL as operand. Depending on the
instruction, only a part of LL may be used
Note that:
the pipeline is never stalled
a NOP is introduced in the decode stage to avoid executing the content of LL
The program counter incrementation is not stopped
RMEM can never be used on both operands. Otherwise, an invalid operand will be detected
in RSTATCNTSU
The first case is called “Immediate load” transfer
This case is used when the data to be stored is contained in the program flow and loaded in a
destination register. The code template to use is the following
movsuto u rmem rdst
LL
x
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Where:
"mov SU ..": any mov instruction with RMEM as a source.
LL: a 32-bit immediate (IMM32) holding the desired value
u: any unit
The effect is that rdst register will be loaded with value LL. Depending on the mov operation
instruction, only a part of LL may be used
Specific actions:
The pipeline is not stalled but a NOP is introduced in the decode stage to avoid executing the content of LL
The program counter incrementation is not stopped during the transfer
RMEM can never be used on both operands. Otherwise, an invalid operand will be detected in RSTATCNTSU
7.1.7.3 BRANCHES
These transfers are used when a jump has to be carried out in the code execution. RPC is the register
to be used in such cases to access the desired program memory address. Note that writing to this
register is exclusively intended for that purpose.
The first case is called “direct branch” transfer . It is used when a conditional operation must be
performed. The condition is firstly computed with a CONDAND or CONDOR instruction which sets
the mask bit accordingly. If the mask bit is set, the next operation is masked and interpreted as a
nop. If the mask bit is not set, the next operation is executed normally. These types of transfer can
be mixed with branches thus providing conditional branches capability.
The template for the "direct branch" is:
X
MOV SU rbrch rpc
Y
Z
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Where :
x, y, z: are any instruction. x and y are always executed. Z does NOT
rbrch: the general register that holds the branch address
The effect is that a jump to the address hold by register rbrch will be made.
Note that:
The pipeline is not stalled
The instruction y, following the instruction commanding the branch, is always executed.
The first case is called “immediate branch” transfer. It works similarly to the direct branch except
that the jump address is given by an immediate value.
The template for the "direct branch" is:
X
MOV SU rmem rpc
LL
Z
Where :
x, y, z: are any instruction. x and y are always executed. Z does NOT
LL: the 32-bit word holding the value of the immediate address
rbrch: the general register that holds the branch address
The effect is that a jump to address LL will be made. Only the 15 LSBs will be taken into account
Note that:
The pipeline is not stalled
a NOP is introduced to avoid executing the content of the literal LL
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7.1.7.4 CONDITIONAL OPERATIONS
These transfers are used when an instruction must be conditionally masked. The bits mask is the one
that is generated through the CONDOR or CONDAND instruction. When the mask bit is set (='1'), the
instruction that has to be executed on the next clock cycle is masked by interpreting it as a NOP. The
mixing with an immediate load is possible. In that case, the immediate value is also masked. The
templates below will be depicted for branches. The extension to any instruction is straightforward.
The template for the "direct conditional branch" is:
x
condxx xx
mov SU rbrch rpc
y
The template for the " immediate direct conditional branch " is:
x
CONDxx xx
mov SU rmem rpc
LL
Where:
"CONDxx": CONDOR or CONDAND
rbrch: the general register in SU that holds the branch address.
x, y: any instruction. They will be executed whatever is the result of the test.
LL: is the 32-bit word holding the immediate address. Value is replaced by NOP if condxx sets mask bit
When WRITEAPB or READAPB instructions are executed, the APB bus is automatically solicited. This
bus is a two-clock cycles protocol composed of a 1st cycle called SETUP followed by a 2nd cycle
called ENABLE. These two APB cycles will be also shown in the description below to give the full
understanding of how the software interacts with the APB cycles.
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7.1.7.5 APB DATA READ
These transfers are used when a data has to be transferred to the peripheral unit through the APB bus. WRITEAPB instruction has to be used in that case. The operands of the instruction contain both the targeted address and the source data. A mix of this transfer with other transfers is possible.
A peripheral read is performed on the APB bus with the following template:
readapb u raddr
x
y
z (=movsuto u routapb rdst)
Where:
x,y any instruction.
z optional
u a or B or SU (ab not allowed)
raddr register (located in a, B or su) that holds peripheral's register address
The effect will be that ROUTAPB register will be updated with value located at 16-bit APB address
held in register raddr. Warning: rsrc and raddr must belong to the same unit
Note that:
The first clock cycle sends to the APB master interface the required APB address. No APB access is initiated on the bus which is still in IDLE mode (or ENABLE if another APB transaction is being completed)
The second clock cycle initiates the SETUP cycle on the APB bus. In the mean time, the CPU is free to execute any other instruction except another APB read or write transfer.
The third clock cycle initiates the ENABLE clock cycle on the APB bus and is dedicated to transfer the data from the selected peripheral to ROUTAPB register. The CPU is also free to execute any other instruction INCLUDING an APB read or write transfer.
The fourth clock cycle is intended to copy the read data to the destination register. This instruction is optional and is not mandatory to perform the APB read
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7.1.7.6 APB DATA WRITE
These transfers are used when a data has to be transferred to the peripheral unit through the APB bus. WRITEAPB instruction has to be used in that case. The operands of the instruction contain both the targeted address and the source data. . A mix of this transfer with other transfers is possible
A peripheral data write is performed on the APB bus with the following template:
WRITEAPB u raddr rdst
x
y
z
Where:
x,y,z: any instruction.
u: A or B or SU (SU not allowed)
raddr: register that holds the peripheral's register address
rdst destination register (located in a, B or SU)
The effect will be that 16-bit APB address held in register raddr will be updated with 32-bit value loaded in rdst
Note that :
The first clock cycle sends to the APB master interface the required APB address and APB data. No APB access is initiated on the bus which is still in IDLE mode (or ENABLE if another APB transaction is being completed)
The second clock cycle initiates the SETUP cycle on the APB bus. In the mean time, the CPU is free to execute any other instruction except another APB read or write transfer.
The third clock cycle initiates the ENABLE clock cycle on the APB bus and is dedicated to transfer the data to the selected peripheral. The CPU is also free to execute any other instruction including another APB read or write transfer.
The fourth cycle is intended to any instruction
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7.1.7.7 INDIRECT BRANCHES
These transfers are used when a jump must be performed to an address whose value is in the program memory. The address is thus not accessed by reading an SU register or in an immediate but rather by reading it by an APB read. This transfer also corresponds to another mixing of the various transfers
The template to use is the following:
READAPB u raddr
x
y
mov SU routapb rpc
z
…
t
Where :
raddr: the SU register that holds the APB address.
x,y,z,t: any instruction.
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7.2 DIRECT MEMORY ACCESS (DMA)
The DMA function provides a mean to automatically exchange application data between a given CPU
and the various peripherals. The purpose of this function is to off-load the software of a number of
operations involving APB accesses. It can be very useful for applications having tight real-time
constraints and a high number of APB transactions from/to fixed addresses. An ADC sample reading
is one example. PWM duty cycles update is another.
Each CPU has its own DMA unit. This one has full access in read and write to the RD0 to RDA31 DMA
registers of units A and B. The registers can be accessed at any time. It is up to the user to correctly
update these DMA registers according to DMA descriptors which have been programmed.
The DMA unit will have the following topology:
DMARD0 to RD31
(unit A and B)
A
P
BREQ
XCHG
RAM
Other APB
peripherals
APB
MANAGER
CPU
(SW)
REQ
(via
WRITEAPB/
READAPB)
ACK
TIMERx
DMA can be enabled/disabled through a dedicated bit in RCONF configuration register . The DMA is
triggered with one of the CLP timers whose source is programmed through RCONF register. The
objective is to synchronise DMA operations with the software that is running on the CPU, based on
time slots sequenced by the same timer or another whose timing is derived from the CPU one. This
allows ensuring that DMA registers which will or have been updated do not collide with the software
that will make use of these ones.
The DMA performs the desired operations according to the DMA 32-bit descriptors that are located
in the XCHG RAM which is connected to the given CPU. The first descriptor is located at APB address
0x4000. Each time a descriptor is read, the DMA immediately performs the requested operation.
When the transfer is completed, the next DMA descriptor, located at the next address, is read and so
on. The figure below describes the DMA descriptor supported values.
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XXXXX X XXXXXXXXXXXXXXXX XX
31 27 26 10 1 0
F#1 F#2 F#3 F#4
FIELD WIDTH VALUE
F#1 5-bits00000 (=RD0), 00001 (=RD1),...
1111 (=RD31)
F#2 1-bit 0=unit A, 1=unit B
F#3 16-bits 16-bit APB address
F#4 2-bits 00= EOD; 01=C2P;10=P2C; 11=EOT
25
00000000
29
DESCRIPTION
DMA REGISTER ADDRESS
FPU Unit source
APB address
DMA COMMAND
Figure 10: DMA descriptor values
When an EOT command is read, the DMA waits for the next timer tick before reading the next descriptor at the next address.
When an EOD (end-of-descriptor) command is read, the descriptor address pointer is reset to 0x4000 and the DMA waits for the occurrence of the next programmed tick.
When a C2P (CPU-to-peripheral) command is read, the DMA reads the required RDx (x=0...31) CPU register from the desired unit then writes the values to the desired APB address bus.
When a P2C (peripheral-to-CPU) command is read, the DMA performs a read at the desired APB address then writes the value to the desired RDx (x=0...31) CPU register from the desired unit.
The DMA actions are conditioned by the availability of the APB bus on which the CPU has always the
priority to avoid breaking its determinism. If the APB bus is not available and a DMA action related to
the APB bus is requested, the action is postponed until it can be processed without modifying CPU
behaviour.
Note that the XCHG RAM size is the only limit to the number of DMA descriptors that can be used.
The user should thus take care of the fact that the XCHGRAM also may handle information from/to
the MIL-STD-1553/SpaceWire/CAN interfaces. No mechanism exists allowing trapping collisions
occurring between DMA actions and the CPU APB transfers. In addition, it is up to the user to also
guarantee that the DMA has finished working with the current descriptors (i.e. until either EOT or
EOD descriptor has been read) before the next tick of the timer used by the DMA occurs.
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7.3 ON-CHIP COMMUNICATION
7.3.1 OVERVIEW
The two CPUs of the CLP interact with the various peripherals through two APB bus as described in
the picture below
A
P
B
B
U
S
C
P
U
0
APB0
XCHG
DUAL-PORT
RAM
CORE 1
XCHG
DUAL-PORT
RAM
CORE 2
MMU
Peripheral
N
AP
B S
LA
VE
I/F
AP
B
SL
AV
E
I/F
AP
B
SLA
VE
I/FAPB1
APB0
DM
A
AP
B m
ana
ger
CP
U 0
DM
A
AP
B m
ana
ger
M
CP
U 1PROGRAM
AND
DATA
MEMORY
RM
EM
APB1
M
PROGRAM
AND
DATA
MEMORY
RM
EM
Array of
WP and AL bits
APB0
APB1
APB1
APB0
APB
SLAVE
I/F
APB
SLAVE
I/F
A
P
B
B
U
S
C
P
U
1
Figure 11: CPUs and APB busses architecture
The communication is made of:
Two separate AMBA APB busses called APB0 and APB1. Each bus is connected to one CPU, one XCHG RAM, one program memory (which is also available for data) and the various CLP peripherals.
one APB manager for each CPU, handling the AMBA APB protocol as a master (one dedicated per CPU). The access is made by software via the WRITEAPB and READAPB instructions
one DMA unit for each CPU, providing a background programmable mean to transfer data to/from the CPU to/from the peripherals via the CPU APB bus
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various APB slave interfaces, each one locally managing the APB bus for a dedicated peripheral's base address and providing an access to the configuration, status and data memory space. As a reminder, each CPU also contains an on-chip SRAM memory holding the program memory. A dedicated bus is foreseen for that purpose and is controlled by the RMEM register. Only read operations are possible via this register and exclusively for program branches and immediate values reading.
The on-chip SRAM memory is also accessible to read/write application information thus providing, in
addition to the internal file registers, some space for data memory.
For peripherals that can be accessed by CPUs, a static allocation and write protection mechanism is available. A dedicated set of AL and WP bits are defined for that purpose and needs to be programmed during boot thus making a given configuration static when the software is running. The allocation and write protection is either segment-based or register-based
All the CLP peripherals are connected to the two APB busses, except the two XCHG RAMs and the
two PRAM memories which are connected to only one APB bus:
The INTERCOM RAM has one port connected to one APB0 bus while the other is connected to APB1
The XCHGRAM0 is connected to APB0
The XCHGRAM1 is connected to APB1
The PRAM0 is connected to APB0
The PRAM1 is connected to APB1
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7.3.2 ADDRESS ALLOCATION
The address allocation between the CPU0 and CPU1 as well as the memory protection mechanism is
handled through an array of WP (Write Protection) and AL (address allocation) bits which are specific
to each peripheral. These bits are programmed once during the boot thus being static during the CLP
operation. After the boot, any attempt to modify the state of AL/WP bits is therefore not taken into
account.
Following table describes for each APB peripheral the WP/AL capability:
I
Table 31: WP/AL table
(*) Registers of this peripheral are only modifiable during the boot sequence. No WP/AL mechanism for these
registers.
(**) No WP/AL mechanism for this peripheral
(***) No AL mechanism for this peripheral
(****) A single segment exists for this peripheral.
Details about segment based/register based concept are given in §7.3.4.
APB
PERIPHERAL
WP/AL TYPE
SPI0 SEGMENT-BASED (****)
SPI1 SEGMENT-BASED (****)
I2C REGISTER-BASED
CRC UNIT REGISTER-BASED
TIMERS REGISTER-BASED
UART REGISTER-BASED
GPIO REGISTER-BASED
PWM REGISTER-BASED
ADC INTERFACE REGISTER-BASED
WAVEFORM GENERATOR REGISTER-BASED
SPACEWIRE #0 SEGMENT-BASED (****)
SPACEWIRE #1 SEGMENT-BASED (****)
CAN SEGMENT-BASED (****)
MIL-STD-1553 RT SEGMENT-BASED (****)
MMU REGISTER-BASED
INTERCOM RAM (low addresses) SEGMENT-BASED
INTERCOM RAM (high addresses) SEGMENT-BASED
XCHG RAM N/A (**)
BOOT DESCRIPTORS TABLE REGISTER-BASED
IOMUX TABLE N/A (*)
CLOCK AND RESET CONTROL N/A (*)
SCRUBBING AND SEU PROTECTION CONTROL REGISTER-BASED
NOMINAL OR CONFIGURATION MODE N/A (*)
PROGRAM MEMORY (low addresses) SEGMENT-BASED (***)
PROGRAM MEMORY… SEGMENT-BASED (***)
PROGRAM MEMORY (high addresses) SEGMENT-BASED (***)
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WP bit determines if the corresponding register is write protected or not.
if write protection is disabled (WP=0), AL bit determines if the corresponding register or segment is write-allocated to either CPU0 or CPU1.
Details about behaviour on APB read or write access according to WP/AL configuration are given in
§7.4.2.
During the boot, the I2C, IOMUX and all segment based peripherals except PRAM are only accessible
from APB0 to configure WP/AL bits or initialise registers. PRAM and all register based peripherals
except I2C and IOMUX are accessible from both APB busses.
7.3.3 APB MODE SWITCH
The APB0 bus dedicates the address 0x6400 to control the APB mode of all APB peripherals. Such
address is called "APB Mode Switch" and controls how an APB write is processed
When CONFIGURATION mode is set by writing value by writing value 0x55555555, all APB peripherals having a WP/AL mechanism (see §7.3.2) disable the access to their respective APB register or memory and make the WP/AL bits available for read and write. APB peripherals that have no WP/AL mechanism (e.g. XCHGRAMs) keep the access to their respective APB register or memory. The WP and AL bits are mapped to the 2 LSBs of the read or written value as described in the following table.
APB
DATA
AL/WP
BIT
EFFECT COMMENT
[1 WP 1 = ENABLES write protection on APB register or
whole segment range.
0 = DISABLES write protection on APB register or
whole segment range
After CLP reset, WP=0
[0 AL 0 = allocates APB register or segment to CPU0
1 = allocates APB register or segment to CPU1
After CLP reset, AL=0
If WP=1, AL has not effect
Table 32: WP/AL definition
When NOMINAL mode is set by writing any other value different from 0x55555555, all APB peripherals behave in line with the state of WP/AL bits.
The NOMINAL/CONFIGURATION mode of the APB bus may be checked by performing a read to the APB mode switch address. Value 0x0000000 is read if the APB is in NOMINAL mode, value 0x55555555 is read in CONFIGURATION mode.
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7.3.4 PERIPHERAL ADDRESS PARTITIONING
The AL/WP bits are accessible, for each APB peripheral, on:
a register-basis, meaning that the mechanisms apply to each individual register composing the APB peripheral.
a segment-basis, meaning that the mechanisms apply to a predefined set of registers composing the APB peripheral.
For register-based APB peripherals, the write protection state of each register is maintained at the
same APB address than the given register and exclusively when the APB peripheral is in
CONFIGURATION mode.
For segment-based APB peripheral, the write protection state of the whole segment is maintained at
any APB address within the segment and exclusively when the APB peripheral is in CONFIGURATION
mode.
7.3.5 SPECIAL BEHAVIOURS
The APB peripheral behaves in the following way when addresses that do not use the full 32-bits
data space of a given APB address is accessed:
any writing to the associated non-used bit(s) is discarded for these specific bit(s)
any reading to the associated non-used bit(s), returns the associated reset value(s) (cfr
values detailed in APB register description in Annex 0).
The APB peripheral behaves in the following way when a non-valid value is written in the field of a
given APB address:
any writing to the associated field is locally REPLACED by the APB peripheral by a valid value.
any reading return the value that is REALLY stored by the APB peripheral i.e. not the value written by the SW but the value that is used.
7.3.6 APB ADDRESS MAPPING
The APB address space is 16-bits wide and is organised in two main fields called BAS_AD and OFF_AD as depicted in the figure below.
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BAS_AD15
OFF_AD0
FIELD LENGTH DESCRIPTION
BAS_AD 8-bits Peripheral’s BASe ADdress, made of TY and SEG fields
OFF_AD 8-bits Peripheral’s register OFFset ADdress(relative to BAS_AD)
78
The table below depicts the whole APB addressing existing in the CLP for each APB bus and that can be addresses by a given CPU software
Table 33: APB address table
PADDR
[15:12]
PADDR
[11:8]
APB
PERIPHERAL
DATA CONF STAT
SE
NS
OR
S A
ND
ON
-
BO
AR
D I
NT
ER
FA
CE
S 0x0 0x0 SPI0 X X X
0x0 0x1 SPI1 X X X
0x0 0x2 I2C X X X
0x0 0x3 CRC UNIT X X X
0x0 0x4 TIMERS X X X
0x0 0x5 UART X X X
0x0 0x6 GPIO X X X
0x0 0x7 PWM X X X
0x0 0x8 ADC INTERFACE X X X
0x0 0x9 WAVEFORM GENERATOR X X X
... ... ... UNUSED
MM
U
INT
ER
FA
CE
S 0x1 0x0 SPACEWIRE #0 X X
0x1 0x1 SPACEWIRE #1 X X
0x1 0x2 CAN X X
0x1 0x3 MIL-STD-1553 RT X X
... ... UNUSED
0x1 0x5 MMU X X
... ... ... UNUSED
D AT A
... 0x2 0x0 INTERCOM RAM (low addresses) X
0x2 0x1 INTERCOM RAM (high addresses) X
... ... ... UNUSED
XC
H
G
RA
M 0x4 0x0 XCHG RAM (low addresses+ DMA descriptors) X
... ... XCHG RAM … X
0x5 0xF XCHG RAM (high addresses) X ... ... ... UNUSED
B O O T 0x6 0x0 BOOT DESCRIPTORS TABLE X
0x6 0x1 IOMUX TABLE X 0x6 0x2 CLOCK AND RESET CONTROL X 0x6 0x3 SCRUBBING AND SEU PROTECTION CONTROL X X 0x6 0x4 NOMINAL OR CONFIGURATION MODE X ... ... UNUSED
RA
M 0x8 0x0 PROGRAM MEMORY (low addresses) X
... ... PROGRAM MEMORY… X
0xF 0xF PROGRAM MEMORY (high addresses) X
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7.4 FAULT TOLERANCE
The section describes how the CLP deals with the faults that might be detected via the mechanisms integrated inside the chip
7.4.1 CPU
7.4.1.1 ILLEGAL OPCODE
The CPU executes a NOP (no operation) when an illegal opcode or a legal opcode on an illegal unit (or units) is detected. It also updates the "illegal opcode" field in the RSTATCNT1 counter. In addition, if the error occurs with an immediate read (see 7.1.7.2) or with a conditional branch with an immediate value (see 7.1.7.4) , the related IMM32 value is replaced with a NOP to avoid executing it.
The CPU continues working even if an illegal opcode is encountered.
7.4.1.2 ILLEGAL OPERAND
When two instructions attempt to write a destination register - even if different fields of RFLAG register are updated -, priority is given to the instruction that was initiated first.
When ROUTADD/RFLAGx (in a given unit a or b) and ROUTMUL/RFLAGx (in the same unit a or b) are simultaneously updated, RSTATCNTA or RSTATCNTB register is incremented only once.
The CPU executes a NOP when a legal opcode and unit(s) attempt to read from addresses not authorized by the instruction. It also updates the "illegal operand" field in the counter associated to the targeted unit(s) (i.e. RSTATCNTA, RSTATCNTB or RSTATCNTSU). This field is maximally incremented once per instruction .
The CPU executes a NOP when a legal opcode and unit(s) attempt to write to addresses not authorized by the instruction. It also updates the "illegal operand" field in the counter associated to the targeted unit(s) (i.e. RSTATCNTA, RSTATCNTB or RSTATCNTSU). This field is maximally incremented once per instruction .
When SU unit is used with MOVSUTO, MOV, MOVATO, MOVBTO and MOVOFF2ABS instructions, RMEM can be used as source operand only. Otherwise, an invalid operand will be detected in RSTATCNTSU.
When SU unit is used with any arithmetic instruction, RMEM can be used for only one operand. Otherwise an invalid operand will be detected in RSTATCNTSU.
The CPU continues working even if an illegal operand is encountered.
7.4.1.3 SIMULTANEOUS WRITE
When two instructions attempt to write simultaneously a destination register - even if different fields of RFLAG register are updated -, priority is given to the instruction that was initiated first.
When ROUTADD, RFLAGA, RFLAGB and ROUTMUL are simultaneously updated, RSTATCNTA or RSTATCNTB register is incremented only once.
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The following table is listing all instructions combinations that are forbidden, since they are all leading to a simultaneous write, where second instruction is not executed. “xxx” represents any instruction.
The CPU continues working even if a simultaneous write is encountered, except if a software reset is programmed on simultaneous write event in RSWREST register.
FIRST INSTRUCTION OR SET
OF INSTRUCTIONS
NEXT INSTRUCTION
fadd_ab/fsub_ab/fmul_ab fcomp_a/fcomp_b/fcomp_ab/
intof_a/intof_b/intof_ab/
ladds_a/ladds_b/ladds_ab/
laddu_a/laddu_b/laddu_ab/
hadds_a/hadds_b/hadds_ab/
haddu_a/haddu_b/haddu_ab/
hadds32_a/hadds32_b/hadds32_ab/
haddu32_a/haddu32_b/haddu32_ab/
lsubs_a/lsubs_b/lsubs_ab/
lsubu_a/lsubu_b/lsubu_ab/
hsubs_a/hsubs_b/hsubs_ab/
hsubu_a/hsubu_b/hsubu_ab/
hsubs32_a/hsubs32_b/hsubs32_ab/
hsubu32_a/hsubu32_b/hsubu32_ab/
lmulsl_a/lmulsl_b/lmulsl_ab/
lmulsh_a/lmulsh_b/lmulsh_ab/
lmulul_a/lmulul_b/lmulul_ab/
lmuluh_a/lmuluh_b/lmuluh_ab/
hmulsh_a/hmulsh_b/hmulsh_ab/
hmulsl_a/hmulsl_b/hmulsl_ab/
hmulsh_a/hmulsh_b/hmulsh_ab/
hmulul_a/hmulul_b/hmulul_ab/
hmuluh_a/hmuluh_b/hmuluh_ab/
lor_a/lor_b/lor_ab/
hor_a/hor_b/hor_ab/
land_a/land_b/land_ab/
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FIRST INSTRUCTION OR SET
OF INSTRUCTIONS
NEXT INSTRUCTION
hand_a/hand_b/hand_ab/
lcompl_a/lcompl_b/lcompl_ab/
hcompl_a/hcompl_b/hcompl_ab/
lcompl2_a/lcompl2_b/lcompl2_ab/
hcompl2_a/hcompl2_b/hcompl2_ab/
shifta_a/shifta_b/shifta_ab/
shiftzero_a/shiftzero_b/shiftzero_ab/
shiftone_a/shiftone_b/shiftone_ab
fadd_a/fsub_a/fmul_a fcomp_a/fcomp_ab/
intof_a/intof_ab/
ladds_a/ladds_ab/
laddu_a/laddu_ab/
hadds_a/hadds_ab/
haddu_a/haddu_ab/
hadds32_a/hadds32_ab/
haddu32_a/haddu32_ab/
lsubs_a/lsubs_ab/
lsubu_a/lsubu_ab/
hsubs_a/hsubs_ab/
hsubu_a/hsubu_ab/
hsubs32_a/hsubs32_ab/
hsubu32_a/hsubu32_ab/
lmulsl_a/lmulsl_ab/
lmulsh_a/lmulsh_ab/
lmulul_a/lmulul_ab/
lmuluh_a/lmuluh_ab/
hmulsh_a/hmulsh_ab/
hmulsl_a/hmulsl_ab/
hmulsh_a/hmulsh_ab/
hmulul_a/hmulul_ab/
hmuluh_a/hmuluh_ab/
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FIRST INSTRUCTION OR SET
OF INSTRUCTIONS
NEXT INSTRUCTION
lor_a/lor_ab/
hor_a/hor_ab/
land_a/land_ab/
hand_a/hand_ab/
lcompl_a/lcompl_ab/
hcompl_a/hcompl_ab/
lcompl2_a/lcompl2_ab/
hcompl2_a/hcompl2_ab/
shifta_a/shifta_ab/
shiftzero_a/shiftzero_ab/
shiftone_a/shiftone_ab
fadd_b/fsub_b/fmul_b fcomp_b/fcomp_ab/
intof_b/intof_ab/
ladds_b/ladds_ab/
laddu_b/laddu_ab/
hadds_b/hadds_ab/
haddu_b/haddu_ab/
hadds32_b/hadds32_ab/
haddu32_b/haddu32_ab/
lsubs_b/lsubs_ab/
lsubu_b/lsubu_ab/
hsubs_b/hsubs_ab/
hsubu_b/hsubu_ab/
hsubs32_b/hsubs32_ab/
hsubu32_b/hsubu32_ab/
lmulsl_b/lmulsl_ab/
lmulsh_b/lmulsh_ab/
lmulul_b/lmulul_ab/
lmuluh_b/lmuluh_ab/
hmulsh_b/hmulsh_ab/
hmulsl_b/hmulsl_ab/
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FIRST INSTRUCTION OR SET
OF INSTRUCTIONS
NEXT INSTRUCTION
hmulsh_b/hmulsh_ab/
hmulul_b/hmulul_ab/
hmuluh_b/hmuluh_ab/
lor_b/lor_ab/
hor_b/hor_ab/
land_b/land_ab/
hand_b/hand_ab/
lcompl_b/lcompl_ab/
hcompl_b/hcompl_ab/
lcompl2_b/lcompl2_ab/
hcompl2_b/hcompl2_ab/
shifta_b/shifta_ab/
shiftzero_b/shiftzero_ab/
shiftone_b/shiftone_ab
fdiv_ab
xxx
xxx
xxx
xxx
xxx
xxx
xxx
fadd_a/fadd_b/fadd_ab/
fsub_a/fsub_b/fsub_ab/
fmul_a/fmul_b/fmul_ab
fdiv_a
xxx
xxx
xxx
xxx
xxx
xxx
xxx
fadd_a/fadd_ab/
fsub_a/fsub_ab/
fmul_a/fmul_ab/
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FIRST INSTRUCTION OR SET
OF INSTRUCTIONS
NEXT INSTRUCTION
fdiv_b
xxx
xxx
xxx
xxx
xxx
xxx
xxx
fadd_b/ fadd_ab/
fsub_b/fsub_ab/
fmul_b/fmul_ab
fdiv_ab
xxx
xxx
xxx
xxx
xxx
xxx
xxx
xxx
fcomp_a/fcomp_b/fcomp_ab/
intof_a/intof_b/intof_ab/
ladds_a/ladds_b/ladds_ab/
laddu_a/laddu_b/laddu_ab/
hadds_a/hadds_b/hadds_ab/
haddu_a/haddu_b/haddu_ab/
hadds32_a/hadds32_b/hadds32_ab/
haddu32_a/haddu32_b/haddu32_ab/
lsubs_a/lsubs_b/lsubs_ab/
lsubu_a/lsubu_b/lsubu_ab/
hsubs_a/hsubs_b/hsubs_ab/
hsubu_a/hsubu_b/hsubu_ab/
hsubs32_a/hsubs32_b/hsubs32_ab/
hsubu32_a/hsubu32_b/hsubu32_ab/
lmulsl_a/lmulsl_b/lmulsl_ab/
lmulsh_a/lmulsh_b/lmulsh_ab/
lmulul_a/lmulul_b/lmulul_ab/
lmuluh_a/lmuluh_b/lmuluh_ab/
hmulsh_a/hmulsh_b/hmulsh_ab/
hmulsl_a/hmulsl_b/hmulsl_ab/
hmulsh_a/hmulsh_b/hmulsh_ab/
hmulul_a/hmulul_b/hmulul_ab/
hmuluh_a/hmuluh_b/hmuluh_ab/
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FIRST INSTRUCTION OR SET
OF INSTRUCTIONS
NEXT INSTRUCTION
lor_a/lor_b/lor_ab/
hor_a/hor_b/hor_ab/
land_a/land_b/land_ab/
hand_a/hand_b/hand_ab/
lcompl_a/lcompl_b/lcompl_ab/
hcompl_a/hcompl_b/hcompl_ab/
lcompl2_a/lcompl2_b/lcompl2_ab/
hcompl2_a/hcompl2_b/hcompl2_ab/
shifta_a/shifta_b/shifta_ab/
shiftzero_a/shiftzero_b/shiftzero_ab/
shiftone_a/shiftone_b/shiftone_ab
fdiv_a
xxx
xxx
xxx
xxx
xxx
xxx
xxx
xxx
fcomp_a/fcomp_ab/
intof_a/intof_ab/
ladds_a/ladds_ab/
laddu_a/laddu_ab/
hadds_a/hadds_ab/
haddu_a/haddu_ab/
hadds32_a/hadds32_ab/
haddu32_a/haddu32_ab/
lsubs_a/lsubs_ab/
lsubu_a/lsubu_ab/
hsubs_a/hsubs_ab/
hsubu_a/hsubu_ab/
hsubs32_a/hsubs32_ab/
hsubu32_a/hsubu32_ab/
lmulsl_a/lmulsl_ab/
lmulsh_a/lmulsh_ab/
lmulul_a/lmulul_ab/
lmuluh_a/lmuluh_ab/
hmulsh_a/hmulsh_ab/
hmulsl_a/hmulsl_ab/
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FIRST INSTRUCTION OR SET
OF INSTRUCTIONS
NEXT INSTRUCTION
hmulsh_a/hmulsh_ab/
hmulul_a/hmulul_ab/
hmuluh_a/hmuluh_ab/
lor_a/lor_ab/
hor_a/hor_ab/
land_a/land_ab/
hand_a/hand_ab/
lcompl_a/lcompl_ab/
hcompl_a/hcompl_ab/
lcompl2_a/lcompl2_ab/
hcompl2_a/hcompl2_ab/
shifta_a/shifta_ab/
shiftzero_a/shiftzero_ab/
shiftone_a/shiftone_ab/
fdiv_b
xxx
xxx
xxx
xxx
xxx
xxx
xxx
xxx
fcomp_b/fcomp_ab/
intof_b/intof_ab/
ladds_b/ladds_ab/
laddu_b/laddu_ab/
hadds_b/hadds_ab/
haddu_b/haddu_ab/
hadds32_b/hadds32_ab/
haddu32_b/haddu32_ab/
lsubs_b/lsubs_ab/
lsubu_b/lsubu_ab/
hsubs_b/hsubs_ab/
hsubu_b/hsubu_ab/
hsubs32_b/hsubs32_ab/
hsubu32_b/hsubu32_ab/
lmulsl_b/lmulsl_ab/
lmulsh_b/lmulsh_ab/
lmulul_b/lmulul_ab/
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FIRST INSTRUCTION OR SET
OF INSTRUCTIONS
NEXT INSTRUCTION
lmuluh_b/lmuluh_ab/
hmulsh_b/hmulsh_ab/
hmulsl_b/hmulsl_ab/
hmulsh_b/hmulsh_ab/
hmulul_b/hmulul_ab/
hmuluh_b/hmuluh_ab/
lor_b/lor_ab/
hor_b/hor_ab/
land_b/land_ab/
hand_b/hand_ab/
lcompl_b/lcompl_ab/
hcompl_b/hcompl_ab/
lcompl2_b/lcompl2_ab/
hcompl2_b/hcompl2_ab/
shifta_b/shifta_ab/
shiftzero_b/shiftzero_ab/
shiftone_b/shiftone_ab
Table 34: forbidden instructions combinations
7.4.2 APB BUS AND WP/AL BITS
One APB peripheral has the following behaviour, when a non-legal or non-allocated address is used:
Writing to a non-legal (i.e. available address not authorised by AL or WP bits) or unavailable (i.e. not specified) APB address automatically increments the error counter in RSTATCNT2 corresponding to the CPU that did the erroneous write access.
Reading a write-only or unavailable APB address (i.e. not specified) returns default value (= 0x00000000).
Reading a non-allocated APB address (i.e. available address not authorised by AL bit) from a register-based peripheral or from the Intercom RAM returns the content of the accessed address.
Reading a non-allocated APB address (i.e. available address not authorised by AL bit) from a segment-based peripheral not being the Intercom RAM returns default value (= 0x00000000).The error counter in RSTATCNT2 corresponding to the CPU that did the erroneous read access is incremented.
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Writing to a read-only, non-legal (i.e. available address not authorised by AL or WP bits) or unavailable (i.e. not specified) APB address will be discarded.
7.4.3 EDAC MANAGEMENT
The CLP provides an embedded protection against SEU in all memory elements in order to make the SW development "SEU-insensitive".
Two detection and correction mechanisms are implemented in the CLP
SEU-hardened flip-flops cells, belonging to the target ASIC technology library, are used. These cells
are part of the design and no action is needed from the software point of view. Their use is
hardwired and transparent to the user
EDAC mechanism is used to protect the CLP memories by the use of 7 check-bits which are added to
the data of each CLP memory (each CLP memory is then (32+7) = 39-bits wide….). These are
controlled either by a programmable background scrubbing function (see §0) or an "on-the-fly"
mechanism – called automated correction - depending on the software execution flow.
All single errors are detected, corrected and reported. These errors will be called "recoverable" in
the text. All multiple errors are detected and reported. These errors will be called "unrecoverable" in
the text.
7.4.3.1 RECOVERABLE ERRORS
The EDAC mechanism is implemented in the PRAM, the INTERCOM RAM and the XCHG RAMs (both
CPU and MMU sides). Whenever a recoverable error is found by the EDAC logic inside these
memories, the CLP:
- corrects the data read from the memory before sending it to the read requester
- writes back the corrected value inside the memory (if programmed) to the corresponding address and increments the associated counter inside RSTATCNT3
The RGP0 to RGP511 registers of A/B units are locally handled by the CPU pipeline management and
depending on the software execution flow. Note that no scrubbing function is possible for these
registers. Whenever a recoverable error is found by the EDAC logic of RGP0 to RGP511 registers of
A/B units, the CLP:
- Replaces the current instruction by a nop and the appropriate counter in RSTATCNT3 is incremented.
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- the operand is corrected and the pipeline stalled.
- the stalled instruction is re-executed and the pipeline restarted.
The user must thus be aware that one operand correction stalls the pipeline for two cycles (then CPU
continues working normally). This should be taken into account to ensure that the software
execution is deterministic in the sense that the maximal number of cycles is well controlled.
7.4.3.2 UNRECOVERABLE ERRORS
Whenever an unrecoverable error is found by the EDAC logic in ANY of the memories, the behaviour
is driven according to the state of RSWREST register.
if the corresponding bit is programmed in RSWREST register, the restart procedure is triggered (cfr section 27.3)
if the corresponding bit is NOT programmed in RSWREST register:
The associated information inside RSTATCNT4 is updated
if the error comes from the program memory, the instruction decoder replace it with a NOP
Then, CPU continues working normally.
7.4.4 MONITORING FUNCTIONS
In addition to SEU management, other monitoring functions are available. The targeted functions are those that are hardwired and potentially sensitive to a deadlock condition. The goal is to have a segregated function (but on the same chip) that is capable to detect these events and to report it externally or to the CPU. Each of these events can trigger a restart with via control register RSWREST (cfr §27.3).
The ADC interface enable its FSM state recovery function when field MONEN is set inside control
register ADCIF_TIMSEL. When the monitoring is enabled, the ADC interface generates an error when
the following conditions are simultaneously met:
the internal state is not equal to IDLE (acquisition phase or reading sequence not completed yet)
the selected TIMER has produced a tick
On boot manager side, a timeout management is programmable via the boot descriptors (see §27).
The MMU contains dedicated APB registers allowing to define which portion of the XCHG RAMs are used for which interface, allowing to detect MMU address access errors.
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8 SPI
8.1 OVERVIEW
The CLP contains two SPI interfaces that can be dynamically configured to function either as a SPI
master or a slave. Each SPI interface can be connected to 12 slaves.
The SPI interfaces also feature configurable word length, bit ordering, clock gap insertion, automatic
slave select and automatic periodic transfers of a specified length. All the SPI modes are supported
and also a 3-wire mode where one bidirectional data line is used.
In master mode, two different reading modes are available. The first one – the classical one - is
called CDOL (=common data out line ). It performs the reading from the various off-chip slaves in a
sequential fashion by activating the various available chip selects. The second one, called
CCS(=Common chip select), performs a parallel reading from the off-chip slaves. This mode is
efficient if a given application desires to minimize the impact of serial communication from external
devices.
In slave mode, the SPI interfaces synchronise the incoming clock and can operate in systems where
other SPI devices are driven by asynchronous clocks.
8.1.1 CONVENTIONS
During a transmission on the SPI bus, data is either changed or read at a transition of SPI0_SCK/
SPI1_SCK. If data has been read at edge n, data is changed at edge n+1. If data is read at the first
transition of SPI0_SCK/ SPI1_SCK the bus is said to have clock phase 0, and if data is changed at the
first transition of SPI0_SCK/ SPI1_SCK the bus has clock phase 1.
The idle state of SPI0_SCK/SPI1_SCK may be either high or low. If the idle state of SPI0_SCK/
SPI1_SCK is low, the bus has clock polarity 0 and if the idle state is high the clock polarity is 1.
The combined values of clock polarity, named CPOL, and clock phase, named CPHA, determine the
mode of the SPI bus.
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8.1.2 4-WIRE EXCHANGES
The CLP transmits (in master mode or slave mode if the CLP answer to a master request) or receive
(in slave mode only) a byte according to the diagram depicted below (CPHA=0).
bit6 bit5 bit4 bit3 bit2 bit1
MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB
1 2 3 4 5 6 7 8SCK Cycle Number
SPI_CLK (CPOL=0)
SPI_CLK (CPOL=1)
SPI_MOSI (from Master)
#MISO# (*)
(from Slave)
#CS# (*)
(from master)
Capture Point
MSB LSB
(*) NOTE (bold text below depicts « active » pin) :
1) When the CCS mode is selected, #MISO# field is SPI_MISO/CS[7:0] and #CS# is SPI_GCSO/GMISO
2) When the CDOL mode is selected, #CS# field is SPI_MISO/CS[7:0] and #MISO# is SPI_GCSO/GMISO3) in
slave mode, #MISO# field is SPI_GCSO/GMISO and #CS# is SPI_MISO/CS[0]
Figure 12: SPI 4-wire mode (CPHA=0)
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The CLP transmits (in master mode or slave mode if the CLP answer to a master request) or receive
(in slave mode) a byte according to the diagram depicted below (CPHA=1)
MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB
MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB
1 2 3 4 5 6 7 8SCK Cycle Number
SPI_SCLK0 (CPOL=0)
SPI_SCLKO (CPOL=1)
SPI_MOSI (from Master)
#MISO# (*)
#CS# (*)
Capture Point
(*) NOTE (bold text below depicts « active » pin) :
1) When the CCS mode is selected, #MISO# field is SPI_MISO/CS[7:0] and #CS# is SPI_GCSO/GMISO
2) When the CDOL mode is selected, #CS# field is SPI_MISO/CS[7:0] and #MISO# is SPI_GCSO/GMISO
3) in slave mode, #MISO# field is SPI_GCSO/GMISO and #CS# is SPI_MISO/CS[0]
Figure 13: SPI 4-wire mode (CPHA=1)
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8.1.3 3-WIRE MODE CASES
Each SPI interface is configured to operate in 3-wire mode, if the TWEN field is set to ‘1’ (cfr
SPI0_MODREG/ SPI1_MODREG registers). In that case, the associated SPI interface uses a
bidirectional data line instead of separate data lines for input and output data. In 3-wire mode the
bus is thus a half-duplex synchronous serial bus.
In the 3-wire mode, the transmission starts when a master selects a slave through SPIx_GCSO or
SPI0_CSO/ SPI1_CSO signals and the clock line SPI0_SCK/ SPI1_SCK transitions from its idle state.
Only the Master-Output-Slave-Input (SPI0_MOSI/ SPI1_MOSI) signal is used for data transfer.
The direction of the first data transfer is determined by the value of the TTO field in SPI0_MODREG/
SPI1_MODREG register:
If TTO is ‘0’, data is first transferred from the master. After a word has been transferred, the slave uses the same data line to transfer a word back to the master.
If TTO is ‘1’ data is first transferred from the slave to the master. After a word has been transferred, the master use the SPI0_MOSI/ SPI1_MOSI line to transfer a word back to the slave.
The data line transitions depend on the clock polarity and clock phase in the same manner as in the
4-wire mode.
The slave delay (cfr field ASELDEL in SPI0_MODREG/ SPI1_MODREG) of the MISO signal in the 4-wire
SPI mode affects the MOSI signal in 3-wire mode, when the SPI interface operates as a slave.
8.1.4 RECEIVE AND TRANSMIT QUEUES
Each SPI interface has receive and transmit queues. Each transmit queue consists of the transmit
register and the transmit FIFO. The receive queue consists of the receive register and the receive
FIFO. The total number of words that can exist in each queue is fixed by the FIFO depth (cfr FDEPTH
field in SPI0_CAPAREG/ SPI1_CAPAREG registers) plus one.
When one SPI interface has available space in the transmit queue, it asserts the Not full (NF) bit in
the event register (cfr SPI0_EVTREG/ SPI1_EVTREG registers).
When one SPI interface has received a word, as defined by word length (cfr LEN filed in
SPI0_MODREG/ SPI1_MODREG registers), it places the data in the receive queue. When the receive
queue has one or more elements stored, the Not Empty (N)E bit in the SPI0_EVTREG/ SPI1_EVTREG
registers is asserted. The receive register only contains valid data if the NE bit is asserted.
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If the receive queue is full and the SPI interface receives a new word, an overrun condition occurs.
The received data is discarded and the Overrun (OV) bit in the SPI0_EVTREG/SPI1_EVTREG registers
is set.
The SPI interface also detects underrun conditions. An underrun condition occurs when the SPI
interface is externally selected by a master, via SPI0_CSI/ SPI1_CSI, and the SPI0_SCK/ SPI1_SCK
clock transitions while the transmit queue is empty. In this scenario, the SPI interface responds with
all bits set to ‘1’ and sets the Underrun bit (UN) in the SPI0_EVTREG/SPI1_EVTREG register. An
underrun condition never occurs in master mode. When the master has an empty transmit queue,
the bus goes into an idle state.
8.1.5 CLOCK GENERATION (MASTER MODE)
In master mode, each SPI interface generates a clock on SPI0_SCK/ SPI1_SCK output with a
frequency depending on the fields DIV16, FACT, and PM in SPI0_MODREG/ SPI1_MODREG. Without
DIV16 the SPI0_SCK/SPI1_SCK frequency is:
50/((4-(2*FACT))*(PM+1))
When DIV16 enabled, the frequency of SPI0_SCK/ SPI1_SCK is:
50/(16*(4-(2*FACT))*(PM+1))
8.1.6 AUTOMATED PERIODIC TRANSFERS (MASTER MODE)
Each SPI interface supports automated periodic transfers if the AMODE field in SPI0_CAPAREG/
SPI1_CAPAREG registers is set to ‘1’. In this mode, the SPI interface performs transfers with a
specified period and length. Note that this mode can be seen as a local DMA handling SPI operation.
When an automated transfer is performed, data is placed in a temporary queue to ensure that a full
transfer can be read out atomically without interference from incoming data (i.e. data related to
non-automated transfers). The AM receive queue is filled with the data from the temporary queue if
the AM receive queue is empty, or if it is full and SEQ bit (in SPI0_AMCONFREG/SPI1_AMCONFREG
registers) is disabled.
If the LOCK bit in SPI0_AMCONFREG/SPI1_AMCONFREG registers is set, the SPI interface does not
place new data in the AM receive queue if the software is reading out data from the queue.
If the SEQ bit is set in SPI0_AMCONFREG/SPI1_AMCONFREG registers, the SPI interface does not
move data from the temporary queue until the AM receive queue has been cleared.
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The SPI interface attempts to place data into the temporary receive queue when the automated
transfer period counter reaches zero. If the temporary queue is filled, which can occur if the SPI
interface is prevented from moving the data to the receive queue, the behaviour depends on the
setting of the STRICT field in the SPI0_AMCONFREG/SPI1_AMCONFREG registers:
If the value of STRICT is ‘0’, the SPI interface delays the transfer and wait until the temporary queue
has been cleared.
If the value of STRICT is ‘1’, and the contents of the temporary queue cannot be moved to the AM
receive queue, there is an overflow condition in the temporary queue. The behaviour on a
temporary queue overflow is defined by the SPI0_AMCONFREG/SPI1_AMCONFREG registers fields
OVTB and OVDB:
If there is a temporary queue overflow and OVTB is set, the transfer is skipped and the internal period counter is reloaded.
If the OVTB bit is not set, the transfer is performed.
If the transfer is performed and the OVDB bit is set, the data is disregarded. If the OVDB bit is not set, the data is placed in the temporary receive queue and the previous data is overwritten.
If the field EACT is set in SPI0_AMCONFREG/SPI1_AMCONFREG registers, the SPI interface activates
the Automated transfers when the CLP timer selected through TIMSEL field (in SPI0_AMCR/
SPI1_AMCR) produces a tick. When the core detects that EACT is set and the selected CLP timer
ticks, it sets the ACT bit (in SPI0_AMCONFREG/SPI1_AMCONFREG registers) and resets the EACT bit.
The field TIMSEL in the SPI0_AMCONFREG/SPI1_AMCONFREG selects the CLP timer that generates
the tick defining the automatic mode transfers period when the external event start input is used.
Subsequent automated transfers are started when the period counter reaches zero, if ERPT field of
the SPI0_AMCONFREG/SPI1_AMCONFREG register is set to zero. If the ERPT field is set to one then
the selected CLP timer tick is used to start subsequent transfers instead.
If the two SPI interfaces have their automated transfers enabled with the same CLP timer output,
synchronised transfers is produced. In such case, if the receive queues of a given SPI interface are
filled and if STRICT transfers are disabled, a delay is produced in the start of the associated SPI
interface’s next transfer.
8.1.7 CCS/CDOL (MASTER MODE)
In master mode, the SPI interface is configured in either Common Chip Select (CCS) or Common Data
Out Line (CDOL) mode. This is controlled via bit of configuration registers SPI0_MODREG and
SPI1_MODREG.
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In CDOL mode, SPIx_CSO/MISO[11:0] I/Os are set to SPIx_CSO[11:0] and SPIx_GCSO/GMISO is set
to SPIx_GMISO. SPIx_CSO[11:0] are used to drive the various chip selects for the driven slaves and
SPIx_GMISO is used a common MISO data line from the slaves which thus share their data out line
(assuming they also control their impedance state)
In CCS mode, SPIx_CSO/MISO[11..0] I/Os are set SPIx_MISO[11..0] and SPIx_GCSO/GMISO is set to
SPIx_GCSO. SPIx_MISO[11:0] are used to acquire the various data out lines coming from the slaves
and SPIx_GMISO is used a common chip select line to the slaves which thus share their chip select
line (the reading is thus made in parallel between the slaves).
The CCS mode is handled with on-chip shift-register connected to the SPI_GCSO/SPI_GMISO[11:0]
pin and that shift the data MSB first and store its content in a 4 word FIFO (32 bits wide) after the
configured amount of bits have been shifted. The shifted data length is specified in the LEN field of
mode register
Note that for applications requiring the SPI interface in master mode, the user must correctly
program the desired IOMUX pins. In particular:
MOSI must be programmed towards an IOMUX output
SPIx_GCSO/SPIx_GMISO must be programmed towards an IOMUX output when CCS mode is selected and an IOMUX input when CDOL mode is selected
SPIx_MISO/ SPIx_CSx must be programmed towards an IOMUX input when CCS mode is selected and an IOMUX output when CDOL mode is selected
CLK is always hardwired in the CLP on pin SPI_CLK
8.1.8 SPECIFIC CASES (MASTER MODE)
When a SPI interface is configured for master operation, it transmits a word when there is data
available in the transmit queue. When the transmit queue is empty, it drives SPI0_SCK/ SPI1_SCK to
its idle state.
If the SPI0_CSI/ SPI1_CSI input goes low during master operation, the SPI interface abort any active
transmission and the MME bit in SPI0_EVTREG/SPI1_EVTREG registers is asserted. The SPI interface
must also be disabled.
The SPI interface reacts to Multiple-Master Errors even if the loop mode (LOOP field in
SPI0_MODREG/SPI1_MODREG) is activated.
Multi-Master Errors detection can be disabled by setting the IGSEL bit of the SPI0_MODREG/
SPI1_MODREG to 1.
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8.1.8.1.1 SLAVE MODE
When one SPI interface is configured for slave operation, it drives any SPI signal exclusively when the
SPI interface has been selected, via the SPI0_CSI/SPI1_CSI input.
If the SPI interface operates in 4-wire SPI mode, when SPI0_CSI/SPI1_CSI goes low, the SPI interface
configures SPI0_MISO/SPI1_MISO as an output and drives the value of the first bit scheduled for
transfer.
If the SPI interface is configured into 3-wire mode, the SPI interface first listen to the SPI0_MOSI/
SPI1_MOSI line and when a word has been transferred, drive the response on the MOSI line if the
TTO bit of the SPI_MODE register is '0', otherwise, the slave transmit first and the master follow.
If the SPI interface is selected when the transmit queue is empty, it transfers a word with all bits set
to ‘1’ and the SPI interface will report an underflow.
Since the SPI interface synchronises the incoming clock, it does not react to transitions on SPI0_SCK/
SPI1_SCK until two CLP clock cycles have passed. This leads to a delay of three CLP clock cycles when
the data output line changes as the result of a SCK transition.
The maximum affordable SPI0_SCK/SPI1_SCK frequency is equal to (CLP clock frequency)/ 8
The SPI interface also filters the SPI0_SCK/SPI1_SCK input. The value of the PM field in the
SPI0_MODREG/SPI1_MODREG register defines for how many system clock cycles the SCK input
must be stable before the SPI interface accepts the new value:
If the PM field is set to zero, then the maximum SPI0_SCK/SPI1_SCK frequency is equal to:
(CLP clock frequency)/ 8
For each increment of the PM field, the maximum SPI0_SCK/SPI1_SCK frequency is prolonged by the equivalent of two times the CLP clock period (as the SPI interface will require longer time to discover and respond to SPI0_SCK/SPI1_SCK transitions)
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8.2 I/O SIGNALS
The two SPI interfaces control the following CLP inputs/outputs (Note: routing to/from IOMUX pins is not taken into account)
I/O NAME I/O/Z WIDTH DESCRIPTION ACTIVE RESET VALUE
SPI0_SCK I/O/Z 1 SPI 0 Serial Clock In or Out N/A Z
SPI0_MOSI I/O/Z 1 SPI 0 Master Out Slave In N/A Z
SPI0_CSI I 1 SPI 0 Chip Select In LOW N/A
SPI0_GMISO/MISO[11..0] I/O/Z 12 SPI 0 Chip Select Out/ Master In Slave Out LOW Z
SPI0_GCSO/GMISO I/O/Z 1 SPI 0 General Chip Select Out/ Master In Slave Out LOW Z
SPI1_SCK I/O/Z 1 SPI 1 Serial Clock In or Out N/A Z
SPI1_MOSI I/O/Z 1 SPI 1 Master Out Slave In N/A Z
SPI1_CSI I 1 SPI 1 Chip Select In LOW N/A
SPI1_GMISO/MISO[11..0] I/O/Z 12 SPI 1 Chip Select Out/ Master In Slave Out LOW Z
SPI1_GCSO/GMISO I/O/Z 1 SPI 1 General Chip Select Out/ Master In Slave Out LOW Z
Table 35: SPI IO table
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8.3 APB INTERFACE
The SPI0 interface is programmed through the following APB address table
APB
ADDRESS
(hex)
TYPE NAME DESCRIPTION R/W
0x0000 C SPI0_CAPAREG SPI controller capability register R
0x0008 C SPI0_MODREG SPI controller mode register R/W
0x0009 C SPI0_EVTREG SPI controller event register R/W
0x000A C SPI0_MASKREG SPI controller mask register R/W
0x000B C SPI0_CMDREG SPI controller command register R/W
0x000C D SPI0_TRSREG SPI controller transmit register W
0x000D D SPI0_RCVREG SPI controller receive register R
0x000E C SPI0_SLVSELREG SPI controller slave select register R/W
0x000F C SPI0_AUTSLVSEL SPI controller automatic slave select register R/W
0x0010 C SPI0_AMCONFREG
SPI controller AM configuration register R/W
0x0011 C SPI0_AMPERREG SPI controller AM period register R/W
0x0014
(*)
C SPI0_AMMSKREG SPI controller AM mask register(s) R/W
0x0040-0x005F
(**)
D SPI0_AMTRSREG SPI controller AM transmit register(s) R/W
0x0080-0x009f
(**)
D SPI0_AMRCVREG SPI controller AM receive register(s) R
0x00C0-0x00CF
(**)
D SPI0_CCS_CDOL SPI Common data line input registers R
Table 36: SPI0 APB registers
(*) Number of implemented registers depend on FDEPTH (bits 15:8) in the SPI0_CAPAREG/
SPI1_CAPAREG registers in the following way:
Number of registers =(FDEPTH-1)/32 + 1.
(**) Number of implemented registers equals FDEPTH (bits 15:8) in the
SPI0_CAPAREG/SPI1_CAPAREG registers.
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The SPI1 interface is programmed through the following APB address table:
APB
ADDRESS
(hex)
TYPE NAME DESCRIPTION R/W
0x0100 C SPI1_CAPAREG SPI controller capability register R
0x0108 C SPI1_MODREG SPI controller mode register R/W
0x0109 C SPI1_EVTREG SPI controller event register R/W
0x010A C SPI1_MASKREG SPI controller mask register R/W
0x010B C SPI1_CMDREG SPI controller command register R/W
0x010C D SPI1_TRSREG SPI controller transmit register W
0x010D D SPI1_RCVREG SPI controller receive register R
0x010E C SPI1_SLVSELREG SPI controller slave select register R/W
0x010F C SPI1_AUTSLVSEL SPI controller automatic slave select register R/W
0x0110 C SPI1_AMCONFREG
SPI controller AM configuration register R/W
0x0111 C SPI1_AMPERREG SPI controller AM period register R/W
0x0114
(*)
C SPI1_AMMSKREG SPI controller AM mask register(s) R/W
0x0140-0x015F
(**)
D SPI1_AMTRSREG SPI controller AM transmit register(s) R/W
0x0180-0x019f
(**)
D SPI1_AMRCVREG SPI controller AM receive register(s) R
0x01C0-0x01CF
(**)
D SPI1_CCS_CDOL SPI Common data line input registers R
Table 37: SPI1 APB registers
(*) Number of implemented registers depends on FDEPTH (bits 15:8) in the SPI0_CAPAREG/
SPI1_CAPAREG registers in the following way:
Number of registers =(FDEPTH-1)/32 + 1.
(**) Number of implemented registers equals FDEPTH (bits 15:8) in the SPI0_CAPAREG/
SPI1_CAPAREG registers.
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9 UART
9.1 OVERVIEW
The CLP contains four independent UARTs to communicate with serial peripherals using the RS-232
standard data format. From the software point of view, an UART will appear as an 8-bit or 32-bit
read-write parallel port working with FIFOs. Each UART performs the serial-to-parallel conversions
and parallel-to-serial conversions according to the RS-232 standard. A number of control registers
allow to trigger a transmission and program the various modes that are available. In particular, the
baud rate is programmable and can be programmed to work up to 5 Mbytes/s (despite the fact that
this speed is not standard). Status register provide the required information to detect FIFO empty or
full states.
9.2 BEHAVIOUR
Each UART is made of two FIFOs, each FIFO is able to store up 16 bytes. One FIFO is dedicated to
transmission while the other is dedicated to reception. On the APB side, the data can be accessed
either byte per byte (though UARTx_DATA8x register) or word (=4 bytes) per word (through
UARTx_DATA32x register). The selection between both data width is made according to TXRDY8 and
TXRDY32 fields (for transmission) and RCVRDY8 and RCVRDY 32 fields (for reception). These fields
are separately controlled in UARTx_DATAx_TSM and UARTx_DATA_x_RCV APB registers (i.e.
transmission can be made byte-based whereas reception can be word-based). Selection of data
width is done by writing the UARTx_DATAx_TSM or by reading UARTx_DATAx_RCV
Each time the software reads or writes a byte or word, the FIFO is popped or pushed with the
corresponding data. On the UART link side, data is always handled byte by byte.
Each UART handles the frame according to the Standard RS-232 definition which is shown in the
following figure:
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Serial Line
Baud Clock
Start Data (5/6/7/8 bits) Parity (if used) Stop (1/1.5/2 bit) idle
Figure 14: UART byte frame
Only the data bits needs to be handled by the software. Other bits are automatically generated,
checked and filtered by the UART link. The data bits can be configured to support from 5 bits data up
to 8 bits wide.
When there is nothing to be sent, the serial line UART_Tx is held high. The first low bit is the start
bit, which indicates the beginning of a new frame. The next five to eight bits are the data bits, which
convey the actual information to be sent, least significant bit first. If enabled, a parity bit is sent on
the serial line after the data bits. Finally, the serial line is held high again for at least one bit to
indicate the end of a frame. This is called the stop bit, which also returns the serial line to the idle
state. The type of parity and length of stop bits is also configurable.
The baud generator creates a baud rate clock for the transmission but also a receiver reference clock
(16 times higher to perform oversampling). The baud generator creates the clock by dividing the CLP
clock by any divisor from 16 to 16*28. The divisor is the unsigned value stored in the UARTx_DR
control Register. It is up to the user to correctly set the baud rate according to the host UART
terminal that is used in the system.
The UART provides to the software its status any time. Reported information includes the line
condition, as well as any errors such as parity, overrun, framing, or line break. Status registers
UARTX_LSR are made for that purpose.
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9.3 I/O SIGNALS
The UART interface controls the following CLP inputs/outputs (Note: routing to/from IOMUX pins is not taken into account)
I/O NAME I/O/Z WIDTH DESCRIPTION ACTIVE RESET VALUE
UART_TX0 O 1 UART#1 Transmit Out LOW Z
UART_RX0 I 1 UART#1 Receive In LOW Z
UART_TX1 O 1 UART#2 Transmit Out LOW Z
UART_RX1 I 1 UART#2 Receive In LOW Z
UART_TX2 O 1 UART#3 Transmit Out LOW Z
UART_RX2 I 1 UART#3 Receive In LOW Z
UART_TX3 O 1 UART#4 Transmit Out LOW Z
UART_RX3 I 1 UART#4 Receive In LOW Z
Table 38: UART I/O signals
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9.4 APB INTERFACE
The UART has the following APB address table
APB
ADDRESS
(hex)
TYPE NAME DESCRIPTION R/W
0x0500 D UART0_DATA8_RCV 8-bit word FIFO receive R
0x0501 D UART0_DATA8_TSM 8-bit word FIFO transmit W
0x0502 C UART0_LCR Line control R/W
0x0503 C UART0_LSR Line status R
0x0504 C UART0_DR Divisor R/W
0x0505 C UART0_FCR FIFO control W
0x0506 D UART0_DATA32_RCV 32-bit word FIFO receive R
0x0507 D UART0_DATA32_TSM 32-bit word FIFO transmit W
0x0508 D UART1_DATA8_RCV 8-bit word FIFO receive R
0x0509 D UART1_DATA8_TSM 8-bit word FIFO transmit W
0x050A C UART1_LCR Line control R/W
0x050B C UART1_LSR Line status R
0x050C C UART1_DR Divisor R/W
0x050D C UART1_FCR FIFO control W
0x050E D UART1_DATA32_RCV 32-bit word FIFO receive R
0x050F D UART1_DATA32_TSM 32-bit word FIFO transmit W
0x0510 D UART2_DATA8_RCV 8-bit word FIFO receive R
0x0511 D UART2_DATA8_TSM 8-bit word FIFO transmit W
0x0512 C UART2_LCR Line control R/W
0x0513 C UART2_LSR Line status R
0x0514 C UART2_DR Divisor R/W
0x0515 C UART2_FCR FIFO control W
0x0516 D UART2_DATA32_RCV 32-bit word FIFO receive R
0x0517 D UART2_DATA32_TSM 32-bit word FIFO transmit W
0x0518 D UART3_DATA8_RCV 8-bit word FIFO receive R
0x0519 D UART3_DATA8_TSM 8-bit word FIFO transmit W
0x051A C UART3_LCR Line control R/W
0x051B C UART3_LSR Line status R
0x051C C UART3_DR Divisor R/W
0x051D C UART3_FCR FIFO control W
0x051E D UART3_DATA32_RCV 32-bit word FIFO receive R
0x051F D UART3_DATA32_TSM 32-bit word FIFO transmit W
Table 39: UART APB registers
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10 INTERCOM RAM
10.1 OVERVIEW
The CLP contains one intercommunication 512x(32+7) bits RAM (the 7 bits are for the EDAC
management).allowing the two CPUs to communicate with each other. The memory is dual-port and
is accessible on both APB busses. From the hardware point of view, all the intercom RAM memory
space is available to the two CPUs. However, a segmented architecture is proposed to allow the user
to restrict portions of this memory to one of the CPU (or none). Only the writing is disabled in that
case, the reading will always be possible.
The simultaneous reads to identical addresses is possible. A simultaneous read and write to the
same address (but on different ports) is possible. In that case, the read value corresponds to the
previous value (before the write).
10.2 I/O SIGNALS
The Intercom RAM is internal. There are no IO signals
10.3 APB INTERFACE
The Intercom RAM has the following APB address table
APB ADDRESS
(hex) TYPE NAME DESCRIPTION R/W SEGMENT
0x2000 D INCOMRAM_ADD0 Address 0 of INTERCOM RAM R/W
1 0x2001 D INCOMRAM_ADD1 Address 1 of INTERCOM RAM R/W
.. .. .. .. ..
0x20FF D INCOMRAM_ADD255 Address 1023 of INTERCOM RAM R/W
0x2100 D INCOMRAM_ADD256 Address 1024 of INTERCOM RAM R/W
2
.. .. .. .. ..
0x21FD D INCOMRAM_ADD509 Address 509 of INTERCOM RAM R/W
0x21FE D INCOMRAM_ADD510 Address 510 of INTERCOM RAM R/W
0x21FF D INCOMRAM_ADD511 Address 511 of INTERCOM RAM R/W
Table 40: Intercom RAM APB registers
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11 CRC
11.1 OVERVIEW
Two CRC units, called CRC0 and CRC1, are integrated in the CLP to allow on-demand verification of data integrity. The CRC polynomial can be modified at any time by the user through dedicated control registers.
A typical use of these CRC units is an application requiring to regularly verify the coherency of a large number of data (a table for instance). This can be useful to check large amounts of internal data (stored in the CLP on-chip memories) or external data coming from an external device (EEPROM,…) typically connected to the MEM interface or even through the Spacewire.
The CRC0 unit is used during by the boot manager to check the global integrity of the code. In that case, the CRC block is based on the CRC-32 polynomial ("x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1") used in the Ethernet standard.
Two CRC units have a data register called "CRC0_DATA_IN" and "CRC1_DATA_IN" allowing pushing
one 32-bit data made of bits a31 to a0. These bits are interpreted by the CRC unit as a 31th order
divider polynom whose weights are defined according to the following formula:
a31*x31 + a30*x30 + a29*x29 +....+a1*x1 +a0
Note: x32 does not exist in order to avoid an overflow (i.e. dividend > divider)
Each time a new data is pushed, the CRC unit performs a CRC computation cycle by dividing the
current 32th order divider polynom (defined by CRC0_POL/ CRC1_POL control registers) with the
current 31th dividend polynom defined in the corresponding CRC0_DATA_IN/CRC1_DATA_IN data
registers. This provides the cyclic redundancy check as one given remainder always contains the
result of previous division.
The result, corresponding to the new 31th order remainder, is stored in the corresponding
CRC0_DATA_OUT/CRC1_DATA_OUT registers which can be read at any moment. The read data
provides the weights of the remainder polynom which has the following form:
r31*x31 + r30*x30 + r29*x29 +....+r1*x1 +r0
Two cycles are needed by one CRC unit to update the CRC remainder which is available on a specific
data register. The initial seed for the CRC remainder is set to 0xFFFFFFFF. The remainder can be
cleared (set to 0xFFFFFFFF) by writing to the CRC0_CFG/CRC1_CFG registers. Note that the
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polynomial definition controlled with the registers CRC0_POL/CRC1_POL always assume that the
high order bit of the divisor (=X32) is equal to 1.
When the remainder computed by a given cycle equals 0, the CRCOK field in CRC0_STAT/CRC1_STAT
status registers are set to 1. This data register is typically the one that must be read by the software
to check the integrity of a given data set
The CRC remainder may be read through both APB busses. If the CRC remainder is read through a
different APB bus than the one used to push the data, only after two clock cycles of the data pushing
event the new remainder is available, otherwise, the last CRC remainder is read.
The data injection to the CRC units is done beginning by the MSB.
During the boot the CRC0 unit is used to guarantee the integrity of the Boot sequence. After the
Boot sequence, the Boot Configuration CRC value is available in the register CRC0_DATA_OUT
11.2 I/O SIGNALS
None. The function is purely internal
11.3 APB REGISTERS
The CRC units have the following APB address table
APB ADDRES
S (hex)
TYPE NAME DESCRIPTION R/W
0x0300 C CRC0_POL Polynom weights for 1st CRC R/W
0x0301 C CRC0_CFG Selects load mode and Clears reminder for 1st CRC R/W
0x0302 D CRC0_DATA_IN Data in for 1st CRC R/W
0x0303 D CRC0_DATA_OUT Remainder for 1st CRC R
0x0304 S CRC0_STAT Status of 1st CRC R
0x0305 C CRC1_POL Polynom weights for 2nd CRC R/W
0x0306 C CRC1_CFG Clears reminder for 2nd CRC R/W
0x0307 D CRC1_DATA_IN Data in for 2nd CRC R/W
0x0308 D CRC1_DATA_OUT Remainder for 2nd CRC R
0x0309 S CRC1_STAT Status of 2nd CRC R
Table 41: CRC APB registers
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12 GPIO AND MEM8 INTERFACE
12.1 OVERVIEW
The GPIO interface is intended to provide fully software programmable inputs and outputs. There
are up to 96 digital signals that can be used in either an independent or a simultaneous fashion.
GPIO are multiplexed with other CLP interfaces with the IOMUX mechanism (cfr section §21 about
IOMUX). Therefore a trade-off must be made by the user on the number of GPIO to use for a given
application. The selection of which GPIO pin is used is made during the boot and remains static
when the software is running. Note also that after the reset, by default, all IOMUX pins are pre-
programmed to use GPIO.
12.2 BEHAVIOUR
The GPIO interface allows two possible modes. The first one is the conventional GPIO mode where a
given pin is controlled as an input, output or input/output. The second one proposes an interesting
feature called MEM8: an automated interface with an 8-bit external memory. This function is used
in a transparent fashion during the boot when the code must be uploaded from an external 8-bit
memory. However, when the software is running, the GPIO and 8-bit (denoted by the MEM8
acronym) interfaces remain accessible.
The use the MEM8 mode is programmed through MEM8SEL field in GPIO_MEM8CONF control
register When the MEM8 mode is selected, the associated GPIO signals (30 in total) are unavailable
to the user. Note that in this mode, the output pins MEM8_CSB, MEM8_OEB and MEM8_RWB are
automatically used. A read is triggered when APB register GPIO_MEM8ADD is written (via WRITEAPB
instruction) and when RW field is set to '1'. The reading operation is performed on corresponding
I/Os on the clock cycle that immediately follows the GPIO_MEM8ADD update. A write is triggered
when APB register GPIO_MEM8WDATA is written (through WRITEAPB instruction) and only if RW
field of APB register GPIO_MEM8ADD has previously been set to '0'. The operation is performed on
the corresponding I/Os (MEM8_ADD[18:0] and MEM8_DATA[7:0] on the clock cycle that follows the
GPIO_MEM8WDATA update. In any other case, no operation is performed. The MEM8 mode
additionally offers a burst mode allowing automatically reading or writing 2 or 4 bytes. Further
details are provided below.
In the conventional mode, a GPIO configured as an input may sample the input signal in several
ways: either in sticky mode or in free mode.
When the sticky mode has been selected, the corresponding value (inside the GPIO_INVAL register)
keeps its value until the CPU has read it. Any other edge occurring in the corresponding GPIO signal
(through the IOMUX pin) is not taken into account. When the sticky mode is desired by the user, and
in order to avoid unwanted sticky mode events, it is mandatory to configure this mode after the
IOMUX configuration. This advice may be considered during the boot or when the software is up.
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Indeed, if the sticky mode is programmed while IOMUX is still to be programmed, glitches may
appear and lead to the detection of an unwanted event. When the sticky mode is set, the user needs
to perform a dummy read in the GPIO_INVALxx registers to clear previous transient detected. Note
also that If the sticky mode is set during boot, the user also has to perform this dummy read.
When a free mode has been selected, the corresponding value (inside the GPIO_INVAL register)
unconditionally updates its contents on each cycle. In Normal Free Mode, the value of GPIO_INVAL
bit corresponds to the pin state. In Invert Free Mode, it the value of corresponds to the inverted pin
state. Any pulse or edge is consequently not detected by the hardware but must be by software if
needed. This mode is consequently more suitable for static signals.
Regarding the associated latencies:
when a GPIO pin is used as an output, the latency between the CPU cycle executing the WRITEAPB instruction and the cycle where the desired state is applied to the corresponding IOMUX pin is equal to 4 clock cycles.
When a GPIO pin is used as an input, the latency between the cycle where the desired event occurs on the corresponding IOMUX pin and the cycle where the corresponding GPIO_INVAL field is updated is equal to 3 clock cycles. This number integrates the metastability logic that is integrated in the CLP.
However, if the GPIO is configured as input and output, the latency between the CPU cycle executing the WRITEAPB instruction and the cycle where the value is reflected in the GPIO_INVAL is equal to 7 clock cycles.
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12.2.1 MEM8 (8-BIT PARALLEL INTERFACE)
12.2.1.1 READ CASE (NO BURST)
When the GPIO interface is configured to use the 8-bit interface, a read operation is performed
according to the following waveforms (MEM8_RWB remains to '1').
MEM8_CSB
MEM8_OEB
MEM8_ADD 19-bit address
MEM8_DATA 8-bit data
t1
D0 D1 D2 D1
t0
NOTES:
- The following timings depend on the memory device characteritics
T0 = data access time from OEB low
T1 = high impedance from OEB high
- The waveforms are triggered by the cycle that follows the writing to MEM8_ADD register
Figure 15: MEM8-read case(no burst)
During the 8-bit read operation, the CLP samples the data read from the external memory and store
it in register GPIO_MEM8RDATA after (D0+D1+D2) cycles (D0, D1 and D2 are control registers that
are under software control in GPIO_MEM8CONF control register):
12.2.1.1.1 READ CASE (BURST)
When the GPIO interface is configured to use the 8-bit interface in burst mode (cfr 31.1.16 BRST
field), a read operation is performed according to the following waveforms (MEM8_RWB remains to
'1').
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MEM8_CSB
MEM8_OEB
MEM8_ADD A
MEM8_DATA GPIO_MEM8RDATA[7:0]
t2
D0 D1 D2 D1
t1
A+1
D2 D1
A+3
D2
2*8-bit burst case4*8-bit burst case
GPIO_MEM8RDATA[15:8] GPIO_MEM8RDATA[31:24]
Figure 16: MEM8-read case burst
During the burst read operation, the CLP samples the data read from the external memory and
stores it in register GPIO_MEM8RDATA after a time length determined by the following formula (D0,
D1 and D2 are control registers that are under software control in GPIO_MEM8CONF control
register):
D0+ (D1+D2) and D0+2*(D1+D2) cycles in case of burst of length 2
D0+(D1+D2), D0+2*(D1+D2), D0+3*(D1+D2) and D0+4*(D1+D2) cycles in case of burst of
length 4
12.2.1.1.2 WRITE CASE (NO BURST)
When the GPIO interface is configured to use the 8-bit interface, a write operation is performed
according to the following waveforms (MEM8_OEB remains to '1').
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MEM8_CSB
MEM8_RWB
MEM8_ADD
MEM8_DATA
t4
D0 D1 D2 D1
t3
NOTES:
- The following timings depend on the memory device characteritics
t3 = setup time w.r.t. MEM8_RWB rising edge
t4 = hold time w.r.t. MEM8_RWB rising edge
- The waveforms are triggered by the cycle that follows the writing to MEM8_WDATA register
GPIO_MEM8WDATA[7:0]
GPIO_MEM8ADD[7:0]
Figure 17: MEM8-write case (no burst)
12.2.1.1.3 WRITE CASE (BURST)
When the GPIO interface is configured to use the 8-bit interface in burst mode (cfr 31.1.16 BRST
field), a write operation is performed according to the following waveforms (MEM8_OEB remains to
'1').
MEM8_CSB
MEM8_RWB
MEM8_ADD
MEM8_DATAGPIO_MEM8WDATA[7:0]
t4
D0 D1 D2 D1
t3
D2 D1 D1
2*8-bit burst case4*8-bit burst case
GPIO_MEM8WDATA[15:8] GPIO_MEM8WDATA[31:24]
GPIO_MEM8ADD[18:0] GPIO_MEM8ADD[18:0]+1 GPIO_MEM8ADD[18:0]+3
Figure 18: MEM8-write case (burst)
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12.3 I/O SIGNALS
The GPIO interface (including the 8-bit interface) controls the following CLP inputs/outputs (Note: During the boot all MEM8 signals are connected directly to the top. Then, all these signals are routed to/from IOMUX pins)
I/O NAME I/O/Z WIDTH DESCRIPTION ACTIVE RESET VALUE
GPIO[95:0] I/O/Z 96 General Purpose Inputs/Outputs N/A Z...Zb
MEM8_ADD[18:0] O 19 19-bit address bus N/A 00..00b
MEM8_DATA[7:0] I/O/Z 8 8-bit data bus N/A Z..Zb
MEM8_CSB O 1 Chip select bar Low 1b
MEM8_OEB O 1 Output Enable bar Low 1b
MEM8_RWB O 1 Read/Write bar Low 1b
Table 42: GPIO/MEM I/O signals
Note:
MEM8_ADD[18:0] and MEM8_DATA[7:0] are multiplexed with GPIO[49:20]
12.4 APB INTERFACE
The GPIO interface has the following APB address table
APB ADDRESS
(hex) TYPE NAME DESCRIPTION R/W
0x0600 C GPIO_MODE15TO0 Configures GPIO [15:0] modes R/W
0x0601 C GPIO_MODE31TO16 Configures GPIO [31:16] modes R/W
0x0602 C GPIO_MODE47TO32 Configures GPIO [47:32] modes R/W
0x0603 C GPIO_MODE63TO48 Configures GPIO [63:48] modes R/W
0x0604 C GPIO_MODE79TO64 Configures GPIO [79:64] modes R/W
0x0605 C GPIO_MODE95TO80 Configures GPIO [95:80] modes R/W
0x0606 D GPIO_OZ15TO0 Sets GPIO [15:0] output state R/W
0x0607 D GPIO_OZ31TO16 Sets GPIO [31:16] output state R/W
0x0608 D GPIO_OZ47TO32 Sets GPIO [47:32] output state R/W
0x0609 D GPIO_OZ63TO48 Sets GPIO [63:48] output state R/W
0x060A D GPIO_OZ79TO64 Sets GPIO [79:64] output state R/W
0x060B D GPIO_OZ95TO80 Sets GPIO [95:80] output state R/W
0x060C D GPIO_INVAL31TO0 Read s GPIO[31:0] value according to selected mode R
0x060D D GPIO_INVAL63TO32 Read s GPIO[63:32] value according to selected mode R
0x060E D GPIO_INVAL95TO64 Read s GPIO[95:64] value according to selected mode R
0x0620 C GPIO_MEM8CONF 8-bit interface configuration register R/W
0x0621 D GPIO_MEM8ADD 8-bit interface address register R/W
0x0622 D GPIO_MEM8RDATA 8-bit interface read data register R
0x0623 D GPIO_MEM8WDATA 8-bit interface write data register R/W
0x0624 C GPIO_MEM8STAT 8-bit interface status register R
Table 43: GPIO/MEM8 APB registers
The details of each APB register can be found in annex 1, section 28.7
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13 PWM
13.1 OVERVIEW
The CLP integrates 24 programmable PWM timers with complemented outputs. As one of the key
applications of the CLP is motor and mechanisms control, such interface is mandatory to provide up-
to-date control strategies. Each complemented output is fully programmable in terms of polarity,
width and dead time. Two modes are programmable and controlled with fields SINGLE_ED and
INDEP in PWMx_CONF (cfr 31.8.1):
The first one, called double edge, is based on two edges event programmable through two separate
control registers.
The second one, called single edge, is based on one edge event. In this mode, two additional mode
can be programmed:
The first one, called independent, makes the two complemented output edges programmable in an independent fashion.
The second one, called complementary, makes the two complemented outputs linked to the same edge event.
In each mode, the PWM frequency is programmable and the synchronization with internal CLP
timers is also possible to discriminate noise from off-chip ADC measurements.
For safety purpose, a specific key (cfr KEY field in PWMx_CONF control register) must be written to
provide access the PWM configuration. This allows to avoid any inadvertent write which could
destroy the electronic board.
13.1.1 ENABLE/DISABLE
Each PWM output has an enable bit which is programmed via PWMx_CONF control register (ENABLE
field):
When the PWM is enabled, the outputs PWM_TIMERS[2x+1;2x is activated and obey to their
corresponding PWMx_T1T2 values when the clock cycle following a tick from the selected CLP timer
occurs; The T2 parameter is firstly handled in double edge mode.
When the PWM is disabled or PWM is enabled and the first tick has not been received yet, the
outputs PWM_TIMERS[2x+1;2x is respectively driven to the values of fields OFF_HIGH and
OFF_LOW in PWMx_CONF control registers.
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After the execution of a given duty cycle, if no tick occurs from the selected CLP timer, the
associated PWM_TIMERS[2x+1;2x outputs keep their current states.
13.1.2 PWM FREQUENCY
The PWM frequency of one PWM timer is programmed through PWMx_CONF control register (field
TPERSEL) which points to one of the CLP timer. When working in double edge mode, the frequency is
consequently not handled inside the PWM. The tick period must be programmed to correspond to
half the desired PWM period i.e. the selected tick frequency needs run two times faster than the
desired PWM frequency. In single edge mode, only one tick is needed and defines the full PWM
frequency.
13.1.2.1 DOUBLE-EDGE MODE
In double edge mode, the duty cycle (T1 and T2 parameters in the figure below) of each PWM timer
is programmed via PWMx_T1T2 control register. This one thus has control on signals
PWM_TIMERS[2x+1;2x
T1 fixes the delay between the tick occurrence (from the selected timer tick) to the falling
edge of PWM_TIMER[2x+1.
T2 fixes the delay between the next tick occurrence (from the selected timer tick) to the
falling edge of PWM_TIMER[2x
PWM_TIMER[2i+1]
T PWM
T 1
T noT no
PWM_TIMER[2i]T 2
Tick from selected
timer
(cfr PWMx_CONF)
Figure 19: PWM double edge mode
Note: T2+Tno and T1+Tno must always be less or equal to tick period
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The non-overlapping delay (Tno parameter) between the two complemented outputs is
programmed through PWMx_CONF control register (TNO field), thus having control on signals
PWM_TIMERS[2x+1;2x. When T1 has been handled, Tno fixes the delay between the falling edge of
PWM_TIMER[2x+1 and the rising edge of PWM_TIMER[2xWhen T2 has been handled, Tno fixes
the delay between the falling edge of PWM_TIMER[2x and the rising edge of PWM_TIMER[2x+1. If
no falling edge is present during a timer period (T1=0 or T2=0), the rising edge on the
complementary signal appears after Tno+1 delay following the timer tick.
13.1.2.2 SINGLE-EDGE COMPLEMENTARY MODE
In single edge complementary mode, parameter T1 controls the duty cycle of PWM_TIMER[2x] and
PWM_TIMER[2x+1].
PWM_TIMER[2i]
T PWM
T 1
T noT no
PWM_TIMER[2i+1]
Tick from selected
timer
(cfr PWMx_CONF)
T 1
T noT no
T PWM
Figure 20: PWM single edge complementary mode
The non-overlapping delay (Tno parameter in the figure above) between the two complemented
outputs is programmed through PWMx_CONF control register (TNO field), thus having control on
signals PWM_TIMERS[2x+1;2x.
When T1 has been handled, Tno fixes the delay between the falling edge of
PWM_TIMER[2x and the rising edge of PWM_TIMER[2x
When the next tick appears, Tno fixes the delay between the falling edge of
PWM_TIMER[2x and the rising edge of PWM_TIMER[2x.
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Note that there is always one clock cycle delay between the tick and the generation of the PWM
signals.
Moreover, the user should be aware of the following constraints:
if T1<=Tno is programmed, no rising nor falling edges occurs on PWM_TIMER[2x].
(T1+Tno) and Tno*2 values should always both be smaller and equal to the tick period.
changing Tno values when the associated PWM has been started is not advised.
13.1.2.3 SINGLE-EDGE INDEPEDENT MODE
In single edge independent mode, the value of T1 is used to control the duty cycle of
PWM_TIMER[2x] and T2 is used to control the duty cycle of the PWM_TIMER[2x+1].
PWM_TIMER[2i]
T PWM
T 1
PWM_TIMER[2i+1]
Tick from selected
timer
(cfr PWMx_CONF)
T 2
Figure 21: PWM single edge independent mode
The non-overlapping delay is not handled in this case and, in addition, one clock cycle delay always
occurs between the tick and rising edge of both signals. Note that the user must ensure that T1 and
T2 are both smaller or equal to the tick period
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13.2 I/O SIGNALS
The PWM controls the following CLP inputs/outputs. To enable this interface, the user needs to
program the required IOMUX pins during the boot as described in the pinout table (cfr 21).
I/O NAME I/O/Z WIDTH DESCRIPTION ACTIVE RESET VALUE
PWM_TIMERS[47:0] O 48 Pulse Width Modulation signals N/A 01010..101b
Table 44: PWM I/O signals
13.3 APB INTERFACE
The PWM interface has the following APB address table
APB ADDRESS
(hex) TYPE NAME DESCRIPTION R/W
0x0700 C PWM0_CONF Configures the 1st
PWM timer R/W
0x0701 D PWM0_T1T2 Pulse width timings R/W
0x0702 C PWM1_CONF Configures the 1st
PWM timer R/W
0x0703 D PWM1_T1T2 Pulse width timings R/W
… .. .. .. ..
0x072E C PWM23_CONF Configures the 24th
PWM timer R/W
0x072F D PWM23_T1T2 Pulse width timings R/W
Table 45: PWM APB registers
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14 TIMERS
14.1 OVERVIEW
The CLP includes ten 16-bit timers and two 8-bit prescalers to provide synchronisation between the
software running on each CPU (through the WAITIC instruction) and theses interfaces:
The 24 PWM, to fix the desired frequency
the 2 AWG, to fix the refresh rate
The ADC interface to trigger the acquisition and reading sequence
the DMA of each CPU to trigger the reading of the descriptors
the SPI, to trigger the automated mode
Each timer can be triggered by one of the two prescalers but may also be chained with another timer
thus extending the 16+8-bit maximal size to a larger value (useful to implement timers with order of
magnitude of 1ms to 1 sec).
The CLP timers have a capture capability that can be used to make precise acquisition of an external
signal. Each timer is routed to 10 predefined IOMUX pins and each timer has its specific set of
IOMUX pins. The capture feature provides a copy of timer state and is available via a specific data
register. Note that these IOMUX may also be used to increment or reset the state of the timer.
A watchdog output signal (WDOG_OUT) is also available. This pin is hardwired to TIMER9 tick output
and produces a pulse that is 5 clock cycles wide
14.1.1 PRESCALERS
The two different prescalers take the CLP clock frequency and divide it by the value loaded into the
TIM_PRESC0 and TIM_PRESC1 registers.
When the corresponding field PS0_EN/PS1_EN are asserted, the resulting prescaled clocks are
started on the next clock cycle and generate the base clocks for the timers using it.
When the corresponding field PS0_EN/PS1_EN are deasserted, the resulting prescaled clocks are
reset to 0 (no base clocks events are generated to the timers).
For synchronisation purpose, it is thus mandatory to the user to start the prescalers and timers after
having initialised and configured all the APB peripherals that immediately depend on the ticks that
will be produced.
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14.1.2 TIMERS
Each timer holds a 16-bit counter that is incremented when a specific event occurs. The source of
this event is configured with TIM_CTRLREGx control register (TCKSEL field). It may be incremented
by the first or the second prescaler or by another timer tick (corresponding to the chaining
capability).
Each timer generates a tick and increments its value according to the value programmed in TCKSEL
field in TIM_CTRLREGx register. The possible choices are
when its counter equals the value specified in the TIM_COMPREGx register (COMP field)
when a timer tick selected in control register TIM_CTRLREGx (TIMSEL field) occurs
when a synchronised external tick occurs. In that case, there is a latency of 4 cycles between the external tick occurrence and the internal counter incrementation.
The timer may also be reset according to the value programmed in RSTSEL field in TIM_CTRLREGx
register. The same choices than those with TCKSEL are available.
The capture capability is programmed with TCKSEL field of TIM_CTRLREGx register which selected
the event source which includes the IOMUX pins that are allocated to the timer. The selected trigger
may also be used, if programmed, to automatically clear the counter. This feature thus provides a
mean to synchronise the counter with an external pin. Note that the external signal can be
asynchronous (an internal resynchronisation mean is foreseen). The edge transition type can also be
programmed.
Each timer can select one of the 10 successive IOMUX and use this selection as an external event to
capture the timer state when a rising edge occurs. The corresponding timer value is loaded into the
TIM_CAPREGx register with latency equal to 3 clock cycles.
Each timer can be started or stopped with a single APB transaction. As the timers have a crucial role
in the CLP software, this feature allows to start the CLP software (and loops) in a single-shot fashion.
To ensure a safe software running, it is consequently mandatory to the user to:
initialise all APB registers required by the application including those that will depend in timer ticks
start the needed timers with a single APB write transaction (cfr WRITEAPB instruction). The unused timers are kept frozen.
14.2 I/O SIGNALS
The timers have the following CLP inputs/outputs. To enable this interface, the user needs to
program the required IOMUX pins during the boot as described in the pinout table (cfr 21).
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I/O NAME I/O/Z WIDTH DESCRIPTION ACTIVE RESET VALUE
WDOG_OUT O 1 Timer 9 Watchdog output N/A 0
GPIO[95:0] I 96 GPIO Inputs for Capture N/A N/A
Table 46: Timers I/O signals
14.3 APB INTERFACE
The timers interface has the following APB address table
APB
ADDRESS TYPE REGISTER NAME DESCRIPTION MODE
0x0400 C TIM_STRTFRZ Control register for starting/resetting the prescalers and starting/freezing the timer counters 0 to 9
R/W
0x0401 C TIM_CLR Control register for clearing timer counters 0 to 9
W
0x0402 D TIM_PRESC0 Register holding value for prescaler R/W
0x0403 D TIM_PRESC1 Register holding value for prescaler R/W
0x0410 D TIM_COMPREG0 Register holding comparison value for timer 0 R/W
0x0411 D TIM_CAPTREG0 Register holding captured count for timer 0 R
0x0412 C TIM_CTRLREG0 Register holding control word for timer 0 R/W
... ... ... ... ...
0x04A0 D TIM_COMPREG9 Register holding comparison value for timer 9 R/W
0x04A1 D TIM_CAPTREG9 Register holding captured count for timer 9 R
0x04A2 C TIM_CTRLREG9 Register holding control word for timer 9 R/W
Table 47: Timers APB registers
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15 ADC PARALLEL INTERFACE
15.1 OVERVIEW
The ADC interface allows the CLP to communicate with any general-purpose ADC having a parallel
data bus. The interface is able to handle up to 4 ADC components and to select the adequate
channel sequence through internal control registers and also via ADC_MUXSEL[3:0] outputs (when
different ADC are used on the application board) . Up to 12 simultaneous acquisitions are possible. A
generic interface is implemented so that no (or minimal) glue logic is required between the CLP and
ADC’s. The figure below shows the main principle existing behind the ADC interface:
State
Machine
ADC1
ADC2
ADC3
ADC4
registers
registers
Control
signals
Start-of
convert
APB
control
registers
APB
data
registers
Data
bus
End-of
convert
ADC_MUXSEL
Figure 22: ADC interface architecture
The ADC interface is synchronised with one of the CLP timer whose tick triggers the whole sequence from the sending of the required "start-of-conversion" signals to the various ADC until the automated transfer of the samples from ADC internal buffers up to the APB registers.
The sequence is thus divided in two phases which fully programmable with dedicated APB control registers to adapt to the off-chip parallel interfaces:
the first one, called the "ACQUISITION" phase, which send the required control signals to the ADCs to command a conversion. This sequence ends when all the end-of -conversions signals have been received.
the second one, called "READ SEQUENCE" phase, which sends the required control signals to the ADCs to perform the sequential transfers of the samples to the APB registers. This operation is made through the ADC parallel bus and two different modes are available (one that is asynchronous oriented and one that is synchronous oriented). Up to 12 transfers can be made. To avoid collision between the SW and the transfers, a toggle buffer mode is
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available to segregate the buffer that is being updated with the one available on the SW side. When all programmed readings have been performed, the ADC interface waits for a new tick to restart the procedure.
The picture below illustrates the principle from a macroscopic point of view i.e
ACQUISITION
SEQUENCE
READING
SEQUENCE
TIMER
TICK
END OF
CONVERT(s)
ACQUISITION
SEQUENCE
ADC
PARALLEL
BUS
Figure 23: ADC acquisition and reading sequence
The control of the length and polarities of the various ADC signals (ADCIF_CS[3:0, ADCIF_SOC,...) signals are fully programmable with dedicated APB registers. Note that the polarity is not programmable and always assumes a negative pulse
For the sample transfer from ADCs buffers to the CLP ones, two modes of transfer are defined. The
first one allows to control the polarity and length of signals ADCIF_CS[3:0, ADCIF_RC and
ADCIF_SOC. The second one controls the polarity and length of signals ADCIF_CS[3:0 and ADCIF_RC.
15.1.1 ACQUISITION PHASE
The acquisition phase of the ADC interface is started with the tick produced by the timer
programmed through the control register ADCIF_TIMSEL. On each tick occurrence, the ADC interface
initiates an new acquisition sequence according to the ADCIF_ACQSEL control register and as
depicted in the figure below. Each SELADCx (x=3...0) bit programmed in the ADC_ACQSEL forces the
corresponding ADCIF_CS[x signal to be activated during the ADCIF_SOC pulse. The parameter D0,
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programmed with control register ADCIF_WAFVSEL, determines the length of the pulses as shown in
the figure below
D0
TIMER
TICK
ADCIF_SOC
ADCIF_RC
ADCIF_CS[x
D0 D03 clock cycles
Figure 24: ADC interface acquisition phase
15.1.2 READ SEQUENCE PHASE
The ADC interface initiates the transfer of samples (from the ADC to ADCIF_REGx) when a negative
pulse lasting at least two cycles is detected on inputs ADCIF_EOCB[3..0. Only the ADC selected via
ADC_ACQSEL control register are taken into account. If the EOC (end-of-convert) occurs during the
acquisition phase, the EOC is considered successful and the reading phase is immediately executed
after the end of the acquisition phase.
The ADC interface performs the reading of samples in a sequential fashion and according to control
register ADCIF_READSEL5TO0 and ADCIF_READSEL11TO6. The first reading is determined by value
of READSEL0 field and the last one by READSEL11 field. Whenever a "no read" value is read from the
corresponding READSELx (x=0...11) field, this one is discarded without any effect on I/O signals and
the next field is handled after a one clock cycle latency. Note that a read sequence configured on
ADCIF_CS[x] without the SELADC[x] associated enabled is forbidden.
For the "reading sequence phase", the ADC interface provides two different modes to program the
protocol that transfer the samples from the ADCs internal buffers to the CLP ones (located in
ADCIF_REGx (x=0..11) registers).
The first mode transfer provides control on the polarity and length of signals ADCIF_CS[x (x=0..3),
ADCIF_RC and ADCIF_SOC as depicted in the figure below. The parameter D1 is applied in
accordance with control register ADCIF_WAVFSEL.
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The waveform for mode 1 is depicted in the figure below and corresponds to ONE sample reading. It
is oriented towards synchronous ADC reading
D1
ADCIF_EOC[x]
ADCIF_SOC
ADCIF_RC
ADCIF_CS[x
MODE 0
D1 D1
ADCIF_DATABUS
ADC
Access Time
Data to CLP
CLP shall sample
data here
Last EOC
received, end of
previous read
sequence or end
of acquisition
phase*
New transfer
protocol shall be
reproduced from
here for next
transfer
3 clock cycle
Figure 25: ADC interface read phase - mode 0
* Read sequence starts at the end of the acquisition phase only if the last EOC is received before the
end of the acquisition phase
The second mode provides control on the polarity and length of signals ADCIF_CS[x (x=0..3) and
ADCIF_RC as depicted in the figure below. ADCIF_SOC signal remain low in this mode. The
parameters D1 is applied in accordance with control register ADCIF_WAVFSEL. The waveform for
mode 2 is depicted in the figure below and corresponds to one sample reading. It is oriented
towards asynchronous ADC readings
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D1
ADCIF_EOC[x]
ADCIF_SOC
ADCIF_RC
ADCIF_CS[x
MODE 0
D1 D1
ADCIF_DATABUS
ADC
Access Time
Data to CLP
CLP shall sample
data here
Last EOC
received, end of
previous read
sequence or end
of acquisition
phase*
New transfer
protocol shall be
reproduced from
here for next
transfer
3 clock cycle
Figure 26: ADC interface read phase - mode 1
* Read sequence starts at the end of the acquisition phase only if the last EOC is received before the
end of the acquisition phase
During the transfer of samples, the ADC interface stores the read values to register ADCIF_REGx
(x=0..11) by starting with ADCIF_REG0 and finishing with ADCIF_REGy (y is fixed by the effective
reads programmed in ADCIF_READSEL5TO0 and ADCIF_READSEL11TO6). ADCIF_ACQSEL control
register are used to determine which ADC is used for a given read. When a "no transfer" value (cfr
ADCIF_READSELxtoy) is read from the corresponding READSELx (x=0...11) field, the corresponding
ADCIF_REGx register is not updated and, on the ADC interfaces I/Os, a one clock cycle latency occurs
before the next reading is handled. However, when programming the ADCIF_READSELxTy registers,
the user should guarantee that the value 111b is never used because side effects may occur (the read
sequence duration is not guaranteed).
When the sample reading sequence (programmed in ADCIF_READSEL5TO0/ADCIF_READSEL11TO6)
is finished, the ADC interface wait until the selected timer tick (configured in TIMERSEL of
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ADCIF_TIMERSEL register) occurs. When this event takes place, the ADC interface re-initiates a new
sequence from the beginning of the sampling protocol.
The ADCIF_REGx (x=0..11) buffers are available to the use either directly or via a toggle buffer
mechanism. This feature is controlled through the ADCIF_ACQSEL register (BUFMODE field):
when the toggle buffer mode is set, ADCIF_REGx point to the buffers that have been read on the previous sequence (i.e. the one triggered by the previous timer tick)
when the direct mode is set, ADCIF_REGx point to the buffers that are currently updated on the current sequence
A number of protection mechanisms exist allowing avoiding a deadlock condition. If the selected
timer tick occurs while the sample reading sequences programmed are not finished and if:
the ADC monitoring flag (ADCIF_TIMSEL register MONEN field) is enabled, the current acquisition or reading phase is stopped and a new acquisition sequence is started at the next tick. RSTATCNT2 associated field (bits 7 and 6) is also incremented and a restart (cfr §27.3) is triggered if programmed in RSWREST register
the ADC monitoring flag (ADCIF_TIMSEL register MONEN field) is disabled, the sequence executed continues and the tick is ignored.
15.2 I/O SIGNALS
The ADC interface control the following CLP inputs/outputs. To enable this interface, the user needs
to program the required IOMUX pins during the boot as described in the pinout table (cfr 21).
I/O NAME I/O/Z WIDTH DESCRIPTION ACTIVE RESET VALUE
ADCIF_SOC O 1 ADC start-of-convert (*) 0b
ADCIF_EOCB[3:0] I 4 ADC end-of-conversion Low 1111b
ADCIF_CS[3:0] O 4 ADC chip select (*) 0000b
ADCIF_RC O 1 ADC read/convert (*) 0b
ADCIF_MUXSEL[3:0] O 4 ADC Multiplexor Select (*) 0000b
ADCIF_DATABUS[15:0] I/Z 16 ADC Data input N/A ZZZZh
Table 48: ADC interface I/O signals
(*) programmed via ADCIF_WAVFSEL control register
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15.3 APB REGISTERS
The ADC interface has the following APB registers:
APB ADDRESS
(hex) TYPE NAME DESCRIPTION R/W
0x0800 C ADCIF_TIMSEL timer selection R/W
0x0801 C ADCIF_ACQSEL Acquisition selection R/W
0x0802 C ADCIF_READSEL5TO0 Read sequence selection R/W
0x0803 C ADCIF_READSEL11TO6 Read sequence selection R/W
0x0804 C ADCIF_WAVFSEL Interface selection R/W
0x0810 D ADCIF_REG0 Buffer 0 value R
… ... ... ... ...
0x081B D ADCIF_REG11 Buffer 11 value R
Table 49: ADC interface APB registers
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16 AWG
16.1 OVERVIEW
The CLP has the capability to generate two arbitrary waveforms (called AWG), named AWG0 and
AWG1, intended to generate excitation signals for LVDT and resolver sensors. The main idea is also
to simplify as much as possible the electronics that filters and drives the sensors primary windings.
These AWG may also be used to generate any signal that might be used for a given application or for
reporting purpose
Up to 64 points are programmable per AWG thus providing a full control on the waveform
characteristics. The period between each point is programmable and common for all points. Each
programmable point produces a 12-bit output bus which can be used to command an external DAC.
Each AWG has 4 waveform descriptors, accessed through APB registers AWGx_WFD0,
AWGx_WFD1, AWGx_WFD2 and AWGx_WFD3, allowing to pre-program up to 4 different
waveforms.
Each waveform descriptor allows to
program the period at which the given point are read and applied to the DACx_OUT 12-bit outputs. This frequency is fixed by the TIMER tick period (selected via the TIMSEL field in AWGx_CONF register) multiplied by a multiplication factor determined by field RFDF.
program the number of times that the given waveform descriptor is generated
the base address (first point) and offset (last point) sequentially delimitating the AWGx_PTy points associated to the desired waveform. If the last point is smaller than the first point, the AWGx_PTy will wrap around from point 63 to point 0 and continue until the last point is reached.
which waveform descriptor to use when the current one has been processed
The relation between the timer tick, the enable (DACx_EN), the programmed points and the DAC
outputs is provided in the pictures below.
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D0
TICKxD1
DACx_EN
CLOCK
DACx_OUT
1 clk
D0
D1
1 clk
AWG_PTs AWG_PTs+1
DACx_OUT
AWG_PTs
TPER TPER
AWG_PTs+1
AWG_PTe
AWG_PTe-1
NOTES:
1) TPER = (Timer Period) * RFMF
Where: Timer Period= Tick Period of TIMER selected by TIMSEL control register
2) s = WFBADD value of corresponding waveform descriptor
3) e = WFOFF value of corresponding waveform descriptor
Figure 27: AWG waveform
Note:
After the boot phase, when enabled, each AWG start reading the first programmable point AWGx_PT0 (x=0 or 1) when the first selected timer tick occurs (cfr field TIMSEL in AWGx_CONF control register)
DACx_EN signal is asserted D0+1 clock cycles after the falling edge of the RFDF multiplied Tick event (cfr AWGx_CONF APB register), and during D1 clock cycles.
The user must ensure that D0+D1 are smaller than one tick period
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16.2 IO SIGNALS
The two AWG control the following CLP outputs. To enable this interface, the user needs to program
the required IOMUX pins during the boot as described in the pinout table (cfr 21).
I/O NAME I/O/Z WIDTH DESCRIPTION ACTIVE
RESET
VALUE
DAC0_OUT[11:0] O 12 1st AWG/DAC output N/A b’00..00’
DAC1_OUT[11:0] O 12 2nd
AWG/DAC output N/A b’00..00’
DAC0_EN O 1 DAC0 enable HIGH b’0’
DAC1_EN O 1 DAC1 enable HIGH b’0’
Table 50: AWG I/O signals
16.3 APB INTERFACE
The AWG interface has the following APB address table
APB ADDRESS
(hex) TYPE NAME DESCRIPTION R/W
0x0900 C AWG0_CONF Configures the 1st
AWG R/W
0x0901 C AWG0_WFD0 1st
waveform descriptor for 1st
AWG R/W
… ... ... ...
0x0904 C AWG0_WFD3 4th
waveform descriptor for 1st
AWG R/W
0x0905 C AWG0_STAT Status related to 1st
AWG R
0x0906 C AWG1_CONF Configures the 2nd
AWG R/W
0x0907 C AWG1_WFD0 1st
waveform descriptor for 2nd
AWG R/W
… ... ... ...
0x090A C AWG1_WFD3 4th
waveform descriptor for 2nd
AWG R/W
0x090B C AWG1_STAT Status related to 2nd
AWG R
0x0940 D AWG0_PT0 Programmable point PT0 for 1st
AWG R/W
… .. .. .. R/W
0x097F D AWG0_PT63 Programmable point PT63 for 1st
AWG R/W
0x0980 D AWG1_PT0 Programmable point PT0 for 2nd
AWG R/W
.. .. R/W
0x09BF D AWG1_PT63 Programmable point PT63 for 2nd
AWG R/W
Table 51: AWG APB registers
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17 MMU AND MIL-STD-1553 RT,SPACEWIRES/RMAP AND CAN
17.1 OVERVIEW
The MMU (Memory Management Unit) works in tight interaction with the following CLP peripherals
The MIL-STD-1553 Remote Terminal
The CAN interface
The two Spacewire/RMAP units
In addition, the MMU interacts with two memories called XCHGRAMs which are used by each CPU to
exchange information with the peripherals given above. Each CPU has its own separate XCHGRAM.
The MMU is thus a sort of intelligent router that is configured by software and allows a background
management of these interfaces to/from the two XCHGRAM(s) through a DMA mechanism (not to
be confounded with the one in the CPU). As all interfaces can work in parallel, the MMU also takes
care of arbitrating the various requests and dispatching the data at the required addresses inside the
XCHGRAM according to pre-programmed ranges (under software control) to avoid overlapping of
data.
A number of protection mechanisms are also available to detect any event occurring between the
MMU and the peripherals or to trace an address corruption due to a misconfiguration.
Due to the tight interaction between the MMU and the peripherals, this section will describe how all
these items work. The mentioned peripherals are configured via the MMU and descriptors inside the
XCHGRAM. However, they also have APB registers that must be in line with the MMU and XCHGRAM
configuration. This should be carefully considered by the user.
Note:
the DMA existing between the MMU and the peripherals is based on AMBA AHB protocol.
This DMA bus can be traced via the CLP RTBT for debugging purpose
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17.2 MMU
The CLP MMU is made of a number of status and control registers allowing to control:
The protection logic of each XCHGRAM.
The management of the different interactions coming from the peripherals to/from the XCHGRAMs memories.
Each peripheral handles the XCHGRAM in a different way which is partially linked to the nature of the associated protocol. This section aims to explain to the user how the software needs to configure the MMU to meet its application needs
The MMU implement a static priority scheme. No specific action is needed by the user as the CLP ensures that, at the CLP maximal frequency (cfr section 6.2.3.4.3), there is no data loss on:
The MIL-STD-1553 RT and CAN even when these run with maximal sustained data rate.
The SPACEWIRE/RMAP when the sustained data rate is not greater than 100 Mbit/s (this figure still needs to be confirmed)
Note that:
Whenever the CLP runs with a lower frequency, such features are not guaranteed
These figures apply even when all interfaces are used
The lack of data loss only applies between the MMU and the XCHGRAM. It does not take into account the software which is in charge of processing the data at the required rate.
17.2.1 MEMORY PROTECTION
The MMU provides a protection logic based on the following control registers:
MMU_PROT0_xx, indicating, for each interface, the portion of the XCHG_RAM0 memory that is allocated.
MMU_PROT1_xx, indicating, for each interface, the portion of the XCHG_RAM1 memory that is allocated.
Each of the 4 MMU peripherals (CAN, MIL-STD-1553 RT and both SPACEWIREs) has its own control
registers. The goal is to indicate to the MMU which part of the XCHGRAM portion is authorized to be
used for each peripheral. These control registers consequently do not perform any kind of allocation
but rather serve as safeguards whenever a peripheral attempts to write outside the expected range.
Addresses ranges (i.e the base addresses and lengths) defined by the user in MMU_PROTx_yy
registers must consequently take all transactions generated by the targeted interface to/from the
XCHGRAM(s) into account. This includes the portion of the XCHGRAM(s) that are used for data but
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also for descriptors set and tables (i.e. for the MIL-STD-1553, the sub-address table must also be
considered).
The MMU protection logic does the following operations:
It permanently reads the various base addresses and buffer lengths programmed in MMU_PROTx_xx of each XCHGRAM and checks that these ones do not:
overlap between each other
exceed the size of the XCHGRAM,i.e. 0x2000.
For each XCHG RAM, if an overlap condition occurs, the field PROTOVLP_x associated to the XCHGRAM in MMU_STAT status register is set to '1'.
When a read/write request is detected from one of the peripherals, before making the effective operation from/to the XCHGRAMs, the transfer is locally checked against an out-of-range condition with respect to pre-programmed ranges. The MMU checks the following rule: base address <= XCHGRAM address < base address + length
If rule fails to comply, the transfer is aborted and the "MMU Address Access error saturating counter" in RSTATCNT2 register is incremented. This event may also trigger a software restart (cfr §27.3) if programmed in RSWREST register (in AHB/MMU error field).
When a write access simultaneously occurs on a same XCHG RAM address, the MMU gives priority to the CPU and discards the write operation coming from requesting peripheral. This event may trigger a software restart (cfr §27.3) if the event is programmed in RSWREST register (in MMU simultaneous access error field)
17.2.2 APB INTERFACE
The MMU has the following APB address table:
APB ADDRESS
(hex) TYPE NAME DESCRIPTION R/W
0x1500 Not used
0x1501 C MMU_PROT0_SPW0 MMU transmit buffer memory protection for SpaceWire0 R/W
0x1502 C MMU_PROT0_SPW1 MMU transmit buffer memory protection for SpaceWire1 R/W
0x1503 C MMU_PROT0_1553RT MMU transmit buffer memory protection for MIL-STD-1553 RT R/W
0x1504 C MMU_PROT0_CAN MMU transmit buffer memory protection for CAN R/W
0x1505 Not used
0x1506 C MMU_PROT1_SPW0 MMU receive buffer memory protection for SpaceWire0 R/W
0x1507 C MMU_PROT1_SPW1 MMU receive buffer memory protection for SpaceWire1 R/W
0x1508 C MMU_PROT1_1553RT MMU receive buffer memory protection for MIL-STD-1553 RT R/W
0x1509 C MMU_PROT1_CAN MMU receive buffer memory protection for CAN R/W
0x150A Not used
0x150B S MMU_STAT MMU status R
Table 52: MMU APB registers
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17.3 MANAGEMENT OF INTERACTIONS BETWEEN THE XCHGRAMS AND ITS INTERFACES
17.3.1 MIL-STD-1553 RT
17.3.1.1 BASIC PRINCIPLES
When a 1553 transmit or receive message is received, the MMU accesses the data with a three-level
memory structure.
Basically, the first access is made to verify if the requested sub-address is valid or not. If so, a pointer
is provided to make the next access.
The second access provides the control and status word related to the subaddress, the data pointer indicating where the data should be read (in case of transmit) or written (in case of receive) and the value of the new pointer to be used for the next access to the same subaddress.
The third access is made for the data handling
The diagram below shows an example of how the three-level memory structure used by the 1553
interface is organised in the XCHGRAM. The arrows represent the values of the pointers.
In the example, subaddress N is configured to accept both transmissions and reception, with both
the Data Transmit descriptor pointer and the Data Receive descriptor pointer not being set to 0x3
(this should be reflected in the SA ctrl word as well).In the transmit case, the Next pointer is set to
the same description table, so the same address will be written to the Data Transmit description
pointer at the end of the transaction. All transmit messages will therefore read from the same
address (Data buffer pointer). In the receive case, the Next pointer is set to another description
table, whose Next pointer is set to 0x03. Therefore two messages can be received at this subaddress,
which will be written at two different sub-addresses.
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17.3.1.2 SUB ADDRESS TABLE
The first access is made to the subaddress table whose XCHGRAM first address location is is given in
APB register M1553_SUBADDTAB. The subaddress table contains consecutive descriptors defining
which subaddress and word counts are legal as well as additional configuration bits such as
“broadcast enable” and so on. Each subaddress descriptor is made of 4 words of 32-bits. All the
descriptors are consecutive thus having a global fixed length of 32*4=128 words of 32-bits. Note that
the first 4 words and the last 4 words are never accessed since they correspond to mode codes
which are not handled via the XCHGRAM but rather inside the RT.
The table below shows the details related to the subaddress table
XCHGRAM OFFSET(*)
VALUE
0x04*SA Sub-address SA control word
0x04*SA +1
(**) Transmit descriptor 32-bit AHB pointer (cfr 17.3.1.3 for contents description) in selected XCHGRAM.
Bits 31-17 shall be set to ‘0’
Bits 16 shall be set to
“1”, if the descriptor is in XCHGRAM0.
“0”, if the descriptor in in XCHGRAM1.
Bit 15 has no effect
Bits 14-2 indicate the 13-bit address in XCHGRAM pointing to first data composing the transmit descriptor. Other data are consecutive . When 0x0000 is written, address points to APB address 0x4000. When 0x1FFF is written, address points to APB address 0x5FFF
Bits 1-0 must be set to ‘0’
Note: If Bits 31-0 are set to 0x00000003, it indicates an invalid pointer.
0x04*SA + 2 (**) Receive descriptor 32-bit AHB pointer (cfr 17.3.1.3 for contents description). Interpretation is as per transmit descriptor
0x04*SA +3 unused
Table 53: MIL-STD-1553 subaddress table description
(*) with respect to M1553_SUBADDTAB value
(**) the following formula can be used to program the pointer value
* pointer = (AX*4) +0x10000, if XCHGRAM0 is to be used
* pointer = (AX*4) +0x00000, if XCHGRAM1 is to be used
where AX is the desired 13-bit address in hexadecimal format:
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The sub-address SA control word of subaddress N has the following definition
31
19 18 17 16 15 14
12
8 7
6 5 4
0
NO
T U
SED
WR
AP
IGN
DV
BC
RX
EN
RX
EN
NO
T U
SED
RX
SZ
TX
EN
NO
T U
SED
TX
SZ
The details of the bit fields will be as follows.
BITS FIELD DESCRIPTION
31...19 - Not used. Should be written with zeroe(s) and masked out on read
18 WRAP
Enables a test mode for this subaddress, where transmit transfers send back the last received data. This is done by copying the finished transfer’s descriptor pointer to the transmit descriptor pointer address after each successful transfer.
17 IGNDV
If this is ‘1’ then receive transfers will proceed (and overwrite the buffer) if the receive descriptor has the data valid bit set, instead of not responding to the request. This can be used for descriptor rings where you don’t care if the oldest data is overwritten.
16 BCRXEN Allow broadcast receive transfers to this subaddress (note that broadcast transmit are not allowed and will set the “broadcast command received” bit in the status word)
15 RXEN Allow receive transfers to this subaddress
14 - Not used. MUST be written with zero by user
13 - Not used. MUST be written with zero by user
12..8 RXSZ Maximum legal receive size (RXSZ) to this subaddress - in16-bit words, 0 means 32. Note that sizes smaller than RXSZ will be declared legal by RT.
7 TXEN Transmit enable (TXEN) - Allow transmit transfers from this subaddress
6 - Not used. MUST be written with zero by user
5 - Not used. MUST be written with zero by user
4..0 TXSZ Maximum legal transmit size from this subaddress - in 16-bit words, 0 means 32. Note that sizes smaller than TXSZ will be declared legal by RT.
Table 54: MIL-STD-1553 subaddress control word
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17.3.1.3 TRANSMIT OR RECEIVE DESCRIPTOR
The second access, depending on the value read in the subaddress descriptor, aims to provide the
first address of the transmit or receive descriptor (depending on the nature of the 1553 message
which is handled). This descriptor is made of 3 consecutive 32-bits words. The first word is the
control and status word that will be updated by the RT when the transfer is completed. The second
word gives the data pointer to one of the two XCHGRAMs. The third word indicates the next
descriptor value to be used for next transfer occurring at the same sub-address and for the same
type of transfer (transmit or receive). The same format than the one given in 17.3.1.2 must be
followed as this word will be used to perform the update
The transmit or receive descriptor have the following definition
XCHGRAM
OFFSET (*)
VALUE
0x000 Control and status word (see below for content description)
0x001
(**) Data buffer pointer in XCHGRAM
Bits 31-16 shall be set to ‘0’
Bits 16-15 indicate the XCHGRAM selection:
For receive cases (X=don’t care):
o If “10” is set, data buffer is written in XCHGRAM0.
o If “0x” is set, data buffer is written in XCHGRAM1.
For transmit cases (X=don’t care):
o If “1x” is set, data buffer is read from XCHGRAM0.
o If “0x” is set, data buffer is read from XCHGRAM1.
Bits 14-2 indicate the 13-bit address in XCHGRAM pointing to the first data location. Other data, if any, are consecutive. When 0x0000 is written, address points to APB address 0x4000. When 0x1FFF is written, address points to APB address 0x5FFF. (***). Note that 0x0000003 does not denote an invalid pointer
0x002 Next descriptor in subaddress table pointer. If 0x0000003 is written, it indicates end of list. This value will be written, after the update of Control and Status word, in the subaddress table pointer to update the transmit or receive descriptor for next access.
Table 55: MIL-STD-1553 Tx/Rx descriptor table
(*) with respect to transmit or receive descriptor pointer value
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(**) the following formula can be used to program the pointer value
* pointer = (AX*4) +0x1_0000, if XCHGRAM0 is to be used
* pointer = (AX*4) +0x0_0000, if XCHGRAM1 is to be used
where AX is the desired 13-bit address in hexadecimal format:
(***) When a given receive 1553 message has a word count that is odd, the MIL-STD-1553 RT duplicates the last 16-bit
word to compose the 32-bit data that will be written in the corresponding XCHGRAM address
The Control and Status control word of a given transmit or receive descriptor has the following
definition
31 30 29
26 25
10 9 8
3 2 0
DV
NO
T U
SED
0
TTIM
E
BC
SZ
TRES
The details of the bit fields will be as follows.
BITS FIELD DESCRIPTION
31 DV Should be set to 0 by software before and set to 1 by hardware after transfer. If DV=1 in the current receive descriptor before the receive transfer begins then a descriptor table error will be triggered. You can override this by setting the IGNDV bit in the subaddress table.
30 - Not used. MUST be written with zero by user
29..26 - Not used. Write 0 and mask out on read
25..10 TTIME Set by the 1553 RT to the value of its internal timer when the transfer is finished. The internal timer is 16-bit counter whose resolution is 1 us.
9 BC Set by the 1553 RT if the transfer was a broadcast transfer
8..3 SZ Count in 16-bit words (0-32). Value updated by 1553 RT when transfer is completed. It is never read by the 1553 RT
2..0 TRES
Transfer result written by the 1553 RT:
000 = Success
001 = Superseded (canceled because a new command was given on the other bus)
010 = DMA error or memory timeout occurred
011 = Protocol error (improperly timed data words or decoder error)
100 = The busy bit or message error bit (*) was set in the transmitted status word and no data was sent
101 = Transfer aborted due to loop back checker error
(*) except for the case where the sub-address is not legalised in the SA control word
Table 56: MIL-STD-1553 Control word description
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17.3.1.4 DATA BUFFER
The third access is made to read or write the data buffer. This one starts at the address indicated by
the Data buffer pointer previously read (i.e. the second word of the transmit or receive descriptor)
and follows the big endian representation.
In case of "Transmit" message, the data must be written by the user in the XCHGRAM in the following
way:
the first 16-bit data to be transmitted on the 1553 bus must be written in the 16 MSBs of the first address of the data buffer in the XCHGRAM
the second 16-bit data to be transmitted on the 1553 bus must be written in the 16 LSBs of the first address of the data buffer in the XCHGRAM
the third 16-bit data to be transmitted on the 1553 bus must be written on the 16 MSBs of the second address of the data buffer and so on.
Therefore, if N is the number of words composing the 1553 message, the data buffer in the XCHGRAM is made of N/2 (even case) or (N+1)/2 (odd case) consecutive 32-bit words. If N is odd, the 16 LSB of the last 32-bit word is not used.
In case of "Receive" message, the data is written by the RT in the following way:
the first 16-bit data received from the 1553 bus is written in the 16 MSBs of the first address of the data buffer in the XCHGRAM
the second 16-bit data received from the 1553 bus is written in the 16 LSBs of the first address of the data buffer in the XCHGRAM
the third 16-bit data received from the 1553 bus is written in the 16 MSBs of the second address of the data buffer and so on.
Therefore, if N is the number of words composing the 1553 message, the data buffer in the
XCHGRAM is made of N/2 (even case) or (N+1)/2 (odd case) consecutive 32-bit words. If N is odd, the
16 LSB of the last 32-bit word is duplicated from the 16 MSB (corresponding to the last 1553 data
word)
The user must be aware that after the completion of a transfer, the DV bit in the control and status
word is set by the RT. This feature allows the user to ensure that no transfer is missed for a same sub-
address and transfer type. Therefore, it is up to the software to clear this bit before a new transfer
occurs to the same subaddress otherwise bit RTTE will be raised in the M1553_EVENTREG. This
feature can be by-passed by setting IGNDV field to ‘1’ in the sub-address control word.
In addition, RT allows handling a ring of buffers inside the XCHGRAM for the same sub-address and
transfer type. In other words various data buffer can be stacked at different locations of the
XCHGRAMs if the need arises. This can be done by using the right value in the “Next descriptor value
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of the subaddress descriptor. If M different locations must be used, M different sub-address
descriptors must be programmed in a chained manner. The last descriptor should program value 0x3
in the “next descriptor” value to allow trapping an overflow in the RTTE field of the
M1553_EVENTREG
17.3.1.5 MODE CODES
Mode codes are handled through APB register M15553_MCREG allowing to legalise or not each
possible mode code. There are separate fields for mode code that must be supported in broadcast
or non-broadcast mode. M1553_SYNCREG is specific to the Synchronise or Synchronised with data
word mode codes. M1553_SWRDSREG are specific to the Transmit Vector Word and Transmit BIT
Word mode codes and must be consequently be handled by the user by software. Note that for each
M1553_MCREG field, the value 1x is forbidden. Indeed, side effects may be expected on the
XCHGRAMs. It is therefore up to the user to take care of avoiding such value.
Note that some mode codes are always activated and cannot be disabled. This is the case for the
Synchronize, Transmit Status Word, Transmitter shutdown, Override Transmitter shutdown,
Synchronise with data word and Transmit Last Command
The Reset RT mode code automatically resets the fail-safe timers, transmitter shutdown and inhibits
terminal flag stats. Such mode code can be trapped in the M1553_STAT register. The Synchronise
with data word and Synchronise mode code can also be trapped with M1553_SWRDSREG values.
There is currently no way of detecting that an Initiate Self Test mode code has arrived. Moreover, it
mandatory that the user never sets DBCA bit in M1553_BUSSTAT as this function is restricted to the
RT which would like to take the BC role (which is not the case for the CLP). It consequently
mandantory for the user to let the Dynamic Bus Control mode code disabled (in M1553_MCREG)
17.3.1.6 ADDITIONAL REMARKS
The MMU is capable to sustain the permanent reception of 1553 messages working at the maximal
frequency (1Mbit/s), for any number of word counts and for transmit/receive messages. This
requirement covers the management from the 1553 I/O interfaces up to the writing/reading to the
corresponding XCHG RAMs and for any MMU configuration.
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17.3.2 SPACEWIRE/RMAP
17.3.2.1 BASIC PRINCIPLES
The two CLP Spacewire/RMAP interface supports both Spacewire messages, according to [AD11] and
RMAP messages, according to [AD14]
One CLP Spacewire interface allows to handle up to 64 different transmit messages and up to 64
different receive messages .This is achieved by defining a transmit descriptors table and a receive
descriptors table that are respectively made of 256 (64*4)words and 128 (64*2) words. These tables
are programmed in the XCHGRAMs and may be defined in separate location and XCHGRAM. Each
transmit descriptor is made of 4 consecutive words. Each receive descriptor is made of 2 consecutive
words.
Each table works as a circular buffer. This means that when a message has been transmitted, based
on the content of a given descriptor, the Spacewire interface will automatically send the message
associated to the next descriptor. The same occurs for a message that is being received. This one is
processed according to the current receive descriptor. When the transfer is ended, it automatically
process a new incoming message with the next descriptor of the receive descriptor table. The
transmit and receive tables location and the value of the current descriptor are maintained
respectively in APB registers SPW_CTRL_TADD and SPW_CTRL_RADD. Note that any descriptor can
be enabled/disabled no matter what the value of the current descriptor is
When a Spacewire message is either to be transmitted or is received, the MMU accesses the packet
content with a two-level memory structure. Basically:
The first access is made to read the transmit or receive descriptor and deduce where the data buffer is located in the XCHGRAMs. These descriptor have different lengths.
The second access is made to make the data buffer read or write accordingly. In case of transmission, the header is previously read and processed. The end of the transfer is terminated by updating the status word located in the previously read descriptor
It is up to the user to correctly handle the transmit and receive descriptors and their associated data buffers
The CLP RMAP interface is target on the Spacewire bus. It can be an initiator, unless SW layers are added. It provides a mapping to the XCHGRAMs and support the Read, write and read—modify-write specification in [AD14].
17.3.2.2 RECEVEIVE AND TRANSMIT DESCRIPTORS
Let’s consider a Spacewire message made of N-data bytes and M-header bytes.
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The first access is always made to the corresponding descriptor. If the message has to transmitted,
the Spacewire interface triggers the descriptor reading by regularly polling APB registers
SPWx_DMA_CTRL (holding availability or not of transmit descriptors) and deduce if the user has
requested a transmission of not. If the message is received, the SpaceWire/RMAP interface triggers
the descriptor reading as soon as a valid message is incoming.
When a transfer is triggered, the location of the descriptor in the XCHGRAMS is deduced from APB
register SPWx_DMA_TADD in case of message transmission and from APB register
SPWx_DMA_RADD in case of message reception.
In case of transmit message, the descriptor is made of 4 consecutive words.
The first word gives the header length and must be programmed by the user to valueM. A number of status bits are also available and are updated when the transmission has ended
The second word indicates in which XCHGRAM and at which 13-bit address the header is located.
The third word give the data length and must be programmed by the user to value N
The fourth word indicates in which XCHGRAM and at which 13-bit address the data buffer is located.
After the message transmission, the first word of the descriptor is updated by setting status bit LE The APB register SPWx_STAT is also updated accordingly.
The detail of these descriptors are given below
The 1st transmit descriptor word has the following definition
31 18 17 16 15 14 13 12 11 8 7 0
NO
T U
SED
DC
HC
LE
NO
T U
SED
WR
EN
NO
NC
RC
LEN
HE
AD
ER
LEN
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The details of the bit fields will be as follows.
BITS FIELD DESCRIPTION
31..18 NOT USED
17 DC Append data CRC - Unused. Append CRC calculated according to the RMAP specification after the data sent from the data pointer. The CRC covers all the bytes from this pointer. A null CRC will be sent if the length of the data field is zero.
16
HC
Append header CRC - Unused. Append CRC calculated according to the RMAP specification after the data sent from the header pointer. The CRC covers all bytes from this pointer except a number of bytes in the beginning specified by the non-crc bytes field. The CRC will not be sent if the header length field is zero.
15 LE Link error - A Link error occurred during the transmission of this packet.
14 - NOT USED IN THE CLP
13 WR Wrap - If set, the descriptor pointer will wrap and the next descriptor read will be the first one in the table (at the base address). Otherwise the pointer is increased with 0x10 to use the descriptor at the next higher memory location.
12 EN
Enable - Enable transmitter descriptor. When all control fields (address, length, wrap and crc) are set, this bit should be set. While the bit is set the descriptor should not be touched since this might corrupt the transmission. The GRSPW clears this bit when the transmission has finished.
11..8 NONCRCLEN
Non-CRC bytes - Unused. Sets the number of bytes in the beginning of the header which should not be included in the CRC calculation. This is necessary when using path addressing since one or more bytes in the beginning of the packet might be discarded before the packet reaches its destination.
7..0 HEADERLEN Header length - Header Length in bytes. If set to zero, the header is skipped.
Table 57: Spacewire 1st transmit descriptor description
The 2nd transmit descriptor word has the following definition
31 0
HEA
DER
AD
DR
ESS
The details of the bit fields will be as follows.
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BITS FIELD DESCRIPTION
31..0 HEADERADDRESS
Header - The XCHGRAM and address from where the packet header is fetched. Does not need to be word aligned
If Bit 14-13 = “01”, the header is in XCHGRAM0.
If Bits 14-13 =“10”, the header is in XCHGRAM1.
Bits 12-0 are the 13-bit base address in XCHGRAM(s).
Table 58: Spacewire 2nd transmit descriptor description
The 3rd transmit descriptor word has the following definition
31
24
23 0
NO
T U
SED
DA
TALE
N
The details of the bit fields will be as follows.
BITS FIELD DESCRIPTION
31..24 NOT USED
23..0 DATALEN
Data length - Length of data part of packet. If set to zero, no data will be sent. If both
data- and header-lengths are set to zero no packet will be sent.
Table 59: Spacewire 3rd transmit descriptor description
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The 4th transmit descriptor word has the following definition
31 0
DA
TAA
DD
RES
S
The details of the bit fields will be as follows.
BITS FIELD DESCRIPTION
31..0 DATAADDRESS
Data address - The XCHGRAM and address from where data is read. Does not need to be word aligned
If Bit 14-13 = “01”, the data is in XCHGRAM0.
If Bits 14-13 =“10”, the data is in XCHGRAM1.
Bits 12-0 are the 13-bit base address in XCHGRAM(s).
Table 60: Spacewire 4th transmit descriptor description
In case of receive message, the descriptor is made of 2 consecutive words.
The first word gives the header length and must be programmed to value M. A number of status bits are also available and are updated when the transmission has ended. To enable the descriptor , the user needs to set field EN to ‘1’
The second word indicates in which XCHGRAM and at which 13-bit address the data buffer starts.
The 1st receive descriptor Word has the following definition
31 30 29 28 27 26 25 24
0
TR
DC
HC
EP
NO
T U
SED
WR
EN
PA
CK
ETLE
NG
TH
The details of the bit fields will be as follows.
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BITS FIELD DESCRIPTION
31 TR Truncated - Packet was truncated due to maximum length violation.
30 DC Data CRC - Unused. 1 if a CRC error was detected for the data and 0 otherwise
29 HC Header CRC - Unused. 1 if a CRC error was detected for the header and 0 otherwise
28 EP EEP termination - This packet ended with an Error End of Packet character
27 - NOT USED ON THE CLP
26 WR
Wrap - If set, the next descriptor used by the GRSPW will be the first one in the descriptor table (at the base address). Otherwise the descriptor pointer will be increased with 0x8 to use the descriptor at the next higher memory location. The descriptor table is limited to 1 kbytes in size and the pointer will be automatically wrap back to the base address when it reaches the 1 kbytes boundary.
25 EN Enable - Set to one to activate this descriptor. This means that the descriptor contains valid control values and the memory area pointed to by the packet address field can be used to store a packet
24..0 PACKETLENGT
H Packet length - The number of bytes received to this buffer. Only valid after EN has been set to 0 by the GRSPW.
Table 61: Spacewire 1st receive descriptor description
The 2nd receive descriptor has the following definition:
31
0
PA
CK
ETA
DD
RES
S
Table 62: Spacewire 2nd receive descriptor description
17.3.2.3 HEADER AND DATA BUFFERS
The second access is made to read or write the data and header (in case of transmission) buffers.
In case of transmission, the header buffer is read starting from the address indicated by the pointer
in the 2nd descriptor word. The header length is taken into account and according to field
HEADERLEN previously read from the 1st descriptor word. When the header is transmitted, the
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packet buffer is read starting from the address indicated by the pointer in the 4th descriptor word.
The packet length is taken into account and according to field DATALEN previously read from the 3rd
descriptor word.
In case of reception, only the packet buffer is handled. This one is written starting from the address
indicated by the pointer in the 2nd descriptor word. The packet length is taken into account and
according to field PACKETLEN previously read from the 3rd descriptor word. If the number of packets
received exceeds this filed, field TR will be updated in the 1st descriptor word.
After the message reception, the first word of the descriptor is updated by setting status bits EEP, DC, HC and TR. The APB register SPWx_STAT is also updated accordingly.
17.3.2.4 RMAP MESSAGES
When a SpaceWire Write-Command RMAP frame made of N data bytes to be written starting from
32-bit address A, is received, the SpaceWire/RMAP interface manage the access to the data in a
straight addressing fashion. It writes N/4 consecutive words starting from address A<12:0> and for
each write, perform the operation into:
XCHGRAM0, if A<14:13>="10"
XCHGRAM1, if A<14:13>="01"
Both XCHGRAMs, if A<14:13>="11"
When a SpaceWire Read-Command RMAP frame, made of a starting 32-bit address A and length N,
is received, the SpaceWire/RMAP interface manage the access to the data in a straight addressing
fashion, it reads N consecutive words starting from address A<12:0> and, for each reading, performs
the operation into:
XCHGRAM0, if A<14:13>="10"
XCHGRAM1, if A<14:13>="01"
When a SpaceWire Read-Modify-Write Command RMAP frame, made of N data bytes to be written
starting from 32-bit address A, is received, the SpaceWire/RMAP interface manage the access to the
data in a straight addressing fashion. It writes N/4 consecutive words starting from address A<12:0>
and for each reading, perform the operation into:
XCHGRAM0, if A<14:13>="10"
XCHGRAM1, if A<14:13>="01"
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17.3.2.4.1.1 PERFORMANCE
The MMU is capable to sustain the permanent reception OR transmission of Spacewire messages
working up to 20 Mbit/s. This feature covers the data flow from the Spacewire I/O interfaces up to
the writing/reading to the corresponding XCHG RAM (or conversely) and when the three other MMU
interfaces are simultaneously used
The MMU is capable to sustain the permanent reception OR transmission of Spacewire messages
working up to 200 Mbit/s. This feature covers the data flow from the Spacewire I/O interfaces up to
the writing/reading to the corresponding XCHG RAMs and when no other MMU interface is
simultaneously used
17.3.3 CAN
17.3.3.1 BASIC PRINCIPLES
When a CAN message, made of N bytes, is received, the CAN interface manage the access to the
data with a two-level memory structure organised as a dedicated circular buffer whose read pointer
is managed by the software and write pointer is managed by the CAN interface. This one
successively:
reads the values held in APB registers CAN_RCAR (holding the buffer 13-bit base address and XCHGRAM location), CAN_RCSIZE (holding the buffer maximal length), CAN_RCWRREG (holding the buffer write pointer) and CAN_RCRDREG (holding the buffer read pointer)
write 2+N/4 consecutive words corresponding to the CAN message content and according to the XCHGRAM mapping presented in §17.3.3.2. The write address is determined by the following formula:
(CAN_RCCREG[12:0]+CAN_RCWRREG[12:0]) modulo CAN_RCSIZE[14:0]
When a CAN message has to be transmitted, the CAN interface manage the access to the data with
a two-level memory structure organised as a dedicated circular buffer whose write pointer is
managed by the software and read pointer is managed by the CAN interface. This one successively:
Read the values held in APB registers CAN_TRAR (holding the buffer 13-bit base address and XCHGRAM location), CAN_TRSIZE (holding the buffer maximal length), CAN_TRWRREG (holding the buffer write pointer) and CAN_TRRDREG (holding the buffer read pointer)
Read 2+N/4 consecutive words corresponding to the CAN message content and according to the XCHGRAM mapping presented in §17.3.3.2. The read address is determined by the following formula:
(CAN_TRAR[12:0]+CAN_TRRDREG[12:0]) modulo CAN_TRSIZE[14:0]
Sends the corresponding frame on the physical layer
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17.3.3.2 XCHGRAM MAPPING
In both receive and transmit cases, the CAN message is mapped inside the XCHGRAM(s) in the following way:
Values: Levels according to CAN standard: 1b shall be recessive, 0b shall be dominant
Legend: Naming and number according to CAN standard
Bits
XCHG_RAM
OFFSET
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x0
IDE
RTR
bID eID
0x1
DLC
TxErrCntr RxErrCntr
AH
BEr
r
OR
OFF
PA
SS
0x2
Byte 0 (transmitted or received first)
Byte 1 Byte 2 Byte 3
0x3
Byte 4 Byte 5 Byte 6 Byte 7 (transmitted or
received last)
Table 63: CAN messages mapping in XCHGRAM
The details of the bit fields will be as follows.
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Field Meaning Description
IDE Identifier Extension 1b for Extended Format, 0b for Standard Format
RTR Remote Transmission
Request 1b for Remote Frame, 0b for Data Frame
bID Base Identifier Base Identifier
eID Extended Identifier Extended Identifier
DLC Data Length Code
According to CAN standard: 0000b 0 bytes 0001b 1 byte 0010b 2 bytes 0011b 3 bytes 0100b 4 bytes 0101b 5 bytes 0110b 6 bytes 0111b 7 bytes 1000b 8 bytes OTHERS illegal
TxErrCntr Transmission Error
Counter Transmission Error Counter
RxErrCntr Reception Error
Counter Reception Error Counter
AHBErr AHB Error AHB interface blocked due to AHB Error when 1b
OR Over Run Reception Over run when 1b
OFF Bus Off Bus Off mode when 1b
PASS Passive Error Passive mode when 1b
Byte 0 to 7 Data Transmit/Receive data, Byte 0 first Byte 7 last
Table 64: CAN messages fields details
17.3.3.3 PERFORMANCE
The MMU is capable to sustain the permanent transmission and reception of CAN messages working
at the maximal frequency (1Mbit/s), for any number of lengths. This feature covers the
management from the CAN I/O interfaces up to the writing/reading to the corresponding XCHG
RAMs and for any MMU configuration.
17.4 IO SIGNALS
None. The function is purely internal
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18 MIL-STD-1553 RT
18.1 OVERVIEW
The CLP provides a Remote Terminal compliant with MIL-STD-1553B communication. It is aimed to
be interfaced with a transceiver and transformers, which are in charge of handling electrical levels,
and therefore covers the “link” layer (OSI level 2) of the standard. The output levels are thus limited
to the standard 0-3.3V.
The CLP Remote Terminal allows to:
Automatically handle the signals received or to be transmitted on the 1553 bus through the transceiver
To provide the user the required SW interface allowing to configure the RT behaviour and read its status
Exchange the data transiting on the 1553 bus via the two XCHG RAMs
Program location of sub-address table
Control the various descriptors indicating where the data can be read/written
Enable the required mode codes
The Remote Terminal controller handles the standard main and redundant busses defined in MIL-
STD-1553B standard (bus A and bus B).
18.1.1 COMPLIANCE TO MIL-STD-1553 STANDARD
The MIL-STD-1553 RT is fully compliant with the Remote Terminal operation. The Bus Controller and Bus Monitor operations are not supported by the CLP.
18.1.2 COMPLIANCE TO ECSS-E-ST-50-13C STANDARD
The CLP being targeted for ESA applications, a mean to provide to the user the full or partial
compliance with ECSS-E-ST-50-13C requirements (cfr AD7) is needed. Some of AD7 requirements can
exclusively be implemented by hardware (in the sense of PCB design rules and adequate component
choice). Other ones can only be made with software.
The following list describes to the user how the compliance to AD7 can be ensured for ESA
applications. This is achieved by indicating, for each section of AD7, how fulfilment is met and by
which mean (HW or SW). The SW implementation is let to the responsibility of the user.
The section 5 of AD7 is related to the physical layer requirements and is under the responsibility of the PCB designer
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The CLP Remote Terminal is compliant with section 6.2 (Data Words and messages)
In particular, for mode code 8 (cfr 6.2.1.2.2 in AD7), the CLP Remote Terminal resets itself automatically and such event is reported in the MMU_STAT status register
The MIL-STD-1553 RT interface is compliant (with the software) with section 8.2.2.2 (Time Synchronise primitive) of AD7. Such event is reported in M1553_SYNCREG
The MIL-STD-1553 RT interface is compliant (with the software) with sections 8.3.1.2 and 8.3.2.2 (Communication Synchonisation service) of AD7.
The CLP Remote Terminal is compliant with section 6.3 (Terminal Operation) of A76
The CLP Remote Terminal is compliant with section 6.4 (Subaddress usage) of AD7. The table 6-1 is configured by SW
The section 7 of AD7 is related to the services requirements and is thus strictly related to SW
The section 8 of AD7 is related to the protocol requirements and is thus mainly related to SW.
Note, as requested by section 6.5 (Message Retries) of AD7, the MIL-STD-1553 RT interface will not
support Message retries
18.1.3 INTERACTION WITH XCHGRAMS, MMU AND SOFTWARE
The interaction is explained in section 17.3.1
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18.2 IO SIGNALS
The MIL-STD-1553 RT interface controls the following CLP outputs
Table 65: MIL-STD-1553 I/O signals
18.3 APB INTERFACE
The MIL-STD-1553 RT interface has the following APB address table
APB ADDRESS
(hex) TYPE NAME DESCRIPTION R/W
0x1300 C/S M1553_EVENTREG (*) 1553 RT Event Register R/W
0x1302 S M1553_HWCONF 1553 RT Hardware Configuration Register R
0x1320 S M1553_STATREG 1553 RT Status Register R
0x1321 C M1553_CONFREG 1553 RT Configuration Register R/W
0x1322 S M1553_BUSSTAT 1553 RT Bus Status Register R/W
0x1323 C M1553_SWRDSREG 1553 RT Status Words register R/W
0x1324 S M1553_SYNCREG 1553 RT Synchronisation register R
0x1325 C M1553_SUBADDTAB 1553 RT Sub Address Table register R/W
0x1326 C M1553_MCREG 1553 RT Mode commands register R/W
Table 66: MIL-STD-1553 APB registers
(*) these registers are IRQ-related control registers from the 1553 RT. No IRQ is available on the CLP but M1553_EVENTREG can be used by software with a polling mechanism.
I/O NAME I/O/Z WIDTH DESCRIPTION ACTIVE RESET VALUE
M1553_RTADDR[4:0 I 5 1553 RT Address High N/A
M1553_RTADDRP I 1 1553 RT Address parity bit High N/A
M1553_RTADDRERR O 1 1553 RT Address error High 0
M1553_BUSAINEN I 1 1553 RT Bus A input enable High N/A
M1553_BUSAINP I 1 1553 RT Bus A positive input High N/A
M1553_BUSAINN I 1 1553 RT Bus A positive input Low N/A
M1553_BUSBINEN I 1 1553 RT Bus B input enable High N/A
M1553_BUSBINP I 1 1553 RT Bus B positive input High N/A
M1553_BUSBINN I 1 1553 RT Bus B positive input Low N/A
M1553_BUSAOUTIN O 1 1553 RT Bus A output inhibit Low 1
M1553_BUSAOUTP O 1 1553 RT Bus A positive output High 0
M1553_BUSAOUTN O 1 1553 RT Bus A negative output Low 1
M1553_BUSBOUTIN O 1 1553 RT Bus B output inhibit Low 0
M1553_BUSBOUTP O 1 1553 RT Bus B positive output High 1
M1553_BUSBOUTN O 1 1553 RT Bus B negative output Low 0
M1553_CLK I 1 1553 Clock high N/A
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19 CAN
19.1 OVERVIEW
The CLP contains a CAN interface that complies with the ISO 11898-1:2003 document.
One channel (implemented as a circular buffer) is supported for receive messages and one channel (also implemented with a circular buffer) for transmit messages. Both channels will be located in the XCHGRAMs and according to the configuration programmed with dedicated APB registers
Note: an additional channel for receive and transmit message is implemented in the design but these ones have never been tested.
19.1.1 INTERACTION WITH XCHGRAMS, MMU AND SOFTWARE
The interaction is explained in section 17.3.1
19.2 APB INTERFACE
The CAN interface has the following APB address table
APB
ADDRESS
(hex)
TYPE NAME DESCRIPTION R/W
0X1200 C CAN_CONF Configuration Register R/W
0X1201 C CAN_STAT Status Register R
0X1202 C CAN_CTRL Control Register R/W
0X1206 C CAN_SYMF
SYNC Mask Filter Register R/W
0X1207 C CAN_SYNC
SYNC Code Filter Register R/W
0X1280 C CAN_TRCR Transmit Channel Control Register W
0X1281 D CAN_TRAR Transmit Channel Address Register R/W
0X1282 D CAN_TRSIZE Transmit Channel Size Register R/W
0X1283 D CAN_TRWRREG Transmit Channel Write Register R/W
0X1284 D CAN_TRRDREG Transmit Channel Read Register R/W
0X12C0 C CAN_RCCR Receive Channel Control Register R/W
0X12C1 D CAN_RCAR Receive Channel Address Register R/W
0X12C2 D CAN_RCSIZE Receive Channel Size Register R/W
0X12C3 D CAN_RCWRREG Receive Channel Write Register R/W
0X12C4 D CAN_RCRDREG Receive Channel Read Register R/W
0X12C6 D CAN_RCMR Receive Channel Mask Register R/W
0X12C7 D CAN_CODR Receive Channel Code Register R/W
Table 67: CAN APB registers
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20 SPACEWIRE/RMAP
20.1 OVERVIEW
The CLP has two Spacewire interface that conform to the SpaceWire -ECSS-E-ST-50-12C
(31July2008) standard These CPUs is used to connect the CLP to Spacewire-enabled peripherals via
a Spacewire network. RMAP is used to set configuration registers, to read status information and to
read from or write data to memory in the units. The two CPUs is viewed by other nodes on the
Spacewire network, as two separate nodes. The two CPUs have Spacewire Initiator as well as Target
node capabilities.
The Spacewire interfaces conform to the SpaceWire LVDS encode-decoder specification described in
AD10 and whose applicable clauses are section 6 (Signal Level), section 7 (Character Level), section 8
(Exchange Level) and section 9 (Packet Level)
The Spacewire interface, in particular, support the SpaceWire system time distribution according to
clause 8.12 of AD10
The timings related to data and strobe skew/jitters are provided in section 9.1
20.2 ECSS-E-ST-50-12C COMPLIANCE
The two Spacewire interfaces conform to the SpaceWire RMAP target only specification of the AD14
document whose requirements are provided in section 5.7.1.3
The two Spacewire interfaces conform to the SpaceWire RMAP Write specification of the AD14
document and whose clauses are the protocol identifier in clause 5 of ECSS-E-ST-50-51C, section 5.3
(Write command) and section 5.6 (Error codes)
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The two Spacewire interfaces support the following RMAP write command
ACTION SUPPORTED MAXIMUM DATA LENGTH (bytes)
NON-ALIGNED ACCESS ACCEPTED
8-bit write No - -
16-bit write
No -
32-bit write
Yes 16 No
64-bit write
no
Verified Write yes 16
Word or byte address Word, 32-bit aligned
Endian order Big endian
Accepted logical addressses
0xFE after power-on or during boot
After boot it is Software configurable.
Target logical addresses What was in command
Accepted keys 0x30
Accepted address ranges
0x2000 to 0x3FFF (write XCHG RAM 1)
0x4000 to 0x5FFF (write XCHG RAM 2)
0x6000 to 0x7FFF (write to both XCHG RAMs)
0xF000 to 0xF004 (during boot only and for BOOT_FRAME)
Address incrementation Incrementing address only
Status codes returned All
Table 68: Spacewire/RMAP write command description
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The Spacewire interfaces conform to the SpaceWire RMAP Read specification of the AD14
document and whose clauses are the protocol identifier in clause 5 of ECSS-E-ST-50-51C, section 5.5
(Read command) and section 5.6 (Error codes)
The two Spacewire interfaces support the following RMAP read command
ACTION SUPPORTED MAXIMUM DATA LENGTH (bytes)
NON-ALIGNED ACCESS ACCEPTED
8-bit write No - -
16-bit write
No -
32-bit write
Yes 16 No
64-bit write
no
Verified Write yes 16
Word or byte address Word, 32-bit aligned
Endian order Big endian
Accepted logical addressses
0xFE after power-on or during boot
After boot it is Software configurable.
Target logical addresses Logical address of target
Accepted keys 0x30
Accepted address ranges
0x2000 to 0x3FFF (write XCHG RAM 1)
0x4000 to 0x5FFF (write XCHG RAM 2)
0xF000 to 0xF004 (during boot only)
Address incrementation Incrementing address only
Status codes returned All
Table 69: Spacewire/RMAP read command description
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The two Spacewire interfaces conform to the SpaceWire RMAP Read-Modify-Write specification of
the AD14 document and whose clauses are the protocol identifier in clause 5 of ECSS-E-ST-50-51C,
section 5.4 (Read-Modify-Write command) and section 5.6 (Error codes)
The two Spacewire interfaces support the following RMAP RMW (Read-Modify-Write) command
ACTION SUPPORTED MAXIMUM DATA LENGTH (bytes)
NON-ALIGNED ACCESS ACCEPTED
8-bit wire No - -
16-bit write
No -
32-bit write
Yes 16 No
64-bit write
no
Verified Write yes 16
Word or byte address Word, 32-bit aligned
Endian order Big endian
Accepted logical addressses
0xFE after power-on or during boot
0x40 after boot
Target logical addresses Logical address of target
Accepted keys 0x30
Accepted address ranges
0x2000 to 0x3FFF (write XCHG RAM 1)
0x4000 to 0x5FFF (write XCHG RAM 1)
0xF000 to 0xF004 (during boot only)
Note: RMW to both XCHG RAMS is not possible
Address incrementation Incrementing address only
Status codes returned All
Table 70: Spacewire/RMAP read-modify-write command description
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20.3 I/O SIGNALS
The Spacewire controls the following CLP inputs/outputs
I/O NAME I/O/Z WIDTH DESCRIPTION ACTIVE RESET VALUE
SPW_DIN1H I 1 Spacewire#1 Data In High High 1
SPW_DIN1L I 1 Spacewire#1 Data In Low Low 0
SPW_SIN1H I 1 Spacewire#1 Strobe In High High 1
SPW_SIN1L I 1 Spacewire#1 Strobe In Low Low 0
SPW_DOUT1H O 1 Spacewire#1 Data Out High High 1
SPW_DOUT1L O 1 Spacewire#1 Data Out Low Low 0
SPW_SOUT1H O 1 Spacewire#1 Strobe Out High High 1
SPW_SOUT1L O 1 Spacewire#1 Strobe Out Low Low 0
SPW_DIN2H I 1 Spacewire#2 Data In High High 1
SPW_DIN2L I 1 Spacewire#2 Data In Low Low 0
SPW_SIN2H I 1 Spacewire#2 Strobe In High High 1
SPW_SIN2L I 1 Spacewire#2 Strobe In Low Low 0
SPW_DOUT2H O 1 Spacewire#2 Data Out High High 1
SPW_DOUT2L O 1 Spacewire#2 Data Out Low Low 0
SPW_SOUT2H O 1 Spacewire#2 Strobe Out High High 1
SPW_SOUT2L O 1 Spacewire#2 Strobe Out Low Low 0
Table 71: Spacewire I/O signals
20.4 APB INTERFACE
The first Spacewire terminal is configured through the following registers
APB
ADDRESS
(hex)
TYPE NAME DESCRIPTION R/W
0x1000 C SPW0_CTRL Control R/W
0x1001 C SPW0_STAT Status source R/W
0x1002 C SPW0_NOD_ADD Node address R/W
0x1003 C SPW0_CLK_DIV Clock divisor R/W
0x1004 C SPW0_DST_KEY Destination key R/W
0x1005 C SPW0_TIM Time R/W
0x1008 C SPW0_DMA_CTRL DMA channel 1 control/status R/W
0x1009 D SPW0_DMA_LEN DMA channel 1 rx maximum length R/W
0x100A D SPW0_DMA_TADD DMA channel 1 transmit descriptor table address R/W
0x100B D SPW0_DMA_RADD DMA channel 1 receive descriptor table address R/W
0x100C D SPW0_DMA_ADD DMA channel 1 address register R/W
Table 72: Spacewire0 APB registers
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The second Spacewire terminal is configured through the following registers
APB
ADDRESS
(hex)
TYPE NAME DESCRIPTION R/W
0x1100 C SPW1_CTRL Control R/W
0x1101 C SPW1_STAT Status -source R/W
0x1102 C SPW1_NOD_ADD Node address R/W
0x1103 C SPW1_CLK_DIV Clock divisor R/W
0x1104 C SPW1_DST_KEY Destination key R/W
0x1105 C SPW1_TIM Time R/W
0x1108 C SPW1_DMA_CTRL DMA channel 1 control/status R/W
0x1109 D SPW1_DMA_LEN DMA channel 1 rx maximum length R/W
0x110A D SPW1_DMA_TADD DMA channel 1 transmit descriptor table address R/W
0x110B D SPW1_DMA_RADD DMA channel 1 receive descriptor table address R/W
0x110C D SPW1_DMA_ADD DMA channel 1 address register R/W
Table 73: Spacewire1 APB registers
20.5 INTERACTION WITH XCHGRAMS, MMU AND SOFTWARE
The interaction is explained in section 17.3.2
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21 IOMUX
21.1 OVERVIEW
The IOMUX pins provide a flexible IO multiplexing capability. Up to 106 pins are available and can be
internally routed to the various CLP on-chip peripherals.
The configuration of IOMUX pins is only accessible during the boot. It must be made by commanding
a write of the desired value to 13 specific APB addresses. These ones are only accessible on APB0.
Note that when the boot is finished and the software running on either CPU0 or CPU1, any attempt
to modify IOMUX is discarded.
Each IOMUX pin is controlled with a dedicated control register IOMUXPINxTOy which also controls
the configuration of the 7 others IOMUX. Thereare 4 fields that are available and that must be
programmed to have a dedicated IOMUX routing. These are GSEL, PSEL, INEN and OE_MASK
The user must mandatorily follow these rules to correctly program IOMUX pins (to be read in
conjunction with table below) :
When GSEL=1 (PSEL, INEN are don’t care),the IOMUX cell routes IOMUX pin to the associated GPIO which is controlled by software with GPIO_MODExTOy, GPIO_OZxTOy and GPIO_INVALxTOy (cfr 12)
When GSEL=0, PSEL=0 and OE_MASK=1 (INEN is don’t care), the IOMUX cell routes IOMUX to P0_OUT (output mode).
When GSEL=0, PSEL=1 and OE_MASK=1 (INEN is don’t care), the IOMUX cell routes the IOMUX pin to P1_OUT(output mode) .
When INEN=1 and PSEL=0 (GSEL and OE_MASK are don’t care), the IOMUX cell routes IOMUX pin to PO_IN (input mode)
When INEN=1 and PSEL=1 (GSEL and OE_MASK are don’t care), the IOMUX cell routes IOMUX pin to P1_IN (input mode)
After the reset, each IOMUX is set into high impedance until boot is finished. The configured IOMUX
are then taken into account. If no IOMUX has been configured during boot, each IOMUX is set to
GPIO
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PIN
P0_IN
P0_OUT
P1_IN
P1_OUT
GPIO
RESET VALUE
(OE_MASK, GSEL, PSEL, INEN)
BOOT VALUE
(OE_MASK, GSEL, PSEL, INEN)
0 NC PWM0_H NC PWM0_H YES 4h 4h
1 NC PWM0_L NC PWM0_L YES 4h 4h
2 NC PWM1_H NC PWM1_H YES 4h 4h
3 NC PWM1_L NC PWM1_L YES 4h 4h
4 NC PWM2_H NC PWM2_H YES 4h 4h
5 NC PWM2_L NC PWM2_L YES 4h 4h
6 NC PWM3_H NC PWM3_H YES 4h 4h
7 NC PWM3_L NC PWM3_L YES 4h 4h
8 NC PWM4_H NC PWM4_H YES 4h 4h
9 NC PWM4_L NC PWM4_L YES 4h 4h
10 NC PWM5_H NC PWM5_H YES 4h 4h
11 NC PWM5_L NC PWM5_L YES 4h 4h
12 NC PWM6_H NC PWM6_H YES 4h 4h
13 NC PWM6_L NC PWM6_L YES 4h 4h
14 NC PWM7_H NC PWM7_H YES 4h 4h
15 NC PWM7_L NC PWM7_L YES 4h 4h
16 NC PWM8_H NC PWM8_H YES 4h 4h
17 NC PWM8_L NC PWM8_L YES 4h 4h
18 NC PWM9_H NC PWM9_H YES 4h 4h
19 NC PWM9_L NC PWM9_L YES 4h 4h
20* NC PWM10_H NC PWM10_H YES 4h ch
21* NC PWM10_L NC PWM10_L YES 4h ch
22* NC PWM11_H NC PWM11_H YES 4h ch
23* NC PWM11_L NC PWM11_L YES 4h ch
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PIN
P0_IN
P0_OUT
P1_IN
P1_OUT
GPIO
RESET VALUE
(OE_MASK, GSEL, PSEL, INEN)
BOOT VALUE
(OE_MASK, GSEL, PSEL, INEN)
24* NC PWM12_H NC DAC0_OUT[0] YES 4h ch
25* NC PWM12_L NC DAC0_OUT[1] YES 4h ch
26* NC PWM13_H NC DAC0_OUT[2] YES 4h ch
27* NC PWM13_L NC DAC0_OUT[3] YES 4h ch
28* NC PWM14_H NC DAC0_OUT[4] YES 4h ch
29* NC PWM14_L NC DAC0_OUT[5] YES 4h ch
30* NC PWM15_H NC DAC0_OUT[6] YES 4h ch
31* NC PWM15_L NC DAC0_OUT[7] YES 4h ch
32* NC PWM16_H NC DAC0_OUT[8] YES 4h ch
33* NC PWM16_L NC DAC0_OUT[9] YES 4h ch
34* NC PWM17_H NC DAC0_OUT[10] YES 4h ch
35* NC PWM17_L NC DAC0_OUT[11] YES 4h ch
36* NC PWM18_H NC DAC1_OUT[0] YES 4h ch
37* NC PWM18_L NC DAC1_OUT[1] YES 4h ch
38* NC PWM19_H NC DAC1_OUT[2] YES 4h ch
39* NC PWM19_L NC DAC1_OUT[3] YES 4h ch
40* NC PWM20_H NC DAC1_OUT[4] YES 4h ch
41* NC PWM20_L NC DAC1_OUT[5] YES 4h ch
42* NC PWM21_H NC DAC1_OUT[6] YES 4h ch
43* NC PWM21_L NC DAC1_OUT[7] YES 4h ch
44* NC PWM22_H NC DAC1_OUT[8] YES 4h ch
45* NC PWM22_L NC DAC1_OUT[9] YES 4h ch
46* NC PWM23_H NC DAC1_OUT[10] YES 4h ch
47* NC PWM23_L NC DAC1_OUT[11] YES 4h ch
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PIN
P0_IN
P0_OUT
P1_IN
P1_OUT
GPIO
RESET VALUE
(OE_MASK, GSEL, PSEL, INEN)
BOOT VALUE
(OE_MASK, GSEL, PSEL, INEN)
48* NC NC NC NC YES 4h ch
49* NC NC NC NC YES 4h ch
50 NC WDOG_OUT NC WDOG_OUT YES 0h 0h
51 NC M1553_RTADDRERR NC M1553_RTADDRERR YES 4h 4h
52 M1553_BUSAINP NC M1553_BUSAINP NC YES 4h 4h
53 M1553_BUSAINN NC M1553_BUSAINN NC YES 4h 4h
54 M1553_BUSBINP NC M1553_BUSBINP NC YES 4h 4h
55 M1553_BUSBINN NC M1553_BUSBINN NC YES 4h 4h
56 NC M1553_BUSAINEN NC M1553_BUSAINEN YES 4h 4h
57 NC M1553_BUSAOUTIN NC M1553_BUSAOUTIN YES 4h 4h
58 NC M1553_BUSAOUTP NC M1553_BUSAOUTP YES 4h 4h
59 NC M1553_BUSAOUTN NC M1553_BUSAOUTN YES 4h 4h
60 NC M1553_BUSBINEN NC M1553_BUSBINEN YES 4h 4h
61 NC M1553_BUSBOUTIN NC M1553_BUSBOUTIN YES 4h 4h
62 NC M1553_BUSBOUTP NC M1553_BUSBOUTP YES 4h 4h
63 NC M1553_BUSBOUTN NC M1553_BUSBOUTN YES 4h 4h
64 NC DAC0_EN NC DAC0_EN YES 4h 4h
65 NC DAC1_EN NC DAC1_EN YES 4h 4h
66 UART_RX0 CAN_TX UART_RX0 NC YES 4h 8h
67 CAN_RX NC CAN_RX UART_TX0 YES 4h 8h
68 UART_RX1 CAN_SEL UART_RX1 NC YES 4h 8h
69 NC UART_TX1 NC UART_TX1 YES 4h 4h
70 UART_RX2 ADCIF_SOC UART_RX2 ADCIF_SOC YES 4h 4h
71 NC UART_TX2 NC UART_TX2 YES 4h 4h
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PIN
P0_IN
P0_OUT
P1_IN
P1_OUT
GPIO
RESET VALUE
(OE_MASK, GSEL, PSEL, INEN)
BOOT VALUE
(OE_MASK, GSEL, PSEL, INEN)
72 UART_RX3 NC I2C_SDA I2C_SDA YES 4h 4h
73 I2C_SCL UART_TX3 I2C_SCL I2C_SCL YES 4h 4h
74 SPI0_CLK SPI0_CLK SPI0_CLK SPI0_CLK YES 4h 4h
75 SPI0_MOSI SPI0_MOSI ADCIF_EOC[0] NC YES 4h 4h
76 SPI0_CSI NC ADCIF_EOC[1] NC YES 4h 4h
77 SPI0_GMISO SPI0_GCSO ADCIF_EOC[2] NC YES 4h 4h
78 SPI0_MISO[0] SPI0_CSO[0] ADCIF_EOC[3] NC YES 4h 4h
79 SPI0_MISO[1] SPI0_CSO[1] M1553_RTADDR[0] ADCIF_CS[0] YES 4h 4h
80 SPI0_MISO[2] SPI0_CSO[2] M1553_RTADDR[1] ADCIF_CS[1] YES 4h 4h
81 SPI0_MISO[3] SPI0_CSO[3] M1553_RTADDR[2] ADCIF_CS[2] YES 4h 4h
82 SPI0_MISO[4] SPI0_CSO[4] M1553_RTADDR[3] ADCIF_CS[3] YES 4h 4h
83 SPI0_MISO[5] SPI0_CSO[5] M1553_RTADDR[4] ADCIF_RC YES 4h 4h
84 SPI0_MISO[6] SPI0_CSO[6] M1553_RTADDRP ADCIF_MUXSEL[0] YES 4h 4h
85 SPI0_MISO[7] SPI0_CSO[7] SPI0_MISO[7] ADCIF_MUXSEL[1] YES 4h 4h
86 SPI0_MISO[8] SPI0_CSO[8] SPI0_MISO[8] ADCIF_MUXSEL[2] YES 4h 4h
87 SPI0_MISO[9] SPI0_CSO[9] SPI0_MISO[9] ADCIF_MUXSEL[3] YES 4h 4h
88 SPI0_MISO[10] SPI0_CSO[10] ADCIF_DATABUS_I[0] NC YES 4h 4h
89 SPI0_MISO[11] SPI0_CSO[11] ADCIF_DATABUS_I[1] NC YES 4h 4h
90 SPI1_CLK SPI1_CLK ADCIF_DATABUS_I[2] NC YES 4h 4h
91 SPI1_MOSI SPI1_MOSI ADCIF_DATABUS_I[3] NC YES 4h 4h
92 SPI1_CSI NC ADCIF_DATABUS_I[4] NC YES 4h 4h
93 SPI1_GMISO SPI1_GCSO ADCIF_DATABUS_I[5] NC YES 4h 4h
94 SPI1_MISO[0] SPI1_CSO[0] ADCIF_DATABUS_I[6] NC YES 4h 4h
95 SPI1_MISO[1] SPI1_CSO[1] ADCIF_DATABUS_I[7] NC YES 4h 4h
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PIN
P0_IN
P0_OUT
P1_IN
P1_OUT
GPIO
RESET VALUE
(OE_MASK, GSEL, PSEL, INEN)
BOOT VALUE
(OE_MASK, GSEL, PSEL, INEN)
96 SPI1_MISO[2] SPI1_CSO[2] ADCIF_DATABUS_I[8] NC NO 4h 4h
97 SPI1_MISO[3] SPI1_CSO[3] ADCIF_DATABUS_I[9] NC NO 4h 4h
98 SPI1_MISO[4] SPI1_CSO[4] ADCIF_DATABUS_I[10] NC NO 4h 4h
99 SPI1_MISO[5] SPI1_CSO[5] ADCIF_DATABUS_I[11] NC NO 4h 4h
100 SPI1_MISO[6] SPI1_CSO[6] ADCIF_DATABUS_I[12] NC NO 4h 4h
101 SPI1_MISO[7] SPI1_CSO[7] ADCIF_DATABUS_I[13] NC NO 4h 4h
102 SPI1_MISO[8] SPI1_CSO[8] ADCIF_DATABUS_I[14] NC NO 4h 4h
103 SPI1_MISO[9] SPI1_CSO[9] ADCIF_DATABUS_I[15] NC NO 4h 4h
104 SPI1_MISO[10] SPI1_CSO[10] SPI1_MISO[10] SPI1_CSO[10] NO 4h 4h
105 SPI1_MISO[11] SPI1_CSO[11] SPI1_MISO[11] SPI1_CSO[11] NO 4h 4h
Table 74: IOMUX table
(*) These IOMUX are also mapped to MEM8 interface (cfr §12.3)
Notes:
NC stands for ‘Not connected’
Boot Value correspond to the (OE_MASK, GSEL, PSEL, INEN) values of each pin during the boot.
Reset Value correspond to the (OE_MASK, GSEL, PSEL, INEN) default values of each pin after the boot (unless modified during the boot).
For the Reset and Boot Values:
value 4h corresponds to ( OE_MASK=0, GSEL=1, PSEL=0, INEN=0)
Value Ch correspond to (OE_MASK=1, GSEL=1, PSEL=0, INEN=0)
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21.2 APB INTERFACE
The IOMUX interface have the following APB address table
APB ADDRESS
(hex) TYPE NAME DESCRIPTION R/W
0x6100 C IOMUX_PIN7TO0 IOMUX[7:0] pins configuration R /W(*)
0x6101 C IOMUX_PIN15TO8 IOMUX[15:8] pins configuration R /W(*)
0x6102 C IOMUX_PIN23TO16 IOMUX[23:16] pins configuration R /W(*)
0x6103 C IOMUX_PIN31TO24 IOMUX[31:24] pins configuration R /W(*)
0x6104 C IOMUX_PIN39TO32 IOMUX[39:32] pins configuration R /W(*)
0x6105 C IOMUX_PIN47TO40 IOMUX[47:40] pins configuration R /W(*)
0x6106 C IOMUX_PIN55TO48 IOMUX[55:48] pins configuration R /W(*)
0x6107 C IOMUX_PIN63TO56 IOMUX[63:56] pins configuration R /W(*)
0x6108 C IOMUX_PIN71TO64 IOMUX[71:64] pins configuration R /W(*)
0x6109 C IOMUX_PIN79TO72 IOMUX[79:72] pins configuration R /W(*)
0x610A C IOMUX_PIN87TO80 IOMUX[87:80] pins configuration R /W(*)
0x610B C IOMUX_PIN95TO88 IOMUX[95:88] pins configuration R /W(*)
0x610C C IOMUX_PIN103TO96 IOMUX[103:96] pins configuration R /W(*)
0x610D C IOMUX_PIN105TO104 IOMUX[105:104] pins configuration R /W(*)
Table 75: IOMUX APB registers
(*) Write enabled during boot only
21.2.1.1 I/O SIGNALS
The IOMUX interface routes the following CLP inputs/outputs
I/O NAME I/O/Z WIDTH DESCRIPTION ACTIVE RESET VALUE
IOMUX[105:0] I/O/Z 105 IO Multiplexing pins N/A Z...Zb
Table 76: IOMUX I/O signals
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22 CLOCK AND RESET CONTROL
22.1 OVERVIEW
In order to limit the power consumption, the boot provides access to the clock and resets of various
peripherals. When the software is running, no further modification is possible.
The clock and reset control are accessible for write on APB0 bus only. The values of the clock and
reset status are readable on both APB0 and APB1.
Note :
The RTBT clock and reset is controlled by the external pin IF_CONFIG[5].
The clock of the GPIO controller, IOMUX, the timers and the APB manager are not gated.
During the boot sequence the clocks of the Boot manager and CRC are unconditionally driven.
During the CPU active phase the Boot manager clock is not driven.
To ensure there will be no invalid configuration, the MMU enables its clock and exit reset when at least one of the following bits (SPW0_CLK, SPW1_CLK, CAN_CLK or M1553_CLK) is set.
The intercom ram is accessible for read or write operations when the CPU connected to the corresponding port is fed with a clock.
22.2 APB REGISTERS
The following mapping is used on the APB bus.
APB
ADDRESS
(hex)
TYPE NAME DESCRIPTION R/W
0x6200 C CLOCKCTRL CLOCK GATES CONTROL R/W (*)
0x6201 C RESETCTRL RESET CONTROL R/W (*)
(*)= write—enabled during boot only
Table 77: clock and reset control APB registers
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23 PROGRAM RAM
23.1 OVERVIEW
The CLP contains two program RAMs, one being dedicated to each CPU. Each program RAM is dual-port and accessible on the APB bus or via the RMEM register (cfr 7.1.7 transfers operations in CPU). The size of each program RAM is 32768x(32+7)bits (the 7 bits are for the EDAC management).
From the hardware point of view, all the program RAM memory space is available to its CPU. That means that the code that is running may be altered if an inadvertent write occurs. However, a segmented architecture is proposed to restrict portions of this memory to the program code. Only the writing is disabled in that case. Each program RAM is segmented in 16 portions.
Note that:
The reading of any address is always possible on both sides even if a segment is write-protected.
The write-protection only applies to an APB access since, on the fetch side, only reading is possible.
The simultaneous reads to identical addresses is possible
A simultaneous read and write to the same address (but on different ports) is possible. The read provides the previous value (before the write).
The limit of the Code size corresponds to the RAM size.
23.2 I/O SIGNALS
The PROGRAM RAM is internal. There are no I/O signals
23.3 APB INTERFACE
The Program RAM of each CPU has the following APB address table
APB ADDRESS
(hex) TYPE NAME DESCRIPTION R/W SEGMENT
0x8000 D PRAM_ADD0 Address 0 of PROGRAM RAM R/W
1 0x8001 D PRAM_ADD1 Address 1 of PROGRAM RAM R/W
.. .. .. .. ..
0x87FF D PRAM _ADD2047 Address 2047 of PROGRAM RAM R/W
0x8800 D PRAM _ADD2048 Address 2048 of PROGRAM RAM R/W
2 .. .. .. .. ..
0x8FFF D PRAM _ADD4095 Address 4095 of PROGRAM RAM R/W
.. .. .. .. ..
.. .. .. .. .. ..
.. .. .. .. ..
.. .. .. .. ..
16 .. .. .. .. ..
0xFFFE D PRAM _ADD32766 Address 32766 of PROGRAM RAM R/W
0xFFFF D PRAM _ADD32767 Address 32767 of PROGRAM RAM R/W
Table 78: Program RAM APB registers
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24 XCHG RAM
24.1 OVERVIEW
The CLP contains two XCHG RAMs, each one being dedicated to one CPU. Each XCHGRAM is dual-port and has a size equal to 8192x32+7bits (the 7-bits are for the EDAC management). One port is accessible by the CPU whereas the other port is accessible by the CPU APB bus.
Note that:
A simultaneous read and write to the same address (but on different ports) is possible. The read provide the previous value (before the write).
The simultaneous reads to identical addresses is possible
A simultaneous write gives priority to the CPU (MMU operation is discarded)
24.2 I/O SIGNALS
The XCHGRAMs are internal. There are no I/O signals
24.3 APB INTERFACE
The two XCHGRAMs have the following APB address table
APB ADDRESS
(hex) TYPE NAME DESCRIPTION R/W
0x4000 D XCHGRAM_ADD0 Address 0 of XCHG RAM R/W
0x4001 D XCHGRAM_ADD1 Address 1 of XCHG RAM R/W
.. .. .. .. ..
0x5FFF D XCHGRAM _ADD8191 Address 8191 of XCHG RAM R/W
Table 79: XCHGRAM APB registers
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25 HW STATUS AND CONFIGURATION
25.1 OVERVIEW
Several dedicated pins are foreseen to provide external access to hardware configuration and CLP
status.
25.1.1 CPU HARDWARE STATUS
The CLP has the following 6 output pins CPU_STAT[5:0] allowing to provide a hardware reporting on
the CPU state:
5 4 3 2 1 0
Boot Manager and CPU state Last Boot Event
The fields have the following definition:
Bit(s) Name Values
5:2 Boot Manager
and CPUs State
*
State Encoding
RESET_ON_ST 0001b
RESET_OFF_ST 0010b
INIT_BD_TABLE_ST 0011b
CHECK_BD_TABLE_CRC_ST 0100b
PROCESS_1ST_BD_ST 0101b
CHECK_1ST_BD_CRC_ST 0110b
PROCESS_2ND_BD_ST 0111b
CHECK_2ND_BD_CRC_ST 1000b
PROCESS_3RD_BD_ST 1001b
CHECK_3RD_BD_CRC_ST 1010b
PROCESS_4TH_BD 1011b
CHECK_4TH_BD_CRC 1100b
CPU0 and CPU1 ACTIVES 1101b
CPU0_ACTIVE 1110b
CPU1_ACTIVE 1111b
ERROR_ST 0000b
1:0 Last Boot Event
Encoding
Boot after Hardware reset 00b
Boot after SWRST detection
(cfr SWRST instruction)
01b
Boot after restart condition
(cfr RSWREST register definition)
10b
Table 80: CPU_STAT description
(*) CPU_STAT has one clock cycle delay with the Boot manager state and CPU state.
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25.1.2 BOOT DESCRIPTORS SELECTION
The CLP has the following 3 input pins allowing to indicate the boot manager from which source it
initialise the boot descriptors (cfr section 27 for further details).
PIN NAME DESCRIPTION WIDTH
BDINIT_SEL[2..0] Selection of source for boot descriptors 3
BDINIT_SELP Odd parity bit 1
The BDINIT_SEL[2:0] inputs have the following definition.
BDINIT_SEL [2:0] SOURCE
000b SPACEWIRE0
001b SPACEWIRE1
010b MEM8
011b CAN
1XXb RTBT
Table 81: BDINIT_SEL[2:0] description
25.1.3 INTERFACE HARDWARE ENABLING
The CLP has the following 6 input pins allowing to enable or disable a number of CLP interfaces
PIN NAME DESCRIPTION WIDTH
IF_CONFIG[0] MIL-STD-1553 RT enable/disable 1
IF_CONFIG[1] CAN interface enable/disable 1
IF_CONFIG[2] SPACEWIRE0 enable/disable 1
IF_CONFIG[3] SPACEWIRE1enable/disable 1
IF_CONFIG[4] SPARE 1
IF_CONFIG[5] RTBT enable/disable 1
Table 82: IF_CONFIG description
The input pin "MIL-STD-1553 RT activation" controls the activity of the MIL-STD-1553 Remote
Terminal function according to the pin state which support the following values
'1': enables the use of the MIL-STD-1553 Remote Terminal function
'0': applies a permanent reset AND disables the clock (through clock-gating) of the MIL-STD-1553 Remote Terminal function
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The input pin "CAN interface activation"controls the activity of the two CAN interface function
according to the pin state which support the following values :
'1': enables the use of the two CAN interface function
'0':applies a permanent reset AND disables the clock (through clock-gating) of the CAN interface function
The input pin "Spacewire0 activation" controls the activity of the 1st Spacewire interface according
to the pin state which support the following values :
'1':enables the use of the 1st Spacewire interface function
'0':applies a permanent reset AND disables the clock (through clock-gating) of the 1st Spacewire function
The input pin "Spacewire1 activation" controls the activity of the 2nd Spacewire interface according
to the pin state which support the following values :
'1': enables the use of the 2nd Spacewire interface function
'0': applies a permanent reset AND disables the clock (through clock-gating) of the 2nd Spacewire function
The input pin "RTBT activation" controls the activity of the two RTBT interfaces according to the pin
state which support the following values :
'1':enables the use of the real-timer background function
'0':applies a permanent reset AND disables the clock (through clock-gating) of the real-time background trace function
The CLP control the output signal WDOG_OUT by unconditionally setting it to
'1': if a tick a occurred on TIMER9. The state is kept until the CLP is reset or if a SW restart (cfr §27.3) is executed
'0':otherwise
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25.2 I/O SIGNALS
The HW Status and configuration control the following CLP inputs/outputs
I/O NAME I/O/Z WIDTH DESCRIPTION ACTIVE RESET VALUE
CPU_STAT[5:0] O 6 CPU 0 and 1 status words N/A 000100b *
BDINIT_SEL[2:0] I 3 Boot descriptor initialisation selection N/A N/A
BDINIT_SELP I 1 Boot descriptor selection (odd) parity N/A N/A
IF_CONFIG[5:0] I 6 Interfaces specific HW configurations LOW N/A
WDOG_OUT O 1 Watchdog output LOW Ob
Table 83: HW status and configuration I/O signals
* Value corresponds to the state of pins while the CLP hardware reset is active (RESET_BAR is 0).
25.3 APB REGISTERS
No APB registers is foreseen. This function is completely hardwired and interaction from the software is possible.
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26 SCRUBBING MANAGEMENT
26.1 OVERVIEW
For fault management, the CLP provides the possibility to configure a scrubbing manager for the
INTERCOM RAM, the XCHGRAMs and the PROGRAM RAMs to automatically handle the correction of
recoverable error. These errors are based on the EDAC mechanism that is embedded in each
memory. The range of addresses to verify as well as the period of verification (through a timer
selection) is configurable.
Two modes are possible and can be programmed according to the application needs:
The first mode activates the scrubbing which performs sequential readings in background and writes-back the right value whenever a correctable error.
The second mode only works if the scrubbing is disabled. In that case, the reading depends on the software and the memory readings that are performed. Whenever a correctable error is found, the right value is written back “on-the-fly” when possible.
This second mode (fully described in §7.4.3) is sufficiently efficient for applications that ensure that
all the addresses of a given memory are regularly fetched. Most CLP applications should be cyclic
and thus naturally avoid SEU error accumulation. However, this may not always be the case.
Applications using data tables are one example. In that case, the scrubbing mechanism should be
programmed.
In both modes, when the software reads a given address, the EDAC correction towards the reader (i.e. the CPU via the APB bus or the MMU via its internal bus) is always activated and made “on-the-fly”. The access is not interrupted and thus transparent for the user
The Intercom RAM has a scrubbing manager on each port. It does the corrections on this same port.
Each XCHG RAM has a scrubbing manager that monitors each APB port and does the corrections on
this same port.
Each Program memory has a scrubbing manager that monitors the CPU instruction fetching
mechanism and does the corrections on the other port (to avoid stalling the CPU).
26.1.1 SCRUBBING PRINCIPLE
The scrubbing capability is activated via SCRUB_ACT field in control register xxx_SCR_CTRL (cfr
31.16.2).
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The scrubbing manager is then started by programming the field SCRUB_PER in control register
xxx_SCR_CTRL with a period that is not equal to 0. This field programs the scrubbing frequency as a
number of ticks coming from one of the CLP timers selected through SCRUB_TMR field from
xxx_SCR_CTRL register.
The scrubbing procedure checks every address located in the range configured in the corresponding
scrubbing address register. It reads the current address and writes the corrected data back if a
recoverable error is detected. The associated counter is incremented in that case (cfr RSTATCNT2).
Note:
a write-back correction on an address being simultaneously written by the software is discarded when the scrubbing is activated.
Note that scrubbing may increase the CLP consumption. To limit it, it is mandatory to correctly set the refresh rate in field SCRUB_PER.
The RGPx registers in unit A/B of both CPUs have no scrubbing mechanism. Therefore, it should be monitored by SW designed by the user if the target application needs it.
26.2 APB REGISTERS
The following APB registers are available to control the scrubbing of each CLP memory (except RGP0 to RGP511 in A/B units)
APB ADDRESS
(hex) TYPE NAME DESCRIPTION R/W
0x6300 C CPU0_SCR_ADDR CPU0 PRAM scrubbing range register R/W
0x6301 C CPU0_SCR_CTRL CPU0 PRAM scrubbing control register R/W
0x6302 C CPU1_SCR_ADDR CPU1 PRAM scrubbing range register R/W
0x6303 C CPU1_SCR_CTRL CPU1 PRAM scrubbing control register R/W
0x6304 C ICOM0_SCR_ADDR Intercom RAM CPU0 side scrubbing range register R/W
0x6305 C ICOM0_SCR_CTRL Intercom RAM CPU0 side scrubbing control register R/W
0x6306 C ICOM1_SCR_ADDR Intercom RAM CPU1 side scrubbing range register R/W
0x6307 C ICOM1_SCR_CTRL Intercom RAM CPU1 side scrubbing control register R/W
0x6308 C XCHG0_SCR_ADDR XCHGRAM0 scrubbing range register R/W
0x6309 C XCHG0_SCR_CTRL XCHGRAM0 scrubbing control register R/W
0x630A C XCHG1_SCR_ADDR XCHGRAM1 scrubbing range register R/W
0x630B C XCHG1_SCR_CTRL XCHGRAM1 scrubbing control register R/W
Table 84: Scrubbing APB registers
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27 BOOT MANAGER
27.1 OVERVIEW
The CLP boot principle is divided into two steps, each one being managed by the CLP boot manager.
The first step allows to initialise a boot descriptors table. This one is made of 4 registers of 32-bits
which are physically available on the APB0 bus. These fields indicate from where and how the boot
must be performed. Each field will be dedicated to one boot thus providing up to 4 tentatives. The
boot descriptors table is loaded from one of the 5 available sources which are:
one of the two Spacewire links (set in RMAP mode),
the 8-bit interface(MEM8) configurable through the GPIO pins
the CAN interface
the Real-Time Background Tracer (RTBT).
The selection is determined by hardware and through the BDINIT_SEL[2:0] input pins. The boot
source parity bit must be set on pin BDINIT_SELP. BDINIT_SEL[2:0] and BDINIT_SELP are verified
with an odd parity logic.
The initialisation of the boot descriptors is explained below and is accompanied by a CRC verification
thus ensuring that the table content is coherent.
The second step is dedicated to initialise the CLP resources, i.e. the CPU program memories and the
APB registers, according to the programmed content of the boot descriptors table. The boot
manager firstly relies on the 1st boot descriptor and continuously read the stream coming from a
given source (whose source is programmed in the boot descriptor) until a specific command is
received (i.e. EOB). The input stream is organised in frames, called BOOT_FRAME in the text, whose
definition is common to all possible sources (one of Spacewires links, CAN, RTBT or 8-bit interface on
the GPIO). The incoming stream is translated into APB transactions (one per BOOT_FRAME) thus
making the boot manager a "bridge" between the external device and the CLP APB busses. The boot
procedure, based on the 1st boot descriptor, is protected against any discrepancy through a CRC. A
time-out mechanism can also be programmed (programmed in the boot descriptor and not available
if boot comes from the RTBT). If any error occurs, the boot manager jumps to the 2nd boot
descriptor and repeats the procedure. Up to 4 boot tentatives can thus be programmed within the
CLP.
The diagram below depicts the architecture of the boot manager in conjunction with the possible
boot sources and the BOOT_FRAME buffer
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PRAM1
PRAM0SPW0
SPW1
CAN
RTBT
APB
bus 0
APB
bus 1
AHB
AH
B
SL
AV
E
BOOT DESCRIPTOR #1
BOOT DESCRIPTOR #2
BOOT DESCRIPTOR #3
BOOT DESCRIPTOR #4
MEM8GPIO
BOOT
MANAGER
BOOT
FRAME buffer
MMU
[DB2]
Figure 28: Boot manager architecture
During the execution of the software, if a SWRST instruction is detected or a restart condition (cfr
§27.3) - enabled by SW - occurs (unrecoverable SEU, etc...), the boot manager automatically
performs a reboot. The difference with the boot occurring after a hardware reset is that the
BDINIT_SEL[2:0] pins will not be managed and the 1st boot descriptor will be immediately read and
processed.
It should be noted that the boot descriptors are write-enabled when the SW is running (it is up to the
user to enable the Write Protection if needed). After the boot, the SW has consequently the ability to
modify how he would like the CLP to react on a SWRST instruction or restart condition. The SW also
has access to the last descriptor that has been successfully handled by the boot manager. The
information is located in RSTATCNT1 while RSTATG1 contains the value of BDINIT_SEL[2:0] read by
the boot manager.
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27.2 USER INTERACTION
The following figure presents the boot manager state machine.
Each state value is available:
in real-time on CPU_STAT[5:2] pins (cfr 25.1.1).
For the MEM8 and RTBT, state can be read using the RTBT frames.
RESET_ON
RESET_OFF
INIT_BD_TABLE
CHECK_BD_TABLE_CRC
EOB detected
others
PROCESS_1ST_BD
CRC ok
others
PROCESS_2ND_BD
others
CHECK_1ST_BD_CRC
EOB detected CRC error
CHECK_2ND_BD_CRC
EOB detected
PROCESS_3RD_BD
others
CHECK_3RD_BD_CRC
EOB detectedCRC error
PROCESS_4TH_BD
others
CHECK_4TH_BD_CRC
EOB detectedCRC error
CPU_ACTIVE
CRC ok CRC ok CRC okCRC ok
RSTSW detected OR
restart condition detectedERROR
CRC error
CRC error
Figure 29: Boot manager state machine
Notes: From states INIT_BD_TABLE, PROCESS_1st_BD, PROCESS_2nd_BD, PROCESS_3rd_BD and,
PROCESS_4th_BD the transition to ERROR state may be possible. However, for readability, it has not
been drawn. When the CAN or SpaceWire is source, the state value can be read using a Boot Frame
containing a read operation. For the RTBT, the state can be read using the commands available
during upload (UPLOAD_COMMANDS, etc…cfr §28.5.3).
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27.2.1 FIRST STEP
When the CLP is turned on, the boot manager automatically reads the BDINIT_SEL pins and checks
their odd parity with BDINIT_SELP. If the parity is correct and PLL is correctly started (PLL_LOCK pin =
‘1’), it goes into the INIT_BD_TABLE state and waits for a command coming from the selected
source. At that moment, the first step (explained in §27.1) starts. The goal is then to initialise the
boot descriptors to the desired values.
To send a command to the boot manager, the user needs to set the BOOT_FRAME to the desired state. The BOOT_FRAME is an 8 bytes buffer described in §0 and whose content allow triggering four different commands via specific values mapped on the last byte:
start of boot, called SOB,
APB write command to a given address (to a single or both APBs if needed),
APB read command from a given address (either on APB0 or APB1),
end of boot, called EOB
To initialize the boot descriptors, the user must sequentially send the following commands to the
boot manager:
1. One SOB
2. 4 APB write command to the boot descriptor APB addresses (cfr 31.11.1) with the desired values
3. Any other APB reading or writing. Note that writing to an address different than the Boot Descriptors is not allowed in this step, and the state will be set to ERROR
4. One EOB with the correct CRC value
At that moment, the boot manager will check the CRC and set its state to CHECK_BD_TABLE_CRC. If
the CRC is correct, it will go the PROCESS_1ST_BD state (it will go to ERROR otherwise). The second
step of the boot process is then triggered.
27.2.2 SECOND STEP
The boot manager will read the first boot descriptor, interpret it, set its state to PROCESS_1ST_BD
and wait for commands coming from the selected source
The commands expected follow the same principles than for the first step. The user must
sequentially send the following commands to the boot manager:
One SOB
The desired number of APB write commands allowing to
initialise the PRAM with the desired SW for the desired CPU(s)
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configure the various APB registers
Any other APB reading that is desired.
One EOB with the correct CRC value in line with all APB write and read commands
When the EOB is received, the boot manager will check the CRC and set its state to
CHECK_1ST_BD_CRC. If the CRC is correct, it will go the CPU_ACTIVE state and the CLP will start
running. If the CRC is not correct, the state will go to CHECK_2nd_BD and the rules above will apply to
perform the 2nd boot tentative and so on. If all tentative fail, the state will be set to ERROR. A reset
on RESET_BAR will be needed to restart the CLP
When a restart or SWREST instruction is executed, the boot manager resets the two CPUs and starts
back from CHECK_1ST_BD (cfr §27.3). Note that boot descriptors are available in read and write by
the allocated CPU (if AL/WP bits have been correctly set). This allows the software to handle the
boot descriptors and thus reprogram how it reboots.
During the whole boot sequence, the CLP pins remain in high impedance (except for those used by
the boot source) thus cutting the device from the external world. When the boot manager is in
CPU_ACTIVE, the CLP upload is completed and:
The CLP IOMUX pins are set back to low impedance and apply the configuration programmed during the boot via IOMUX table (cfr §21) · If the boot source was MEM8, the associated GPIO pins are set back to their post-reset values·
If at least one of the "Clock and Reset Control" registers is correctly configured during the boot (cfr §22), the respective(s) CPU(s) reset are released and the CPU(s) start executing the code located in their respective PRAM from address 0. If both CPU(s) are not correctly configured (either Clock was not enabled or reset was not released), the boot manager unconditionally jumps to ERROR state.
This part is the key one which allows the user to have the full control over the CLP before it is started.
The full knowledge of APB resources is thus necessary are presented in this document. The section 31
presents all the APB registers that are available. The user must take into account the reset values
that are given to have the correct snapshot of the CLP when the boot is finished.
A few constraints or remarks must however be highlighted to the user:
Regarding the CRC used during the first and second steps of the boot, the CRC0 unit constantly spies any write transaction occurring on one of both APB busses to guarantee the integrity of the upload. Both data and address are pushed inside the CRC with the 32-bit data being firstly handled followed by the 16-bit address (padded with zeroes on the MSBs). If both APB busses are simultaneously accessed, only APB0 is taken into account. Therefore, the CRC computed by the user must take account of this feature.
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if the CRC0 polynomial needs to be changed, the new value is taken into account after the boot. During Boot the predefined polynomial is always used ("x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1") and there is no way to alter it.
WP/AL programmed during the boot are effective after the boot i.e. any modification on the allocation or write protection are not taken into account during the boot
Before writing to the XCHGRAMs and PRAMs, the associated CPU clock and reset must be configured in the Clock and Reset Control.
IOMUX must be programmed by the user in accordance with interfaces (and APB registers) that are needed
The table describing the various APB peripherals should be carefully used as some of these peripherals are exclusively located on APB1
It is up to the user to manually re-initialise the APB registers of a respective interface/peripheral after each Boot Tentative or SWRST by writing to the "Clock and Reset Control" registers using Boot frames.
27.3 RESTART PROCEDURE
the restart procedure is triggered which makes the boot manager automatically:
reset the two CPUs which resets all its registers except
o RGP0 to RG511 in unit A and B
o the RSTATCNTx counters in SU unit
keeps the context of the PRAM, the INTERCOM RAM and the XCHG RAMs
reads the 1st boot descriptor as explained in section 27.2.2 (boot descriptor tables are not re-initialised). The APB peripherals are consequently not reset unless explicitly commanded by the boot frames issued by boot source (i.e. by writing 0 to the respective Reset control in the "Clock and Reset Control" register.
Stop any RTBT activity
The associated information inside RSTATCNT4 is updated
the status pins CPU_STAT[5:0] are updated accordingly
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27.4 BOOT_FRAME
The BOOT_FRAME used by all possible boot sources has the following definitions
ID NAME MEANING VALUES WRITE
CONTROL(*)
0 BURST_SIZE
Burst Size [7:0] (Only valid for writes when BOOTSRC is MEM8, otherwise Burst_Size must be set to 00)
Burst Size = 1 to 255 (Number of 32 bits words, each word corresponding to an APB write access)
BOOTSRC
1 APB_ADD1 APB ADDRESS [15:8] 16-bit APB address to be accessed by boot manager
BOOTSRC
2 APB_ADD0 APB ADDRESS [7:0]
3 APB_DATA3 or CRC3
APB WRITE DATA [31:24] or CRC VALUE [31:24]
If the Boot Command is an EOB: CRC value applicable to all APB transactions that occurred from the SOB up to the EOB. These fields are only interpreted at the end of a boot
Otherwise, 32-bit data to be written on APB bus(ses)
BOOTSRC
4 APB_DATA2 or CRC2
APB WRITE DATA [23:16] or CRC VALUE [23:16]
5 APB_DATA1 or CRC1
APB WRITE DATA [15:8] or CRC VALUE [15:8]
6 APB_DATA0 or CRC0
APB WRITE DATA [7:0] or CRC VALUE [7:0]
7 RBF BCOM SPARE
REQUEST NEW BOOT FRAME BIT (Bit 7) BOOT COMMAND (Bits 6:4) SPARE (Bits 3:0)
0 = Request acknowledged 1 = Request activated 000 = Write APB0 001 = Write APB1 010 = Write APB0 and APB1 011 = Read APB0 100 = Read APB1 110 = SOB (START-OF-BOOT) 111 = EOB (END-OF-BOOT) Not used
BMGR (0 only) BOOTSRC (1 only) BOOTSRC
Table 85: BOOT_FRAME description
(*) column identifies who has a write control between the boot manager (BMGR) and the selected boot source (BOOTSRC). Read is always possible on both sides. Notes:
When BCOM is SOB, ID fields 0 to 6 are discarded.
When BCOM is EOB, ID fields 0 to 2 are discarded.
Each write operation specified in the Boot Frame corresponds to a Write APB transaction. For example, in order to initialize the Boot Descriptor 1, a Boot Frame pointing to the address 0x6000 (Fields 1 and 2 of the Boot Frame equals to 0x60 and 0x00 respectively) must be specified with the required data (Fields 3 to 4 of the Boot Frame).
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When the boot source is the MEM8, a dedicated field is available to increase boot time by providing
a burst capability. This field is named BURST_SIZE and specifies the number of APB writes (from 1 up
to 255) that is desired in a consecutive fashion. When specifying a burst transfer, a normal
BOOT_FRAME must be sent with the desired burst size, the first data to be written and the desired
starting write address. The boot manager will then automatically read the next BOOT_FRAME as 8-
bytes data and sequentially write the 32-bit value to the next consecutive APB address and until the
programmed burst size is achieved. This feature is useful to rapidly fill the two PRAMs which are
made of consecutive data and to reduce the amount of required Memory size.
The following sections will explain how the BOOT_FRAME is accessed and controlled for the various
possible sources.
27.4.1 MAPPING WITH SPACEWIRE/RMAP,CAN AND RTBT
When the boot source originates from the SpaceWire/RMAP, CAN or RTBT, the following mapping is used to control the various fields of the BOOT_FRAME
BOOT_FRAME FIELD
SPW/RMAP AHB
ADDRESS (bit assign)
CAN AHB
ADDRESS (bit assign)
RTBT AHB
ADDRESS
BOOT SOURCE WRITE
CONTROL?
BURST_SIZE/ RTBT Header
0xF004 (31:24)
0xF004 (31:24)
0x4000_0028 (*)
YES
APB_ADD1 0xF004 (23:16)
0xF004 (23:16)
0x4000_002C YES
APB_ADD0 0xF004 (15:8)
0xF004 (15:8)
0x4000_0030
APB_DATA3 0xF004 (7:0)
0xF004 (7:0)
0x4000_0034 YES
APB_DATA2 0xF008 (31:24)
0xF008 (31:24)
0x4000_0038
APB_DATA1 0xF008 (23:16)
0xF008 (23:16)
0x4000_003C YES
APB_DATA0 0xF008 (31:24)
0xF008 (31:24)
0x4000_0040 YES
RBF 0xF008 (7:7)
0xF008 (7:7)
0x4000_0044 YES
BCOM 0xF008 (6:4)
0xF008 (6:4)
N/A YES
BMGR_STATE 0xF008 (3:0)
0xF008 (3:0)
N/A NO (AHB write discarded)
Table 86: Spacewire, CAN and RTBT mapping with RTBT
Note: RTBT Header must be 0x01 for code upload
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27.4.2 MEM8 CASE
When the selected source is the 8-bit interface (MEM8), the BOOT_FRAME buffer is updated by the boot manager itself. The only constrain is that the external memory must be made of the consecutive 8-bytes values providing the values for each BOOT_FRAME.
27.5 BOOT DESCRIPTOR TABLE
The boot descriptor table is accessible on the two APB busses and hold 4 different descriptors. It has
the following definition:
APB ADDRESS
(hex) TYPE NAME DESCRIPTION R/W
0x6000 C BD0 1ST
BOOT DESCRIPTOR R/W
0x6001 C BD1 2nd
BOOT DESCRIPTOR R/W
0x6002 C BD2 3rd
BOOT DESCRIPTOR R/W
0x6003 C BD3 4th
BOOT DESCRIPTOR R/W
Table 87: Boot descriptors APB registers
Each boot descriptor field has the definition shown in Section 31.11.1.
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28 REAL-TIME BACKGROUND TRACER
28.1 OVERVIEW
The CLP integrates a debugging interface called Real-Time Background Tracer. This link makes use of
the Ethernet standard link to provide tracing data on a high number of events occurring in the CLP.
The objective is firstly to provide the required support to perform software debugging but also to
provide, with the same interface, validation data that can be used on the system with the
application software running with the real hardware on the loop.
Two key features can simultaneously be used. The acquisition of data:
in real-time i.e. at the frequency of the fastest loop
in background i.e. without needing code instrumentation
The RTBT provides the visibility of
both CPU registers and program memory activity,
both APB busses transactions
MMU interfaces (MIL-STD-1553 RT,…) transfers.
Only the 100 Mbit/s Ethernet transfer rate limits the number of information that can be read.
The RTBT communicates with the external world through an Ethernet bus running an UDP/IPv4
protocol. The communication assumes that a point-to-point connection is used. Technically, nothing
forbids the use of a switch between the CLP and the device that communicates with the RTBT unit.
However, please keep in mind that the UDP protocol does not guarantee the quality of service, and
that any collision could lead to data loss.
The UDP packet structure is given in the figure below. The source and destination addresses are respectively the IP address of the sender and of the receiver. The source port is ignored. However, the destination port is important and will be discussed below.
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28.2 ETHERNET FRAME
28.2.1 UDP PACKET STRUCTURE
The UDP/IPv4 packet are structured as described below:
Table 88: RTBT UDP packet
The UDP/IP packet on Ethernet consists of 3 different layers of data:
First, there is the Ethernet layer itself, with a header in which the fact that we use an IPv4 protocol is defined. The header is followed by a payload, and terminated with a 32-bit CRC.
The Ethernet payload is composed of an IPv4 header, followed by an IPv4 payload.
The IPv4 payload is composed of an UDP header and the actual data that need to be transmitted.
28.2.2 ETHERNET HEADER STRUCTURE
The Ethernet header is composed as described below:
Table 89: RTBT Ethernet packet
The Ethernet header is composed of 14 bytes:
The first 6 bytes contain the MAC address of the destination.
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The following 8 bytes contain the MAC address of the source.
The 2 following bytes contain the Ethernet type. In this case, the value will be 0x0800 (IPv4 Protocol).
28.2.3 IPV4 HEADER STRUCTURE
The IPv4 header is composed as described below:
Table 90: RTBT IPv4 header
In our case, the header is composed of 20 bytes:
The first byte (byte 0) contains the version (here 4 because we are using IPv4) and the number of 32-bits words that form the header (in this case 5). So, for us, the value is 0x45.
The second byte (byte 1) is dedicated to services that we will not use, and can be set to 0.
The following two bytes (byte 2-3) contain the IPv4 frame length (IPv4 header + payload) in bytes.
The bytes 4-5 contain an identifier that we don’t need. The value can be set to 0.
The bytes 6-7 manage fragments. They can also be set to 0 since we will not use them.
The byte 8 contains the time (in seconds) the packet can live on the network (transit time). It is typically set at 0x80 in typical situations, so we propose to keep the same value.
The byte 9 contains the protocol. In our case, we use UDP, whose value is 0x11.
Bytes 10-11 contain the checksum of the IPv4 header (see description below)
Bytes 12-15 contain the IP address of the transmitter.
Bytes 16-19 contain the IP address of the receiver. IPv4 header checksum calculation: The 16-bit checksum field is used for error-checking of the header. When a packet arrives at a router, the router calculates the checksum of the header and compares it to the checksum field. If the values do not match, the router discards the packet. Errors in the data field must be handled by the encapsulated protocol. Both UDP and TCP have checksum fields. When a packet arrives at a router, the router decreases the TTL field. Consequently, the router must calculate a new checksum. RFC 1071 defines the checksum calculation: The checksum field is the 16-bit one's complement of the one's complement sum of all 16-bit words in the header. For purposes of computing the checksum, the value of the checksum field is zero. For example, consider Hex 4500003044224000800600008c7c19acae241e2b (20 bytes IP header), using a machine which uses standard two's complement arithmetic:
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Step 1) 4500 + 0030 + 4422 + 4000 + 8006 + 0000 + 8c7c + 19ac + ae24 + 1e2b = 0002BBCF (32-bit sum)
Step 2) 0002 + BBCF = BBD1 = 1011101111010001 (1's complement 16-bit sum, formed by "end around carry" of 32-bit 2's complement sum)
Step 3) ~BBD1 = 0100010000101110 = 442E (1's complement of 1's complement 16-bit sum) To validate a header's checksum the same algorithm may be used - the checksum of a header which contains a correct checksum field is a word containing all zeros (value 0): 2BBCF + 442E = 2FFFD. 2 + FFFD = FFFF. the 1's complement of FFFF = 0.
28.2.4 UDP HEADER STRUCTURE
The UDP header is composed as described below:
Table 91: RTBT UDP header structure
This header is composed of 8 bytes:
The 2 first bytes contain the source port.
The 2 following bytes contain the destination port
The 2 following bytes contain the UDP packet (UDP header + data) length
The 2 last bytes contain the UDP packet (UDP header + data) checksum (optional - put 0 in case no checksum is used).
28.2.5 IP ADDRESS
The UDP protocol is characterised by a communication between an IP address to another IP address,
from a source port to a destination port. The first thing to set is thus the IP address of the CLP unit (if
the default IP address needs to be changed). In order to make it parametrable, it is mandatory to the
user to let a broadcast message define the IP address of the CLP.
The way the system works is thus as follows: once the CLP is powered up, the RTBT refuses all
communication except those related to address setting or related to the default IP address, until it
receives either a broadcast message at port 50010, or a specific message at the same port 50010,
containing a payload with the CLP and the opposite host IPv4 addresses. It will then set these
addresses internally, and stand ready to receive messages at this address.
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28.3 RTBT FRAMES
28.3.1 HOST TO RTBT FRAME DEFINITION
The Frame that must sent from the Host to the RTBT is shown hereunder
First 16-bits Transmitted
MAC Destination Address (*)
(Depends on GENERICS)
MAC Destination Address
(Depends on GENERICS)
MAC Source Address
(Depends on Host)
MAC Source Address
(Depends on Host)
EtherType
0x0800
Version
0x4
IHL
0x5
DSCP
0x0
ECN
0x0
Total Length
(Depends on Command)
Identification
0x0
Flags
0x0
Fragment Offset
0x0
Time To Live
0x80
Protocol
0x11
Header Checksum
(Depends on Command)
Source IP Address
(Depends on RTBT Configuration)
Destination IP Address
(Depends on RTBT Configuration)
Source Port
0xC350
Destination Port
(Depends on Command)
Length
(Depends on Command)
Checksum
0x0
PAYLOAD
Command_Word0
PAYLOAD
Command_Word1
…
PAYLOAD
Command_WordN
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PAYLOAD
Last 16-bits transmitted
Table 92: Host to RTBT frame
Where the "PAYLOAD" depends on the desired command . Available commands are defined in section 28.6. Supported commands depend on the RTBT state described in section 28.5
28.3.2 RTBT TO HOST FRAME DEFINITION
The Frame sent by the RTBT to the Host is shown hereunder
First 16-bits Transmitted
MAC_DST
0xFFFF (*)
MAC_DST
0xFFFF FFFF (*)
MAC_SRC (*)
(Depends on GENERICS)
MAC_SRC (*)
(Depends on GENERICS)
EtherType
0x0800
Version
0x4
IHL
0x5
DSCP
0x0
ECN
0x0
Total Length
(Depends of Command)
Identification
0x0
Flags
0x0
Fragment Offset
0x0
Time To Live
0x80
Protocol
0x11
Header Checksum
(Depends on Command)
Source IP Address
(Depends on RTBT Configuration)
Destination IP Address
(Depends on RTBT Configuration)
Source Port
0xC350
Destination Port
(Depends on Command)
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Length
(Depends on Command)
Checksum
0x0
ZEROS (padding) *
0x0
Packet Counter(31:16)
Packet Counter(15:0) Slot0 Counter(15:0)
Slot1 Counter(15:0) RTBT Payload
Answer_Word0(31:16)
RTBT Payload
Answer_Word0(15:0)
RTBT Payload
Answer_Word1(31:16)
RTBT Payload
Answer_Word1(15:0)
…
… RTBT Payload
Answer_WordN(31:16)
RTBT Payload
Answer_WordN(15:0)
Last 16-bits transmitted
Table 93: RTBT to Host frame
Where:
"Packet Counter" is a counter that is incremented each time a Packet is sent to the Host (32 bit counter) .
"Slot 0 Counter" is a counter that is incremented when there is a tick from timer 7 (16 bit counter) .
"Slot 1 Counter" is a counter that is incremented when there is a tick from timer 8 (16 bit counter) .
"PAYLOAD" is either:
The traced data
The Inverse of received command
Answer to the Commands REPORT_STATUS
Answer to the Command REPORT_IP
Destination port is given by the following table .
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Type of message Destination port
Traced data:
Address Tracer data
Variable Tracer data
APB Tracer data
AHB Tracer data
52010
RTBT Command answer (Report Status, Report IP and answers with inverse of the type received)
52020
Table 94: Destination port used in RTBT to Host frame
ZEROS: 16-bits to Zero are added after the UDP header for Hardware simplifications (Alignment
purposes).
28.4 TRACING CAPABILITIES
The RTBT support the following traces
APB tracer: Data and address can be sampled on each APB bus. The acquisition is made at the end of each APB access. It is exclusively triggered by the execution of WRITEAPB and READAPB instructions
AHB tracer: Data and address can be sampled on the AHB bus existing between the MMU (implementing a slave function) and the SpaceWire/CAN/MIL-STD-1553 interfaces (implementing a master function). The acquisition is made when relevant data are present and valid on the master side
Variable tracer: Up to 16 RGPx registers can be traced per CPU. For that purpose a table, called Variable Tracer Table, is configured to indicate when the trace should be produced. For a given CPU, data is sampled when there is a match between any of 16 addresses values programmed in the Variable Tracer Table and the address of the executed instruction. Further indications are given below.
Address tracer: Data and address are sampled in the program memory of each CPU:
either when there is a jump instruction , triggered by instructions described in §7.1.7.3
or when the Mask bit is active (‘1’). In the case of an immediate load with mask bit set (='1'),
data is sampled once.
Note: mask bit and jump are both reported to discriminate a real jump from a masked one
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28.4.1 VARIABLE TRACER
Each time the address of the instruction being executed on the respective CPU matches one of the
16 programmed addresses (in the variable tracer configuration table), the destination register(s) of
the specified units is traced and creates an entry in the RTBT buffer
The trace entry is exclusively produced if a MOVxxx instructions (MOVATO, MOVBTO, MOVSUTO,
MOV, MOVOFF2ABS) or/and a SWAP instruction is executed. In any other case, including when the
operands are not legal, no entry is created.
The traced data is guaranteed if the destination registers are RGPx/ROFFx registers, RDx registers,
RSPx registers, RCONF or RSWREST
Note: the traces generated by the variable tracer are meaningless and should not be interpreted by
the user when the unit(s) selected in the variable tracer configuration table:
are not involved in the MOVxxx or/and SWAP instruction(s) under execution (e.g. SU tracing in case of "MOV A RGP0 RGP1" instruction)
are involved in the MOVxxx or/and SWAP instruction(s) under execution but the destination register(s) does not belong to the registers listed in 7.1.4.5 (e.g. unit SU tracing in case of "MOV SU RGP0 RFLAGA" instruction) .
This “variable tracer” capability is enough from software point of view for debugging purpose,
knowing that the APB tracer, the address tracer and the AHB tracer are also available to expand the
visibility of the CLP. Whenever ROUTADD, ROUTMUL and ROUTDIV must be traced, the next MOVxx
or SWAP instruction that uses these registers as source must be used by the user.
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28.5 RTBT STATE MACHINE
The communication between PC and RTBT is summarized in next Figure. It behaves globally as a state machine with 4 states: IDLE, CONFIGURATION TRACERS, CODE UPLOAD and CPU RUN.
IDLE
CONFIGURATION_TRACERS
CODE_UPLOAD CPU_RUN
reset
Figure 30: RTBT state machine
After reset, the RTBT is in "IDLE" state. From the "IDLE" state, the FSM can evolve to the next states:
CODE_UPLOAD: In this state, if the boot source is the RTBT, the CLP is ready to receive Boot Frames.
CONFIGURATION_TRACERS: In this state the configuration of the different tracers is done.
CPU_RUN: In this state the CPU begins execution of the program. Only after reception of "GO_TO_CPU_RUN" command, the CPU program execution begins. The enabled tracers (cfr section 28.4) are started, the CPU automatically performs the various programmed acquisitions and transmits them to the host with dedicated frames.
At startup, the RTBT will take a fixed IP address (192.168.0.53) and wait for an external order. It will
refuse all communication, except for the messages being sent to port 50010. These messages will
essentially set the IP address of the RTBT terminal and the IP address where it must talk, and will tell
the RTBT what sort of use is going to be performed with it. If the terminal is going to perform data
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acquisition and reporting, the order is sent to the terminal to go into "CONFIGURATION TRACERS"
state, where the transmission and acquisition parameters will be sent.
Once the RTBT has been configured, the command GO_INTO_IDLE state followed by the command
GO_INTO_CPU_RUN must be sent in order to begin the acquisition (When the RTBT is enabled, the
CPU program execution is started when the RTBT is in CPU Run).
When the host sends a typed command to the RTBT, this one automatically answers by sending the
inverse of the type received followed by three 32-bits words of zeroes (for padding purpose). For
instance, if the RTBT receives the typed command 0000000AA, it will automatically send back the
type FFFFFF55. The only case where the type is not used is for UPLOAD_COMMANDS,
FLUSH_RTBT_BUFFER and UPLOAD_DATA commands. In that case it is ignored for performance
reasons and because it would be redundant with the port number used. Note also that for these
commands the RTBT obviously does send back the inverted type. Note that it is mandatory that the
inverted type is received before the sending of a new command.
The list of commands that are supported by the RTBT and that may be send by the host are listed
below (cfr 28.3.1 for the full frame content). The destination UDP ports are provided as well as the
command code and the inverted command that is sent back automatically (cfr 28.3.2 for the full
frame content)
Note that:
the RTBT always supported the “GO_INTO_IDLE_STATE” and” REPORT_STATUS”” commands no matter what the RTBT state is
If the terminal is going to be used to boot the CLP (for boot descriptors or APB/PRAM upload, cfr 27), the RTBT must firstly be set into CODE_UPLOAD state.
Type_of_commands Destination_port Command Inverse_of_Command
REPORT_STATUS 51010 or 53010 0x00000011 0xFFFFFFEE
SET_IP_ADDRESS 50010 0x00000053 0xFFFFFFAC
REPORT_IP_ADDRESS 50010 0x000000CC 0xFFFFFF33
GO_INTO_IDLE_STATE 50010 0x000000DD 0xFFFFFF22
GO_INTO_CONFIGURATION_TRACERS_STATE
50010 0x0000003A 0xFFFFFFC5
GO_INTO_CODEUPLOAD_STATE 50010 0x000000A5 0xFFFFFF5A
GO_INTO_CPU_RUN_STATE 50010 0x000000FF 0xFFFFFF00
EDAC_CORRUPTION 51010 0x00005353 0xFFFFACAC
FLUSH_RTBT_BUFFER 51010 0x0000AACC (*)
ENABLE_ACQUISITIONS 51010 0x00001144 0xFFFFEEBB
DISABLE_ACQUISITIONS 51010 0x00000044 0xFFFFFFBB
SET_VARIABLE_TRACER_TABLE 51010 0x0053A25C 0xFFAC5DA3
CPU0_VARIABLE_TRACER_ENABLE 51010 0x005CA253 0xFFA35DAC
CPU0_VARIABLE_TRACER_DISABLE 51010 0x005C53A2 0xFFA3AC5D
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Type_of_commands Destination_port Command Inverse_of_Command
CPU1_VARIABLE_TRACER_ENABLE 51010 0x00A25C53 0xFF5DA3AC
CPU1_VARIABLE_TRACER_DISABLE 51010 0x00A2535C 0xFF5DACA3
CPU0_ADDRESS_TRACER_ENABLE 51010 0x0000CAAC 0xFFFF3553
CPU0_ADDRESS_TRACER_DISABLE 51010 0x0000ACCA 0xFFFF5335
CPU1_ADDRESS_TRACER_ENABLE 51010 0x0000CA87 0xFFFF3578
CPU1_ADDRESS_TRACER_DISABLE 51010 0x000087CA 0xFFFF7835
APB0_TRACER_ENABLE 51010 0x003572AC 0xFFCA8D53
APB0_TRACER_DISABLE 51010 0x0035AC72 0xFFCA538D
APB1_TRACER_ENABLE 51010 0x023572AC 0xFDCA8D53
APB1_TRACER_DISABLE 51010 0x0235AC72 0xFDCA538D
SPACEWIRE0_AHB_TRACER_ENABLE 51010 0x00AC6732 0xFF5398CD
SPACEWIRE0_AHB_TRACER_DISABLE 51010 0x00AC3267 0xFF53CD98
SPACEWIRE1_AHB_TRACER_ENABLE 51010 0x00AC0001 0xFF53FFFE
SPACEWIRE1_AHB_TRACER_DISABLE 51010 0x00AC1001 0xFF53EFFE
CAN_AHB_TRACER_ENABLE 51010 0x00AC0002 0xFF53FFFD
CAN_AHB_TRACER_DISABLE 51010 0x00AC1002 0xFF53EFFD
M1553_TRACER_ENABLE 51010 0x00AC0004 0xFF53FFFB
M1553_TRACER_DISABLE 51010 0x00AC1004 0xFF53EFFB
UPLOAD_COMMANDS (load of boot descriptors)
53010 Boot_Frame (*)
UPLOAD_DATA (load of clp program and configuration)
53020 Boot_Frame (*)
Table 95: Host to RTBT commands
(*)_No_inverse_of_command_sent_to_the_Host.
28.5.1 IDLE STATE
The RTBT is in IDLE state at power up. Its internal IP address (source address) is by default
192.168.0.53. The IP destination address (where to send the packets) is by default set to
255.255.255.255 (broadcast) after reset.
In IDLE state, the RTBT may receive the next commands:
SET_IP_ADDRESS
REPORT_IP_ADDRESS
REPORT_STATUS
GO_INTO_IDLE_STATE
GO_INTO_CONFIGURATION_TRACERS_STATE
GO_INTO_CODE UPLOAD_STATE
GO_INTO_CPU_RUN_MODE
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28.5.2 CONFIGURATION TRACERS STATE
In CONFIGURATION_TRACERS_STATE, the RTBT can receive commands and parameters from the
external world. The goal of this is to specify which data are to be traced by the RTBT and in which
conditions.
There are two data buffers (transmission buffers), used most of the time in double buffering mode
(default configuration); which means that when one buffer is full, the acquired data are sent to the
other buffer, and the buffer that is full is transmitted to the external world.
A buffer is considered as full when the available space in the buffer is less than 96 bits
Each of the two buffers can contain 1024 8-bit values. Each of these buffers have to be shared
between the address tracer, the variable tracer, the AHB bus monitor and the APB bus monitor.
Each time a new trace event is detected, it is written to the buffer. Each event will have a Header
identifier which will allow the Host to decode the information. This header is received in the Least
Significant Bits of the traced event.
In Configuration Tracers state, the RTBT is able to receive next commands:
GO_INTO_IDLE_STATE
REPORT_STATUS
SET_VARIABLE_TRACER_TABLE
CPU0_VARIABLE_TRACER_ENABLE
CPU0_VARIABLE_TRACER_DISABLE
CPU1_VARIABLE_TRACER_ENABLE
CPU1_VARIABLE_TRACER_DISABLE
CPU0_ADDRESS_TRACER_ENABLE
CPU0_ADDRESS_TRACER_DISABLE
CPU1_ADDRESS_TRACER_ENABLE
CPU1_ADDRESS_TRACER_DISABLE
APB0_TRACER_ENABLE
APB0_TRACER_DISABLE
APB1_TRACER_ENABLE
APB1_TRACER_DISABLE
SPACEWIRE0_AHB_TRACER_ENABLE
SPACEWIRE0_AHB_TRACER_DISABLE
SPACEWIRE1_AHB_TRACER_ENABLE
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SPACEWIRE1_AHB_TRACER_DISABLE
CAN_AHB_TRACER_ENABLE
CAN_AHB_TRACER_DISABLE
M1553_TRACER_ENABLE
M1553_TRACER_DISABLE
ENABLE_ACQUISITIONS
DISABLE_ACQUISITIONS
EDAC_CORRUPTION
The effect of each these commands are implicit. Note that:
the ENABLE_ACQUISITIONS command enables all the acquisition from enabled tracers.
The DISABLE_ACQUISITIONS command disables all the acquisition from enabled tracers.
The SET_VARIABLE_TRACER command configures which RGPx traces (linked to an RPC value) are enabled inside the CPUs
The EDAC_CORRUPTION is for test purpose and allow to control, for a given address which implements EDAC, the 32-bits data AND the 7-bits correction code.
28.5.3 CODE UPLOAD STATE
In CODE_UPLOAD state, the RTBT is able to receive next commands
GO_INTO_IDLE_STATE
REPORT_STATUS
UPLOAD_COMMANDS
UPLOAD_DATA
The boot principles are explained in section 27 and imply the control of the BOOT_FRAME buffer handled by the boot manager. In order to correctly initialize the CLP resources when the RTBT is the boot source, the RTBT must be in CODE_UPLOAD_STATE. The Frame to be sent from the Host to the RTBT contains the desired value for the BOOT_FRAME (cfr 28.3.1).The first BOOT_FRAME byte must be transmitted first followed by the second BOOT_FRAME bytes and so on.
For example, for the initialization of the Boot Descriptor 0 (APB address 0x6000) with value 0x12345768, the host needs to send an UPLOAD_COMMANDS frame with the Payload set to the following:
Command_Word0 = 0x000000 00 (Boot Frame ID0:BURST_SZE -> not used in this case)
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Command_Word1 = 0x000000 60 (Boot Frame ID1: APB_Add(15 to 8))
Command_Word2 = 0x000000 00 (Boot Frame ID2: APB_Add(7 to0))
Command_Word3 = 0x000000 12 (Boot Frame ID3: APB_Data(31 to 24))
Command_Word4 = 0x000000 34 (Boot Frame ID4:APB_Data(23 to 16))
Command_Word5 = 0x000000 56 (Boot Frame ID5:APB_Data(15 to 8))
Command_Word6 = 0x000000 78 (Boot Frame ID6:APB_Data(7 to 0))
Command_Word7 = 0x000000 80 (Boot Frame ID7: RBF, Write APB0)
Another example for the initialization of the APB register M1553_CONFREG (APB address 0x1321)
with value 0x15530003 on APB0, the host needs to send an UPLOAD_DATA frame with the Payload
set to the following:
Command_Word0 = 0x000000 00 (Boot Frame ID0:BURST_SZE -> not used in this case)
Command_Word1 = 0x000000 13 (Boot Frame ID1: APB_Add(15 to 8))
Command_Word2 = 0x000000 21 (Boot Frame ID2: APB_Add(7 to0))
Command_Word3 = 0x000000 15 (Boot Frame ID3: APB_Data(31 to 24))
Command_Word4 = 0x000000 53 (Boot Frame ID4:APB_Data(23 to 16))
Command_Word5 = 0x000000 00 (Boot Frame ID5:APB_Data(15 to 8))
Command_Word6 = 0x000000 03 (Boot Frame ID6:APB_Data(7 to 0))
Command_Word7 = 0x000000 80 (Boot Frame ID7: RBF, Write APB1)
Another example for the initialization of the XCHGRAM1 address 0x4000 with value 0x12345678, the
host needs to send an UPLOAD_DATA frame with the Payload set to the following:
Command_Word0 = 0x000000 00 (Boot Frame ID0:BURST_SZE -> not used in this case)
Command_Word1 = 0x000000 40 (Boot Frame ID1: APB_Add(15 to 8))
Command_Word2 = 0x000000 00 (Boot Frame ID2: APB_Add(7 to0))
Command_Word3 = 0x000000 12 (Boot Frame ID3: APB_Data(31 to 24))
Command_Word4 = 0x000000 34 (Boot Frame ID4:APB_Data(23 to 16))
Command_Word5 = 0x000000 56 (Boot Frame ID5:APB_Data(15 to 8))
Command_Word6 = 0x000000 78 (Boot Frame ID6:APB_Data(7 to 0))
Command_Word7 = 0x000000 90 (Boot Frame ID7: RBF, Write APB1)
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28.5.3.1 CPU RUN STATE
In CPU Run state, the RTBT is able to receive next command
GO_INTO_IDLE_STATE
REPORT_STATUS
FLUSH_RTBT_BUFFER
In that state, the transmission of enabled traces also automatically started. Each trace event is sent
according to the frame defined in section §28.3.2. Each traced event will start with a Header (0x55)
and followed with the tracer identifier (unique for each tracer) given in the following table:.
Tracer Identifier
CPU0 Address tracer 0x0
CPU1 Address tracer 0x1
APB0 trace 0x2
APB1 tracer 0x3
AHB trace 0x4
CPU0 Variable tracer Unit A 0x8
CPU1 Variable tracer Unit A 0x9
CPU0 Variable tracer Unit B 0xA
CPU1 Variable tracer Unit B 0xB
CPU0 Variable tracer Unit SU 0xC
CPU1 Variable tracer Unit SU 0xD
Traced data from the different sources are internally concatenated in an internal buffer. This one is
transmitted through the Ethernet Link as soon as it is full or when the FLUSH_RTBT_BUFFER
command is received. The internal buffer is considered as full when the available space in the buffer
is less than 96 bits (size of an AHB trace which is the biggest RTBT trace event).
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28.6 RTBT COMMANDS
28.6.1 REPORT_STATUS COMMAND
The host may interrogate the RTBT on its status with the command REPORT_STATUS (sent to port
51010 or 53010). The RTBT frame has the following payload content:
Command_Word0 = 0x00000011
The RTBT will answer with the following frame having the following payload content:
Answer_Word0 = 0xFFFFFFEE
Answer_Word1 = RTBT state
Answer_Word2 =
Bit 31 : RTBT Lost traced data (*) Bits 29-24 : Padding (Zeros) Bits 23-16 : CPU_STAT[5:0] (**) Bits 15-8 : APB address[15:8] in Boot Frame (***) Bits 7-0 : APB address[7:0] in Boot Frame
Answer_Word3 =
Bits 31-24 : APB data[31:24] in Boot Frame Bits 23-16 : APB data[23:16] in Boot Frame Bits 15-8 : APB data[15:8] in Boot Frame Bits 7-0 : APB data[7:0] in Boot Frame Where:
The RTBT state is encoded as shown hereunder:
Idle State = 0xACACACAC Configuration Tracers State = 0xA5555555 Code Upload State = 0xC3333333 CPU Run State = 0xCA535353
The CLP flags will be encoded as shown hereunder:
RTBT Error Buffer Not Available CLP_Flags[1] RTBT FIFO overflow CLP_Flags[0]
(*) RTBT Lost traced data: This flag is asserted when there is data lost in RTBT. This flag is cleared after a REPORT_STATUS command is received.
(**) CPU_STAT is defined in 25.1.1.
(***)Values of Answer Words of REPORT_STATUS command depend on the contents of the Previous Boot Frame:
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If BCOM of previous Boot Frame was READ_APB, Answer_Word2 (Bits 15:0) and Answer_Word3 (Bits 31:0) will have the results of the READ_APB.
If BCOM of previous Boot Frame was WRITE_APB, Answer_Word2 (Bits 15:0) and Answer_Word3 (Bits 31:0) will have the APB address and APB data of the previous Boot Frame.
If BCOM of previous Boot Frame was SOB, Answer_Word2 (Bits 15:0) and Answer_Word3 (Bits 31:0) will be 0x0.
If BCOM of previous Boot Frame was EOB, Answer_Word2 (Bits 15:0) will be 0x0 and Answer_Word3 will be CRC sent with the previous EOB.
28.6.2 SET_IP_ADDRESS COMMAND
The command SET_IP_ADDRESS sets the source and destination IP addresses. The RTBT frame has
the following payload content
Command_Word0 = 0x00000053
Command_Word1 = New RTBT IP Address
Command_Word2 = New External IP Address
The RTBT will answer with the following frame having the following payload content:
Answer_Word0 = 0xFFFFFFAC
Answer_Word1 = 0x00000000 (Padding)
Answer_Word2 = 0x00000000 (Padding)
Answer_Word3 = 0x00000000 (Padding)
With the RTBT IP address setting its source address and the External IP address setting its destination address. From this moment, the source and destination address used by the RTBT will always be those ones (the destination address can be broadcast).
28.6.3 REPORT_IP_ADDRESS COMMAND
The command REPORT_IP_ADDRESS reports the source and destination IP addresses. The RTBT
frame has the following payload content:
Command_Word0 = 0x000000CC
The RTBT will answer with the following frame having the following payload content:
Answer_Word0 = 0xFFFFFF33
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Answer_Word1 = RTBT IP address
Answer_Word2 = External IP address
Answer_Word3 = 0x00000000 (Padding)
where RTBT IP address is the source address and External IP address is the destination address.
28.6.4 GO_INTO_CONFIGURATION_TRACERS_STATE COMMAND
The command GO_INTO_CONFIGURATION_TRACERS_STATE sets the RTBT state to
CONFIGURATION_TRACERS_STATE if the current state is IDLE. The RTBT frame has the following
payload content :
Command_Word0 = 0x0000003A
The RTBT will answer with the following frame having the following payload content:
Answer_Word0 = 0xFFFFFFC5
Answer_Word1 = 0x00000000 (Padding)
Answer_Word2 = 0x00000000 (Padding)
Answer_Word3 = 0x00000000 (Padding)
28.6.5 GO_INTO_UPLOAD_STATE COMMAND
The command GO_INTO_UPLOAD_STATE sets the RTBT state to CODE_UPLOAD_STATE if the
current state is IDLE. The RTBT frame has the following payload content :
Command_Word0 = 0x000000A5
The RTBT will answer with the following frame having the following payload content:
Answer_Word0 = 0xFFFFFF5A
Answer_Word1 = 0x00000000 (Padding)
Answer_Word2 = 0x00000000 (Padding)
Answer_Word3 = 0x00000000 (Padding)
28.6.6 GO_INTO_CPU_RUN COMMAND
The command GO_INTO_CPU_RUN sets the RTBT state to CPU_RUN if the current state is IDLE. The
RTBT frame has the following payload content :
Command_Word0 = 0x000000FF
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The RTBT will answer with the following frame having the following payload content:
Answer_Word0 = 0xFFFFFF00
Answer_Word1 = 0x00000000 (Padding)
Answer_Word2 = 0x00000000 (Padding)
Answer_Word3 = 0x00000000 (Padding)
28.6.7 GO_INTO_IDLE_STATE COMMAND
The command GO_INTO_IDLE_STATE unconditionally sets the RTBT state to and reset both CPUs
(except the File Registers (Unit A and Unit B) and the PRAM).. The RTBT frame has the following
payload content :
Command_Word0 = 0x000000DD
The RTBT will answer with the following frame having the following payload content:
Answer_Word0 = 0xFFFFFF22
28.6.8 EDAC_CORRUPT COMMAND
The command EDAC_CORRUPT is used for test purpose and allows to emulate an EDAC corruption in
CLP memory areas that are controlled by such feature. Both the 32-bit data and 7-bit may be
controlled.. This command must only be sent when the RTBT state is in CODE_UPLOAD state. The
RTBT frame has the following payload content :
Command_Word0 = 0x00005353
Command_Word1 =
Bits 24:23 = APB_ID
Bits 22:16 = EDAC_IN (cfr 28.6.8.1)
Bits 15:0 = APB Address
Command_Word2 = APB Data
Where:
APB_ID must be set according to this table
APB0 00b
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APB1 01b
APB_BOTH 1xb
The RTBT will answer with the following frame having the following payload content:
Answer_Word0 = 0xFFFFACAC
Answer_Word1 = 0x00000000 (Padding)
Answer_Word2 = 0x00000000 (Padding)
Answer_Word3 = 0x00000000 (Padding)
28.6.8.1 EDAC ALGORITHM
The following EDAC algorithm must be used to generate the correct value of the 7 check bits, called
cb[6] to cb[0], from the 32-bits data, called d[31] to d[0]
cb[0] = d[0] xor d[4] xor d[6] xor d[7] xor d[8] xor d[9] xor d[11] xor d[14] xor d[17] xor d[18] xor
d[19] xor d[21] xor d[26] xor d[28] xor d[29] xor d[31];
cb[1] = d[0] xor d[1] xor d[2] xor d[4] xor d[6] xor d[8] xor d[10] xor d[12] xor d[16] xor d[17] xor
d[18] xor d[20] xor d[22] xor d[24] xor d[26] xor d[28];
cb[2] = d[0] xnor d[3] xnor d[4] xnor d[7] xnor d[9] xnor d[10] xnor d[13] xnor d[15] xnor d[16] xnor
d[19] xnor d[20] xnor d[23] xnor d[25] xnor d[26] xnor d[29] xnor d[31];
cb[3] = d[0] xnor d[1] xnor d[5] xnor d[6] xnor d[7] xnor d[11] xnor d[12] xnor d[13] xnor d[16] xnor
d[17] xnor d[21] xnor d[22] xnor d[23] xnor d[27] xnor d[28] xnor d[29];
cb[4] = d[2] xor d[3] xor d[4] xor d[5] xor d[6] xor d[7] xor d[14] xor d[15] xor d[18] xor d[19] xor
d[20] xor d[21] xor d[22] xor d[23] xor d[30] xor d[31];
cb[5] = d[8] xor d[9] xor d[10] xor d[11] xor d[12] xor d[13] xor d[14] xor d[15] xor d[24] xor d[25] xor
d[26] xor d[27] xor d[28] xor d[29] xor d[30] xor d[31];
cb[6] = d[0] xor d[1] xor d[2] xor d[3] xor d[4] xor d[5] xor d[6] xor d[7] xor d[24] xor d[25] xor d[26]
xor d[27] xor d[28] xor d[29] xor d[30] xor d[31];
To provoke an EDAC corruption, it is up to the user to flip the state of any of these bits
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28.6.9 FLUSH_RTBT_BUFFER COMMAND
The command FLUSH_RTBT_BUFFER automatically transmits the content of the RTBT internal
buffer. The RTBT frame has the following payload content:
Command_Word0 = 0x0000AACC
The RTBT will answer with the corresponding traces frames padded with ‘0’ for fields which are empty. If the payload field size is less than 16 bytes, RTBT will insert zeroes to be in line with the 64 bytes minimal size requested by Ethernet standard.
28.6.10 SET_VARIABLE_TRACER_TABLE COMMAND
The tracing of internal variables is specified with the command SET_VARIABLE_TRACER_TABLE. Up to 16 RGPx registers can be traced per CPU. The RTBT frame has the following payload content:
Command_Word0 = 0x0053A25C
Command_Word1 = First variable to trace in CPU0
Command_Word2 = Second variable to trace in CPU0 ...
Command_Word16 = 16th variable to trace in CPU0
Command_Word17 = First variable to trace in CPU1
Command_Word18 = Second variable to trace in CPU1 ...
Command_Word32 = 16th variable to trace in CPU1
Where, each traced variable is specified as follows:
Bits 31-19: Not used and not interpreted
Bits 18-16: Specifies the unit(s) to trace (the 3 units can be simultaneously enabled)
Bit 16: Select SU Bit 17: Select A
Bit 18: Select B Bit 15: Not used
Bits 14-0 Specifies the address (in the PRAM) of the instruction that must be traced ( i.e. 0x0 points to 1st instruction executed, 0x1 points the 2nd, etc...).The constraints described §28.4.1 apply.
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28.6.11 ADDRESS TRACER
The payload of the RTBT frame sent by the CLP holding tracing information is made of successive
traces related to the various events that occurred in the CLP. When an address tracer event occurs
the following data is added in the trace
CPU0 Address Tracer:
Bits 47 to 40
Bits 39 to 36 Bits 35 Bit 34 Bits 33 to 19 Bits 18 to 4 Bits 3 to 0
Header
Address Tracer
Core 0 Identifier
Mask instruction
Detected
Jump Instruction Detected
RPC A
RPC B
Padding
0x55 0x0 if Jump Detected:
Address of the last instruction executed before the Jump plus one
if Masked Instruction:
Address of the masked instruction
if Jump Detected:
Address of the first instruction executed after the Jump
if Masked Instruction
Address of the masked instruction plus one
0x0
Table 96: RTBT CPU0 Address trace content
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CPU1 Address Tracer:
Bits 47 to 40
Bits 39 to 36 Bits 35 Bit 34 Bits 33 to 19 Bits 18 to 4 Bits 3 to 0
Header
Address Tracer
Core 1 Identifier
Mask instruction
Detected
Jump Instruction Detected
RPC A
RPC B
Padding
0x55 0x1 if Jump Detected:
Address of the last instruction executed before the Jump plus one
if Masked Instruction:
Address of the masked instruction
if Jump Detected:
Address of the first instruction executed after the Jump
if Masked Instruction
Address of the masked instruction plus one
0x0
Table 97: RTBT CPU1 Address trace content
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28.6.12 APB TRACER
The payload of the RTBT frame sent by the CLP holding tracing information is made of successive
traces related to the various events that occurred in the CLP. When an APB tracer event occurs the
following data is added in the trace
APB0 Tracer:
Bits 79 to 72 Bits 71 to 68 Bits 67 to 53 Bit 52 Bits 51 to 20 Bits 19 to 4
Bits 3 to 0
Header
APB Identifier
RPC
PWrite
Pwdata/Prdata
PAddr
Padding
0x55 0x2 1: Write
0: Read
Pwdata (if Write)
Prdata (if Read)
0x0
Table 98: RTBT APB0 trace content
APB1 Tracer:
Bits 79 to 72 Bits 71 to 68 Bits 67 to 53 Bit 52 Bits 51 to 20 Bits 19 to 4
Bits 3 to 0
Header
APB Identifier
RPC
PWrite
Pwdata/Prdata
PAddr
Padding
0x55 0x3 1: Write
0: Read
Pwdata (if Write)
Prdata (if Read)
0x0
Table 99: RTBT APB1 trace content
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28.6.13 AHB TRACER
The payload of the RTBT frame sent by the CLP holding tracing information is made of successive
traces related to the various events that occurred in the CLP. When an AHB tracer event occurs the
following data is added in the trace
AHB Tracer:
Bits 95 to 88
Bits 87 to 84
Bits 83 to 69
Bits 67 Bit 66 Bits 65 to 34 Bits 33 to 2 Bits 1 to 0
Header
AHB Identifier
Tick Counter Timer 9
Hresp HWrite
Hwdata/Hrdata
HAddr
Padding
0x55 0x4 (*) 0: Ok
1: Error
1: Write
0: Read
Pwdata (if Write)
Prdata (if Read)
00b
Table 100: RTBT AHB trace content
(*) 16-bits counter of the events on Timer 9
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28.6.14 EVENTS OCCURING IN CASE OF MIL-STD-1553 TRANSFERS
The following AHB traces are reported each time a MIL-STD-1553 message is processed by the CLP. This does not apply to mode codes as these ones never request an AHB access
reading of the 2 (transmit case) or 3 (receive case) consecutive 32-bit words located in the subaddress table whose XCHGRAM location and 13-bit starting address is given by the APB register M1553_SUBADDTAB.
In case of transmit message, the 2nd word provides the value of the Transmit descriptor pointer which is used for the next AHB access.
In case of Receive message, the 3rd word provides the value of the Receive descriptor pointer which is used for the next AHB access
Reading of the 2 consecutive 32-bit words starting from the transmit or receive descriptor pointer previously read. These 2 words correspond to:
The control and status word
The Data Transmit descriptor pointer (in case of transmit message) or the Data Receive descriptor pointer (in case of receive message). This pointer is used for the next AHB access
If N is the number of data words composing the 1553 message :
in case of "Transmit" request, reading of N/2 (even case) or (N+1)/2 (odd case) consecutive 32-bit words corresponding to the data buffer starting from the Data Transmit descriptor pointer previously read.
in case of "Receive" request, writing of N/2 (even case) or (N+1)/2 (odd case) 32-bit consecutive words in the data buffer starting from the Data Receive descriptor pointer previously read. If N is odd, the 16 LSB of the last 32-bit word is duplicated from the 16 MSB (corresponding to the last 1553 data word)
Update of the value of the control and status word previously read
In the corresponding transmit or receive descriptor (cfr accesses made in 4)), reading of the 32-bit word that immediately follows the Data Transmit (or Receive) descriptor pointer and use the value to update the Transmit (or Received) Descriptor pointer in the sub-address table. If wrap has been enabled for the sub-address and if a receive message is handled, the value of the current Receive Descriptor is used to also update the Transmit Descriptor pointer in the sub-address table.
28.6.15 EVENTS OCCURING IN CASE OF SPACEWIRE TRANSFERS
To be completed in next release
28.6.16 EVENTS OCCURING IN CASE OF CAN TRANSFERS
To be completed in next release
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28.6.17 VARIABLE TRACER
The payload of the RTBT frame sent by the CLP holding tracing information is made of successive
traces related to the various events that occurred in the CLP. When an variable tracer event occurs
the following data is added in the trace
CPU0 Variable Tracer Unit A:
Bits 63 to 56 Bits 55 to 52 Bits 51 to 37 Bits 36 to 5 Bits 4 to 0
Header Variable Tracer Unit A Identifier RPC File Register A Padding
0x55 0x8 00000b
Table 101: RTBT CPU0 A unit variable tracer content
CPU1 Variable Tracer Unit A:
Bits 63 to 56 Bits 55 to 52 Bits 51 to 37 Bits 36 to 5 Bits 4 to 0
Header Variable Tracer Unit A Identifier RPC File Register A Padding
0x55 0x9 00000b
Table 102: RTBT CPU1 A unit variable tracer content
CPU0 Variable
Tracer Unit
B:Bits 63 to 56
Bits 55 to 52 Bits 51 to 37 Bits 36 to 5 Bits 4 to 0
Header Variable Tracer Unit B Identifier RPC File Register A Padding
0x55 0xA 00000b
Table 103: RTBT CPU0 B unit variable tracer content
CPU1 Variable Tracer Unit B:
Bits 63 to 56 Bits 55 to 52 Bits 51 to 37 Bits 36 to 5 Bits 4 to 0
Header Variable Tracer Unit B Identifier RPC File Register A Padding
0x55 0xB 00000b
Table 104: RTBT CPU1 B unit variable tracer content
CPU0 Variable Tracer Unit SU:
Bits 47 to 40 Bits 39 to 36 Bits 35 to 21 Bits 20 to 5 Bits 4 to 0
Header Variable Tracer Unit SU Identifier RPC File Register A Padding
0x55 0xC 00000b
Table 105: RTBT CPU0 SU unit variable tracer content
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CPU1 Variable Tracer Unit SU:
Bits 47 to 40 Bits 39 to 36 Bits 35 to 21 Bits 20 to 5 Bits 4 to 0
Header Variable Tracer Unit SU Identifier RPC File Register A Padding
0x55 0xD 00000b
Table 106: RTBT CPU1 SU unit variable tracer content
28.7 NOTE TO THE USER
This section provides a number of advices or constraints that should be considered by the user when
interacting with the RTBT
The RTBT internally handles a toggle buffer made of 1024 bytes each. A buffer is considered as full
when the available space in the buffer is less than 96 bits. However, the user may provoke a data loss
condition inside the RTBT if:
the FLUSH_RTBT_BUFFER command is sent while data is being written to the internal buffer. This side effect implies that sending such command should only be done when the user is sure that CLP SW has stopped doing activities that are traced.
the RTBT traffic is bigger than the Ethernet bandwidth (100 Mbit/s). The maximal amount of traced data per unit of time that the CLP is capable to support is hard to estimate. In this case, the REPORT_STATUS command would report a “RTBT lost traced data”. However, since each trace entry has a fixed length, a raw estimation can be done for a given application.
It is mandatory to check that the inverted command, in response to an RTBT command, is received
before sending another RTBT command. This allows a handshake mechanism which is safer than
transmitting burst of commands. Indeed, commands arriving too close from each other are not
indefinitely supported by the CLP.
It is forbidden to trace CPU activity while this one is reset or not clocked (i.e. “Clock and Reset
Control” fields CPUx_CLK and CPUx_RST shall be written to 1 for tracing the CPU activity).
ARP support is not implemented in the CLP. For this reason, before stablishing the link between the
RTBT and the HOST, the next linux commands must be successively executed:
sudo ifconfig eth0 down
sudo ifconfig eth0 up 192.168.0.1 (IP address of the Host is set to be in the same address domain of the RTBT)
sudo arp -s 192.168.0.53 00:00:5E:00:00:ED (CLP MAC address 00:00:5E:00:00:ED is associated to the CLP IP address 192.168.0.53)
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29 I2C
This section will provide more details in the next release
29.1 OVERVIEW
The CLP integrates the I2C interface and is compliant with version 2.1 except for:
A "general call address" access occurring on the I2C bus which is not handled
a "START byte" access occurring on the I2C bus which is not acknowledged
a "CBUS address" access occurring on the I2C bus which is not acknowledged
Both the master and slave interfaces are available. Only the Standard (100kbit/s) and Fast Mode (400kbit/s) are supported. However, the I2C slave interface support the High-Speed Mode but this one has not been tested and its behavior is not guaranteed
The I2C_SDA and I2C_SCL is managed by the I2C master AND slave IPs
Some APB registers are not controlled by the CLP reset. These APB registers should be initialised by
the use before being used thought the enable bit
29.2 IO SIGNALS
The I2C interface control the following CLP outputs
I/O NAME I/O/Z WIDTH DESCRIPTION ACTIVE RESET VALUE
I2C_SDA I/O/Z 1 I2C Serial Data N/A Z
I2C_SCL I/O/Z 1 I2C Serial Clock N/A Z
Table 107: I2C I/O signals
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29.3 APB REGISTERS
The I2C interface has the following APB address table
APB ADDRESS
(hex) TYPE NAME DESCRIPTION R/W
0x0200 C I2C_MCKPRE Master Clock Prescale register R/W
0x0201 C I2C_MCTRL Master Control register R/W
0x0202 D I2C_MTRREG Master Transmit register W
0x0202 D I2C_MRECREG Master Receive register R
0x0203 C I2C_MCOM Master Command register W
0x0203 S I2C_MSTAT Master Status register R
0x0210 C I2C_SADD Slave address register R/W
0x0211 C I2C_SCTRL Slave Control register R/W
0x0212 S I2C_SSTAT Slave Status register R/W
0x0213 C I2C_SMASK Slave Mask register R/W
0x0214 D I2C_SRECREG Slave Receive register R/W
0x0215 D I2C_STRREG Slave Transmit register R/W
Table 108: I2C APB registers
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30 JTAG INTERFACE
The CLP supports the 4 standards modes available with boundary scan (SAMPLE, EXTEST, ID, BYPASS)
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31 APB REGISTERS DESCRIPTION
31.1 GENERAL-PURPOSE INPUTS OUTPUTS
31.1.1 GPIO_MODE15TO0 (CONFIGURATION REGISTER)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GM
15
GM
14
GM
13
GM
12
GM
11
GM
10
GM
9
GM
8
GM
7
GM
6
GM
5
GM
4
GM
3
GM
2
GM
1
GM
0
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..30 GM15 Configures GPIO[15] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode sensitive to level;inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
29..28 GM14 Configures GPIO[14] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; sensitive to level;inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
27..26 GM13 Configures GPIO[13] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; sensitive to level;inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
25..24 GM12 Configures GPIO[12] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; sensitive to level;inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
23..22 GM11 Configures GPIO[11] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; sensitive to level;inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
21..20 GM10 Configures GPIO[10] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; sensitive to level;inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
19..18 GM9 Configures GPIO[9] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; sensitive to level;inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
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BITS FIELD DESCRIPTION VALUES RESET VALUE
17..16 GM8 Configures GPIO[8] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; sensitive to level;inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
15..14 GM7 Configures GPIO[7] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; sensitive to level;inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
13..12 GM6 Configures GPIO[6] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; sensitive to level;inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
11..10 GM5 Configures GPIO[5] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; sensitive to level;inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
9..8 GM4 Configures GPIO[4] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; sensitive to level;inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
7..6 GM3 Configures GPIO[3] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; sensitive to level;inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
5..4 GM2 Configures GPIO[2] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; sensitive to level;inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
3..2 GM1 Configures GPIO[1] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; sensitive to level;inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
1..0 GM0 Configures GPIO[0] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; sensitive to level;inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
Note: when the field GM[X] is configured in sticky mode, the associated value INVAL[X] in GPIO_INVAL registers is
reset to its reset value
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31.1.2 GPIO_MODE31TO16 (CON FIGURATION REGISTER)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GM
31
GM
30
GM
29
GM
28
GM
27
GM
26
GM
25
GM
24
GM
23
GM
22
GM
21
GM
20
GM
19
GM
18
GM
17
GM
16
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..30 GM31 Configures GPIO[31] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; senstive to level; inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
29..28 GM30 Configures GPIO[30] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; senstive to level; inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
27..26 GM29 Configures GPIO[29] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; senstive to level; inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
25..24 GM28 Configures GPIO[28] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; senstive to level; inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
23..22 GM27 Configures GPIO[27] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; senstive to level; inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
21..20 GM26 Configures GPIO[26] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; senstive to level; inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
19..18 GM25 Configures GPIO[25] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; senstive to level; inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
17..16 GM24 Configures GPIO[24] mode 00b
01b
10b
free mode; sensitive to level
free mode; senstive to level; inverts value
sticky mode; sensitive to rising edge
00b
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BITS FIELD DESCRIPTION VALUES RESET VALUE
11b sticky mode; sensitive to falling edge
15..14 GM23 Configures GPIO[23] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; senstive to level; inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
13..12 GM22 Configures GPIO[22] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; senstive to level; inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
11..10 GM21 Configures GPIO[21] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; senstive to level; inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
9..8 GM20 Configures GPIO[20] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; senstive to level; inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
7..6 GM19 Configures GPIO[19] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; senstive to level; inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
5..4 GM18 Configures GPIO[18] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; senstive to level; inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
3..2 GM17 Configures GPIO[17] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; senstive to level; inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
1..0 GM16 Configures GPIO[16] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; senstive to level; inverts value
sticky mode; sensitive to a rising edge
sticky mode; sensitive to a falling edge
00b
Note: when the field GM[X] is configured in sticky mode, the associated value INVAL[X] in GPIO_INVAL registers is
reset to its reset value
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31.1.3 GPIO_MODE47TO32 (CON FIGURATION REGISTER)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GM
47
GM
46
GM
45
GM
44
GM
43
GM
42
GM
41
GM
40
GM
39
GM
38
GM
37
GM
36
GM
35
GM
34
GM
33
GM
32
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..30 GM47 Configures GPIO[47] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; sensitive to level; inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
29..28 GM46 Configures GPIO[46] mode idem 00b
27..26 GM45 Configures GPIO[45] mode idem 00b
25..24 GM44 Configures GPIO[44] mode idem 00b
23..22 GM43 Configures GPIO[43] mode idem 00b
21..20 GM42 Configures GPIO[42] mode idem 00b
19..18 GM41 Configures GPIO[41] mode idem 00b
17..16 GM40 Configures GPIO[40] mode idem 00b
15..14 GM39 Configures GPIO[39] mode idem 00b
13..12 GM38 Configures GPIO[38] mode idem 00b
11..10 GM37 Configures GPIO[37] mode idem 00b
9..8 GM36 Configures GPIO[36] mode idem 00b
7..6 GM35 Configures GPIO[35] mode idem 00b
5..4 GM34 Configures GPIO[34] mode idem 00b
3..2 GM33 Configures GPIO[33] mode idem 00b
1..0 GM32 Configures GPIO[32] mode idem 00b
Note: when the field GM[X] is configured in sticky mode, the associated value INVAL[X] in GPIO_INVAL registers is
reset to its reset value
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31.1.4 GPIO_MODE63TO48 (CONFIGURATION REGISTER)
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..30 GM63 Configures GPIO[63] mode 00b 01b 10b 11b
free mode; sensitive to level free mode; senstive to level; inverts value sticky mode; sensitive to rising edge sticky mode; sensitive to falling edge
00b
29..28 GM62 Configures GPIO[62] mode idem 00b
27..26 GM61 Configures GPIO[61] mode idem 00b
25..24 GM60 Configures GPIO[60] mode idem 00b
23..22 GM59 Configures GPIO[59] mode idem 00b
21..20 GM58 Configures GPIO[58] mode idem 00b
19..18 GM57 Configures GPIO[57] mode idem 00b
17..16 GM56 Configures GPIO[56] mode idem 00b
15..14 GM55 Configures GPIO[55] mode idem 00b
13..12 GM54 Configures GPIO[54] mode idem 00b
11..10 GM53 Configures GPIO[53] mode idem 00b
9..8 GM52 Configures GPIO[52] mode idem 00b
7..6 GM51 Configures GPIO[51] mode idem 00b
5..4 GM50 Configures GPIO[50] mode idem 00b
3..2 GM49 Configures GPIO[49] mode idem 00b
1..0 GM48 Configures GPIO[48] mode idem 00b
Note: when the field GM[X] is configured in sticky mode, the associated value INVAL[X] in GPIO_INVAL registers is reset to its reset value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GM
63
GM
62
GM
61
GM
60
GM
59
GM
58
GM
57
GM
56
GM
55
GM
54
GM
53
GM
52
GM
51
GM
50
GM
49
GM
48
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31.1.5 GPIO_MODE79TO64 (CONFIGURATION REGISTER)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GM
79
GM
78
GM
77
GM
76
GM
75
GM
74
GM
73
GM
72
GM
71
GM
70
GM
69
GM
68
GM
67
GM
66
GM
65
GM
64
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..30 GM79 Configures GPIO[79] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; senstive to level; inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
29..28 GM78 Configures GPIO[78] mode idem 00b
27..26 GM77 Configures GPIO[77] mode idem 00b
25..24 GM76 Configures GPIO[76] mode idem 00b
23..22 GM75 Configures GPIO[75] mode idem 00b
21..20 GM74 Configures GPIO[74] mode idem 00b
19..18 GM73 Configures GPIO[73] mode idem 00b
17..16 GM72 Configures GPIO[72] mode idem 00b
15..14 GM71 Configures GPIO[71] mode idem 00b
13..12 GM70 Configures GPIO[70] mode idem 00b
11..10 GM69 Configures GPIO[69] mode idem 00b
9..8 GM68 Configures GPIO[68] mode idem 00b
7..6 GM67 Configures GPIO[67] mode idem 00b
5..4 GM66 Configures GPIO[66] mode idem 00b
3..2 GM65 Configures GPIO[65] mode idem 00b
1..0 GM64 Configures GPIO[64] mode idem 00b
Note: when the field GM[X] is configured in sticky mode, the associated value INVAL[X] in GPIO_INVAL registers is
reset to its reset value
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31.1.6 GPIO_MODE95TO80 (CON FIGURATION REGISTER)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GM
95
GM
94
GM
93
GM
92
GM
91
GM
90
GM
89
GM
88
GM
87
GM
86
GM
85
GM
84
GM
83
GM
82
GM
81
GM
80
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..30 GM95 Configures GPIO[95] mode 00b
01b
10b
11b
free mode; sensitive to level
free mode; senstive to level; inverts value
sticky mode; sensitive to rising edge
sticky mode; sensitive to falling edge
00b
29..28 GM94 Configures GPIO[94] mode idem 00b
27..26 GM93 Configures GPIO[93] mode idem 00b
25..24 GM92 Configures GPIO[92] mode idem 00b
23..22 GM91 Configures GPIO[91] mode idem 00b
21..20 GM90 Configures GPIO[90] mode idem 00b
19..18 GM89 Configures GPIO[89] mode idem 00b
17..16 GM88 Configures GPIO[88] mode idem 00b
15..14 GM87 Configures GPIO[87] mode idem 00b
13..12 GM86 Configures GPIO[86] mode idem 00b
11..10 GM85 Configures GPIO[85] mode idem 00b
9..8 GM84 Configures GPIO[84] mode idem 00b
7..6 GM83 Configures GPIO[83] mode idem 00b
5..4 GM82 Configures GPIO[82] mode idem 00b
3..2 GM81 Configures GPIO[81] mode idem 00b
1..0 GM80 Configures GPIO[80] mode idem 00b
Note: when the field GM[X] is configured in sticky mode, the associated value INVAL[X] in GPIO_INVAL registers is
reset to its reset value
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31.1.7 GPIO_OZ15TO0 (CONFIGURATION REGISTER)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GO
Z15
GO
Z14
GO
Z13
GO
Z12
GO
Z11
GO
Z10
GO
Z9
GO
Z8
GO
Z7
GO
Z6
GO
Z5
GO
Z4
GO
Z3
GO
Z2
GO
Z1
GO
Z0
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..30 GOZ15 Controls GPIO[15] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
29..28 GOZ14 Controls GPIO[14] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
27..26 GOZ13 Controls GPIO[13] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
25..24 GOZ12 Controls GPIO[12] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
23..22 GOZ11 Controls GPIO[11] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
21..20 GOZ10 Controls GPIO[10] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
19..18 GOZ9 Controls GPIO[9] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
17..16 GOZ8 Controls GPIO[8] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
15..14 GOZ7 Controls GPIO[7] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
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BITS FIELD DESCRIPTION VALUES RESET VALUE
13..12 GOZ6 Controls GPIO[6] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
11..10 GOZ5 Controls GPIO[5] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
9..8 GOZ4 Controls GPIO[4] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
7..6 GOZ3 Controls GPIO[3] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
5..4 GOZ2 Controls GPIO[2] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
3..2 GOZ1 Controls GPIO[1] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
1..0 GOZ0 Controls GPIO[0] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
31.1.8 GPIO_OZ31TO16 (CONFIGURATION REGISTER)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GO
Z31
GO
Z30
GO
Z29
GO
Z28
GO
Z27
GO
Z26
GO
Z25
GO
Z24
GO
Z23
GO
Z22
GO
21
GO
20
GO
Z19
GO
Z18
GO
Z17
GO
Z16
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..30 GOZ31 Controls GPIO[31] output state and Low/high impedance 00b
01b
‘0’
‘1’
10b
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BITS FIELD DESCRIPTION VALUES RESET VALUE
1xb High impedance
29..28 GOZ30 Controls GPIO[30] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
27..26 GOZ29 Controls GPIO[29] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
25..24 GOZ28 Controls GPIO[28] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
23..22 GOZ27 Controls GPIO[27] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
21..20 GOZ26 Controls GPIO[26] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
19..18 GOZ25 Controls GPIO[25] output state and Low/high impedance 00
01
1x
‘0’
‘1’
High impedance
10b
17..16 GOZ24 Controls GPIO[24] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
15..14 GOZ23 Controls GPIO[23] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
13..12 GOZ22 Controls GPIO[22] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
11..10 GOZ21 Controls GPIO[21] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
9..8 GOZ20 Controls GPIO[20] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
7..6 GOZ19 Controls GPIO[19] output state and Low/high impedance 00b
01b
‘0’
‘1’
10b
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BITS FIELD DESCRIPTION VALUES RESET VALUE
1xb High impedance
5..4 GOZ18 Controls GPIO[18] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
3..2 GOZ17 Controls GPIO[17] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
1..0 GOZ16 Controls GPIO[16] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
31.1.9 GPIO_OZ47TO32 (CONFIGURATION REGISTER)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GO
Z47
GO
Z46
GO
Z45
GO
Z44
GO
Z43
GO
Z42
GO
Z41
GO
Z40
GO
Z39
GO
Z38
GO
37
GO
36
GO
Z35
GO
Z34
GO
Z33
GO
Z32
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..30 GOZ47 Controls GPIO[47] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
29..28 GOZ46 Controls GPIO[46] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
27..26 GOZ45 Controls GPIO[45] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
25..24 GOZ44 Controls GPIO[44] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
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BITS FIELD DESCRIPTION VALUES RESET VALUE
23..22 GOZ43 Controls GPIO[43] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
21..20 GOZ42 Controls GPIO[42] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
19..18 GOZ41 Controls GPIO[41] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
17..16 GOZ40 Controls GPIO[40] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
15..14 GOZ39 Controls GPIO[39] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
13..12 GOZ38 Controls GPIO[38] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
11..10 GOZ37 Controls GPIO[37] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
9..8 GOZ36 Controls GPIO[36] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
7..6 GOZ35 Controls GPIO[35] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
5..4 GOZ34 Controls GPIO[34] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
3..2 GOZ33 Controls GPIO[33] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
1..0 GOZ32 Controls GPIO[32] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
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31.1.10 GPIO_OZ63TO48 (CONFIGURATION REGISTER)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GO
Z63
GO
Z62
GO
Z61
GO
Z60
GO
Z59
GO
Z58
GO
Z57
GO
Z56
GO
Z55
GO
Z54
GO
53
GO
52
GO
Z51
GO
Z50
GO
Z49
GO
Z48
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..30 GOZ63 Controls GPIO[63] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
29..28 GOZ62 Controls GPIO[62] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
27..26 GOZ61 Controls GPIO[61] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
25..24 GOZ60 Controls GPIO[60] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
23..22 GOZ59 Controls GPIO[59] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
21..20 GOZ58 Controls GPIO[58] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
19..18 GOZ57 Controls GPIO[57] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
17..16 GOZ56 Controls GPIO[56] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
15..14 GOZ55 Controls GPIO[55] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
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BITS FIELD DESCRIPTION VALUES RESET VALUE
13..12 GOZ54 Controls GPIO[54] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
11..10 GOZ53 Controls GPIO[53] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
9..8 GOZ52 Controls GPIO[52] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
7..6 GOZ51 Controls GPIO[51] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
5..4 GOZ50 Controls GPIO[50] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
3..2 GOZ49 Controls GPIO[49] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
1..0 GOZ48 Controls GPIO[48] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
31.1.11 GPIO_OZ79TO64 (CONFIGURATION REGISTER)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GO
Z79
GO
Z78
GO
Z77
GO
Z76
GO
Z75
GO
Z74
GO
Z73
GO
Z72
GO
Z71
GO
Z70
GO
Z69
GO
Z68
GO
Z67
GO
Z66
GO
Z65
GO
Z64
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..30 GOZ79 Controls GPIO[79] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
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BITS FIELD DESCRIPTION VALUES RESET VALUE
29..28 GOZ78 Controls GPIO[78] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
27..26 GOZ77 Controls GPIO[77] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
25..24 GOZ76 Controls GPIO[76] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
23..22 GOZ75 Controls GPIO[75] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
21..20 GOZ74 Controls GPIO[74] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
19..18 GOZ73 Controls GPIO[73] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
17..16 GOZ72 Controls GPIO[72] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
15..14 GOZ71 Controls GPIO[71] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
13..12 GOZ70 Controls GPIO[70] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
11..10 GOZ69 Controls GPIO[69] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
9..8 GOZ68 Controls GPIO[68] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
7..6 GOZ67 Controls GPIO[67] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
5..4 GOZ66 Controls GPIO[66] output state and Low/high impedance 00b ‘0’ 10b
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BITS FIELD DESCRIPTION VALUES RESET VALUE
01b
1xb
‘1’
High impedance
3..2 GOZ65 Controls GPIO[65] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
1..0 GOZ64 Controls GPIO[64] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
31.1.12 GPIO_OZ95TO80 (CONFIGURATION REGISTER)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GO
Z95
GO
Z94
GO
Z93
GO
Z92
GO
Z91
GO
Z90
GO
Z89
GO
Z88
GO
Z87
GO
Z86
GO
85
GO
84
GO
Z83
GO
Z82
GO
Z81
GO
Z80
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..30 GOZ95 Controls GPIO[95] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
29..28 GOZ94 Controls GPIO[94] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
27..26 GOZ93 Controls GPIO[93] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
25..24 GOZ92 Controls GPIO[92] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
23..22 GOZ91 Controls GPIO[91] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
21..20 GOZ90 Controls GPIO[90] output state and Low/high impedance 00b ‘0’ 10b
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BITS FIELD DESCRIPTION VALUES RESET VALUE
01b
1xb
‘1’
High impedance
19..18 GOZ89 Controls GPIO[89] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
17..16 GOZ88 Controls GPIO[88] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
15..14 GOZ87 Controls GPIO[87] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
13..12 GOZ86 Controls GPIO[86] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
11..10 GOZ85 Controls GPIO[85] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
9..8 GOZ84 Controls GPIO[84] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
7..6 GOZ83 Controls GPIO[83] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
5..4 GOZ82 Controls GPIO[82] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
3..2 GOZ81 Controls GPIO[81] output state and Low/high impedance 00b
01b
1xb
‘0’
‘1’
High impedance
10b
1..0 GOZ80 Controls GPIO[80] output state and Low/high impedance 00b
01b
1xb
‘1’
‘0’
High impedance
10b
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31.1.13 GPIO_INVAL31TO0 (DATA REGISTER)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INV
AL3
1
INV
AL3
0
INV
AL2
9
INV
AL2
8
INV
AL2
7
INV
AL2
6
INV
AL2
5
INV
AL2
4
INV
AL2
3
INV
AL2
2
INV
AL2
1
INV
AL2
0
INV
AL1
9
INV
AL1
8
INV
AL1
7
INV
AL1
6
INV
AL1
5
INV
AL1
4
INV
AL1
3
INV
AL1
2
INV
AL1
1
INV
AL1
0
INV
AL9
INV
AL8
INV
AL7
INV
AL6
INV
AL5
INV
AL4
INV
AL3
INV
AL2
INV
AL1
INV
AL0
BITS FIELD DESCRIPTION VALUES RESET VALUE
31 INVAL31 GPIO[31] read value according to selected mode
(cfr GPIO_MODE31TO16)
0b
30 INVAL30 GPIO[30] read value according to selected mode
(cfr GPIO_MODE31TO16)
0b
.. 0b
... 0b
1 INVAL1 GPIO[1] read value according to selected mode
(cfr GPIO_MODE15TO0)
0b
0 INVAL0 GPIO[0] read value according to selected mode
(cfr GPIO_MODE15TO0)
0b
* Reset value corresponds to the state of these fields after the boot (CPU is in active state).
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31.1.14 GPIO_INVAL63TO32 (DATA REGISTER)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INV
AL6
3
INV
AL6
2
INV
AL6
1
INV
AL6
0
INV
AL5
9
INV
AL5
8
INV
AL5
7
INV
AL5
6
INV
AL5
5
INV
AL5
4
INV
AL5
3
INV
AL5
2
INV
AL5
1
INV
AL5
0
INV
AL4
9
INV
AL4
8
INV
AL4
7
INV
AL4
6
INV
AL4
5
INV
AL4
4
INV
AL4
3
INV
AL4
2
INV
AL4
1
INV
AL4
0
INV
AL3
9
INV
AL3
8
INV
AL3
7
INV
AL3
6
INV
AL3
5
INV
AL3
4
INV
AL3
3
INV
AL3
2
BITS FIELD DESCRIPTION VALUES RESET VALUE
31 INVAL63 GPIO[63] read value according to selected mode
(cfr GPIO_MODE63TO48)
0b
30 INVAL62 GPIO[62] read value according to selected mode
(cfr GPIO_MODE63TO48)
0b
.. 0b
... 0b
1 INVAL33 GPIO[33] read value according to selected mode
(cfr GPIO_MODE47TO32)
0b
0 INVAL32 GPIO[32] read value according to selected mode
(cfr GPIO_MODE47TO32)
0b
* Reset value corresponds to the state of these fields after the boot (CPU is in active state).
31.1.15 GPIO_INVAL95TO64 (DATA REGISTER)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INV
AL9
5
INV
AL9
4
INV
AL9
3
INV
AL9
2
INV
AL9
1
INV
AL9
0
INV
AL8
9
INV
AL8
8
INV
AL8
7
INV
AL8
6
INV
AL8
5
INV
AL8
4
INV
AL8
3
INV
AL8
2
INV
AL8
1
INV
AL8
0
INV
AL7
9
INV
AL7
8
INV
AL7
7
INV
AL7
6
INV
AL7
5
INV
AL7
4
INV
AL7
3
INV
AL7
2
INV
AL7
1
INV
AL7
0
INV
AL6
9
INV
AL6
8
INV
AL6
7
INV
AL6
6
INV
AL6
5
INV
AL6
4
BITS FIELD DESCRIPTION VALUES RESET VALUE
31 INVAL95 GPIO[95] read value according to selected mode
(cfr GPIO_MODE95TO80)
0b
30 INVAL94 GPIO[94] read value according to selected mode
(cfr GPIO_MODE95TO80)
0b
.. 0b
... 0b
1 INVAL65 GPIO[65] read value according to selected mode
(cfr GPIO_MODE79TO64)
0b
0 INVAL64 GPIO[64] read value according to selected mode
(cfr GPIO_MODE79TO64)
0b
* Reset value corresponds to the state of these fields after the boot (CPU is in active state).
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31.1.16 GPIO_MEM8CONF (CONTROL REGISTER)
31 23 22 21 18 17 14 13 10 9 0
NO
T U
SED
MEM
8SE
L
D2L
EN
D1L
EN
D0L
EN
BR
ST
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..23 - NOT USED 0..0b
22 MEM8SEL Select 8-bit interface. When set, the associated IOMUX pins are automatically routed to MEM8_x I/Os
1b
0b
Enable
disable
0b
21..18 D2LEN D2 duration length
(cfr 12.2.1)
0000b
0001b
...
1111b
1 clock cycle
2 clock cycles
...
16 clock cycles
1111b
17..14
D1LEN D1 duration length
(cfr 12.2.1)
0000b
0001b
...
1111b
1 clock cycle
2 clock cycles
...
16 clock cycles
1111b
13..10
D0LEN D0 duration length
(cfr 12.2.1))
0000b
0001b
...
1111b
1 clock cycle
2 clock cycles
...
16 clock cycles
1111b
9..0 BRST Burst Type selection
(cfr 12.2.1))
0000000000b
0000000001b
0000000010b
others
1*8-bit(no burst)
1*8-bit(no burst)
2 * 8-bit
4 * 8-bit
0..0b
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31.1.17 GPIO_MEM8ADD (DATA REGISTER)
31 20 19 18 0
NOT USED R/W ADD19
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..20 - NOT USED - - 0..0b
19 RW Read/Write selection on MEM8_CSB/OEB/RWB control signals 0b
1b
Write
Read
0b
18..0 ADD19 19-bit address, mapped to MEM8_ADD[18:0] outputs - - 0..0b
31.1.18 GPIO_MEM8RDATA (DATA REGISTER)
31 0
RA
DA
TA
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..0 RDATA 32-bit register mapped to the data read on MEM8_DATA[31:0] during the last read requested via GPIO_MEM8ADD register (RW field).
If BRST was set to 8-bit, data is aligned to the 8 LSBs (others=’0’)
If BRST was set to 16-bit, data is aligned to the 16 LSBs (others=’0’)
If BRST was set to 32-bit, data is aligned to the 32 LSBs
- - 0..0b
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31.1.19 GPIO_MEM8WDATA (DATA REGISTER)
31 0
WD
ATA
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..0 WDATA 32-bit register mapped to the data to be written on the MEM8_DATA[31:0] outputs and when a write is requested via GPIO_MEM8ADD register (RW field).
If BRST is set to 8-bit, only the 8 LSBs are taken into account
If BRST is set to 16-bit, only the 16 LSBs are taken into account. The first 8 LSBs are transmitted first.
If BRST is set to 32-bit, the whole 32-bits are taken into account. The first 8 LSBs are transmitted first and then the next 8 LSBs
- - 0..0b
31.1.20 GPIO_MEM8STAT (STATUS REGISTER)
31 1 0
NO
T U
SED
STA
T
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..2 - NOT USED 0..0b
1..0 STAT 8-bit memory interface status 00b
01b
1Xb
WRITING
IDLE
READING
01b
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31.2 ADC INTERFACE
31.2.1 ADCIF_TIMSEL (CONFIGURATION REGISTER)
31 5 4 3 2 1 0
NO
T U
SED
MO
NEN
TIM
ERSE
L
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..5 - Not used - 0000b
4 MONEN Enables monitoring function 1b
0b
Enable
Disable
0b
3..0 TIMERSEL TIMER SELECTION 0000b
...
1001b
others
TIMER0
...
TIMER9
TIMER9
0000b
31.2.2 ADCIF_ACQSEL (CONFIGURATION REGISTER)
31 4 3 2 1 0
NO
T
USE
D
BU
FMO
DE
AD
CSE
L3
AD
CSE
L2
AD
CSE
L1
AD
CSE
L0
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..5 - Not used - 0000b
4 BUFMODE Selects either direct or toggle buffer mode 1b
0b
Toggle
Direct
0b
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3 SELADC3 Selection of acquisition pulse on ADCIF_CS[3] 1b
0b
Enable
Disable
0b
2 SELADC2 Selection of acquisition pulse on ADCIF_CS[2] 1b
0b
Enable
Disable
0b
1 SELADC1 Selection of acquisition pulse on ADCIF_CS[1] 1b
0b
Enable
Disable
0b
0 SELADC0 Selection of acquisition pulse on ADCIF_CS[0] 1b
0b
Enable
Disable
0b
Note: SELADCx fields can be used as ADCs interface enable bits.
31.2.3 ADCIF_READSEL5TO0 (CONFIGURATION REGISTER)
31 18 17 15 14 12 11 9 8 6 5 3 2 0
NO
T
USE
D
REA
DSE
L5
REA
DSE
L4
REA
DSE
L3
REA
DSE
L2
REA
DSE
L1
REA
DSE
L0
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..18 - Not used - 00..00b
17..15 READSEL5 6th transfer in ADC reading sequence 111b
000b
001b
010b
011b
others
Forbidden
ADCIF_CS[0]
ADCIF_CS[1]
ADCIF_CS[2]
ADCIF_CS[3]
No transfer
100b
14..12 READSEL4 5th transfer in ADC reading sequence As per READSEL5
100b
11..9 READSEL3 4th transfer in ADC reading sequence As per READSEL5
100b
8..6 READSEL2 3th transfer in ADC reading sequence As per READSEL5
100b
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5..3 READSEL1 2th transfer in ADC reading sequence As per READSEL5
100b
2..0 READSEL0 1st transfer in ADC reading sequence As per READSEL5
100b
Note : If the SELADCx is not Enabled in ADCIF_ACQSEL for an ADC, its reading sequence is replaced
by No transfer.
31.2.4 ADCIF_READSEL11TO6 (CONFIGURATION REGISTER)
31 18 17 15 14 12 11 9 8 6 5 3 2 0
NO
T
USE
D
REA
DSE
L11
REA
DSE
L10
REA
DSE
L9
REA
DSE
L8
REA
DSE
L7
REA
DSE
L6
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..18 - Not used - 00..00b
17..15 READSEL11 12th transfer in ADC reading sequence 111b
000b
001b
010b
011b
others
Forbidden
ADCIF_CS[0]
ADCIF_CS[1]
ADCIF_CS[2]
ADCIF_CS[3]
No transfer
100b
14..12 READSEL10 11th transfer in ADC reading sequence As per READSEL11
100b
11..9 READSEL9 10th transfer in ADC reading sequence As per READSEL11
100b
8..6 READSEL8 9th transfer in ADC reading sequence As per READSEL11
100b
5..3 READSEL7 8th transfer in ADC reading sequence As per READSEL11
100b
2..0 READSEL6 7th transfer in ADC reading sequence As per READSEL11
100b
Note : If the SELADCx is not Enabled in ADCIF_ACQSEL for an ADC, its reading sequence is replaced by No transfer.
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31.2.5 ADCIF_WAVFSEL (CONFIGURATION REGISTER)
31 28 27 26 25 24 23 12 11 0
AD
C
MU
X
MO
DE
PC
S
PR
C
PSO
C
WID
THD
2
WID
THD
1
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..28 ADC_MUX ADC MUX selection
(ADCIF_MUXSEL output pins are updated 1 clk cycle after modification of this field).
0h
1h
…
fh
Pins ADCIF_MUXSEL[3..0] = 0h
Pins ADCIF_MUXSEL[3..0] = 1h
…
Pins ADCIF_MUXSEL[3..0]= fh
0h
27 MODE * Select waveform type 0b
1b
Mode 1
Mode 2
0b
26 PCS * Selects ADCIF_CS[3:0] polarity 0b
1b
Active low
Active high
0b
25 PRC * Selects ADCIF_RC polarity 0b
1b
Active low
Active high
0b
24 PSOC * Selects ADCIF_SOC polarity 0b
1b
Active low
Active high
0b
23..12 WIDTHD1 * Dilatation time for parameter D1 (mode 1 only)
000h
001h
...
ffeh
fffh
1 clock cycle
2 clock cycle
...
4095 clock cycles
4096 clock cycles
fffh
11..0 WIDTHD0 * Dilatation time for parameter D0 (mode 2 only)
000h
001h
...
ffeh
fffh
1 clock cycle
2 clock cycle
...
4095 clock cycles
4096 clock cycles
fffh
* Those fields are read-only when at least one SELADCx bit is enabled (register ADCIF_ACQSEL cfr 31.2.2)
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31.2.6 ADCIF_REG0 TO ADCIF_REG11 (DATA REGISTER)
31 16 15 0 N
OT
USE
D
DA
TA
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..16 - Not used - 00..00b
15..0 DATA xth 16-bit data read during ADC reading sequence. If toggle buffer mode is selected (cfr BUFMODE IN ADC_ACQSEL), the register points to the samples that were read during the previous sequence. Otherwise, it points to the samples read in the current sequence
- - 0000h
31.3 UART
31.3.1 UART0_DATA8_RCV, … , UART3_DATA8_RCV (8-BIT WORD FIFO RECEIVE) (DATA REGISTER)
31
8 7 0
RES
ERV
ED
RD
ATA
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..8 R RESERVED (R) - Read as zero and should be written as zero to ensure forward compatibility.
00..00b
7..0 RDATA First incoming byte in the FIFO. 00h
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31.3.2 UART0_DATA8_TSM, … , UART3_DATA8_TSM (8-BIT WORD FIFO TRANSMIT) (DATA REGISTER)
31
8 7 0
RES
ERV
ED
TDA
TA
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..8 R RESERVED (R) - Read as zero and should be written as zero to ensure forward compatibility.
00..00b
7..0 TDATA First ongoing byte in the FIFO. 00h
31.3.3 UART0_LCR, … , UART3_LCR (LINE CONTROL REGISTER) (CONTROL REGISTER)
31
8 7 6 5 4 3 2 1 0
RES
ERV
ED
BR
K
STIC
KP
EV
PTY
PTY
EN
STP
BT
CH
AR
LEN
EN
AB
LE
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..8 R RESERVED (R) - Read as zero and should be written as zero to ensure forward compatibility.
00..00b
7 BRK Break condition (BRK)
0 = transmitter has control of UART_TX
1 = force UART_TX to 0 and cause a break condition. Under a break condition, the transmitter finishes shifting out the bits in the shift register, and remains idle until the break condition is cleared.
0b
6 STICKP Stick parity (STICKP)
0 = disable stick parity.
0b
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BITS FIELD DESCRIPTION VALUES RESET VALUE
1 = enable stick parity. Used in conjunction with LCR[4:3]. When enabled with even parity, the parity bit is sent as 0. When enabled with odd parity, the parity bit is sent as 1.
5 EVPTY Even parity (EVPTY)
0 = enable odd parity. Used in conjunction with LCR[5] and LCR[3].
1 = enable even parity. Used in conjunction with LCR[5] and LCR[3].
Even parity means the total number of ‘1’s transmitted (data bits and parity bit) is even.
0b
4 PTYEN Parity enable (PTYEN)
0 = send no parity bit after data bits.
1 = generate or check a parity bit after data bits. This has precedence over LCR[5:4].
0b
3 STPBT Stop bits (STPBT)
0 = transmit 1 stop bit after data bits are sent.
1 = transmit 1.5 stop bits for a 5-bit character, or 2 stop bits for a 6-, 7-, or 8-bit character. The receiver checks the first stop bit only regardless of the number of stop bits selected.
0b
2..1 CHARLEN Character length (CHARLEN)
00 = transmit 5 bits of data per frame.
01 = transmit 6 bit of data per frame.
10 = transmit 7 bit of data per frame.
11 = transmit 8 bit of data per frame.
00b
0 ENABLE UART Enable
0 = Disabled
1 = Enabled
0b
31.3.4 UART0_LSR, … , UART3_LSR (LINE STATUS REGISTER) (STATUS REGISTER)
31
9 8 7 6 5 4 3 2 1 0
RES
ERV
ED
TXA
CTIV
E
TXRD
Y32
TXRD
Y8
BR
KIN
D
FRM
ERR
PRTY
ERR
OV
ERR
UN
RC
VR
DY3
2
RC
VR
DY8
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..9 R RESERVED (R) - Read as zero and should be written as zero to ensure forward compatibility.
00..00b
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BITS FIELD DESCRIPTION VALUES RESET VALUE
8 TXACTIVE Transmit ongoing (TXACTIVE)
0 = UART is IDLE.
1 = UART is transmitting.
0b
7 TXRDY32 Transmit FIFO is writable with 1 word (i.e 4 bytes) (TXRDY32)
0 = transmit FIFO is full.
1 = the transmit FIFO is writable with four words.
1b
6 TXRDY8 Transmit FIFO is writable with 1 byte (TXRDY8)
0 = transmit FIFO is full.
1 = the transmit FIFO is writable with one word (i.e 4 bytes).
1b
5 BRKIND Break indication (BRKIND)
This is set to 1 if the receiver detects a string of 0 for longer than a full word transmission time. The receiver remains idle until it detects a valid start bit.
0b
4 FRMERR Framing error (FRMERR)
This is set to 1 when the received character has an invalid stop bit.
This bit is cleared after read.
0b
3 PRTYERR Parity error (PRTYERR)
This is set to 1 when the received character has an incorrect parity bit. This is associated with a particular character in the FIFO.
This bit is cleared after read.
0b
2 OVERRUN Overrun error (OVERRUN)
This is set to 1 when the receiver FIFO (containing 16 bytes) is full and a completed character in the receive shift register is destroyed. All new data is discarded until old data has been read out of the FIFO.
This bit is cleared after read.
0b
1 RCVRDY32 Receiver data ready (RCVRDY32)
0 = the receive FIFO is empty.
1 = four bytes are ready to be read from the receive FIFO.
0b
0 RCVRDY8 Receiver data ready (RCVRDY8)
0 = the receive FIFO is empty.
1 = one byte is ready to be read from the receive FIFO.
0b
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31.3.5 UART0_FCR, … , UART3_FCR (FIFO CONTROL REGISTER) (CONTROL REGISTER)
31
2 1 0
RES
ERV
ED
CLR
TRS
CLR
RC
V
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..2 R RESERVED (R) - Read as zero and should be written as zero to ensure forward compatibility.
00..00b
1 CLRTRS Clear transmit FIFO (CLRTRS)
Set this to 1 to reset the transmit FIFO. This bit is self-clearing, and does
not clear the transmit shift register.
0b
0 CLRRCV Clear receive FIFO (CLRRCV)
Set this to 1 to reset the receive FIFO. This bit is self-clearing, and does
not clear the receive shift register.
0b
31.3.6 UART0_DR, … , UART3_DR (DIVISOR REGISTER) (CONTROL REGISTER)
31
8 7
0
RE
SE
RV
ED
DIV
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..8 R RESERVED (R) - Read as zero and should be written as zero to ensure forward compatibility.
00..00b
7..0 DIV Divisor (DIV)
The Divisor shall determine the UART TX and RX Baud Rate.
It shal be given by the next equation:
DIV=0
DIV=255
BR=Freq_CLP/16
BR=Freq_CLP/4096
00h
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BR= Freq_CLP/((DIV+1)*16)
The CLP shall generate a new internal clock for ensuring oversampling of the received bits.
31.3.7 UART0_DATA32_RCV, … , UART3_DATA32_RCV (32-BIT WORD FIFO RECEIVE) (DATA REGISTER)
31 24 23 16 15 8 7 0
BYTE 3
BYTE 2
BYTE 1
BYTE 0
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..24 BYTE3 Fourth incoming byte in the FIFO.
00h
23..16 BYTE2 Third incoming byte in the FIFO.
00h
15..8 BYTE1 Second incoming byte in the FIFO.
00h
7..0 BYTE0 First incoming byte in the FIFO.
00h
31.3.8 UART0_DATA32_TSM, … , UART3_DATA32_TSM (32-BIT WORD FIFO TRANSMIT) (DATA REGISTER)
31 24 23 16 15 8 7 0
BYTE 3
BYTE 2
BYTE 1
BYTE 0
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..24 BYTE3 Fourth ongoing byte in the FIFO. 00h
23..16 BYTE2 Third ongoing byte in the FIFO. 00h
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15..8 BYTE1 Second ongoing byte in the FIFO
00h
7..0 BYTE0 First ongoing byte in the FIFO 00h
31.4 CRC
31.4.1 CRC0_POL, CRC1_POL (CONFIGURATION REGISTER)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W3
1
W3
0
W2
9
W2
8
W2
7
W2
6
W2
5
W2
4
W2
3
W2
2
W2
1
W2
0
W1
9
W1
8
W1
7
W1
6
W1
5
W1
4
W1
3
W1
2
W1
1
W1
0
W9
W8
W7
W6
W5
W4
W3
W2
W1
W0
BITS FIELD DESCRIPTION VALUES RESET VALUE
31 W31 weight for x31 1b
0b
1*x31
0*x31
0b
30 W30 weight for x30 1b
0b
1*x30
0*x30
0b
... ... ... ... ... W26,W23,W22,W16,W12,W11,W10,W8,W7,W5,W4,W2,W1,W0=1
Others=0
1 W1 weight for x1 1b
0b
1*x1
0*x1
1b
0 W0 weight for x0(=1) 1b
0b
1
0
1b
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31.4.2 CRC0_CFG, CRC1_CFG (CONFIGURATION REGISTER)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NO
T U
SED
CLE
AR
SP
YMO
D
BITS FIELD DESCRIPTION VALUES RESET VALUE
31-2 NOT USED 00..00b
1 CLEAR Clears reminder of CRC (Remainder is set to 0xFFFFFFFF) *
1b
0b
Clear reminder
Nothing to do
0b
0 SPYMOD Programs state of SPY MODE bit in CRC0 unit **
1b
0b
SPY MODE on
SPY MODE off
0b
Notes:
* CLEAR Bit is automatically set to 0b after clearing the remainder.
** SPYMOD is only available for CRC0 unit
31.4.3 CRC0_DATA_IN, CRC1_DATA_IN (DATA REGISTER)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
A31
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BITS FIELD DESCRIPTION VALUES RESET VALUE
31 A31 weight for x31 1b
0b
1*x31
0*x31
*
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BITS FIELD DESCRIPTION VALUES RESET VALUE
30 A30 weight for x30 1b
0b
1*x30
0*x30
*
... ... ... ... ... *
1 A1 weight for x1 1b
0b
1*x1
0*x1
*
0 A0 weight for x0(=1) 1b
0b
1
0
*
(*) CRC0_DATA_OUT reset value depends on the Boot Frames. CRC1_DATA_OUT reset value is 0xFFFFFFFF
31.4.4 CRC0_DATA_OUT, CRC1_DATA_OUT (DATA REGISTER)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R31
R30
R29
R28
R27
R26
R25
R24
R23
R22
R21
R20
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
BITS FIELD DESCRIPTION VALUES RESET VALUE
31 R31 weight for x31 1b
0b
1*x31
0*x31
0b
30 R30 weight for x30 1b
0b
1*x30
0*x30
0b
... ... ... ... ... 0b
1 R1 weight for x1 1b
0b
1*x1
0*x1
0b
0 R0 weight for x0(=1) 1b
0b
1
0
0b
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31.4.5 CRC0_STAT, CRC1_STAT (STATUS REGISTER)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NO
T U
SED
CR
CO
K
BITS FIELD DESCRIPTION VALUES RESET VALUE
31-1 NOT USED 00..00b
0 CRCOK CRC calculation status 1b
0b
CRC OK
CRC FAIL
0b
31.5 SPI
31.5.1 SPI0_CAPAREG, SPI1_CAPAREG (CONTROL REGISTER)
This register is READ-ONLY and described the supported SPI functinalities
31 24 23 20 19 18 17 16 15
8 7 6 5 4
0
SSSZ
MA
XW
LEN
TWEN
AM
OD
E
ASE
LA
SSEN
FDEP
TH
NO
T U
SED
REV
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..24 SSSZ Slave Select register size – contains the number of available slave select signals. This field is only valid is the SSEN bit (bit 16) is ‘1
- - 0Ch
23..20 MAXWLEN Maximum word Length - The maximum word length supported by the IP
0b0000 - 4-16, and 32-bit word length
- - 0000b
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BITS FIELD DESCRIPTION VALUES RESET VALUE
0b0011-0b1111 - Word length is MAXWLEN+1, allows words of length 4-16 bits.
The core must not be configured to use a word length greater than what is defined by this register.
19 TWEN Three-wire mode Enable - If this bit is ‘1’, the core supports three-wire mode.
1b
0b
SUPPORTED
NOT SUPP.
1b
18 AMODE Auto mode - If this bit is ‘1’, the core supports Automated transfers.
1b
0b
SUPPORTED
NOT SUPP.
1b
17 ASELA Automatic slave select available - If this bit is set, the core has support for setting slave select signals automatically.
1b
0b
SUPPORTED
NOT SUPP.
1b
16 SSEN Slave Select Enable - If the core has a slave select register, and corresponding slave select lines, the value of this field is one. Otherwise the value of this field is zero.
1b
0b
SUPPORTED
NOT SUPP.
1b
15..8 FDEPTH FIFO depth - This field contains the depth of the core’s internal FIFOs. The number of words the core can store in each queue is FDEPTH+1, since the transmit and receive registers can contain one word each.
00h
..
FFh
1
...
256
10h
7..5 NOT USED 000b
4..0 REV Core revision - This manual applies to IP revision . - - 0101b
31.5.2 SPI0_MODREG, SPI1_MODREG (CONTROL REGISTER)
31 30 29 28 27 26 25 24 23 20 19 16 15 14 13 12 11
7 6 5 4 3 2 1 0
AM
EN
LOO
P
CP
OL
CP
HA
DIV
16
REV
MS
EN
LEN
PM
TWEN
ASE
L
FAC
T
OD
CG
ASE
LDEL
TAC
TT
O
IGSE
L
CIT
E
CC
S/C
DO
L
BITS FIELD DESCRIPTION VALUES RESET VALUE
31 AMEN
Auto mode enable (AMEN) - When this bit is set to ‘1’ the core will be able to perform automated periodic transfers. See the AM registers below. The core supports this mode if the AMODE field in the capability register is set to ‘1’. Otherwise writes to this field has no effect. When this bit is set to ‘1’ the core can only perform automated transfers. Software is allowed to initialize the transmit queue
0b
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BITS FIELD DESCRIPTION VALUES RESET VALUE
and to read out the receive queue but no transfers except the automated periodic transfers may be performed. The core must be configured to act as a master (MS field set to ‘1’) when performing automated transfers.
30 LOOP
Loop mode (LOOP) - When this bit is set, and the core is enabled, the core’s transmitter and receiver are interconnected and the core will operate in loopback mode. The core will still detect, and will be disabled, on Multiple-master errors.
0b
29 CPOL Clock polarity (CPOL) - Determines the polarity (idle state) of the SCK clock.
0b
28 CPHA Clock phase (CPHA) - When CPHA is ‘0’ data will be read on the first transition of SCK. When CPHA is ‘1’ data will be read on the second transition of SCK.
0b
27 DIV16 Divide by 16 (DIV16) - Divide system clock by 16, see description of PM field below. This bit has no significance in slave mode.
0b
26 REV
Reverse data (REV) - When this bit is ‘0’ data is transmitted LSB first, when this bit is ‘1’ data is transmitted MSB first. This bit affects the layout of the transmit and receive registers.
0b
25 MS
Master/Slave (MS) - When this bit is set to ‘1’ the core will act as a master, when this bit is set to ‘0’ the core will operate in slave mode. This bit is set to 0 if a multiple master error occurs.
0b
24 EN
Enable core (EN) - When this bit is set to ‘1’ the core is enabled. No fields in the mode register should be changed while the core is enabled. This bit can be set to ‘0’ by software, or by the core if a multiple-master error occurs.
0b
23..20 LEN
Word length (LEN) - The value of this field determines the length in bits of a transfer on the SPI bus. Values are interpreted as:
0b0000 - 32-bit word length
0b0001-0b0010 - Illegal values
0b0011-0b1111 - Word length is LEN+1,
allows words of length 4-16 bits.
The value of this field must never specify a word length that is greater than the maximum allowed word length specified by the MAXWLEN field in the Capability register.
0000b
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BITS FIELD DESCRIPTION VALUES RESET VALUE
19..16 PM
Prescale modulus (PM) - This value is used in master mode to divide the system clock and generate the SPI SCK clock. The value in this field depends on the value of the FACT bit.
If bit 13 (FACT) is ‘0’:The system clock is divided by 4*(PM+1) if the DIV16 field is ‘0’ and 16*4*(PM+1) if the DIV16 field is set to ‘1’. The highest SCK frequency is attained when PM is set to 0b0000 and DIV16 to ‘0’, this configuration will give a SCK frequency that is (system clock)/4. With this setting the core is compatible with the SPI register interface found in MPC83xx SoCs.
If bit 13 (FACT) is ‘1’: The system clock is divided by 2*(PM+1) if the DIV16 field is ‘0’ and 16*2*(PM+1) if the DIV16 field is set to ‘1’. The highest SCK frequency is attained when PM is set to 0b0000 and DIV16 to ‘0’, this configuration will give a SCK frequency that is (system clock)/2.
In slave mode the value of this field defines the number of system clock cycles that the SCK input must be stable for the core to accept the state of the signal.
0000b
15 TWEN
Three-wire mode (TW) - If this bit is set to ‘1’ the core will operate in 3-wire mode. This bit can only be set if the TWEN field of the Capability register is set to ‘1’.
0b
14 ASEL
Automatic slave select (ASEL) - If this bit is set to ‘1’ the core will swap the contents in the Slave select register with the contents of the Automatic slave select register when a transfer is started and the core is in master mode. When the transmit queue is empty, the slave select register will be swapped back. Note that if the core is disabled (by writing to the core enable bit or due to a multiplemaster- error (MME)) when a transfer is in progress, the registers may still be swapped when the core goes idle. This bit can only be set if the ASELA field of the Capability register is set to ‘1’. Also see the ASELDEL field which can be set to insert a delay between the slave select register swap and the start of a transfer.
0b
13 FACT PM factor (FACT) - If this bit is 1 the core’s register interface is no longer compatible with the MPC83xx
0b
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BITS FIELD DESCRIPTION VALUES RESET VALUE
register interface. The value of this bit affects how the PM field is utilized to scale the SPI clock. See the description of the PM field.
12 OD
Open drain mode (OD) - If this bit is set to ‘0’, all pins are configured for operation in normal mode. If this bit is set to ‘1’ all pins are set to open drain mode. The implementation of the core may or may not support open drain mode. If this bit can be set to ‘1’ by writing to this location, the core supports open drain mode. The pins driven from the slave select register are not affected by the value of this bit.
0b
11..7 CG
Clock gap (CG) - The value of this field is only significant in master mode. The core will insert CG SCK clock cycles between each consecutive word. This only applies when the transmit queue is kept non-empty. After the last word of the transmit queue has been sent the core will go into an idle state and will continue to transmit data as soon as a new word is written to the transmit register, regardless of the value in CG. A value of 0b00000 in this field enables back-to-back transfers.
00000b
6..5 ASELDEL
Automatic Slave Select Delay (ASELDEL) - If the core is configured to use automatic slave select (ASEL field set to ‘1’) the core will insert a delay corresponding to ASELDEL*(SPI SCK cycle time)/2 between the swap of the slave select registers and the first toggle of the SCK clock. As an example, if this field is set to “10” the core will insert a delay corresponding to one SCK cycle between assigning the Automatic slave select register to the Slave select register and toggling SCK for the first time in the transfer. This field can only be set if the ASELA field of the Capability register is set to ‘1’.
00b
4 TAC
Toggle Automatic slave select during Clock Gap (TAC) - If this bit is set, and the ASEL field is set, the core will perform the swap of the slave select registers at the start and end of each clock gap. The clock gap is defined by the CG field and must be set to a value >= 2 if this field is set. This field can only be set if the ASELA field of the Capability register is set to ‘1’.
0b
3 TTO
3-wire Transfer Order (TTO) - This bit controls if the master or slave transmits a word first in 3-wire mode.If this bit is ‘0’, data is first transferred from the master to the slave. If this bit is ‘1’, data is first transferred from the slave to the master. This bit can
0b
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BITS FIELD DESCRIPTION VALUES RESET VALUE
only be set if the TWEN field of the Capability register is set to ‘1’.
2 IGSEL Ignore SPIx_CSI input (IGSEL) - If this bit is set to ‘1’ then the core will ignore the value of the SPIx_CSI input.
0b
1 CITE
Require Clock Idle for Transfer End (CITE) - If this bit is ‘0’ the core will regard the transfer of a word as completed when the last bit has been sampled. If this bit is set to ‘1’ the core will wait until it has set the SCK clock to its idle level (see CI field) before regarding a transfer as completed. This setting only affects the behavior of the TIP status bit, and automatic slave select toggling at the end of a transfer, when the clock phase (CPHA field) is ‘0’.
0b
0 CCS/CDOL
Common Chip Select/ Common Data Out Line – If this bit is ‘0’, the core will function with one MOSI line and 12 CS lines. If this bit is set, the CS lines become inputs and can be used for parallel acquisition. MISO is used as Chip-Select line. This mode is only available as master when 3 wires mode is not enabled.
0b
31.5.3 SPI0_EVTREG, SPI1_EVTREG (CONTROL REGISTER)
31 30 16 15 14 13 12 11 10 9 8 7
0
TIP
R
AT LT
R
OV
UN
MM
E
NE
NF R
BITS FIELD DESCRIPTION VALUES RESET VALUE
31 TIP Transfer in progress (TIP) - This bit is ‘1’ when the core has a transfer in progress. Writes have no effect. This bit is set when the core starts a transfer and is reset to ‘0’ once the
0b
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core considers the transfer to be finished. Behavior affected by setting of CITE field in Mode register.
30..16 R RESERVED (R) - Read as zero and should be written to zero to ensure forward compatibility.
0000h
15 AT
Automated transfers (AT) – This bit is ‘1’ when the core has an automated transfer in progress. This bit is cleared automatically by the core. Writes have no effect.
This bit is also cleared when auto-mode is enabled and a multiple master error occurs.
0b
14 LT
Last character (LT) - This bit is set when a transfer completes if the transmit queue is empty and the LST bit in the Command register has been written. This bit is cleared by writing ‘1’, writes of ‘0’ have no effect.
0b
13 R RESERVED (R) - Read as zero and should be written to zero to ensure forward compatibility.
0b
12 OV
Overrun (OV) - This bit gets set when the receive queue is full and the core receives new data. The core continues communicating over the SPI bus but discards the new data. This bit is cleared by writing ‘1’, writes of ‘0’ have no effect.
0b
11 UN
Underrun (UN) - This bit is only set when the core is operating in slave mode. The bit is set if the core’s transmit queue is empty when a master initiates a transfer. When this happens the core will respond with a word where all bits are set to ‘1’. This bit is cleared by writing ‘1’, writes of ‘0’ have no effect.
0b
10 MME
Multiple-master error (MME) - This bit is set when the core is operating in master mode and the SPISEL input goes active (SPIx_CSI goes low or IOMUX INEN is low or IOMUX PSEL is high). In addition to setting this bit the core will be disabled. This bit is cleared by writing ‘1’, writes of ‘0’ have no effect.
0b
9 NE Not empty (NE) - This bit is set when the receive queue contains one or more elements. It is cleared automatically by the core, writes have no effect.
0b
8 NF Not full (NF) - This bit is set when the transmit queue has room for one or more words. It is cleared automatically by the core when the queue is full, writes have no effect.
0b
7..0 R RESERVED (R) - Read as zero and should be written to zero to ensure forward compatibility.
00h
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31.5.4 SPI0_MASKREG, SPI1_MASKREG (CONTROL REGISTER)
31 30 16 15 14 13 12 11 10 9 8 7
0
TIP
E
R
AT
LTE R
OV
E
UN
E
MM
EE
NEE
NFE
R
BITS FIELD DESCRIPTION VALUES RESET VALUE
31 TIPE Transfer in progress enable (TIPE) - When this bit is set the core will generate an interrupt when the TIP bit in the Event register transitions from ‘0’ to ‘1’.
0b
30..16 R RESERVED (R) - Read as zero and should be written to zero to ensure forward compatibility.
0000h
15 AT Automated transfers (AT) – When this bit is set, the core will generate an interrpt when an automated transfer is completed
0b
14 LTE Last character enable (LTE) - When this bit is set the core will generate an interrupt when the LT bit in the Event register transitions from ‘0’ to ‘1’.
0b
13 R RESERVED (R) - Read as zero and should be written to zero to ensure forward compatibility.
0b
12 OVE Overrun enable (OVE) - When this bit is set the core will generate an interrupt when the OV bit in the Event register transitions from ‘0’ to ‘1’.
0b
11 UNE Underrun enable (UNE) - When this bit is set the core will generate an interrupt when the UN bit in the Event register transitions from ‘0’ to ‘1’.
0b
10 MMEE
Multiple-master error enable (MMEE) - When this bit is set the core will generate an interrupt when the MME bit in the Event register transitions from ‘0’ to ‘1’.
0b
9 NEE
Not empty enable (NEE) - When this bit is set the core will generate an interrupt when the NE bit in the Event register transitions from ‘0’ to ‘1’.
0b
8 NFE
Not full enable (NFE) - When this bit is set the core will generate an interrupt when the NF bit in the Event register transitions from ‘0’ to ‘1’.
0b
7..0 R RESERVED (R) - Read as zero and should be written to zero to ensure forward compatibility.
00h
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31.5.5 SPI0_CMDREG, SPI1_CMDREG (CONTROL REGISTER)
31 23 22 21
0
R
LST R
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..23 R RESERVED (R) - Read as zero and should be written to zero to ensure forward compatibility.
0000h
22 LST
Last (LST) - After this bit has been written to ‘1’ the core will set the Event register bit LT when a character has been transmitted and the transmit queue is empty. If the core is operating in 3-wire mode the Event register bit is set when the whole transfer has completed. This bit is automatically cleared when the Event register bit has been set and is always read as zero.
0b
21..0 R RESERVED (R) - Read as zero and should be written to zero to ensure forward compatibility.
000000h
31.5.6 SPI0_TRSREG, SPI1_TRSREG (DATA REGISTER)
31
0
TDA
TA
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..0 TDATA
Transmit data (TDATA) - Writing a word into this register places the word in the transmit queue. This register will only react to writes if the Not full (NF) bit in the Event register is set. The layout of this register depends on the value of the REV field in the
00h
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Mode register:
Rev = ‘0’: The word to transmit should be written with its least significant bit at bit 0.
Rev = ‘1’: The word to transmit should be written with its most significant bit at bit 31.
31.5.7 SPI0_RCVREG, SPI1_RCVREG (DATA REGISTER)
31
0
RD
ATA
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..0 RDATA
Receive data (RDATA) - This register contains valid receive data when the Not empty (NE) bit of the Event register is set. The placement of the received word depends on the Mode register fields LEN and REV:
For LEN = 0b0000 - The data is placed with its MSb in bit 31 and its LSb in bit 0.
For other lengths and REV = ‘0’ - The data is placed with its MSB in bit 15.
For other lengths and REV = ‘1’ - The data is placed with its LSB in bit 16.
To illustrate this, a transfer of a word with eight bits (LEN = 7) that are all set to one will have the following placement:
REV = ‘0’ - 0x0000FF00
REV = ‘1’ - 0x00FF0000
00h
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31.5.8 SPI0_SLVSELREG, SPI1_SLVSELREG (CONTROL REGISTER)
31
SSSZ SSSZ-1
0
R
SLV
SEL
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..SSSZ R
RESERVED (R) - The lower bound of this register is determined by the Capability register field SSSZ if the SSEN field is set to 1. If SSEN is zero bits 31:0 are reserved.
00h
SSSZ-1..0
SLVSEL
Slave select (SLVSEL) - If SSEN in the Capability register is 1 the core’s slave select signals are mapped to this register on bits (SSSZ-1):0. Software is solely responsible for activating the correct slave select signals, the core does not assert or deassert any slave select signal automatically.
00h
31.5.9 SPI0_AUTSLVSEL, SPI1_AUTSLVSEL (CONTROL REGISTER)
31
SSSZ SSSZ-1
0
R
ASL
VSE
L
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..SSSZ R
RESERVED (R) - The lower bound of this register is determined by the Capability register field SSSZ if the SSEN field is set to 1. If SSEN is zero bits 31:0 are reserved.
00h
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SSSZ-1..0
ASLVSEL
Automatic Slave select (ASLVSEL) - If SSEN and ASELA in the Capability register are both ‘1’ the core’s slave select signals are assigned from this register when the core is about to perform a transfer and the ASEL field in the Mode register is set to ‘1’. After a transfer has been completed the core’s slave select signals are assigned the original value in the slave select register.
Note: This register is only available if ASELA (bit 17) in the SPI controller Capability register is set
00h
31.5.10 SPI0_AMCONFREG, SPI1_AMCONFREG (CONTROL REGISTER)
31
12
9 8 7 6 5 4 3 2 1 0
RES
ERV
ED
TIM
SEL
ECG
C
LOCK
ERPT
SEQ
STR
ICT
OV
TB
OV
DB
ACT
EACT
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..13 R RESERVED - This field is reserved for future use and should always be written as zero.
00h
12…9 TIMSEL Timer tick selection for automatic mode. The SPI acquisition shall start at each timer tick
00h
8 ECGC
External clock gap control (ECGC) - If software sets this bit to ‘1’ then the clock gap between individual transfers in a set of automated transfers is controller by the core’s CSTART input instead of the CG field in the Mode registers. Note that the requirement that the CG field must be set to a value >= 2 if the TAC bit is set still applies even if this bit is set. Reset value ‘0’.
00h
7 LOCK Lock bit (LOCK) - If software sets this bit to ‘1’ then the core will not place new data in the AM Receive registers while software is reading out new data.
00h
6 ERPT
External repeat (ERPT) - When this bit is set the core will use the tick generated by the timer selected in the TIMSEL field to start a new periodic transfer. If this bit is cleared, the period counter will be used instead.
00h
5 SEQ
Sequential transfers (SEQ) - When this bit is set the core will not update the receive queue unless the queue has been emptied by reading out its contents. Note that the contents in the temporary FIFO may still be overwritten
00h
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with incoming data, depending on the setting of the other fields in this register.
4 STRICT
Strict period (STRICT) - When this bit is set the core will always try to perform a transfer when the period counter reaches zero, if this bit is not set the core will wait until the receive FIFO is empty before it tries to perform a new transfer.
0x00
3 OVTB
Overflow Transfer Behavior (OVTB) - If this bit is set to ‘1’ the core will skip transfers that would result in data being overwritten in the temporary receive queue. Note that this bit only decides if the transfer is performed. If this bit is set to ‘0’ a transfer will be performed and the setting of the Overflow Data Behavior bit (OVDB) will decide if data is actually overwritten.
00h
2 OVDB
Overflow Data Behavior (OVDB) - If this bit is set to ‘1’ the core will skip incoming data that would overwrite data in the receive queues. If this bit is ‘0’ the core will overwrite data in the temporary queue.
00h
1 ACT
Activate automated transfers (ACT) - When this bit is set to ‘1’ the core will start to decrement the AM period register and perform automated transfers. The system clock cycle after this bit has been written to ‘1’ there will be a pulse on the core’s ASTART output.
Automated transfers can be deactivated by writing this bit to ‘0’. The core will wait until any ongoing transfer has finished before deactivating automated transfers. Software should not perform any operation on the core before this bit has been read back as ‘0’. The data in the last transfer(s) will be lost if there is a transfer in progress when this bit is written to ‘0’. All words present in the transmit queue will also be dropped.
00h
0 EACT
External activation of automated transfers (EACT) - When this bit is set to ‘1’ the core will activate automated transfers when a tick of the timer selected in the TIMSEL field is received. When the core has been activated by the external signal this bit will be reset and the ACT field (bit 1 will be set).
00h
Note: This register is only available if AMODE (bit 18) in the SPI controller Capability register is set
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31.5.11 SPI0_AMPERREG, SPI1_AMPERREG (CONTROL REGISTER)
31
0
AM
PER
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..0 AMPER
AM Period (AMPER) - This field contains the period, in system clock cycles, of the automated transfers. The core has an internal counter that is decremented each system clock cycle. When the counter reaches zero the core will begin to transmit all data in the transmit queue and reload the internal counter, which will immediately begin to start count down again. If the core has a transfer in progress when the counter reaches zero, the core will stall and not start a new transfer, or reload the internal counter, before the ongoing transfer has completed.
The number of bits in this register is implementation dependent. Software should write this register with 0xFFFFFFFF and read back the value to see how many bits that are available.
00h
Note: This register is only available if AMODE (bit 18) in the SPI controller Capability register is set
31.5.12 SPI0_AMMSKREG AND SPI1_AMMSKREG (CONTROL REGISTER)
31
16 15
0
AM
MA
SK
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..16 NOT USED 0x0000
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15..0 AMMASK
AM Mask - This field is used as a bit mask to determine which words in the AM Transmit / Receive queues to read from / write to. Bit 0 of the first mask register corresponds to the first position in the queues, bit 1 of the first mask register to the second position, bit 0 of the second mask register corresponds to the 33:d position, etc. The total number of bits implemented equals FDEPTH (bit 15:8) in the SPI controller Capability register. If a bit is set to one then the core will read / write the corresponding position in the queue, otherwise it will be skipped. Software can write these registers at all times. However if a automated transfer is in progress when the write occurs, then the core will save the new value in a temporary register until the transfer is complete. The reset value is all ones.
FFFFh
Note: This register is only available if AMODE (bit 18) in the SPI controller Capability register is set
31.5.13 SPI0_AMTRSREG AND SPI1_AMTRSREG (DATA REGISTER)
31
0
TDA
TA
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..0 TDATA
Transmit data (TDATA) - Writing a word into these register places the word in the AM Transmit queue. The address of the register determines the position in the queue. Address offset 0x200 corresponds to the first position, offset 0x204 to the second position etc.
The layout of the registers during write depends on the value of the REV field in the Mode register:
Rev = ‘0’: The word to transmit should be written
with its least significant bit at bit 0.
00h
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Rev = ‘1’: The word to transmit should be written
with its most significant bit at bit 31.
The layout of the registers during read is fixed, the word is read with its least significant bit at bit 0.
Note: This register is only available if AMODE (bit 18) in the SPI controller Capability register is set
31.5.14 SPI0_AMRCVREG, SPI1_AMRCVREG (DATA REGISTER)
31
0
RD
ATA
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..0 RDATA
Receive data (RDATA) - The address of the register determines the position in the queue. Address offset 0x200 corresponds to the first position, offset 0x204 to the second position etc. The placement of the received word depends on the Mode register fields LEN and REV.
For LEN = 0b0000 - The data is placed with its MSb in bit 31 and its LSb in bit 0.
For other lengths and REV = ‘0’ - The data is placed with its MSB in bit 15.
For other lengths and REV = ‘1’ - The data is placed with its LSB in bit 16.
To illustrate this, a transfer of a word with eight bits (LEN = 7) that are all set to one will have the following placement:
REV = ‘0’ - 0x0000FF00
REV = ‘1’ - 0x00FF0000
00h
Note: This register is only available if AMODE (bit 18) in the SPI controller Capability register is set
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31.5.15 SPI0_CCS_CDOL, SPI1_CCS_CDOL (DATA REGISTER)
31
0
CC
S_D
ATA
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..0 CCS_DATA
Receive data on each of the CS lines. The behaviour is exactly the same as RDATA register with regard to the SPI mode register (CPOL, CPHA, REV, LEN, LOOPBACK). When loopback is enabled, the MOSI is appearing on all the CCS channels
00h
31.6 I2C
31.6.1 I2C_MCKPRE (CONFIGURATION REGISTER)
31 16 15 0
NO
T U
SED
CK
PR
E
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..16 - Not used - 00..00b
15..0 CKPRE
Clock prescale - Value is used to prescale the SCL clock line. Do not change the value of this register
unless the EN field of the control register is set to ‘0’. The minimum recommended value of this register
63h
24h
others
100 kHz
400 kHz
Cfr (*)
FFFFh
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is 0x0003. Lower values may cause the master to violate I2C timing requirements due to synchronization
issues
(*) CKPRE value = ((50000)/(5*Freq))-1, where Freq= desired clock frequency . The CKPRE value must be stored in hexadecimal format
31.6.2 I2C_MCTRL (CONFIGURATION REGISTER)
31 8 7 6 5 0
NO
T U
SED
EN
IEN
NO
T U
SED
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..8 - Not used - 00..00b
7 EN Enable MASTER I2C core. The core is enabled when this bit is set to ‘1’.
1b
0b
Enable
Disable 0b
6 IEN THIS BIT IS ACCESSIBLE AND MUST NEVER BE USED 0b
5..0 - Not used 00..00b
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31.6.3 I2C_MTRREG (DATA REGISTER)
31 8 7 1 0
NO
T U
SED
TDA
TA
RW
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..8 - Not used - 00..00b
7..1 TDATA Transmit data - Most significant bits of next byte to transmit via I2C MASTER
U..U
0 RW
Read/Write - In a data transfer this is the data’s least significant bit. In a slave address transfer
this is the RW bit. ‘1’ reads from the slave and ‘0’ writes to the slave.
1b
0b
Read
Write U
31.6.4 I2C_MRECREG (DATA REGISTER)
31 8 7 0
NO
T U
SED
RD
ATA
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..8 - Not used - 00..00b
7..0 RDATA I2C MASTER Receive data - Last byte received over I2C-bus. U..U
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31.6.5 I2C_MCOM (CONTROL RE GISTER)
31 8 7 6 5 4 3 2 1 0
NO
T U
SED
STA
STO
RD
WR
AC
K
NO
T U
SED
IAC
K
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..8 - Not used -
7 STA Start - Generate START condition on I2C-bus. This bit is also used to generate repeated START conditions
1b
0b
Enable
disable 0b
6 STO Stop - Generate STOP condition 1b
0b
Enable
disable 0b
5 RD Read - Read from slave 1b
0b
Enable
disable 0b
4 WR Write - Write to slave 1b
0b
Enable
disable 0b
3 ACK Acknowledge - Used when acting as a receiver. 0b
1b
ACK
NACK
1b
2..1 - Not used
0 IACK THIS BIT IS ACCESSIBLE BUT MUST NEVER BE USED Clear
No effect
0b
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31.6.6 I2C_MSTAT (STATUS REGISTER)
31 8 7 6 5 4 3 2 1 0
NO
T U
SED
RxA
Ck
BU
SY
AL
NO
T U
SED
TIP
IF
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..8 - Not used -
7 RxACK Receive acknowledge - Received acknowledge from slave 1b
0b
NO ACK
ACK
1b
6 BUSY I2C-bus busy - This bit is set to ‘1’ when a start signal is detected and reset to ‘0’ when a stop signal is detected
1b
0b
START
STOP
1b
5 AL Arbitration lost - Set to ‘1’ when the I2C MASTER core has lost arbitration. This happens when a stop signal is detected but not requested or when the master drives SDA high but SDA is low.
1b
0b
LOST
NOT LOST
0b
4..2 - NOT USED 000b
TIP
Transfer in progress - ‘1’ when transferring data and ‘0’ when the transfer is complete. This bit is also set when the core will generate a STOP condition.
1b
0b
COMPLETED
IN PROGRESS
0b
0 IF THIS BIT IS ACCESSIBLE BUT MUST NEVER BE USED EFFECT 0b
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31.6.7 I2C_SADD (CONFIGURATION REGISTER)
31 30 7 6 0
TBA
N
OT
USE
D
NO
T U
SED
SLV
AD
DR
BITS FIELD DESCRIPTION VALUES RESET VALUE
31 TBA Ten-bit Address Cfr Note. 0b 0b
30..7 - Not used 00..00b
6..0 SLVADDR
Slave address - Contains the slave I2C address. The width of the slave address field is 7 bits. Depending on the hardware configuration this register
may be read only. The core checks the length of the programmed address and will function with
7-bit addresses even if it has support for 10-bit addresses.
20h
Note: TBA is not used by CLP(This bit is mapped to 10-bit addressing mode of IPCore which is
disabled by hardware).
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31.6.8 I2C_SCTRL (CONTROL REGISTER)
31 5 4 3 2 1 0
NO
T U
SED
RM
OD
TMO
D
TV
TAV
EN
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..5 - Not used - 00..00b
4 RMOD
Receive Mode - Selects how the I2C SLAVE core handles writes:
‘0’: The slave accepts one byte and NAKs all other transfers until software has acknowledged the received byte by reading the Receive register.
‘1’: The slave accepts one byte and keeps SCL low until software has acknowledged the received byte by reading the Receive register.
Cfr descritpion U
3 TMOD
Transmit Mode (TMOD) - Selects how the I2C SLAVE core handles reads:
‘0’: The slave transmits the same byte to all if the master requests more than one byte in the transfer. The slave then NAKs all read requests as long as the Transmit Valid (TV) bit is unset.
‘1’: The slave transmits one byte and then keeps SCL low until software has acknowledged that the byte has been transmitted by setting the Transmit Valid (TV) bit.
Cfr descritpion U
2 TV
Transmit Valid (TV) - Software sets this bit to indicate that the data in the SLAVE transmit register is valid. The SLAVE interface automatically resets this bit when the byte has been transmitted. When this bit is ‘0’ the SLAVE interface will either NAK or insert wait states on incoming read requests, depending on the Transmit Mode (TMOD).
U
1 TAV Transmit Always Valid - When this bit is set, the I2C SLAVE interface will not clear the Transmit Valid (TV) bit when a byte has been transmitted.
U
0 EN
Enable core - Enables SLAVE interface. When this bit is set to ‘1’ the core will react to requests to the address set in the Slave address register. If this bit is ‘0’ the core will keep both SCL and SDA inputs in Hi-Z state.
1b
0b
ENABLE
DISABLE
0b
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31.6.9 I2C_SSTAT (STATUS REGISTER)
The I2C_SSTAT register has the following layout and bit fields definition
31 3 2 1 0
NO
T U
SED
REC
TRA
NA
K
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..3 - Not used - - 00..00b
2 REC
Byte Received (REC) - This bit is set to ‘1’ when the SLAVE interface
accepts a byte and is automatically cleared when the Receive register
has been read.
Cfr description
0b
1 TRA
Byte Transmitted (TRA) - This bit is set to ‘1’ when the SLAVE interface
has transmitted a byte and is cleared by writing ‘1’ to this position.
Writes of ‘0’ have no effect.
Cfr description
0b
0 NAK
NAK Response (NAK) - This bit is set to ‘1’ when the SLAVE interface
has responded with NAK to a read or write request. This bit does not
get set to ‘1’ when the core responds with a NAK to an address that
does not match the cores address. This bit is cleared by writing ‘1’ to
this position, writes of ‘0’ have no effect.
Cfr description
0b
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31.6.10 I2C_SMASK (CONTROL REGISTER)
31 3 2 1 0
NO
T U
SED
REC
E
TRA
E
NA
KE
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..3 - Not used - - UU..UUb
2 - This bit must never be used. - - U
1 - This bit must never be used. - - U
0 - This bit must never be used. - - U
31.6.11 I2C_SRECREG (DATA REGISTER)
31 8 7 0
NO
T U
SED
REC
BYT
E
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..8 - Not used -
7..0 RECBYTE Received Byte - Last byte received from master. This field only contains valid data if the Byte received (REC) bit in the I2C_STAT status register has been set.
U
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31.6.12 I2C_STRREG (DATA REGISTER)
31 8 7 0
NO
T U
SED
TR
AB
YTE
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..8 - Not used -
7..0 TRABYTE Transmit Byte - Byte to transmit on the next master read request.
U
31.7 INTERCOM RAM
31.7.1 INCOMRAM_ADD0 TO INCOMRAM_ADD511(DATA REGISTER)
31 0
DA
TA
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..0 DATA 32-bit data at address x N/A
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31.8 PWM
31.8.1 PWM0_CONF, ..., PWM23_CONF (CONFIGURATION REGISTER)
31 20 16 15 14 13 12 9 8 7 0
KEY
NO
T U
SED
OFF
_HIG
H
OFF
_LO
W
IND
EP
SIN
GLE
_ED
HP
ERSE
L
ENA
BLE
TNO
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..20 KEY Protection key. All the fields except ENABLE can only be modified if key is set to 0xACE. This field is read as 000h.
N/A 00..00b
19..17 NOT USED - 0b
16 OFF_HIGH Value of the PWM high line when PWM timer is disabled (cfr ENABLE field below)
1b
15 OFF_LOW Value of the PWM low line when PWM timer is disabled (cfr ENABLE field below)
0b
14 INDEP
Single edge output is complementary
Or independent (not taken into account in double edge mode)
0b
1b
Complementary
Independent 0b
13 SINGLE_ED Single Edge working, uses only one tick 0b
1b
Double edge
Single edge 0b
12..9 TPERSEL
Selects the timer tick fixing the desired PWM period or half period. When the selected tick occurs, the PWM, if enabled, unconditionnally generates the signals programmed through PWMx_T1T2 and PWMx_CONF registers
0000b
0001b
...
1001b
others
TIMER 0
TIMER 1
...
TIMER 9
TIMER 9
0000b
8 ENABLE Enables the PWM timer by making it sensitive to a tick produced by the selected timer
0b
1b
Disabled
Enabled 0b
7..0 TNO
Non-overlapping delay (also known as dead time) introduced between complemented outputs driven by associated PWM. The delay is programmed with multiples of the
00h
01h
0 clock cycle
1 clock cycle 00h
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clock cycle period. 02h
...
FFh
2 clock cycles
...
255 clock cycles
31.8.2 PWM0_T1T2, ..., PWM23_T1T2 (DATA REGISTER)
31 30 29 16 15 7 6 5 4 3 2 1 0
T2
T1
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..16 T2 Value for T2 parameter.
0000h
0001h
0002h
...
FFFFh
0
1 clock cycle
2 clock cycles
...
65535 clock cycles
0000h
15..0 T1 Value for T1 parameter.
0000h
0001h
0002h
...
FFFFh
0
1 clock cycle
2 clock cycles
...
65535 clock cycles
0000h
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31.9 TIMERS
31.9.1 TIM_STRTFRZ (CONTROL REGISTERS)
31 12 11 10 9 8 7 6 5 4 3 2 1 0
NO
T U
SED
PS1
_EN
PS0
_EN
SF9
SF8
SF7
SF6
SF5
SF4
SF3
SF2
SF1
SF0
BITS FIELD DESCRIPTION VALUE ACTION RESET VALUE
31..12 --- Not used --- --- 0000b
11 PS1_EN Prescaler 1 Enable/Reset 0b 1b
Prescaler reset to 0 Prescaler enabled
0b
10 PS0_EN Prescaler 0 Enable/Reset 0b 1b
Prescaler reset to 0 Prescaler enabled
0b
9 SF9 Start or Freeze timer 9 counter
0b 1b
Freeze timer 9 counter Start timer 9 counter
0b
8 SF8 Start or Freeze timer 8 counter
0b 1b
Freeze timer 8 counter Start timer 8 counter
0b
7 SF7 Start or Freeze timer 7 counter
0b 1b
Freeze timer 7 counter Start timer 7 counter
0b
6 SF6 Start or Freeze timer 6 counter
0b 1b
Freeze timer 6 counter Start timer 6 counter
0b
5 SF5 Start or Freeze timer 5 counter
0b 1b
Freeze timer 5 counter Start timer 5 counter
0b
4 SF4 Start or Freeze timer 4 counter
0b 1b
Freeze timer 4 counter Start timer 4 counter
0b
3 SF3 Start or Freeze timer 3 counter
0b 1b
Freeze timer 3 counter Start timer 3 counter
0b
2 SF2 Start or Freeze timer 2 counter
0b 1b
Freeze timer 2 counter Start timer 2 counter
0b
1 SF1 Start or Freeze timer 1 counter
0b 1b
Freeze timer 1 counter Start timer 1 counter
0b
0 SF0 Start or Freeze timer 0 counter
0b 1b
Freeze timer 0 counter Start timer 0 counter
0b
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31.9.2 TIM_CLR (CONTROL REGISTER)
31 10 9 8 7 6 5 4 3 2 1 0
NOT USED
CLR
9
CLR
8
CLR
7
CLR
6
CLR
5
CLR
4
CLR
3
CLR
2
CLR
1
CLR
0
BITS FIELD DESCRIPTION VALUE ACTION RESET VALUE
31..10 --- Not used --- --- 0000b
9 CLR9 Clear or keep timer 9 content (always read as 0)
0b 1b
No effect Clear counter content
0b
8 CLR8 Clear or keep timer 8 content (always read as 0)
0b 1b
No effect Clear counter content
0b
7 CLR7 Clear or keep timer 7 content (always read as 0)
0b 1b
No effect Clear counter content
0b
6 CLR6 Clear or keep timer 6 content (always read as 0)
0b 1b
No effect Clear counter content
0b
5 CLR5 Clear or keep timer 5 content (always read as 0)
0b 1b
No effect Clear counter content
0b
4 CLR4 Clear or keep timer 4 content (always read as 0)
0b 1b
No effect Clear counter content
0b
3 CLR3 Clear or keep timer 3 content (always read as 0)
0b 1b
No effect Clear counter content
0b
2 CLR2 Clear or keep timer 2 content (always read as 0)
0b 1b
No effect Clear counter content
0b
1 CLR1 Clear or keep timer 1 content (always read as 0)
0b 1b
No effect Clear counter content
0b
0 CLR0 Clear or keep timer 0 content (always read as 0)t
0b 1b
No effect Clear counter content
0b
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31.9.3 TIM_PRESC0 AND TIM_PRESC1 (CONTROL REGISTER)
31 22 8 7 0
NO
T U
SED
DIV
BITS FIELD DESCRIPTION VALUE ACTION EVERY
RESET VALUE
31..8 - NOT USED 0h
7..0 DIV Holds frequency divider value for prescaler
00h 01h 02h 03h 04h ...
FFh
Divide by 2 Divide by 2 Divide by 3 Divide by 4 Divide by 5 ... Divide by 256
01h
31.9.4 TIM_COMPREG0 TO TIM_COMPREG9 (DATA REGISTER)
31 16 15 0
NO
T
USE
D
CO
MP
BITS FIELD DESCRIPTION VALUE ACTION EVERY
RESET VALUE
31..16 - NOT USED 0000h
15..0 COMP Holds comparison value for timer. When comparison value matches current timer value, a tick is generated
0000h 0001h
... FFFFh
1 tick 2 ticks ... 65536 ticks
0000h
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31.9.5 TIM_CAPTREG0 TO TIM_CAPTREG9 (DATA REGISTER)
31 16 15 0
NO
T
USE
D
CA
PT
BITS FIELD DESCRIPTION VALUE ACTION RESET VALUE
31..16 - NOT USED 0000h
15..0 CAPT
Holds captured timer value when input selected through field CAPSEL presents a rising/falling edge (selected by CAPEDG)
0000h ...
FFFFh - 0000h
31.9.6 TIM_CTRLREG0 TO TIM_CTRLREG9 (CONTROL REGISTER)
31 17 16 15 14 13 12 11 8 7 4 3 0
NOT USED
CAPE
DG
TCKS
EL
RST
SEL
TIM
SEL
CHSE
L
CAPS
EL
BITS FIELD DESCRIPTION VALUE ACTION RESET VALUE
31..17 --- Not used --- --- 00..00b
16 CAPEDG Select Capture Edge
0b 1b
Rising Edge Falling Edge
0b
15..14 TCKSEL Select Tick source
00b 01b 10b 11b
Select tick from PRESCALER 0 Select tick from PRESCALER 1 Select tick from CHSEL field Select tick from CAPSEL (tick_in)
00b
13…12 RSTSEL Select reset source 00b 01b 1xb
Select comparator tick Select timer selected by TIMSEL Select tick from CAPSEL (tick_in)
00b
11..8 TIMSEL Select reset source timer
0000b ...
1001b
Select timer 0 ... Select timer 9
0000b
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BITS FIELD DESCRIPTION VALUE ACTION RESET VALUE
others Select timer 9
7..4 CHSEL Select source timer for chaining
0000b ...
1001b others
Select timer 0 ... Select timer 9 Select timer 9
0000b
3..0 CAPSEL Select capture event source
0000b 0001b
... 1001b others
Select GPIOIN from GPIO[I] (*)
Select GPIOIN from GPIO[I+1] (*)
...
Select GPIOIN from GPIO[I+9] (*)
Select GPIOIN from GPIO[I+9] (*)
0000b
(*) I =0 for TIMER 0; I=10 for TIMER 1; ...; I=90 for TIMER 9
(*) For TIMER 9, GPIOIN[96], GPIOIN[97], GPIOIN[98], GPIOIN[99] are always 0 (these are no GPIO pin)
31.10 IOMUX
31.10.1 IOMUX_PIN7TO0,.., IOMUX_PIN105TO104 (CONFIGURATION REGISTER)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OE_
MA
SK7
GSE
L7
PSEL
7
INEN
7
OE_
MA
SK6
GSE
L6
PSEL
6
INEN
6
OE_
MA
SK5
GSE
L5
PSEL
5
INEN
5
OE_
MA
SK4
GSE
L4
PSEL
4
INEN
4
OE_
MA
SK3
GSE
L3
PSEL
3
INEN
3
OE_
MA
SK2
GSE
L2
PSEL
2
INEN
2
OE_
MA
SK1
GSE
L1
PSEL
1
INEN
1
OE_
MA
SK0
GSE
L0
PSEL
0
INEN
0
The details of the bit fields for IOMUX_PIN7TO0 will be as follows (the details of other register are
determined by analogy).
BITS FIELD DESCRIPTION VALUES RESET VALUE
31 OE_MASK
7 Control Output enable mask bit of IOMUX[7]
1b
0b Cfr section 21
Cfr section 21
30 GSEL7 Controls GSEL bit ofIOMUX[7] 1b
0b Cfr section 21
Cfr section 21
29 PSEL7 Controls PSEL bit ofIOMUX[7] 1b
Cfr section 21 Cfr section 21
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0b
28 INEN7 Control INEN bit of IOMUX[7] 1b
0b Cfr section 21
Cfr section 21
27 OE_MASK
6 Control Output enable mask bit of IOMUX[6]
1b
0b Cfr section 21
Cfr section 21
26 GSEL6 Controls GSEL bit ofIOMUX[6] 1b
0b Cfr section 21
Cfr section 21
25 PSEL6 Controls PSEL bit ofIOMUX[6] 1b
0b
Cfr section 21
Cfr section 21
24 INEN6 Control INEN bit of IOMUX[6] 1b
0b Cfr section 21
Cfr section 21
..
..
7 OE_MASK
1 Control Output enable mask bit of IOMUX[1]
1b
0b Cfr section 21
Cfr section 6.3
6 GSEL1 Controls GSEL bit ofIOMUX[1] 1b
0b Cfr section 21
Cfr section 21
5 PSEL1 Controls PSEL bit ofIOMUX[1] 1b
0b
Cfr section 21
Cfr section 21
4 INEN1 Control INEN bit of IOMUX[1] 1b
0b Cfr section 21
Cfr section 21
3 OE_MASK
0 Control Output enable mask bit of IOMUX[0]
1b
0b Cfr section 21
Cfr section 21
2 GSEL0 Controls GSEL bit ofIOMUX[0] 1b
0b
Cfr section 21
Cfr section 21
1 PSEL0 Controls PSEL bit ofIOMUX[0] 1b
0b Cfr section 21
Cfr section 21
0 INEN0 Control INEN bit of IOMUX[0]
1b
0b Cfr section 21
Cfr section 21
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31.11 BOOT MANAGER
31.11.1 BD0, BD1, BD2 AND BD3 (CONFIGURATION REGISTER)
31 29 28 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 0
BO
OTS
RC
ME
M8
BA
D
NO
T U
SED
TIM
OU
TVA
L
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..29 BOOTSRC BOOT source selection
000b 001b 010b 011b
Others
SPW0 SPW1 MEM8
CAN RTBT
000b
28..10 MEM8ADD Address to be used when boot source is the MEM8 interface
0…0b
9..8 NOT USED
7..0 TIMOUTVAL Upload timeout value, given as multiple of 65536 clock cycles
00h 01h 02h ...
FFh
None 1*65536 cycles 2*65536 cycles
... 255*65536 cycles
FFh
- Notes: - When TIMOUTVAL is None (00h), the internal Timeout is disabled for that Boot Descriptor tentative. - When the Boot Source is the RTBT, Timeout is always disabled (value of TIMOUTVAL is ignored).
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31.12 CLOCK AND RESET CONTROL
31.12.1 CLOCKCTRL (CONTROL REGISTER)
31 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NO
T U
SED
CP
U1
_CLK
CP
U0
_CLK
CR
C_C
LK
RT1
55
3_C
LK
CA
N_C
LK
SPW
1_C
LK
SPW
0_C
LK
AW
G_C
LK
AD
C_
CLK
PW
M_C
LK
UA
RT_
CLK
I2C
_C
LK
SPI1
_CLK
SPI0
_CLK
BITS FIELD DESCRIPTION VALUES RESET
VALUE
31..14 RESERVED RESERVED 0..0b
13 CPU1_CLK CPU1 Clock gate is active 0b
1b
Clock halted
Clock running 0b
12 CPU0_CLK CPU0 Clock gate is active 0b
1b
Clock halted
Clock running 0b
11 CRC_CLK CRCs Clock gate is active 0b
1b
Clock halted
Clock running 0b
10 RT1553_CLK RT1553 Clock gate is active 0b
1b
Clock halted
Clock running 0b
9 CAN_CLK CAN Clock gate is active 0b
1b
Clock halted
Clock running 0b
8 SPW1_CLK SpaceWire1 Clock gate is active 0b
1b
Clock halted
Clock running 0b
7 SPW0_CLK SpaceWire0 Clock gate is active 0b
1b
Clock halted
Clock running 0b
6 AWG_CLK AWG Clock gate is active 0b
1b
Clock halted
Clock running 0b
5 ADC_CLK ADC Clock gate is active 0b
1b
Clock halted
Clock running 0b
4 PWM_CLK PWM Clock gate is active 0b
1b
Clock halted
Clock running 0b
3 UART_CLK UART Clock gate is active 0b
1b
Clock halted
Clock running 0b
2 I2C_CLK I2C Clock gate is active 0b
1b
Clock halted
Clock running 0b
1 SPI1_CLK SPI1 Clock gate is active 0b
1b
Clock halted
Clock running 0b
0 SPI0_CLK SPI0 Clock gate is active 0b
1b
Clock halted
Clock running 0b
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31.12.2 RESETCTRL (CONTROL REGISTER)
Each bit of this control register controls a synchronous reset.
31 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NO
T U
SED
CP
U1_
RST
CP
U0_
RST
CR
C_R
ST
RT1
553
_ R
ST
CA
N_
RST
SPW
1_ R
ST
SPW
0_ R
ST
AW
G_
RST
AD
C_
RST
PW
M_
RST
UA
RT_
RST
I2C
_RST
SPI1
_RST
SPI0
_RST
BITS FIELD DESCRIPTION VALUES RESET
VALUE
31..14 RESERVED RESERVED 0..0b
13 CPU1_RST CPU1 Reset state 0b
1b
Under reset
Running 0b
12 CPU0_RST CPU0 Reset state 0b
1b
Under reset
Running 0b
11 CRC_RST CRCs Reset state 0b
1b
Under reset
Running 0b
10 RT1553_RST RT1553 Reset state 0b
1b
Under reset
Running 0b
9 CAN_RST CAN Reset state 0b
1b
Under reset
Running 0b
8 SPW1_RST SpaceWire1 Reset state 0b
1b
Under reset
Running 0b
7 SPW0_RST SpaceWire0 Reset state 0b
1b
Under reset
Running 0b
6 AWG_RST AWG Reset state 0b
1b
Under reset
Running 0b
5 ADC_RST ADC Reset state 0b
1b
Under reset
Running 0b
4 PWM_RST PWM Reset state 0b
1b
Under reset
Running 0b
3 UART_RST UART Reset state 0b
1b
Under reset
Running 0b
2 I2C_RST I2C Reset state 0b
1b
Under reset
Running 0b
1 SPI1_RST SPI1 Reset state 0b
1b
Under reset
Running 0b
0 SPI0_RST SPI0 Reset state 0b
1b
Under reset
Running 0b
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31.13 PROGRAM RAM
31.13.1 PRAM_ADD0 TO PRAM_ADD32767(DATA REGISTER)
31 0
DA
TA
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..0 DATA 32-bit data at address x N/A
31.14 XCHGRAM
31.14.1 XCHGRAM_ADD0 TO XCHGRAM_ADD8191 (DATA REGISTER)
The XCHGRAM_ADD0 to XCHGRAM_ADD8191 register have the following definition
31 0
DA
TA
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..0 DATA 32-bit data at address x N/A
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31.15 AWG
31.15.1 AWG0_CONF, AWG1_CONF (CONFIGURATION REGISTER)
31 13 12 9 8 5 4 3 0
NO
T U
SE
D
D
1
D
0
EN
AB
LE
TIM
SE
L
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..13 - Not used - 00..00b
12..9 D1 * Enable Duration
0
1
2
…
15
0 clock cycle
1 clock cycle
2 clock cycles
…
15 clock cycles
0000b
8..5 D0 * Number of clock cycles between the falling edge of the Tick and the rising edge of the DACx_EN signal
0
1
2
…
15
0 clock cycle
1 clock cycle
2 clock cycles
…
15 clock cycles
0000b
4 ENABLE
Enables or disables function. When enabled, the 1st waveform descriptor shall be processed. When disabled, the corresponding DACx_EN and all internal state register of the given AWG (not the configuration registers) are reset, and the corresponding DACx_OUT keeps the last value.
1
0
Enable
disable
0b
3..0 TIMSEL *
Selects, for the given AWGx function, which timer is used to cadence the reading of each PTy point.
0000b
0001b
TIMER0
TIMER1 0000b
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...
1001b
others
..
TIMER9
TIMER9
(*) Those registers cannot be written when the ENABLE field = ‘1’
31.15.2 AWG0_WFD0, . .., AWG0_WFD3, AWG1_WFD0,.. .AWG1_WFD3 (CONFIGURATION REGISTER)
31 25 24 22 21 14 13 8 7 2 1 0
NO
T U
SED
WFR
EP
RFM
F
WFB
AD
D
WFE
ND
AD
D
NXT
WD
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..25 - Not used - 00..00b
24..22 WFREP Number of times that the programmed waveform must be generated
000b
..
111b
1
..
8
000b
21..14 RFDF
Reading Frequency division factor with respect to selected TIMER period (cfr TIMSEL in AWGx_CONF register)
00h
01h
02h
..
FFh
1
2
3
..
256
00h
13..8 WFBADD Base address specifying where the initial DAC value is found in PTx registers (cfr 31.15.4)
00..00b PT0 00..00b
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..
11..11b
..
PT63
7..2 WFENDADD Address specifying where the last DAC value is found in PTx registers (cfr 31.15.4)
00..00b
..
11..11b
PT0
..
PT63
11..11b
1..0 NXTWD
Indicates which waveform descriptor must be read when the current one has been processed (including WFREP management)
00b
01b
10b
11b
WFD0
WFD1
WFD2
WFD3
00b
Notes:
The Current Waveform Descriptor AWGx_WFDy is loaded at the beginning of the specified waveform generation
Waveform Descriptors must never be modified when being used by the AWG (cfr CURWD in AWGx_STAT).
31.15.3 AWG0_STAT, AWG1_STAT (STATUS REGISTER)
31 8 7 2 1 0
NO
T U
SED
CU
RP
T
CU
RW
D1
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..8 - Not used - 00..00b
7..2 CURPT Value of current waveform programmable point (PTx) being processed by AWG
00..00b
..
11..11b
PT0
..
PT63
00..00b
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1..0 CURWD Value of current waveform descriptor being processed by AWG
00
01
10
11
WFD0
WFD1
WFD2
WFD3
00b
Notes:
When the AWGx is disabled (i.e. Field Enable of AWGx_Conf is 0), AWGx_STAT keeps its last value.
AWGx_STAT and DAC_OUT are simultaneously updated.
31.15.4 AWG0_PT0, … , AWG0_PT63, AWG1_PT0, … , AWG1_PT63 (DATA REGISTER)
31 12 11 0
NO
T U
SE
D
PR
OG
PO
INT
BITS FIELD DESCRIPTION VALUES/EFFECT (on DAC
output) RESET VALUE
31..12 - Not used - 00..00b
11..0 PROGPOINT
Value to be stored in corresponding programmable point (determined by APB address). The 12-bit value is sent to DAC to make the digital to analog conversion
000h
001h
...
FFEh
FFFh
0
1
...
4094
4095
0000b
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31.16 SCRUBBING MANAGEMENT
31.16.1 CPU0_SCR_ADDR, CPU1_SCR_ADDR, ICOM0_SCR_ADDR, ICOM1_SCR_ADDR, XCHG0_SCR_ADDR, XCHG1_SCR_ADDR (CONTROL REGISTER)
31 15 0
HI_
AD
DR
LO_
AD
DR
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..16 HI_ADDR Scrubbing high bound address 0000h
15..0 LO_ADDR Scrubbing low bound address 0000h
31.16.2 CPU0_SCR_CTRL, CPU1_SCR_CTRL, ICOM0_SCR_CTRL, ICOM1_SCR_CTRL, XCHG0_SCR_CTRL, XCHG1_SCR_CTRL (CONTROL REGISTER)
31 12 11 8 7 0
NO
T U
SED
SCR
UB
_A
CT
SCR
UB
_TM
R
SCR
UB
_PER
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..13 NOT USED
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12 SCRUB_ACT Scrubbing is currently active (Read Only)
0b
1b
Scrubbing IDLE
Scrubbing operation in progress
0b
11…8 SCRUB_TMR Scrubbing timer selection
0h
…
9h
A-Fh
Timer 0
…
Timer 9
Timer 9
0h
7…0 SCRUB_PER Scrubbing Period (in timer ticks)
00h
01h
…
FFh
Disabled
2 timer ticks
…
256 timer ticks
00h
31.17 MMU
31.17.1 MMU_PROT0_SPW0, MMU_PROT0_SPW1,MMU_PROT0_1553RT, MMU_PROT0_CAN (CONFIGURATION REGISTER)
31 29 28 16 15 12 0
NO
T U
SED
BA
NO
T U
SED
LEN
BITS FIELD DESCRIPTION VALUES/ EFFECT RESET VALUE
31..29 - Not used 000b
28..16 BA Specifies the 13-bit base address of the buffer in XCHG RAM.
000h
...
0
... 0000h
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1FFFh 8191
15..13 - Not used 000b
12..0 LE
Specifies the 13-bit length of the buffer in XCHG RAM. When value is disabled, the MMU makes no range verification for the concerned interface.
000h
...
1FFFh
DISABLED
...
8191
0000h
31.17.2 MMU_PROT1_SPW0, MMU_PROT1_SPW1, MMU_PROT1_1553RT, MMU_PROT1_CAN (CONFIGURATION REGISTER)
31 29 28 16 15 12 0
NO
T U
SED
BA
NO
T U
SED
LEN
BITS FIELD DESCRIPTION VALUES/ EFFECT RESET VALUE
31..29 - Not used 000b
28..16 BA Specifies the 13-bit base address of the buffer in XCHG RAM.
000h
...
1FFFh
0
...
8191
0000h
15..13 - Not used 000b
12..0 LE
Specifies the 13-bit length of the buffer in XCHG RAM. When value is disabled, the MMU makes no range verification for the concerned interface.
000h
...
1FFFh
DISABLED
...
8191
0000h
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31.17.3 MMU_STAT (STATUS REGISTER)
31 3 2 1 0
NO
T U
SED
155
3 R
ESET
PR
OTO
VLP
1
PR
OTO
VLP
0
BITS FIELD DESCRIPTION VALUES/ EFFECT
RESET VALUE
Read/Write/Wri
te to clear
31..3 - Not used 00..00b
2 1553_RESET
The RT1553 has received a RT Reset mode code. (Bit reset on read)
0
1
0
1 0
r
1 PROTOVLP1
AHB masters connected to XCHG RAM1 have overlapping address/length configurations
0h
1h
0
1 0
wc (*)
0 PROTOVLP0
AHB masters connected to XCHG RAM0 have overlapping address/length configurations
0h
1h
0
1 0
wc (*)
(*)If set, PROTOVLP0 and PROTOVLP1 can be cleared by writing 1 in them.
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31.18 CAN
31.18.1 CAN_CONF (CONFIGURATION REGISTER)
31 30 29 28 27 26 24 23 20 19 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCA
LER
PS1
PS2
RSJ
BP
R
SAM
Sile
nt
Sele
ct
En
able
1
En
able
0
Ab
ort
Bits Field Description VALUES RESET VALUE
31..24 SCALER Prescaler setting: system clock / (SCALER +1)
00h
...
FFh
1*clock cycle
..
256 clock cyles
00h
23..20 PS1 Phase Segment 1
0001b
...
1111b
1
..
15
0000b
19..16 PS2 Phase Segment 2, 4-bit: (valid range 2 to 8)
0000b
..
1111b
0000b
15 - Not used 0b
14..12 RSJ ReSynchronization Jumps, 3-bit: (valid range 1 to 4)
001b
...
100b
1
..
4
000
11 - Not used 0b
10 - Not used 0b
9..8 BPR Baud rate,
00b
01b
10b
11b
SCALER/1
SCALER/2
SCALER/4
SCALER/8
00b
7 - Not used 0b
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Bits Field Description VALUES RESET VALUE
6 - Not used 0b
5 SAM Single sample (slow bus) or triple sample (high-speed bus)
1b
0b
Triple sample
Single sample
0b
4 SILENT Listen only to the CAN bus, send recessive bits.
1b
0b
Enable
disable
0b
3 SELECT
Selection receiver input and transmitter output:
Select receive input 0 as active when 0b,
Select receive input 1 as active when 1b
Select transmit output 0 as active when 0b,
Select transmit output 1 as active when 1b
0b
1b
Select Rx/Tx0
Select Rx/Tx1
0b
2 ENABLE1 Set value of output 1 enable 1b
0b
Enable
disable
0b
1 ENABLE0 Set value of output 0 enable 1b
0b
Enable
disable
0b
0 ABORT Abort transfer on AHB ERROR 1b
0b
Error
No error
0b
Constraints on PS1, PS2 and RSJ are defined as:
PS1 +1 >= PS2
PS1 > PS2
PS2 >= RSJ
CAN standard TSEG1 is defined by PS1+1.
CAN standard TSEG2 is defined by PS2.
The SCALER setting define the CAN time quantum, together with the BPR setting:
system clock / ((SCALER+1) * BPR)
where SCALER is in range 0 to 255, and the resulting division factor due to BPR is 1, 2, 4 or 8.
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For a quantum equal to one system clock period, an additional quantum is added to the node delay.
For minimizing the node delay, then is set either SCALER > 0 or BRP > 0.
The resulting bit rate is:
system clock / ((SCALER+1) * BPR * (1+ PS1+1 + PS2))
where PS1 is in the range 1 to 15, and PS2 is in the range 2 to 8.
RSJ defines the number of allowed resynchronisation jumps according to the CAN standard, being in the range 1 to 4.
For SAM = 0b (single), the bus is sampled once; recommended for high speed buses (SAE class C).
For SAM = 1b (triple), the bus is sampled three times; recommended for low/medium speed buses (SAE class A and B) where filtering spikes on the bus line is beneficial.
31.18.2 CAN_STAT (STATUS REGISTER)
31 28 27 24 23 16 15 8 7 6 5 4 3 2 1 0
TxC
han
ne
ls
RxC
han
ne
ls
TxEr
rCn
tr
RxE
rrC
ntr
Act
ive
AH
BEr
r
OR
Off
Pas
s
Bits Field Description VALUE RESET
VALUE
31..28 TxChannels Number of TxChannels
0000b
...
1111b
1 ch
..
16 ch
0000b
27..24 RxChannels Number of RxChannels
0000b
...
1111b
1 ch
..
16 ch
0000b
23..16 TxErrCntr Transmission error counter, 8-bit 00h
..
No error
..
00h
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Bits Field Description VALUE RESET
VALUE
FFh 255 errors
15..8 RxErrCntr Reception error counter, 8-bit
00h
..
FFh
No error
..
255 errors
00h
7 - Not used 0b
6 - Not used 0b
5 - Not used 0b
4 ACTIVE Transmission ongoing 0b
3 AHBErr AMBA AHB master interface blocked due to previous AHB error
1b
0b
Error
No error
0b
2 OR Overrun during reception 1b
0b
Overrun
error
0b
1 OFF Bus-off condition 1b
0b
Error
No error
0b
0 PASS Error-passive condition 1b
0b
Error
No error
0b
The OR bit is set if a message with a matching ID is received and cannot be stored via the AMBA AHB
bus, this can be caused by bandwidth limitations or when the circular buffer for reception is already
full.
The OR and AHBErr status bits is cleared when the register has been read.
TxErrCntr and RxErrCntr is defined according to CAN protocol.
The AHBErr bit is only set to 1b if an AMBA AHB error occurs while the Can-CONF.ABO
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31.18.3 CAN_CTRL (CONTROL RE GISTER)
31
1 0
Re
set
En
able
Bits Field Description VALUES RESET
VALUE
31..2 - Not used - 00..00b
1 RESET Reset complete CAN IP core 1b
0b
Reset
No effect
0b
0 ENABLE Enable or set CAN controller in sleep mode 1b
0b
Enable
sleep
0b
RESET is read back as 0b.
ENABLE is cleared to 0b while other settings are modified, ensuring that the CAN core is properly synchronised.
When ENABLE is cleared to 0b, the CAN interface is in sleep mode, only outputting recessive bits.
The CAN core require that 10 recessive bits be received before receive and transmit operations can begin.
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31.18.4 CAN_SYNC (CONTROL REGISTER)
31 30 29 28
0
SYNC
Bits Field Description VALUES RESET
VALUE
31..29 - Not used - 000b
28..0 SYNC
Represents the SYNC Message Identifier. Base
ID is bits 28 to 18 and Extended ID is bits 17 to
0.
00..00b
Base ID is bits 28 to 18 and Extended ID is bits 17 to 0.
31.18.5 CAN_SYMF (CONTROL REGISTER)
31 30 29 28
0
MASK
Bits Field Description VALUES RESET
VALUE
31..29 - Not used - 000b
28..0 MASK
Represents the MASK Message Identifier.
Base ID is bits 28 to 18 and Extended ID is bits
17 to 0.
A RxSYNC message ID is matched when:
((Received-ID XOR CAN_CODR.SYNC) AND
CAN_RCMR.MASK) = 0
A TxSYNC message ID is matched when:
11..11b
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((Transmitted-ID XOR CAN_CODR.SYNC) AND
CAN_RCMR.MASK) = 0
A RxSYNC message ID is matched when:
((Received-ID XOR CAN_CODR.SYNC) AND CAN_RCMR.MASK) = 0
A TxSYNC message ID is matched when:
((Transmitted-ID XOR CAN_CODR.SYNC) AND CAN_RCMR.MASK) = 0
31.18.6 CAN_TRCR (CONTROL RE GISTER)
31
3 2 1 0
Sin
gle
On
goin
g
En
able
If the SINGLE bit is 1b, the channel is disabled (i.e. the ENABLE bit is cleared to 0b) if the arbitration on the CAN bus is lost.
In the case an AHB bus error occurs during an access while fetching transmit data, and the ABORT (cfr CAN_CONF) bit is 1b, then the ENABLE bit is reset automatically.
Bits Field Description EFFECT/VALUE RESET
VALUE
31..3 - Not used
2 SINGLE Single shot mode 1b
0b
Single-shot
nominal
0b
1 ONGOING Transmission ongoing 1b
0b
On-going
idle
0b
0 ENABLE Enable channel 1b
0b
Enable
disable
0b
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At the time the ENABLE is cleared to 0b, any ongoing message transmission not be aborted, unless the CAN arbitration is lost or communication has failed
The ONGOING bit being 1b indicate that message transmission is ongoing and that configuration of the channel is not safe.
31.18.7 CAN_TRAR (CONTROL REGISTER)
31
10 9
0
ADDR
Bits Field Description VALUES RESET
VALUE
31..25 - Not used - 00..00b
24..23 XCHGRAM_SEL
Indicates XCHGRAM location:
“10b” is used for XCHGRAM0.
“01b" is used for XCHGRAM1.
"11b" is used for both XCHGRAMs
00b
22..10 ADDR Indicate the 13-bit base address into the
selected XCHGRAM 00..00b
9..0 - Not used 00..00b
31.18.8 CAN_TRSIZE (CONTROL REGISTER)
31
21 20
6 5
0
SIZE
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Bits Field Description VALUES RESET
VALUE
31..21 - Not used - 00..00b
20..6 SIZE
Represents the size of the circular buffer
inside the selected XCHGRAM(s). The size of
the circular buffer is SIZE*4 messages. Valid
SIZE values is between 0 and 16384
00..00b
5..0 - Not used 00..00b
31.18.9 CAN_TRWRREG (DATA REGISTER)
31
20 19
4 3
0
WRITE
Bits Field Description VALUES RESET
VALUE
31..20 - Not used - 00..00b
19..4 WRITE
Interpreted as a pointer to last write message
+ 1.
The WRITE field will be written by the
software to in order to initiate a transfer,
indicating the position +1 of the last message
to transmit.
It will not be possible to fill the buffer. There
will always be one message position in buffer
unused.
Software will be responsible for not
overwriting the buffer on wrap around (i.e.
setting WRITE=READ).
The field will be implemented as relative to
the buffer base address (scaled with the SIZE
00..00b
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field).
3..0 - Not used 0000b
The WRITE field will be written by the software to in order to initiate a transfer, indicating the
position +1 of the last message to transmit.
It will not be possible to fill the buffer. There will always be one message position in buffer unused.
Software will be responsible for not overwriting the buffer on wrap around (i.e. setting
WRITE=READ).
The field will be implemented as relative to the buffer base address (scaled with the SIZE field).
31.18.10 CAN_TRRDREG (DATA REGISTER)
31
20 19
4 3
0
READ
Bits Field Description VALUES RESET
VALUE
31..20 - Not used - 00..00b
19..4 READ
Represents a pointer to last read message + 1.
The READ field is written to automatically
when a transfer has been completed
successfully, indicating the position +1 of the
last message transmitted.
The READ field will be automatically
00..00b
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incremented even if the transmit channel has
been disabled, since the last requested
transfer is not aborted until CAN bus
arbitration is lost.
The field is implemented as relative to the
buffer base address (scaled with the SIZE
field).
The READ field can be used by the software to
read out the progress of a transfer.
The READ field can be written by the software
in order to set up the starting point of a
transfer. This should only be done while the
transmit channel is not enabled.
When the CAN_TRRDREG catches up with the
CAN_TRWRREG, this will indicate that all
messages in the XCHGRAM have been
transmitted (i.e. this is equivalent to a FIFO
empty case).
3..0 - Not used 0000b
The READ field is written to automatically when a transfer has been completed successfully,
indicating the position +1 of the last message transmitted.The READ field be automatically
incremented even if the transmit channel has been disabled, since the last requested transfer is not
aborted until CAN bus arbitration is lost.
The field is implemented as relative to the buffer base address (scaled with the SIZE field).
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31.18.11 CAN_RCCR (CONTROL RE GISTER)
31
2 1 0
On
goin
g
En
able
Bits Field Description VALUES RESET
VALUE
31..2 - Not used - 00..00
b
1 ONGOING Reception on-going (read-only) 1b
0b
On-going
idle
0b
0 ENABLE Enable received channel 1b
0b
Enable
sleep
0b
If an AHB bus error occurs during an access while fetching transmit data and if the CAN_CONF
ABORT bit is 1b, then the ENABLE bit is reset automatically.
At the time the ENABLE is cleared to 0b, any ongoing message reception not be aborted
The ONGOING bit being 1b indicate that message reception is ongoing and that configuration of the
channel is not safe.
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31.18.12 CAN_RCAR (DATA REGISTER)
31
10 9
0
ADDR
Bits Field Description VALUES RESET
VALUE
31..25 - Not used - 00..00b
24..23 XCHGRAM_SEL
Indicates XCHGRAM location:
“10b” is used for XCHGRAM0.
“01b" is used for XCHGRAM1.
"11b" is used for both XCHGRAMs
00b
22..10 ADDR Indicate the 13-bit base address into the
selected XCHGRAM 00..00b
9..0 - Not used 00..00b
31.18.13 CAN_RCSIZE (DATA REGISTER)
31
21 20
6 5
0
SIZE
Bits Field Description VALUES RESET
VALUE
31..21 - Not used - 00..00b
20..6 SIZE
Represents the size of the circular buffer
inside the selected XCHGRAM(s). The size of
the circular buffer is SIZE*4 messages. Valid
SIZE values is between 0 and 16384
00..00b
5..0 - Not used 00..00b
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31.18.14 CAN_RCWRREG (DATA REGISTER)
31
20 19
4 3
0
WRITE
Bits Field Description VALUES RESET
VALUE
31..20 - Not used - 00..00b
19..4 WRITE
Interpreted as a pointer to last write message
+ 1.
The WRITE field is written to automatically
when a transfer has been completed
successfully, indicating the position +1 of the
last message received.
The WRITE field can be used by the software
to read out the progress of a transfer.
The WRITE field can be written by the
software in order to set up the starting point
of a transfer. This should only be done while
the receive channel is not enabled.
The field will be implemented as relative to
the buffer base address (scaled with the SIZE
field).
00..00b
3..0 - Not used 0000b
The WRITE field is written to automatically when a transfer has been completed successfully,
indicating the position +1 of the last message received.
The WRITE field can be used by the software to read out the progress of a transfer.
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31.18.15 CAN_RCRDREG (DATA REGISTER)
31
20 19
4 3
0
READ
Bits Field Description VALUES RESET
VALUE
31..20 - Not used - 00..00b
19..4 READ
The field is implemented as relative to the
buffer base address (scaled with the SIZE
field).It will not be possible to fill the buffer.
There will always be one message position in
buffer unused.
The READ field will be written by the software
in order to release the receive buffer,
indicating the position +1 of the last message
that has been read out.
The software will be responsible for not over-
reading the buffer on wrap around (i.e.
setting WRITE=READ).
00..00b
3..0 - Not used 0000b
The field is implemented as relative to the buffer base address (scaled with the SIZE field).
It not be possible to fill the buffer. There always be one message position in buffer unused.
The READ field will be written by the software in order to release the receive buffer, indicating the
position +1 of the last message that has been read out.
The software will be responsible for not over-reading the buffer on wrap around (i.e. setting WRITE=READ).
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31.18.16 CAN_RCMR (CONTROL REGISTER)
31 30 29 28
0
AM
Bits Field Description VALUES RESET
VALUE
31..29 - Not used - 000b
28..0 AM
Represents the Acceptance Mask. Bits set to 1b are taken into account in the comparison between the received message ID and the CAN_CODCR AC field.
The Base ID is bits 28 to 18 and Extended ID is bits 17 to 0
11..11b
31.18.17 CAN_CODR (CONTROL RE GISTER)
31 30 29 28
0
AC
Bits Field Description VALUES RESET
VALUE
31..29 - Not used - 000b
28..0 AC
Represents the Acceptance Code, used in comparison with the received message.
The Base ID is bits 28 to 18 and Extended ID is bits 17 to 0.
A message ID is matched when: ((Received-ID XOR CAN_.RCMR.AC) AND CAN_RCMR.AM) = 0
00..00b
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31.19 MIL-STD-1553 RT
31.19.1 M1553_EVENTREG (CONTROL REGISTER)
31 1
1 10 9 8 7 0
NO
T U
SED
RTT
E
RTD
NO
T U
SED
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..11 - 00..00b (constant) - 00..00b
10 RTTE RT Table access error. Cleared when written to 1. (*)
1b
0b
ERROR
CLEARED 0b
9 RTD RT DMA Error. Cleared when written to 1. 1b
0b
ERROR
CLEARED 0b
8 - Not used. Should be written with zeroe(s) and masked out on read.
0b
7..0 - Not used. Constant 0..0b. 0..0b
(* ) reports any message that has been legalized by subaddress table but that could not be fulfilled
either because:
there is no valid descriptor ready i.e. pointer to descriptor was the "null pointer" (value= 0x3) or
descriptor had DV bit already set
or data could be accessed within the required response time thus indicating that 1553 timings have
not been respected. This is due to XCHGRAM access that took too long or software that does not
fill up the descriptor tables fast enough.
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31.19.2 M1553_HWCONF (STATUS/CONTROL REGISTER)
The M1553_HWCONF register have the following definition
31 30
12 11 10 9 8 7
3 2 1 0
MO
D
NO
T U
SED
XK
EYS
END
IAN
SCLK
CC
FREQ
BITS FIELD DESCRIPTION VALUES RESET VALUE
31 MOD
“Modified” field (Reserved to indicate that the core has been modified / customized in an unspecified manner)
Constant 0b
N/A 0b
30..12 - “00..00” (constant) N/A 00..00b
11 XKEYS
Set if safety keys are enabled for the BM Control Register and for all RT Control Register fields.
Constant 0b (safety keys not enabled)
N/A 0b
10..9 ENDIAN AHB endianness
Constant 00b (bit endian) N/A 00b
8 SCLK “Same clock”, spare field.
Constant 0b.
N/A 0b
7..0 CCFREQ “Codec clock frequency”, spare field.
Constant 0..0b (20 MHz) N/A
00..00b
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31.19.3 M1553_STATREG (STATUS REGISTER)
31 30
4 3 2 1 0
RTS
UP
NO
T U
SED
AC
T
SHD
A
SHD
B
RU
N
BITS FIELD DESCRIPTION VALUES RESET VALUE
31 RTSUP RT Supported - Reads ‘1’ if core supports RT mode
1b
0b
RT ON
RT OFF 1b
30..4 - Not used. Should be written with zeroe(s) and masked out on read
00…00b
3 ACT RT Active (ACT) – set to ‘1’ if RT is currently processing a transfer
1b
0b
Transfer
No transfer 0b
2 SHDA
Bus A shutdown (SHDA) - Reads ‘1’ if bus A has been shut down by the BC (using the transmitter shutdown mode command on bus A)
1b
0b
Bus A OFF
BUS A ON 0b
1 SHDB Bus B shutdown - Reads ‘1’ if bus B has been shut down by the BC (using the transmitter shutdown mode command on bus B)
1b
0b
BUS B OFF
BUS B ON
0b
0 RUN RT Running – set to ‘1’ if the RT is listening to commands.
1b
0b
LISTENING
NOT ENABLED
0b
31.19.4 M1553_CONFREG (CONTROL REGISTER)
31
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT
KE
Y
SYS
SYD
S
BR
S
NO
T U
SED
RT
EIS
RT
AD
DR
RT
EN
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..16 RTKEY Safety code - Must be written as 0x1553 when changing the RT address (RTADDR field),
1553h Enable RTADDR update
Disable RTADDR update 0000h
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BITS FIELD DESCRIPTION VALUES RESET VALUE
otherwise value is unaffected by the write. When reading the register, this field reads 0x0000.
other
15 SYS
Sync signal enable - Set to ‘1’ to enable update of M1553_SYNCREG (SYNC TIME field) when a synchronize mode code (without data) has been received.
1b
0b
ENABLE
DISABLE 1b
14 SYDS
Sync with data signal enable Set to ‘1’ to enable update of M1553_SYNCREG (SYNC DATA field) when a synchronize with data word mode code has been received
1b
0b
ENABLE
DISABLE 1b
13 BRS
Bus reset signal enable - Set to ‘1’ to enable effect of “1553 RESET” field in MMU_STAT when a reset remote terminal mode code has been received.
1b
0b
ENABLE
DISABLE 1b
12..7 - Not used. Should be written with zeroe(s) and masked out on read
00..00b
6 RTEIS
Reads ‘1’ if current address was set (and validated against parity) through external inputs. After setting the address from software, this field is set to ‘0’
1b
0b
HW conf
SW conf 0b
5..1 RTADDR RT Address - This RT:s address (0-30)
00000b
..
11110b
RT address=0
..
RT address=30
*
0 RTEN RT Enable - Set to ‘1’ to enable listening for requests
1b
0b
ENABLE
DISABLE 0b
(*)Reset value is affected by the external M1553_RTADDR_x/M1553_RTADDRP input signals available just after the CLP reset release. Any change occurring after the reset release is not taken into account. If parity is wrong, reset value is 11111b and RTEIS=0b.
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31.19.5 M1553_BUSSTAT (STATUS REGISTER)
31
9 8 7 5 4 3 2 1 0
NO
T U
SED
TFD
E
NO
T U
SED
SREQ
BU
SY
SSF
DB
CA
TFLG
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..9 - Not used. Should be written with zeroe(s) and masked out on read
00..00b
8 TFDE Set Terminal flag automatically on DMA errors (*)
1b
0b
SET
UNSET
0b
7..5 - Not used. Should be written with zeroe(s) and masked out on read
000b
4 SREQ Service request - This bit will be sent in the RT’s Status Word over the 1553 bus.
1b
0b
SET
UNSET 0b
3 BUSY
Busy bit - This bit will be sent in the RT’s Status Word over the 1553 bus. Note: If the busy bit is set, the RT will respond with only the status word and the transfer “fails”
1b
0b
SET
UNSET 0b
2 SSF Subsystem Flag - This bit will be sent in the RT’s Status Word over the 1553 bus.
1b
0b
SET
UNSET 0b
1 DBCA
Dynamic Bus Control Acceptance - This bit will be sent in the RT’s Status Word over the 1553 bus. Note: This bit is only sent in response to the Dynamic Bus Control mode code
1b
0b
SET
UNSET
0b
0 TFLG
Terminal Flag - This bit will be sent in the RT’s Status Word over the 1553 bus. The BC can mask this flag using the “inhibit terminal flag” mode command, if legal
1b
0b
SET
UNSET 0b
(*) covers any message that has been legalized by subaddress table but that could not be fulfilled either because:
there is no valid descriptor ready i.e. pointer to descriptor was the "null pointer" (value= 0x3) or descriptor had DV bit already set
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or data could be accessed within the required response time thus indicating that 1553 timings have
not been respected. This is due to XCHGRAM access that took too long or software that does not
fill up the descriptor tables fast enough.
or data could be accessed within the required response time thus indicating that 1553 timings have not been respected. This is due to XCHGRAM access that took too long or software that does not fill up the descriptor tables fast enough.
31.19.6 M1553_SWRDSREG (STATUS REGISTER)
31
16 15
0
BIT
W
VEC
W
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..16 BITW BIT Word - Transmitted in response to the “Transmit BIT Word” mode command, if legal
0000h
...
FFFFh
Cfr AD8 0000h
15..0 VECW Vector word - Transmitted in response to the “Transmit vector word” mode command, if legal.
0000h
...
FFFFh
Cfr AD8 0000h
31.19.7 M1553_SYNCREG (STATUS REGISTER)
31
16 15
0
SYTM
SYD
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..16 SYTM SYNC TIME – The value of the RT timer at the last sync or sync with data word mode
00..00b See descri
00..00b
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BITS FIELD DESCRIPTION VALUES RESET VALUE
command, if legal. …
11..11b
ption
15..0 SYD SYNC DATA – The data received with the last synchronize with data word mode command, if legal.
00..00b
…
11..11b
See description
00..00b
31.19.8 M1553_SUBADDTAB (CONTROL REGISTER)
31
9 8
0
SAT
B
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..0 SATB
SUBADDRESS TABLE BASE (*) – Indicates XCHGRAM selection and the base address where the 1553 subaddress table is located. This table is made of 128 consecutive addresses segmented in 4 addresses per subaddress (Note: the first and last 4 addresses are never accessed as they correspond to mode code)
Bits 31 to 16 have no effect
Bits 16 indicate which XCHGRAM is used (bit 15 has not effect):
1b is used for XCHGRAM0.
0b is used for XCHGRAM1.
Bits 14-2 indicate the 13-bit address in XCHGRAM pointing to where the subaddress table starts . This base address shall always be a multiple of 128 i.e bits 8 to 2 have no effect and are always read as ‘0’. When 0000h is written, address points to APB address 0x4000. When 1F00h is written, address points to APB address
00..00b
...
11.11b
See descripti
on 00..00b
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BITS FIELD DESCRIPTION VALUES RESET VALUE
5F00h
Bits 14 to 2 shall represent the 13-bit base address inside the selected XCHGRAM where the subaddress table starts. This base address shall always be a multiple of 128 i.e bits 8 to 2 have no effect and are always read as 0b.
Bits 1 to 0 have no effect. They are always read as ‘0’
(*) the following formula can be used to program the APB register
o * SATB = (AX*4) +10000h, if XCHGRAM0 is to be used
o * SATB = (AX*4) +00000h, if XCHGRAM1 is to be used
where AX is the desired 13-bit address in hexadecimal format:
31.19.9 M1553_MCREG (CONTROL REGISTER)
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..30 - Not used. Should be written with zeroe(s) and masked out on read
00..00b
29..28 RRTB Reset remote terminal broadcast
00b
01b
1Xb
ILLEGAL
LEGAL
FORBIDDEN(*)
00b
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NO
T U
SED
RR
TB
RR
T
ITFB
ITF
ISTB
IST
DB
C
TWB
TVW
TSB
TS
SDB
SD
SB
S
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BITS FIELD DESCRIPTION VALUES RESET VALUE
27..26 RRT Reset remote terminal
00b
01b
1Xb
ILLEGAL
LEGAL
FORBIDDEN(*)
00b
25..24 ITFB Inhibit and override inhibit terminal flag bit broadcast
00b
01b
1Xb
ILLEGAL
LEGAL
FORBIDDEN(*)
00b
23..22 ITF Inhibit and override inhibit terminal flag
00b
01b
1Xb
ILLEGAL
LEGAL
FORBIDDEN(*)
00b
21..20 ISTB Initiate self test broadcast
00b
01b
1Xb
ILLEGAL
LEGAL
FORBIDDEN(*)
00b
19..18 IST Initiate self test
00b
01b
1Xb
ILLEGAL
LEGAL
FORBIDDEN(*)
00b
17..16 DBC Dynamic bus control
00b
01b
1Xb
ILLEGAL
LEGAL
FORBIDDEN(*)
00b
15..14 TBW Transmit BIT word
00b
01b
1Xb
ILLEGAL
LEGAL
FORBIDDEN(*)
00b
13..12 TVW Transmit vector word
00b
01b
1Xb
ILLEGAL
LEGAL
FORBIDDEN(*)
00b
11..10 TSB Transmitter shutdown and override transmitter shutdown broadcast
00b
01b
1Xb
ILLEGAL
LEGAL
FORBIDDEN(*)
01b
9..8 TS Transmitter shutdown and override transmitter shutdown
00b
01b
1Xb
ILLEGAL
LEGAL
FORBIDDEN(*)
01b
7..6 SDB Synchronize with data word broadcast
00b
01b
1Xb
ILLEGAL
LEGAL
FORBIDDEN(*)
01b
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BITS FIELD DESCRIPTION VALUES RESET VALUE
5..4 SD Synchronize with data word
00b
01b
1Xb
ILLEGAL
LEGAL
FORBIDDEN(*)
01b
3..2 SB Synchronize broadcast
00b
01b
1Xb
ILLEGAL
LEGAL
FORBIDDEN(*)
01b
1..0 S Synchronize
00b
01b
1Xb
ILLEGAL
LEGAL
FORBIDDEN(*)
01b
(*) not authorized because side-effects (i.e. undesired writes) may occur in XCHGRAM memories
31.20 SPACEWIRE/RMAP
31.20.1 SPW0_CTRL, SPW1_CTRL (CONTROL REGISTER)
31 30 29 28 27 26 25 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RA RX RC PO LBE
PS NP
RD RE TR TT LI TQ
RESE
RVED
RS PM TI IE AS LS LD
RESE
RVED
RESE
RVED
NCH
RESE
RVED
BITS FIELD DESCRIPTION VALUES RESET VALUE
31 RA RMAP available - Set to one if the RMAP target is available. Only readable.
1b
0b
RMAP on
RMAP off 1b
30 RX RX unaligned access - Set to one if unaligned writes are available for the receiver. Only readable.
1b
0b
Unaligned
aligned 0b
29 RC RMAP CRC available - Set to one if RMAP CRC is enabled in the core. Only readable.
1b
0b
CRC on
CRC off
1b
28..27 NCH Number of DMA channels – set to 1 for the CLP (NCH=0)
00b 1 DMA 00b
26 PO Number of ports – set to 1 for the CLP (PO=0) 00b 1 port 0b
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BITS FIELD DESCRIPTION VALUES RESET VALUE
25..23 - NOT USED 000b
22 LBE Loop-back enable. The value of this bit is driven on the swno.loobpack output.
1b
0b
Enable
disable 0b
21 PS Port select - Selects the active port when the no port force bit is zero. Not used for the CLP as only one port is available
0b disable 0b
20 NP No port force - Disable port force. Not used for the CLP as only one port is available
0b disable 0b
19..18 - NOT USED 00b
17 RD RMAP buffer disable - If set only one RMAP buffer is used. This ensures that all RMAP commands will be executed consecutively.
1b
0b
Enable
disable 0b
16 RE RMAP Enable - Enable RMAP target.. 1b
0b
Enable
disable 1b
15..12 - NOT USED 0000b
11 TR Time Rx Enable - Enable time-code receptions. 1b
0b
Enable
disable 0b
10 TT Time Tx Enable - Enable time-code transmissions.
1b
0b
Enable
disable 0b
9 LI Link error Status – Set when a link error occurs. Not reset.
1b
0b
Enable
disable 0b
8 TQ Tick-out Status – Set when a valid time-code is received. Not reset.
1b
0b
Enable
disable 0b
7 - NOT USED 0b
6 RS Reset - Make complete reset of the SpaceWire node. Self clearing.
1b
0b
Enable
disable 0b
5 PM Promiscuous Mode - Enable Promiscuous mode. 1b
0b
Enable
disable 0b
4 TI
Tick In - The host can generate a tick by writing a one to this field. This will increment the timer counter and the new value is transmitted after the current character is transferred. A tick can also be generated by asserting the tick_in signal.
1b
0b
Enable
disable 0b
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BITS FIELD DESCRIPTION VALUES RESET VALUE
3 IE Status Enable - If set, a status is generated when one of bit 8 to 9 is set and its corresponding event occurs.
1b
0b
Enable
disable 0b
2 AS
Autostart - Automatically start the link when a NULL has been received. Reset value: 0b if the RMAP target is not available. If available the reset value is set to the value of the rmapen input signal.
1b
0b
Enable
disable 0b
1 LS Link Start - Start the link, i.e. allow a transition from ready to started state.
1b
0b
Enable
disable 0b
0 LD Link Disable - Disable the SpaceWire codec. 1b
0b
Enable
disable
0b
31.20.2 SPW0_STAT, SPW1_STAT (STATUS REGISTER)
31 24 23 21 20 10 9 8 7 6 5 4 3 2 1 0
AP
EE
IA PE
DE
ER
CE
TO
RE
SE
RV
ED
LS
RE
SE
RV
ED
RE
SE
RV
ED
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..24 NOT USED 0..0b
23..21 LS Link State - The current state of the start-up sequence.
000b
001b
010b
011b
100b
101b
Error-reset
Error-wait
Ready
Started
Connecting
Run
000b
20..10 NOT USED 0..0b
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BITS FIELD DESCRIPTION VALUES RESET VALUE
9 AP Active port - Shows the currently active port. For the CLP only one port is used (“ports” generic is set to 1).
0b 1 port 0b
8 EE
Early EOP/EEP - Set to one when a packet is received with an EOP after the first byte for a non-rmap packet and after the second byte for a RMAP packet. Cleared when written with a one.
1b
0b
Cfr description
0b
7 IA
Invalid Address (- Set to one when a packet is received with an invalid destination address field, i.e it does not match the nodeaddr register. Cleared when written with a one. Reset value: 0b.
1b
0b
Cfr description
0b
6..5 RES RESERVED 00b
4 PE Parity Error (PE) - A parity error has occurred. Cleared when written with a one. Reset value: 0b.
0b
3 DE Disconnect Error (DE) - A disconnection error has occurred. Cleared when written with a one. Reset value: 0b.
0b
2 ER Escape Error (ER) - An escape error has occurred. Cleared when written with a one. Reset value: 0b.
0b
1 CE Credit Error (CE) - A credit has occurred. Cleared when written with a one. Reset value: 0b.
0b
0 TO Tick Out (TO) - A new time count value was received and is stored in the time counter field. Cleared when written with a one. Reset value: 0b.
0b
31.20.3 SPW0_NOD_ADD, SPW1_NOD_ADD (CONTROL REGISTER)
31 16 15 8 7 0
RES
ERV
ED
DEF
MA
SK
DEF
AD
DR
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..16 RES RESERVED 0
15..8 DEFMASK
Default mask - Default mask used for node identification on the SpaceWire network. This field is used for masking the address before comparison. Both the received address and the DEFADDR field are anded with the inverse of DEFMASK before the
00h
..
FFh
No mask
..
Mask all
00h
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BITS FIELD DESCRIPTION VALUES RESET VALUE
address check.
7..0 DEFADDR Default address - Default address used for node identification on the SpaceWire network.
00h
..
FFh
0
..
254
FEh
31.20.4 SPW0_CLK_DIV, SPW1_CLK_DIV (CONTROL REGISTER)
31 16 15 8 7 0
RES
ERV
ED
CLK
DIV
STA
RT
CLK
DIV
RU
N
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..16 - NOT USED 0..0b
15..8 CLKDIVSTART
Clock divisor startup - Clock divisor value used for the clock-divider during startup (link-interface is in other states than run). The actual divisor value is Clock Divisor register + 1. Reset value: clkdiv10 input signal.
00h
...
FFh
1
...
256
04h
7..0 CLKDIVRUN
Clock divisor run - Clock divisor value used for the clock-divider when the link interface is in the run-state. The actual divisor value is Clock Divisor register + 1. Reset value: clkdiv10 input signal.
00h
...
FFh
1
...
256
04h
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31.20.5 SPW0_DST_KEY, SPW1_DST_KEY (CONTROL REGISTER)
31 8 7 0
DES
TKEY
RES
ERV
ED
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..8 - NOT USED 0
7..0 DESTKEY Destination key - RMAP destination key (the deskey VHDL generic Shall be set to 1b))
00h
..
FFh
0
..
255
30h
31.20.6 SPW0_TIM, SPW1_TIM (CONTROL REGISTER)
31 8 7 6 5 0
RES
ERV
ED
TCTR
L
TIM
ECN
T
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..8 - NOT USED 0..Ob
7..6 TCTRL
Time control flags - The current value of the time control flags. Sent with time-code resulting from a tick-in. Received control flags are also stored in this register.
00b
..
11b
0b
5..0 TIMECNT
Time counter - The current value of the system time counter. It is incremented for each tick-in and the incremented value is transmitted. The register can also be written directly but the written value will not be transmitted. Received time-counter values are also stored in this register.
0..0b
..
1..1b
0b
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31.20.7 SPW0_DMA_CTRL, SPW1_DMA_CTRL (CONTROL REGISTER)
31 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LE SP SA EN NS
RD
RX
AT
RA
TA PR PS AI
RI TI RE
TE
RES
ERV
ED
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..17 - NOT USED 0..0b
16 LE Link error disable - Disable transmitter when a link error occurs. No more packets will be transmitted until the transmitter is enabled again.
1b
0b
Disable
enable 0b
15 SP Strip pid - Remove the pid byte (second byte) of each packet. The address byte (first byte) will also be removed when this bit is set independent of the SA bit.
1b
0b
Remove
unremove 0b
14 SA Strip addr - Remove the addr byte (first byte) of each packet.
1b
0b
Remove
unremove 0b
13 EN Enable addr - Enable separate node address for this channel.
1b
0b
enable
disable 0b
12 NS No spill - If cleared, packets will be discarded when a packet is arriving and there are no active descriptors. If set, the GRSPW will wait for a descriptor to be activated.
1b
0b
Wait descr.
discard 0b
11 RD
Rx descriptors available - Set to one, to indicate to the GRSPW that there are enabled descriptors in the descriptor table. Cleared by the GRSPW when it encounters a disabled descriptor:
1b
0b
Rx descr.
No descr. 0b
10 RX RX active - Is set to 1b if a reception to the DMA channel is currently active otherwise it is 0b. Only readable.
1b
0b
Rx descr.
No descr. 0b
9 AT
Abort TX - Set to one to abort the currently transmitting packet and disable transmissions. If no transmission is active the only effect is to disable transmissions. Self clearing.
1b
0b
abort
no effect 0b
8 RA RX AHB error - An error response was detected on the AHB bus while this receive DMA channel was accessing the bus. Cleared when written with a one.
1b
0b
Error
Cleared 0b
7 TA TX AHB error - An error response was detected on the AHB bus while this transmit DMA channel was accessing the bus. Cleared when written with a one.
1b
0b
Error
Cleared 0b
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BITS FIELD DESCRIPTION VALUES RESET VALUE
6 PR Packet received - This bit is set each time a packet has been received. IT is never cleared by the SW node. Cleared when written with a one.
1b
0b
Packet received.
Cleared
0b
5 PS Packet sent - This bit is set each time a packet has been sent. Never cleared by the SW-node. Cleared when written with a one.
1b
0b
Packet sent.
Cleared 0b
4 AI not available on the CLP (the design shall freeze this bit to 0b)
0b
3 RI not available on the CLP (the design shall freeze this bit to 0b)
0b
2 TI not available on the CLP (the design shall freeze this bit to 0b)
0b
1 RE Receiver enable - Set to one when packets are allowed to be received to this channel.
1b
0b
Enable
disable 0b
0 TE
Transmitter enable - Write a one to this bit each time new descriptors are activated in the table. Writing a one will cause the SW-node to read a new descriptor and try to transmit the packet it points to. This bit is automatically cleared when the SW-node encounters a descriptor which is disabled.
1b
0b
Enable
disable 0b
31.20.8 SPW0_DMA_LEN, SPW1_DMA_LEN (DATA REGISTER)
31 25 24 0
RXM
AXL
EN
RES
ERV
ED
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..25 - NOT USED 0
24..2 RXMAXLEN
RX maximum buffer length in XCHGRAM - Receiver packet maximum length in bytes. Bits 24 to 13 should be set to 0b by the software and are not interpreted by the MMU.
00..00b
...
11..00b
1
…
213-1
U
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BITS FIELD DESCRIPTION VALUES RESET VALUE
Only the Bit 12 to 0 values are specified on next column.
1..0 - NOT USED 0
31.20.9 SPW0_DMA_TADD, SPW1_DMA_TADD (DATA REGISTER)
31 10 9 4 3 0
RES
ERV
ED
DES
CSE
L
DES
CB
ASE
AD
DR
BITS FIELD DESCRIPTION VALUES
RESET VALUE
31..10 DESCBASEADDR
Descriptor table location and base address in XCHGRAM. Bits 19-18 indicate XCHGRAM location. 10b is used for XCHGRAM0. 01b is used for XCHGRAM1. Bits 17-10 indicate the 13-bit base address into the selected XCHGRAM
Cfr description
U
9..4 DESCSEL
Descriptor selector - Offset into the descriptor table. Shows which descriptor is currently used by the SpaceWire. For each new descriptor read, the selector will increase with 16 and eventually wrap to zero again.
00..00b
..
11..11b
0
..
63
0
3..0 - NOT USED 0
31.20.10 SPW0_DMA_RADD, SPW1_DMA_RADD (CONTROL REGISTER)
31 10 9 3 2 0
DES
CB
ASE
AD
DR
DES
CSE
L
RES
ERV
ED
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BITS FIELD DESCRIPTION VALUES RESET VALUE
31..10 DESCBASEADDR
Descriptor table location and base address in
XCHGRAM. Bits 19-18 indicate XCHGRAM lcoation.
10b is used for XCHGRAM0. 01b is used for
XCHGRAM1. 11b is used for both XCHGRAMs.Bits
17-10 indicate the 13-bit base address into the
selected XCHGRAM
Cfr
descripti
on
U
9..3 DESCSEL
Descriptor selector - Offset into the descriptor
table. Shows which descriptor is currently used by
the SpaceWire. For each new descriptor read, the
selector will increase with 16 and eventually wrap
to zero again.
00..00b
..
11..11b
0
..
63
0b
2..0 RES NOT USED 0b
31.20.11 SPW0_DMA_ADD, SPW1_DMA_ADD (DATA REGISTER)
31 16 15 8 7 0
RES
ERV
ED
MA
SK
AD
DR
BITS FIELD DESCRIPTION VALUES RESET VALUE
31..16 - NOT USED 0
15..8 MASK
Mask - Mask used for node identification on the SpaceWire network. This field is used for masking the address before comparison. Both the received address and the ADDR field are anded with the inverse of MASK before the address check.
00h
..
FFh
No mask
..
Mask all
U
7..0 ADDR
Address - Address used for node identification on the SpaceWire network for the corresponding DMA channel when the EN bit in the SPWx_DMA_XTRL is set.
00h
..
FEh
0
..
254
U
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31.21 IEEE-754 COMPLIANCE
This section gives the compliance of the CLP architecture with respect to IEEE-754 standard mandatory requirements i.e. sentences making use of the ”shall” word. Other sentences have not been considered since compliance to IEEE-754 is not required
The compliance is achieved either by:
Hardware (HW) i.e. the implementation is made through the CLP functionality (logic cells,
registers and memories)
Software (SW) i.e. the implementation is made through a dedicated piece of assembly code.
In that case the function is part of the macro library described in document [RD5]
Note also that all requirements of the IEEE-754 standard have not been implemented to
keep the CLP design simple. Strictly speaking, the CLP is thus not fully compliant. However,
these deviances aimed to avoid embarking the CLP in an uncontrolled environment (i.e.
propagation or handling of NaN or infinite values) because of the nature of the targeted
applications (i.e. real-time embedded software)
The table below provides the full picture and indicates the following information
The IEEE-754 paragraph number (as given in the IEEE-754 standard)
The compliance status: C (compliant) / NC (not compliant) / PC (partially compliant)
In case of compliance or partial compliance, how this is achieved
Any relevant comment or additional explanation
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IEEE-754 PARAGRAPH COMPLIANCE HW SW COMMENT
1. Overview N/A Description
1 1.1 Scope N/A Description
1 1.2 Purpose N/A Description
1 1.3 Inclusions N/A Description
1 1.4 Exclusions N/A Description
1.5 Programming environment
considerations
N/A Description
1.6 Word usage N/A Description
2. Definitions, abbreviations, and
acronyms
N/A Definitions
2.1 Definitions N/A Definitions
2.2 Abbreviations and acronyms N/A Definitions
3. Floating-point formats N/A Title
3.1 Overview N/A Title
3.1.1 Formats C X Only 32-bit binary arithmetic and interchange format is supported
Other arithmetic and interchange formats are not supported
Extended arithmetic formal are not supported
3.1.2 Conformance N/A Conformance (or not) is documented in this table
3.2 Specification levels N/A Description
3.3 Sets of floating-point data PC X +∞, -∞, NaN and denormalized value are not supported. Detection of such values is
integrated in the CLP which in turn replaces theses ones by a real value (cfr §7.1.1)
3.4 Binary interchange format
encodings
PC Comment in “3.3 Sets of floating-point data” applies
3.5 Decimal interchange format
encodings
NC Also applies to sub-paragraphs
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IEEE-754 PARAGRAPH COMPLIANCE HW SW COMMENT
3.6 Interchange format parameters C X Only 32-bit binary interchange format is supported (binary32 in Table 3.5 of
standard)
3.7 Extended and extendable precisions NC Not supported
4. Attributes and rounding N/A Title
4.1 Attribute specification N/A Definition
4.2 Dynamic modes for attributes NC Not supported
4.3 Rounding-direction attributes C X Decimal format is not supported
4.3.1 Rounding-direction attributes to
nearest
PC X roundTiesToAway is not supported
4.3.2 Directed rounding attributes PC X roundTowardPositive and roundTowardNegative are not supported
4.3.3 Rounding attribute requirements PC X roundTowardPositive and roundTowardNegative are not supported
5. Operations N/A Title
5.1 Overview N/A Description
5.2 Decimal exponent calculation N/A Decimal format is not supported
5.3 Homogeneous general-
computational operations
N/A Title
5.3.1 General operations PC X X roundTiesToAway ,roundTowardPositive and roundTowardNegative are not
supported
See SW macro library for exhaustive list of supported operations
Remainder() is not supported
5.3.2 Decimal operation NC Decimal format is not supported
5.3.3 logBFormat operations NC
5.4 formatOf general-computational
operations
Title
5.4.1 Arithmetic operations PC X X Addition (FADD), subtraction (FSUB), multiplication (FMUL) and division
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IEEE-754 PARAGRAPH COMPLIANCE HW SW COMMENT
(FDIV) and convertFromInt (INTOF) are supported by HW. Rounding restriction
highlighted in “5.3.1 General operations” apply
Other operations are supported with the SW macro library
5.4.2 Conversion operations for
floating-point formats and decimal
character sequences
N/A Decimal format is not supported
5.4.3 Conversion operations for binary
formats
NC May however be supported by SW (extension of SW macro library)
5.5 Quiet-computational operations Title
5.5.1 Sign bit operations C X X copy(x) is supported with the various MOVxx instructions.
negate(x), abs(x) and copySign(x, y) supported by macro library
5.5.2 Decimal re-encoding operations N/A Decimal format is not supported
5.6 Signaling-computational operations N/A Title
5.6.1 Comparisons PC X Implemented in SW macro library via instructions CONDOR and CONDAND.
Error signalling is not implemented but may be detected via RSTATCNTxx
5.7 Non-computational operations N/A Title
5.7.1 Conformance predicates NC Only 2008 version is applicable
5.7.2 General operations PC X X Only class(x), are implemented in SW macro library. Other functions are not
supported due to limitation given in “3.3 Sets of floating-point data”
5.7.3 Decimal operation N/A Decimal format is not supported
5.7.4 Operations on subsets of flags NC X Invalid and inexact Flags are not implemented. Divide by zero, overflow and
underflow are available but occurrence is accumulated in RSTATCNT3 counter
5.8 Details of conversions from
floating-point to integer formats
PC X X Implemented with instruction FTOINT but only convertToIntegerTiesToEven
(round-to-nearest in text) and convertToIntegerTowardZero(round-to-zero in text)
are available
5.9 Details of operations to round a
floating-point datum to integral value
NC
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IEEE-754 PARAGRAPH COMPLIANCE HW SW COMMENT
5.10 Details of totalOrder predicate PC X X implemented in SW macro library and with limitation given in “3.3 Sets of
floating-point data”
5.11 Details of comparison predicates C X X
5.12 Details of conversion between
floating-point data and external
character sequences
NC
6. Infinity, NaNs, and sign bit Title
6.1 Infinity arithmetic NC +∞, -∞ are not supported and flushed to a known value according to Table 10
6.2 Operations with NaNs NC NaN is not supported and flushed to a known value according to Table 10
6.3 The sign bit C X
7. Default exception handling Title
7.1 Overview: exceptions and flags N/A Description
7.2 Invalid operation PC Not implemented since NaN and ∞ are not implemented. 0/0 result is presented in
§7.1.1. Square root is handled by SW but invalid flag and sqrt(-0.0) will not be
supported.
7.3 Division by zero PC X Signaling is made on register RSTATCNTA or RSTATCNTB. However,
MaxFloat is generated instead of ∞
7.4 Overflow PC X roundTiesToEven carries all overflows to MaxFloat (instead of ∞) with the sign
of the intermediate result
No overflow flag exist but event is trapped RSTATCNTA or RSTATCNTB
registers when rounded result is ∞
7.5 Underflow PC X No underflow flag exist but event is trapped in RSTATCNTA or RSTATCNTB
registers when rounded result is denormalised .
7.6 Inexact PC X No inexact flag exist but event is trapped in RSTATCNTA or RSTATCNTB
registers when rounded result is denormalised .
8. Alternate exception handling
attributes
N/A Title
8.1 Overview NC
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IEEE-754 PARAGRAPH COMPLIANCE HW SW COMMENT
8.2 Resuming alternate exception
handling attributes
NC Note that AbruptUnderflow attribute is the default behaviour in the CLP
8.3 Immediate and delayed alternate
exception handling attributes
NC
9. Recommended operations N/A Title
9.1 Conforming language- and
implementation-defined functions
C X A few additional functions are available by SW
9.1.1 Exceptions PC Exceptions are trapped in RSTATCNTA or RSTATCNTB registers
9.2 Recommended correctly rounded
functions
PC X X Only sin(x), cos(x), rSqrt(x), sqrt(x), hypoth(x,y), atan(x)
9.3 Operations on dynamic modes for
attributes
N/A Title
9.3.1 Operations on individual dynamic
modes
NC Not supported
9.3.2 Operations on all dynamic modes NC Not supported
9.4 Reduction operations NC Not supported
10. Expression evaluation N/A Title
10.1 Expression evaluation rules N/A To be defined in assembler and/or C compiler user manual
10.2 Assignments, parameters, and
function values
N/A To be defined in assembler and/or C compiler user manual
10.3 preferredWidth attributes for
expression evaluation
N/A To be defined in assembler and/or C compiler user manual
10.4 Literal meaning and value-
changing optimizations
N/A To be defined in assembler and/or C compiler user manual
11. Reproducible floating-point results C X Reproducible results are at least possible with 32-bit floating point instructions
described in section 7.1.6.1