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Self Oscillating Class-D Audio Amplifier with Regulated Half

Bridge Power SupplyMIT 6.100 Lab Report

Michael Price

Advisor: Ron Roscoe

Dec. 14, 2005

Abstract

In the interest of investigating more energy-efficient circuit technologies and new concepts for high-

fidelity audio, I have designed and built a complete audio amplifier system using switching electronics toaccomplish accurate output with very low losses. The equipment is smaller and lighter, and the audioperformance is similar, compared to well-designed linear power amplifiers. This report details threecircuits: a power factor correction (PFC) stage, a half-bridge DC-DC converter, and a self-oscillatingClass-D audio amplifier. I explain the significance of each circuits switching converter topology, theirexpected behavior, construction details, and measured performance.

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Contents

1 Introduction 3

2 Circuit Design 42.1 PFC Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2 Half Bridge Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.3 Audio Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Magnetic Components 11

4 PCB and Mechanical Layout 14

5 Construction Notes and Debugging 16

6 Tests and Measurements 186.1 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186.2 Audio Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7 Conclusion 23

8 Appendix: Schematics and PCB Designs 24

9 References 29

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1 Introduction

All amplifiers deliver current to a load from their power supplies. Class-A and Class-AB amplifiers accomplish

this by linear amplification: transistor circuits designed to develop an output voltage proportional to input.

The efficiency of these amplifiers is limited to a theoretical maximum of 78% for sine wave signals because the

output devices (regardless of type or output stage topology) must sustain a voltage drop equal to the power

supply minus output voltage. In practice, audio amplifiers are operated well below their maximum power

capabilities, which lowers the efficiency even more: a 100W class AB amplifier dissipates approximately 12W

to deliver 1W.

Class-D amplifiers accomplish nonlinear amplification by producing a PWM output (switching between

V+ and V-) with the duty cycle tightly regulated by feedback. This method is theoretically lossless, and

in practice delivers much higher efficiency than Class-AB amplifiers at all power levels. However, Class-D

audio amplifiers have delivered limited fidelity - not only because of the large HF carrier wave in the output

signal, but also because it is difficult to control the duty cycle accurately. Most Class-D amplifiers, including

those using standard triangle-wave PWM generation, tend to generate significant high order (4th and higher

harmonics) distortion because of timing errors.

The linear power supplies used to drive amplifiers incur fewer losses, but they must be large and bulky

due to the 60 Hz power transformer and smoothing capacitors. Switching power supplies, which deliver

energy from source to load in short impulses, require much smaller magnetic components because the peak

magnetic flux in the transformer is proportional to cycle time.

This report describes the design, construction and testing of a high-fidelity audio amplifier capable of

60W into 8 and 120W into 4. For this device I designed three separate circuit boards: (1) a 500W

power-factor-correction stage, to smooth the input current drawn from AC mains; (2) a 500W half-bridge

converter, to produce mains-isolated 35V rails from the PFC output; and (3) a self-oscillating Class-D

power amplifier. I discuss the circuit designs, their implementation, and performance below.

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2 Circuit Design

2.1 PFC Stage

The purpose of a power-factor correction (PFC) stage is to ensure that the device draws a sinusoidal current

from the AC mains. Power factor is defined as the ratio of actual load power (in W) to apparent load (in

VA) which is the product of RMS current and RMS voltage. In a typical linear power supply, the rectifier

diodes conduct to the smoothing capacitors during short intervals at the peaks of the AC waveform. The

graph below shows voltage and current waveforms for a nominal 35V DC supply delivering 41W to a 30

load. The input current has peaks of11A and represents 3.1A RMS; the input voltage is 26.5V RMS, for

an apparent load of 82VA. The power factor is 0.5.

Figure 1: Voltage and current waveforms of standard linear power supply

For a power supply drawing 500 watts, these brief currents can be more than 20A from the AC power

lines. This behavior causes a distortion in the mains signal and EMI radiated by mains wiring. A power

supply with an ideal power factor of 1 will, in contrast, draw a sinusoidal current in phase with the mains

voltage. Besides creating less interference from large current peaks, the PFC-input power supply is a less

demanding load for the power company. For these reasons, IEC regulations enforced in Europe and Japan

place limits on the THD of input currents, forcing manufacturers to use some form of PFC in most electronic

devices.

In this amplifier I implemented a PFC stage as a non-isolated boost converter, delivering a nominal 390V

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to the DC-DC converter from an input of 90V to 250V AC. This is a common method, and several varieties of

control ICs are designed to provide the appropriate gate drive for a power switch. I used the NCP1653 chip

from ONSemi with voltage and current feedback; the power switch is an International Rectifier IRFB18N50K

MOSFET. I wound the common mode choke and energy storage inductor; see section 3 for details. The

converter is intended to provide 500W continuous output power at about 92% efficiency.

Figure 2: Concept schematic of PFC stage

The circuit directly rectifies the voltage between AC line and neutral, with no bulk smoothing capacitor.

When the transistor is turned on, current is drawn from the AC mains, building up energy in L3. When

the transistor M1 is turned off, current flows from L3 into the bulk capacitor or the load. The NCP1653

chip varies the duty cycle in phase with the AC waveform. I used a 0.1 current sense resistor to providefeedback, so the chip can compare the input current with AC voltage. A complete schematic of this stage

can be found in the appendix.

2.2 Half Bridge Converter

This circuit accomplishes the task of a standard power supply: converting the high input voltage to the

split power supply rails for the amplifier, and providing isolation from the AC mains. It is implemented as

a 50KHz half-bridge power converter controlled by an ONSemi MC34025 chip. The concept schematic is

shown below.

One end of the transformer primary is connected at the output of a half bridge formed by two IRFB11N50A

MOSFETs. The other end of the primary is connected between two 0.22F capacitors. The capacitors are

large enough to hold this node at approximately half of the input voltage. Therefore, the overall voltage

across the primary switches between +Vin/2 and Vin/2, instead of +Vin and Vin. In comparison to a push-

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Figure 3: Concept schematic of half bridge converter

pull converter, the VDS blocking voltage requirement of the power MOSFETs is halved from 2Vin (800V) to

Vin (400V). This is important because lower-voltage MOSFETs have lower gate charge and RDS(on) (0.52

for the 500V-rated IRFB11N50A versus 3.7 for the 900V-rated IRFBF30). These characteristics reduce

the switching losses in the power devices.

The secondary side of the converter is a typical full-wave rectifier bridge. Note that the capacitance on

each output rail is only 1000F. This would be insufficient for a linear power supply because of the 120Hz

ripple, but these capacitors are charged at the switching frequency of 50KHz. It is very important that the

supply has low output impedance at high frequencies, so I used Panasonic FC-series capacitors which have

low ESR (0.043) and high ripple current capability (2.67A at 100KHz).

I used an optoisolator feedback network in conjunction with the MC34025s error amplifier to regulate

the output to 35V. Part of this network is shown in the figure below, with V1 and V2 representing the

positive and negative rail outputs. The diode side of the optoisolator is connected in series with 35k from

V+ to V-. A resistor on the phototransistor side develops a voltage proportional to the current through U1.

This voltage is connected to the inverting input of the MC34025s error amplifier; the noninverting input isconnected to an internal 5.1V reference. When the two inputs match, the supply is operating at the correct

duty cycle. Therefore

Vout =5.1 35k

AR2

where A is the current gain of the optoisolator. I used a 10k potentiometer for R2 to account for the variation

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in A (in the PS2701-1 optoisolator, A is specified between 0.5 and 3). For A = 1 and Vout = 35V, R2 should

be adjusted to the center position of 5k. Since the output LC filter functions as a 2nd-order lowpass with

a corner frequency of 730Hz, much slower than the switching frequency, no extra compensation was needed

to ensure stability.

Figure 4: Optoisolator feedback network for DC-DC converter

The half-bridge converter needs to accomodate variations in line voltage and load-dependent losses. The

conversion ratio of the buck converter is M(D) = D where D is the duty cycle; this isolated half-bridge

converter also has the step-down factor from the power transformer.

Vout = M(D)Vin =1

NDVin

where N is the turns ratio of the transformer. Given a minimum input voltage from the PFC stage of 320V,

and the 90% maximum duty cycle of the MC34025, I chose a turns ratio of 4:1. At the nominal input of

390V and 70V across the output rails, the duty cycle should be around 72%. I describe the design of the

transformer in more detail in section 3.

2.3 Audio Amplifier

In an effort to explore the possibities for high-fidelity Class-D audio amplification, I designed a circuit based

on the UCD self-oscillating topology proposed by Putzeys in May 2005. This circuit relies on a phase-lead

compensation network to create a consistent oscillation with feedback taken after the amplifiers 2nd-order

output filer.

The most common Class-D amplifier topology compares the input (or error) to a triangle wave, generating

a PWM output signal. The triangle wave must be extremely accurate in order to keep distortion low. Many

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amplifiers built around this topology have been criticized for their poor sound quality in comparison to

Class-AB and Class-A amplifiers, though some have achieved excellent measured performance: LC Audio

of Denmark claims 0.002% at 1W. In any case, this topology has been built in many variations for several

years.

I instead focused my attention on self-oscillating amplifiers, which do not generate a carrier signal. They

are designed to oscillate because of positive feedback at the intended switching frequency: where the output

applied to negative feedback has a 180 degree phase shift. However, it is difficult to use post-filter feedback

in a standard self-oscillating amplifier because the output filter introduces almost 180 degrees of phase

shift. (This is because the corner frequency of the filter, 30-40KHz, is well below the switching frequencies

of 200KHz or higher.) Instead, the feedback is taken from before the LC filter and the loop response is

controlled by extra components in the feedback loop (possibly RC filters).

The concept of the UCD amplifier is shown below. E3 represents the comparator or gain block of the

amplifier, with the transfer function shown: a gain of 2.75 and a propagation delay of 200ns.

Figure 5: Feedback network and output filter for UCD audio amplifier

Putzeys derived that the Class-D power stage can be treated as a DC gain block with gain KDC =

12Hfb (0)

. The output filter and feedback components must be calculated to achieve the desired switching

frequency and gain given the propagation delay of the comparator. These are functions of the loop response

Hloop(s); most importantly, the low-frequency gain is KDC and the switching frequency is the point at which

Hloop(s) = . The transfer function is given by:

Hloop(s) = KDC Hdelay(s) Hfilt(s) Hfb(s)

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Hloop(s) = esTdelay

1

2 RinRin+Rfb

1

1 +sLfiltRload

+ s2LfiltCfilt

Rin

Rin +Rfb (1+sRplCpl)1+s(Rpl+Rfb)Cpl

The estimated propagation delay of the comparator, as simulated by LTSpice, is Tdelay = 200ns. Note

the delay between the transition of the purple and tan curves in Figure 6.

Figure 6: Comparator and gate drive switching waveforms

With the goal of a 400KHz switching frequency and 30KHz output filter cutoff with loads from 4 to

16, I selected the following values for these components:

Rin Rfb Rpl Cpl Lfilt Cfilt

1.6k 7.2k 220 220pF 15uH 1.5uF

Given these component values and a 6 load, the output and loop phase responses should be something

like Figure 7. Note how the blue curve, loop phase response, has a bump caused by the phase-lead network;

and it crosses -180 degrees around 400KHz. The output phase shift is mostly caused by the LC filter.

The amplifier section uses a differential instrumentation amplifier input stage with the AD8620 dual

opamp. It is not enclosed in the feedback loop of the Class-D power stage. The differential gain is set to 5,

or 14dB; and the overall gain of the amplifier is 5 2.75 = 13.75, or 23dB. The comparator is fully discrete,

using a 3mA long-tailed pair as suggested by Putzeys.

Comparator output signals are fed to gate drivers which provide the appropriate charging current to the

IRF540Z power MOSFETs. The schematic of one gate driver is shown below in Figure 8. Each uses two

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Figure 7: Predicted loop and output phase response

101

102

103

104

105

106

210

180

160

120

90

60

30

0

Loop and Overall Phase Response of UCD Amplifier

Frequency (Hz)

Phase

(deg)

BCP53 PNP transistors, one (Q11) to conduct current into the gate at turn-on and one (Q12) to short the

gate to source. The turn-off is designed to be very fast to avoid shoot-through (where both high and low

MOSFETs are on, shorting V+ to V-); the turn-on speed is limited by R19 to approximately 50ns.

Figure 8: Lower gate driver for UCD amplifier

The gate driver circuits are supplied by a 12V linear regulator referenced to V-. I added 15V regulated

supples based on the LM317 and LM337 to power the opamps. A complete schematic of this amplifier can

be found in the appendix.

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3 Magnetic Components

Since inductors and transformers for switching power electronics are not readily available in small quantities,

I decided to wind my own. The PFC stage required a common mode choke and a large energy storage in-

ductor; the half-bridge converter required a power transformer and filter inductors; and the audio amplifier

required a filter inductor. For simplicity I chose toroidal cores for all inductors and E-cores for the trans-

former. The specifications for these devices are shown in the following table.

Component Value Construction Power Handling

Common Mode Filter any Balanced toroidal 4A

Energy Storage Inductor 470H+ Toroidal 2A

Power Transformer 4:1 Turns E-core 500W

Supply Filter Inductors 47H+ Toroidal 7A

Audio Filter Inductor 15H Toroidal 5A

All of the cores were soft ferrites purchased on Ebay. The number of turns of wire on each coil is derived

from the following formula:

L =0rn

2Aclm

=(4 107)(125)(352)(4.84 104)

0.1197= 778H

where n is the number of turns, Ac is the cross sectional area of the core, lm is the magnetic path length

(average circumference), and r is the relative permeability of the core material. (The example values are

from the PFC energy storage inductor. Note the error in the actual measured value below.)

I determined the necessary size of each inductor core by computing the magnetic flux corresponding to

the inductance and maximum current, then dividing by the cross sectional area to find the peak flux density.

This density must be significantly lower than the saturation flux density Bsat of the core material. For

example, for the PFC energy storage inductor:

Bmax =

0rIn

lm =

(4 107)(125)(4)(35)

0.1197 = 0.1837 T

which is less than the saturation flux density, Bsat = 0.235 T, of the material.

The core and construction specifications of the inductors are summarized below. The inductance of the

common mode coil was not critical, only the balancing of the two windings (so that the flux cancels out); so

I wound as many turns of 20-gauge wire as would fit on the core. Inductance measurements were performed

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on a GenRad LCR meter. I checked the audio filter inductor (since its accuracy is important) with an HP

4392A impedance analyzer, with similar results. The coils maintain their inductance up to around 1MHz.

Component r Bsat (gauss) Wire Gauge Turns L (H) DCR ()

Common Mode Filter 125 2350 20 26 71.9 0.043Energy Storage Inductor 125 2350 16 35 581.2 0.068

Power Transformer 2000 4500 18[p]/16[s] 60[p]/15[s] N/A N/A

Supply Filter Inductors 10000 4300 18 2 65.7 0.012

Audio Filter Inductor 125 2350 20 11 15.154 0.084

I wound the power transformer on the matching plastic bobbin with 60 turns of 18-gauge wire for the

primary; a layer of insulating tape; then 15 turns of 16-gauge wire for each of the two secondary windings.

Similar to the inductors, the number of turns are optimized for maximum inductance while avoiding core

saturation at the maximum primary current of 3A.

I tested the transformer to verify that the voltages on the secondary windings were indeed both about 14

of the primary:

Measurement Voltage (AC RMS)

Primary 2.187

Secondary 1 0.562

Secondary 2 0.562

Series secondaries 1.202

Parallel secondaries 0.562

The input-to-output voltage ratio measured here is 3.89 with no load; it will be slightly lower than that

under normal operating conditions. The parallel and series measurements show that secondaries are balanced

and wound in the correct orientation. These ratios were consistent at frequencies up to about 500KHz.

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Figure 9: Power transformer for 500W half-bridge converter, shown from below. The core is 2.18 square.

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4 PCB and Mechanical Layout

The physical implementation of switching electronics presents two challenges: to ensure that the high currents

and rapid rise-times are accomodated by the PCB layout, and to allow adequate heat dissipation in the diodes

and MOSFETs. I designed three double-sided PCBs and an aluminum frame to support the PFC stage,

half-bridge converter, and audio amplifier.

The aluminum frame provides rigid support for the PCBs and heatsinking for the power devices. It

consists of two pieces: a bottom plate 14 wide and 7 deep, and a mounting plate 14 wide and 3 high.

Both pieces are 14 thick. Together they form an asymmetrical T shape supporting the PCBs. All of the

power devices are lined up on one edge of the PCBs and the outside connections (AC, audio input, etc.) are

along the other edge. I milled out a very flat region on the mounting plate to improve heat transfer, and

used Kapton tape as electrical isolation between the power devices and the frame.

Figure 10: Side view showing mechanical arrangement of PCBs.

With one channel of the power amplifier driving 120W into 4, the DC-DC converter must provide an

average current of 2A through each supply rail, and the PFC must draw 1.3A RMS from AC mains. Assuming

that each stage operates at 80% efficiency, the steady-state heat demands placed on each component can be

estimated as follows:

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Component Dissipation

PFC Rectifier Diodes (4) 1.5W

PFC Power Switch 8W

PFC Output Diode 1WSMPS Power Switches (2) 5W

SMPS Rectifier Diodes (4) 2W

Amplifier Power Switches (2) 10W

The total heat dissipation is around 50W, which is reasonable for a bracket of this size and thickness. I

chose not to equip the amplifier with additional heatsinks, especially considering that 120W into 4 is the

worst-case condition and will not be reached consistently.

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5 Construction Notes and Debugging

I attempted to assemble and test the amplifier in several steps, to ensure that each piece worked separately

and avoid unnecessarily damaging components. The audio amplifier section worked as expected without any

modifications; see the next section for measurements. The switching power supply, in contrast, proved more

difficult to test independently because my PFC board is the only readily available source for the half-bridge

converters expected 390V input.

The assembled frame and PCB (without the necessary connections between boards) appears in Figure

11.

Figure 11: Switching amplifier ready for testing.

The PFC stage presented an unusual safety risk during construction because it is not isolated from the

AC mains and produces high voltages (in the 400V range) at the output. Using this circuit required me to

carefully plan zones of circuit ground and mains earth connection. The PFC has a single ground which is

not connected to earth (doing so would alternatively short line and neutral to earth through the rectifier

diodes). The PFC output and ground are connected to the inputs of the half-bridge converter. Mains earth

and all other grounds are connected to the secondary side of the power transformer.

After bringing the PFC stage carefully up to 120V mains using a variac, I found that the output voltage

held at 160V instead of the specified 390V. This means that the power switch never turned on and the

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bulk capacitor was being charged directly through the output diode. Preliminary checks revealed that the

NCP1653 chip was receiving the correct current and voltage feedback, but its gate drive output was disabled;

it may have been damaged in earlier testing. This highlights a peculiar aspect of the boost converter, which

is that the conversion ratio M(D) = 11D is 1 for a duty cycle of zero.

When connected to the output of the PFC stage, the half-bridge converter experienced an unusual failure.

Q6 (the upper power switch) had not been fully secured to the heatsink and heated more quickly than the

other parts. The nylon screw holding Q6 began to melt, and as the plastic softened Q6 moved farther

from the heatsink. This did not destroy Q6, but it did enforce a delay on any further testing because the

transformer must be removed to mount or unmount transistors.

Figure 12: Heatsink attachment failure of Q6 in half-bridge converter

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6 Tests and Measurements

6.1 Power Supplies

After replacing the damaged NCP1653 chip, the PFC board behaved as expected on start-up. The output

was maintained at 427.3V DC, 10% higher than expected. The switching frequency, visible in the gate drive

waveform, was close to 100KHz. I was unable to provide the PFC board with a suitable load (besides the

half-bridge converter) for testing. With no load, when the AC power was switched on the duty cycle was

close to zero - the MOSFET was only turned for very short pulses since no additional energy was required

to maintain the output voltage. I noticed a slight mechanical vibration from the large inductor, which was

not secured to the PCB except by its two leads. With AC power disconnected, the duty cycle increased as

the NCP1653 attempted to compensate for the drooping output.

The half-bridge converter regulates its output voltage by comparing a fraction of the isolated feedback

voltage with an internal reference in the MC34025 chip (see section 2.2). To test the control section, I

connected the output to the isolated 15V outputs of a bench power supply and viewed the gate drive

signals. With the feedback adjustment potentiometer set to a minimum, the gate signals showed a square

wave of approximately 45% duty cycle and period of 44.6s. This is consistent with the 90% overall duty

cycle limit, 50KHz intended switching frequency and the push-pull behavior of the system (each MOSFET is

on half of the time). Then, when adjusting the feedback potentiometer, there was a point at which the duty

cycle fell quickly to zero. This is an indication of sufficient loop gain to regulate the output. The decision

point determining the duty cycle corresponds to the expected steady-state output voltage for any given

amount of feedback.

I tested the combination of PFC stage and half-bridge converter using a light bulb in the AC line for soft

current limiting. I observed output of7V with the input at 31V and the feedback potentiometer set to

minimum (open loop) before the mechanical failure described above. This agrees with the transformer turns

ratio of 4:1 and the 90% maximum duty cycle. (If the supply was totally unregulated, the output voltage

would always remain proportional to the input.) Figure 13 shows the unloaded secondary voltage waveform

at a very low input.

Subsequent testing of the half-bridge converter revealed that a problem in the upper gate drive circuit

prevents the upper MOSFET from ever switching off. When I connected it to the output of the PFC stage,

the NCP1653 engaged its over-current protection. The cause of the problem is shown in Figure 14. Notice

how the upper gate drive switches at the correct times, but never drops below 7.2V (the threshold voltage

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Figure 13: Half-bridge converter voltage before rectification

Vt of the IRF540Z MOSFET is between 2V and 4V). Hence the power switches are both on 45% of the time,

creating an intermittent short-circuit from the input to ground. This explains the over-heating of the upper

MOSFET described above. I went on to test the audio amplifier with a separate linear power supply.

6.2 Audio Amplifier

When connected to a 18V bench supply, the audio amplifier section works almost as expected. I verified

its self-oscillation behavior by measuring the gate drive signals, as well as the pre- and post-filter output

voltages. The gain is a little over 8, or 18dB. The input stage has a very high bandwidth, limited only by

the AD8620s slew rate (50V/s); so the amplifiers frequency response closely follows that of the output

filter, which is a 2nd-order rolloff at 33.5KHz.

A close-up of the output residual (Figure 16) indicates that it is mostly a sine wave with an amplitude

of 230mV RMS.

The amplifier switches at about 280KHz, significantly lower than anticipated. The pre-filter output

waveform is shown below in Figure 17. The output impedance of the 18V bench supply and its connection

leads interacted with the rapidly changing current demands of the amplifier, creating significant voltage

ripple. After the addition of two 0.47F bypass capacitors, the MOSFET gates (Figure 18) and output

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Figure 14: Gate drive waveforms for half-bridge converter with input disconnected.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

x 104

2

0

2

4

6

8

10

12

14

16Upper and Lower Gate Drive Waveforms

Time (sec)

SignalAmplitude(V)

Lower Gate

Upper Gate

Figure 15: Response of amplifier to 1KHz, 1V RMS input.

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 103

15

10

5

0

5

10

15Amplifier Input and Output with 1KHz Input

Time (sec)

SignalAmplitude(V)

switched more cleanly.

Overall, the UCD audio amplifiers performance met my expectations. It appears to oscillate reliably at

a reasonable frequency (though lower than expected) and provide clean output switching. I look forward to

increasing the input stage gain and testing it with the switching power supplies working at 35V. With the

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Figure 16: Amplifier output residual.

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 105

0.4

0.3

0.2

0.1

0

0.1

0.2

0.3

0.4Switching Ripple and Noise on Output

Time (sec)

SignalAmplitude(V)

Figure 17: Output switching with and without bypass capacitors.

0 0.5 1 1.5 2 2.5

x 10

6

25

20

15

10

5

0

5

10

15

20

25Comparison of PreFilter Output with and without Bypass Capacitors

Time (sec)

SignalAmplitude(V)

With Bypass

Without Bypass

current input stage, single-ended input of 3V RMS (slightly higher than usual) would be required to drive

the amplifier to clipping.

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Figure 18: Gate drive waveforms for lower MOSFET (non-floating).

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

x 106

20

18

16

14

12

10

8Lower Gate Drive Waveforms for UCD Amplifier

Time (sec)

SignalAmplitude(V)

Without BypassWith Bypass

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7 Conclusion

Designing switching electronics requires a different technique from linear amplifiers. As opposed to finding a

bias point and linearizing the device characteristics to predict small-signal behavior, I had to understand the

behavior of each circuit in terms of two wildly different states. The primary output control for each stage

of this amplifier, instead of a continuous input voltage such as the audio signal, was a duty cycle describing

the percentage of time the circuit was on. In the half-bridge converter, the duty cycle defines the on-time

of two power MOSFETs, and hence the magnitude of the impulse (in volt-seconds) applied to the primary

of the transformer. This corresponds linearly to the rectified output voltage on the other side. In the audio

amplifier the duty cycle is also directly proportional to filtered output voltage, but the output tracks an

input with 20KHz bandwidth. Finally, the PFC stage (as a boost converter) builds up energy in the large

inductor during the on state and delivers it to the load during the off state.

Controlling the duty cycle remains one of the most difficult tasks in switching electronics. Very complex

circuits have been devised so the circuits can handle a wide range of operating conditions: the PFC stage is

intended to produce 390V DC from 90V to 250V AC at either 50Hz or 60Hz, without any part substitutions.

To take advantage of this flexibility provided by switching circuits and offer several modes of protection,

most forms of duty-cycle control have been implemented as integrated circuits (such as the NCP1653 and

MC34025 I used in my power supplies). Even when using an integrated circuit, proper operation is still

not foolproof. I needed to design and debug the half-bridge converters gate drive and feedback networks -

discrete circuits made specifically for the MC34025s expected mode of operation.

The comparatively simple self-oscillating amplifier allowed me the opportunity to use a high-performance

discrete control circuit. I am impressed by the simplicity and functionality of Putzeys UCD design concept;

the design is straightforward given the transfer function model, and the circuit is capable of excellent audio

quality. I look forward to exploring other applications, such as a differential ampliverter that converts AC

mains voltage directly into audio.

The switching power topologies I used in this project are useful for reducing the power consumption and

heat dissipation of devices that would otherwise have been linear circuits, such as 60 Hz power supplies and

Class-AB amplifiers. More importantly, they are capable of similar performance. By exploring an application

of switched power conversion and Class-D amplification, I have learned a lot about high-power analog circuit

design.

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8 Appendix: Schematics and PCB Designs

Figure 19: Complete schematic of PFC stage

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Figure 20: Complete schematic of DC-DC converter

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Figure 21: Complete schematic of Class-D amplifier stage

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Figure 22: PCB layout of PFC stage

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Figure 23: PCB layout of DC-DC converter

Figure 24: PCB layout of Class-D amplifier stage

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9 References

I consulted many online datasheets and application notes from ON Semiconductor, NEC, and International

Rectifier for the design and construction of this switching amplifier. I used LTSpice for circuit simulation;

schematics and layouts were done in EAGLE.

Chryssis, George, High-frequency Switching Power Supplies: Theory and Design. New York: McGraw-

Hill, 1989.

Hancock, Jon M., Simplifying Power-factor Correction in SMPS. Power Electronics Technology, Octo-

ber 2004. http://powerelectronics.com/mag/410pet21.pdf

Putzeys, Bruno, Simple Self-Oscillating Class D Amplifier With Full Output Filter Control. Audio

Engineering Society (118th Convention), May 28, 2005.

[Multiple contributors], My DIY UCD, online forum discussion started April 14, 2005.

http://www.diyaudio.com/forums/showthread.php?threadid=55385.

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class d com fonte

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