chrec: the new industry/university center for high...
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CHREC: the New Industry/University Center forCHREC: the New Industry/University Center forHighHigh--Performance Reconfigurable ComputingPerformance Reconfigurable Computing
Alan D. George, Ph.D.Alan D. George, Ph.D.Director, NSF CHREC CenterDirector, NSF CHREC Center
Professor of ECE, University of FloridaProfessor of ECE, University of Florida
(on behalf of faculty/staff of CHREC at Florida, GWU, BYU, and V(on behalf of faculty/staff of CHREC at Florida, GWU, BYU, and VT)T)
2008 Non2008 Non--Conventional Computing Conference (NCCC)Conventional Computing Conference (NCCC)
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OutlineOutline
Motivations, challenges, vision
A new national research center
Research activities
Conclusions
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Motivations, Challenges, Vision
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Computing ReformationComputing ReformationEnd of wave (Moore’s Law) riding fclk + ILP (CPU)
Explicit parallelism & multicore the new waveMany promising technologies on new wave
Fixed & reconfigurable multicore device architecturesMany R&D challenges on new wave
Tried & true methods no longer sufficient; complexity aboundsSemantic gap widening between applications & systems
e.g. App developers must now understand & exploit parallelismInherent traits of fixed device architectures
App-specific: inflexible, costly (e.g. ASIC)App-generic: power, cooling, & speed challenges (e.g. Xeon)Many niches between extremes (DSP, Cell, GPU, NP, etc.)
Reconfigurable architectures may offer best of both worldsSpeed, flexibility, power, adaptability, economy of scale, sizeBridging embedded & general-purpose computing, superset of fixed
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What is a Reconfigurable Computer?What is a Reconfigurable Computer?System capable of changing hardware structure to address application demands
Static or dynamic reconfigurationReconfigurable computing, configurable computing, custom computing, adaptive computing, etc.May be mix of conventional fixed & reconfigurable devices (e.g. control-flow CPUs, data-flow FPLDs)
Enabling technology?Field-programmable multicore devicesFPGA et al. (broad & growing space)
Applications?Vast range – computing and embedded worldsFaster, smaller, cheaper, less power & heat, more adaptable and versatile, selectable precision
FPGAECA
FPCAFPOATILEXPPet al.
FPGAECA
FPCAFPOATILEXPPet al.
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Opportunities for RC?Opportunities for RC?
From Satellites to Supercomputers!
From Satellites to Supercomputers!
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When and Where to Apply RC?When and Where to Apply RC?When do we need?
When performance & versatility are criticalHardware gates targeted to application-specific requirementsSystem mission or applications change over time
When the environment is restrictiveLimited power, weight, area, volume, etc.Limited communications bandwidth for work offload
When autonomy and adaptivity are paramountWhere do we need?
In conventional servers, clusters, and supercomputers (HPC)Field-programmable hardware fits many demandsHigh DOP, finer grain, direct dataflow mapping, bit manipulation, selectable precision, direct control over H/W (e.g. perf. vs. power)
In space, air, sea, undersea, and ground systems (HPEC)Embedded & deployable systems can reap many advantages w/ RC
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Challenges @ Many LevelsChallenges @ Many LevelsPerformance prediction
When and where to exploit RC?Performance analysis
How to optimize complex systems and apps?Numerical analysis
Must we throw DP floats at every problem?Programming languages & compilers
How to productively express & achieve parallelism?System services
How to support variety of run-time needs?Portable core libraries
Where cometh building blocks?System architectures
How to scalably feed hungry devices?Device architectures
Broad device types, how track for HPC and HPEC?
PerformancePerformancePredictionPrediction
PerformancePerformanceAnalysisAnalysis
NumericalNumericalAnalysisAnalysis
LanguagesLanguages& Compilers& Compilers
SystemSystemServicesServices
PortablePortableLibrariesLibraries
SystemSystemArchitecturesArchitectures
DeviceDeviceArchitecturesArchitectures
Perfo
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dapta
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A New National Research Center
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What is CHREC?What is CHREC?NSF Center for High-Performance Reconfigurable Computing
Pronounced “shreck” ☺Under development since Q4 of 2004 (LOI to NSF)
Lead institution grant by NSF to Florida awarded on 09/05/06Partner institution grant by NSF to GWU awarded on 12/04/06 BYU and VT became official new partner sites on 12/04/07
CHREC began operations in January 2007CHREC began operations in January 2007Under auspices of I/UCRC Program at NSF
Industry/University Cooperative Research CenterCHREC is supported by both CISE & Engineering Directorates @ NSF
CHREC is both a Center and a Research ConsortiumUniversity groups form the research base (faculty, students)Industry & government organizations are research partners, sponsors, collaborators, and technology-transfer recipients
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Objectives for CHRECObjectives for CHREC
Serve as foremost national research center in this fieldBasis for long-term partnership and collaboration amongst industry, academe, and government; a research consortiumRC: from supercomputers to high-speed embedded systems
Directly support research needs of our Center membersHighly cost-effective manner with pooled, leveraged resources and maximized synergy
Enhance educational experience for a large set of high-quality graduate and undergraduate students
Ideal recruits after graduation for Center members, many US
Advance knowledge and technologies in this fieldCommercial relevance ensured with rapid technology transfer
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Research Interaction
Basic Applied/Development
University Industry
I/U Centers
NSFNSF’’s Model for I/UCRC Centerss Model for I/UCRC Centers
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University of Florida (lead)Dr. Alan D. George, Professor of ECE – Center DirectorDr. Herman Lam, Associate Professor of ECEDr. K. Clint Slatton, Assistant Professor of ECE and CCEDr. Greg Stitt, Assistant Professor of ECEDr. Ann Gordon-Ross, Assistant Professor of ECEDr. Saumil Merchant, Research Scientist in ECE
George Washington University (partner)Dr. Tarek El-Ghazawi, Professor of ECE – GWU Site DirectorDr. Ivan Gonzalez, Research Scientist in ECEDr. Sergio Lopez, Research Scientist in ECE
Brigham Young University (partner)Dr. Brent E. Nelson, Professor of ECE – BYU Site DirectorDr. Michael J. Wirthlin, Associate Professor of ECEDr. Michael Rice, Professor of ECEDr. Brad L. Hutchings, Professor of ECE
Virginia Tech (partner)Dr. Shawn A. Bohner, Associate Professor of CS – VT Site DirectorDr. Peter Athanas, Professor of ECEDr. Wu-Chun Feng, Associate Professor of CS and ECEDr. Francis K.H. Quek, Professor of CS
We also feature a strong team of
dozens of graduate students spanning the four
CHREC sites, many of them US
citizens.
CHREC Faculty CHREC Faculty (17 & growing)(17 & growing)
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1. AFRL Munitions Directorate 2. Altera3. Arctic Region Supercomputing Center 4. Boeing [new]5. Cadence 6. GE Aviation Systems7. Harris Corp. [new]8. Hewlett-Packard 9. Honeywell 10. IBM Research 11. Intel 12. L-3 Communications [new]13. Los Alamos National Laboratory [new]14. Luna Innovations [new]15. NASA Goddard Space Flight Center 16. NASA Langley Research Center 17. NASA Marshall Space Flight Center 18. National Instruments [new]19. National Reconnaissance Office 20. National Security Agency 21. Network Appliance [new]22. Oak Ridge National Laboratory 23. Office of Naval Research 24. Raytheon 25. Rincon Research Corp. [new]26. Rockwell Collins 27. Sandia National Laboratories
27 members with 37 memberships
in 2008
27 members with 37 memberships
in 2008
CHREC MembersCHREC Members
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Membership Fee StructureMembership Fee StructureNSF provides base funds for CHREC via I/UCRC grants
Base grant to each participating university site to defray admin costsIndustry and govt. partners support CHREC through memberships
NOTE: Each membership is associated with ONE universityPartners may hold multiple memberships (supporting multiple students) at one or multiple univ. sites (e.g. NSA, NRO, AFRL/MN, GSFC, MSFC, etc.)
Membership Fee: $35K per annumWhy $35K unit? Base cost of graduate student for one year
Stipend, tuition, and related expenses (IDC is waived, otherwise >$50K)Fee represents tiny fraction of budget (1-2%) & benefits of Center
CHREC budget projected to exceed $3M/yr in 2008Equivalent to >$10M if Center founded in govt. or industry
Each university invests in various costs of CHREC operations25% matching of industry membership contributionsIndirect Costs waived on membership fees (~1.5× multiplier)Matching on administrative personnel costs
More bangfor your buck!
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Center Membership BenefitsCenter Membership BenefitsResearch and collaboration
Selection of project topics that membership resources supportDirect influence over cutting-edge research of prime interestReview of results on semiannual formal basis & continual informal basisRapid transfer of results and IP from projects @ ALL sites of CHREC
Leveraging and synergyHighly leveraged and synergistic pool of funding resourcesCost-effective R&D in today’s budget-tight environment, ideal for ROI
Multi-member collaborationMany benefits between memberse.g. new industrial partnerships & teaming opportunities
PersonnelAccess to strong cadre of faculty, students, post-docs
RecruitmentStrong pool of students with experience on industry & govt. R&D issues
FacilitiesAccess to university research labs with world-class facilities
e.g. RC testbed equipment from Alpha Data, Altera, Celoxica, Cray, DRC, GiDEL, MathStar, Nallatech, SGI, SRC, XDI, Xilinx, et al. plus custom
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CHREC & CHREC & OpenFPGAOpenFPGA
CHREC
ProductionUtilization
OpenFPGACommunity
Research context and support
Technology innovations
Standa
rds an
d Vali
datio
n
Suppo
rt and
Dire
ctionEmerging challenges
Preproduction prototypesDiagram c/o
Dr. Eric Stahlberg
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Education & OutreachEducation & OutreachCHREC is enabling advancements at all its sites
New & updated coursesDegree curricula enhancementsStudent internship connectionsVisiting scholars
Example: new RC courses @ Florida siteNew undergraduate (EEL4930) & graduate (EEL5934) dual-listed courses in RC began in Aug’07
Lectures, lab experiments, research projectsFundamental topicsSpecial topics from research in CHREC
Supported by new RC teaching clusterSponsored by educational grant from Rockwell CollinsCluster of 21 RC workstations each housing Nallatech PCI-X card with Xilinx Virtex-4 LX100 user FPGA (supported by RCI grant)
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ResearchActivities
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2007 CHREC Projects (Florida Site)2007 CHREC Projects (Florida Site)F1F1--0707: Simulative Performance Prediction
Before you invest major $$$ in new systems, software design, & hardware design, better to first predict potential benefits
F2F2--0707: Performance Analysis & ProfilingWithout new concepts and powerful tools to locate and resolve performance bottlenecks, max. speedup is extremely elusive
F3F3--0707: Application Case StudiesRC for HPC or HPEC is relatively new & immature; need to build/share new knowledge with apps & tools from case studies
F4F4--0707: Partial Run-Time ReconfigurationMany potential advantages to be gained in performance, adaptability, power, safety, fault tolerance, security, etc.
F5F5--0707: FPLD Device Architectures & TradeoffsHow to understand and quantify performance, power, et al. advantages of FPLDs vs. competing processing technologies
Performance Prediction
Performance Analysis
Application Case Studies & HLLs
Systems Architecture
Device Architecture
F1
F2
F3
F4
F5
Perfo
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dapta
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,Fau
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, Den
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2007 CHREC Projects (GWU Site)2007 CHREC Projects (GWU Site)G1--0707: SW/HW Partitioning & Co-Scheduling
Algorithms and tools for profiling, partitioning, co-scheduling, and targeting of RC Systems
G4--0707: High-Level Languages ProductivityInsight to understand underlying differences among available tools, guide programmer in choosing correct language, impact future HLL development
G5--0707: Library Portability and Acceleration CoresFramework for portable and reusable library of hardware cores populated with key modules for RC
Initial focus upon case studies in computational biology & medical imaging
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2008 CHREC Projects2008 CHREC ProjectsFlorida Site
F1-08: System-Level Formulation for Alg/Arch ExpAbstraction layer exploring complex alg. & arch. formulations
F2-08: Application Performance AnalysisExtending run-time performance analysis to HLL-based RC apps
F3-08: Case Studies in Multi-FPGA Application DesignNew insight in multi-device apps, extend RAT prediction models
F4-08: Reconfigurable Fault Tolerance & Partial Reconfig.System-level FT, exploiting RTR and PR for dynamic response to rad hazards
F5-08: Device Characterization & Design Space ExplorationExtending studies to broader range of RC devices (FPCA, ECA, TILE, etc.)
George Washington SiteG5-08: Library Portability for HLL Acceleration Cores
Exploring and defining portable interface framework (PFIF)G6-08: Intelligent Deployment of IP Cores
Identify HW tasks, deploy intelligently (grouping, IP interconnect)G7-08: Partial Run-Time Reconfiguration for HPRC
Explore PR for HPC apps to reduce RTR delay, HW virtualization
CPU 3CPU 2CPU 1CPU 0
904MB/s88%
10MB/s1%
812MB/s79%
914MB/s89%
1.79GB/s72%
6MB/s0%
2.50GB/s100%
0MB/s0%
0MB/s0%
FPGA 0 FPGA 1
2.76GB/s69%
CPU 4 CPU 5
1.98GB/s99%
Network
210MB/s10%
FPGA 2
Throughput (MB/s)
Time (sec)
IDLE75%
PHASE 19% PHASE 2
16%
Potential Bottlenecks CPU Interconnect
121MB/s12%
691MB/s67%
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2008 CHREC Projects2008 CHREC ProjectsBYU Site
B1-08: Core Library Framework for HPC/HPECFramework for encapsulating details of reusable circuit cores
B2-08: Heterogeneous Architectures for HPEC RCDevice characterizations with RC/Fixed hybrids (FPGA, Cell, GPU)
B3-08: High-Reliability RC Design Tools and TechniquesDevice-level FT, auto. insertion of SEU mitigation, SEU estimation & detection
B4-08: Reliable RC DSP/Comm SystemsApplication-specific techniques for DSP/communications system design
Virginia Tech SiteV1-08: Model-Based Engineering Framework for HPRC Applications
Adapt model-based design methods for RC, feature SDR for case studiesV2-08: Process-to-Core Mapping for Advanced Architectures
Explore process-to-core mappings for hybrid multicore and RC architectures
Library Standard
Coregen JHDL Vendor1 OpenFPGA…
Libraries
ToolsHLL (Matlab/Fortran) HLL (C/C++/SysC)
32 data3 control
32 data3 control
Processor configuration
FPGAA
FPGAB
FPGAC
SRAM SRAM SRAM
32 data3 control
32 data3 control
Processor configuration
FPGAA
FPGAB
FPGAC
SRAM SRAM SRAM
PlatformIndependent
Models
ComputationIndependent
Models
Platform SpecificModels
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DARPA Studies @ CHRECDARPA Studies @ CHRECResearch roadmaps for app development on FPGA systems
Bridging app/arch semantic gapPrevalent challenge of multi-core
RC to revolutionize DOD missions2 DARPA studies @ CHREC
One at founding sites + ClemsonOne at new sites
Focus areasStudy underlying tools limitations
Theory, practice, technologiesFormulate strategic research paths
Revolutionary, impactfulCraft research roadmaps
Highlight DARPA-hard challenges
I. Formulation
(a) Algorithm design exploration
(b) Architecture design exploration
(c) Performance prediction (speed, area, etc.)
II. Design
(a) Linguistic design semantics and syntax
(b) Graphical design semantics and syntax
(c) Hardware/software codesign
III. Translation
(a) Compilation
(b) Libraries and linkage
(c) Technology mapping (synthesis, place & route)
IV. Execution
(a) Test, debug, and verification
(b) Performance analysis and optimization
(c) Run-time services
• Exploration of a Research Roadmap for Application Development & Execution on FPGA-based Systems
• Future FPGA Design Methodologies and Tool Flows
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Conclusions
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ConclusionsConclusionsRC making inroads in ever-broadening areas
HPC and HPEC; from satellites to supercomputers!
As with any new field, early adopters are brave at heartFace challenges with design methods, tools, apps, systems, etc.Fragmented technologies with gaps and proprietary limitations
Research & technology challenges aboundApplication FDTE, device/system arch., FT, RTR, PR, etc.CHREC sites and partners leading key R&D projects
Industry/university collaboration is critical to meet challengesIncremental, evolutionary advances will not lead to ultimate successResearchers must take more risks, explore & solve tough problemsIndustry & government as partners, catalysts, tech-transfer recipients
FormulationDesign
TranslationExecution
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Y1 Achievements of CHRECY1 Achievements of CHRECAmong best new NSF Centers on record
Cited by NSF as their “model” new I/UCRC centerGrown to >30 academic, industry, and govt. partners in 1 year
“Your Center's feedback is extraordinary. In all my survey research work over the years I have not seen such outstanding feedback.”
NSF Evaluator, Dr. Vida Scarpello, 12/29/07, surveyed CHREC members16 founding members cited net ROI of $2.4M in Y1 [avg $ gain > 4]
Awarded Fundamental Research Supplement by NSF in July ‘07Selected by DARPA for dual studies
Laying foundation to spur revolution in app developmentMany research successes from Y1 projects, such as:
First performance analysis framework & tool for RCRAT model for rapid prediction of RC app performanceVariety of app case studies (LIDAR, MD, SAR, HSI, DDC)Quantitative analyses of HLLs and FPLD devices for RC
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AcknowledgementsAcknowledgements
We express our gratitude for support of CHREC byNational Science Foundation
Program managers & assistants, center evaluator, panel reviewersCHREC Industry and Government Partners
27 members holding 37 memberships in 2008University administrations @ CHREC sites
University of FloridaGeorge Washington UniversityBrigham Young UniversityVirginia Tech
Equipment and tools vendors providing supportAldec, Altera, Celoxica, Cray, DRC, GiDEL, Impulse, Intel, Mellanox, Nallatech, SGI, SRC, Synplicity, Voltaire, XDI, Xilinx
