chittick - ceramic capacitor testing

510 IEEE TRANSACTIONS ON COMPOmm, mBRID$ AND ~UFACXJIUNG TECHNOLOGY, VOL CHMT6, NO. 4, DECEMBER 1983

Nondestructive Screening for Low Voltage Failure in Multilayer Ceramic Capacitors

ROBERT C. CHITTICK, EDMUND GRAY, JOHN H. ALEXANDER, MILES I’. DRAKE, AND ERIC L. BUSH

Absfmct--Low voltage failure in multilayer ceramic capacitors is now generally accepted to be associated with an electrochemical dissolution of electrode materials in a humid environment and subse- quent migration and deposition of material between electrodes of opposite polarity. This migration is particularly related to surface cracks or linked porosity. A novel screening technique for chip capacitors has been developed at Standard Telecommunication Laboratories (STL) that can detect the structural defects that are likely to give rise to low voltage failure. The technique is rapid and nondestructive, and is particularly suited to on-line production testing of chips as well as being suitable for goods inward inspection by the customer. Encapsu- lated capacitors can also be screened and information is then obtained concerning the quality of the encapsulation;

I. INTRODUCTION

L OW VOLTAGE failure of multilayer ceramic capacitors is a phenomenon that has been recognized only in recent

years [l] , [2]. The term is used to describe insulation resistance failure obcurring at a voltage well below the design and test voltage of the capacitor. Two main categories of low voltage can be defined.

1) Low impedance circuit failures which tend to be catastrophic, often resulting in the burn up of the capacitor and sometimes even the circuit board itself.

2) High impedance circuit failures which can be intermittent or permanent.

The permanent failures in the second category can be switched to a high insulation resistance by the application of a voltage somewhat higher than that resulting in the failure.

Some applications, notably in telecommunications and aerospace, seem particularly vulnerable. Failure rates are low but the failures are becoming more apparent as circuit designs change and the number -of multilayer ceramic capacitors in use increases. It is therefore desirable that a nondestructive technique for detecting potential-failures should be developed.

There are a number of approaches to screening currently in use. One is based on the assumption that failed capacitors have some physical defect and that the detection and removal of the defectives will eliminate low voltage failure and generally improve reliability at all voltages. The most comrilonly used techniques of this type are ultrasonic scanning [3] , and crack detection by acoustic emission [4] , both of which are used on chip capacitors. Electrical testing based on discharge tech-

Manuscript received March 15, 1983; revised July 11, 1983. This paper was presented at the 33rd Electronic Components Conference, Orlando, FL, May 16-18,1983.

The authors are with Standard Telecommunication Laboratories, Ltd., London Road, Harlow, Essex, CM17 9NA England.

niques has also been applied to both chips and encapsulated components. Another approach is to s,creen out potential failures by accelerated life testing as typified by the recent MIL C-123 procedure which specifies a test in 85 percent RH, 85°C with 1.5 Vdc applied [:5] . Murata et al. [6] use the same environment but with 1 s 1.5 V pulses. These humidity dependent tests are derived from the work of Sato et al. [7], [8] who describe a test involving th(e measurement of insulation resistance of chip capacitors before and after extended boiling in water. These tests are time-consuming and their use is likely to be limited to quality assessment on a sampling basis.

This paper reports on an ongoing research program, partly U.K. Government funded [lo], to investigate these phenom- ena and to develop a rapid nondestructive test to detect potential failures.

II. FAILURE MECHANISM

The models proposed to explain low voltage failure involve migration of electrode materials along defects such as cracks or voids between the electrode plates which have ad- sorbed films of water or are water filled [7], [8]. The general process of migration involves

l dissolution of the anode material ; l transport of the metal moiety to the cathode in the form

of a simple ion, clsmplex ion, or a colloidal ion (oxide or hydroxide);

l deposition of a conducting dendrite by electroconduc- tion or precipitation.

In the case of Pt, Pd, and Au it is necessary to have com- plexing ions present, in particular Cl-, to allow solution and transport.

Transport of simple silver ions will be by diffusion and field- induced mobility. However that of platinum, palladium, and gold complexes will be by diffusion against the field, hence transport of these negatively charged ions may be greater at low fields. Vgriation of pH values and contamination levels on different ceramic surfaces may also affect the rate of solution and transport.

The physical requirl:ments of such a me’chanism are a structural defect connecting two opposing electrodes and a path to the outside environment. Fig. 1 is a schematic diagram showing some of the defects that are thought to give rise to low voltage failure. Migration of internal electrode materials can occur along a crack, linked porosity, or void surface between opposing electrode plates if moisture is present. It is possible that silver migration can occur, even if the internal electrodes contain no silver themselves, by transport along a

0148-6411/83/1200-0510$01.00 0 IEEE 1984

CHITTICK et&.: NONDESTRUCTIVE SCREENING FOR FAILURE IN CAPACITORS

Crack Void

+ / /-

\ Knit line

fault

Fig. 1. Capacitor chip flaws likely to result in low voltage failure.

knit line fault from an anodic end termination. Linked porosity in the dielectric between an end termination and an opposing electrode can produce the same effect.

In the case of encapsulated capacitors the interelectrode track need not be within the chip but can result from a poorly bonded encapsulant. Moisture can penetrate between the lead wires and encapsulant to the chip surface resulting in migration between the end terminations.

III. AMBIENT LIFE TESTS

Our investigation began in March 1979 with a life test prd- gram that had the objective of generating a number of low voltage failures from lot samples of chip and molded capacitors made by five leading manufacturers. These were tested at 1.5, 3, 4.5, and 6 Vdc with series resistances of 10 ka and 20 kS2 in an uncontrolled ambient environment. The failure detection level was 1 Ma.

After some 32 000 h on test, 29 failures occurred out of a total of 920 capacitors. As a result of this test it was apparent that

1) none of the voltages used produced significantly more failures than the rest;

2) the failure rate increased in periods of high humidity; 3) all the chip failures examined by sectioning showed

cracks or delaminations extending to the surface as shown in Figs. 2 and 3, but it proved extremely dif- ficult to detect the actual site of failure. Very careful sectioning of one of the molded capacitor failures re- vealed a probable site. Fig. 4 is a scanning electron microscopy (SEM) of the suspect region. It can be seen from the contrast that charge is leaking away along the crack in which traces of silver were found by elemental analysis.

IV. ENVIRONMENTAL TESTS

More recently an endurance test program was undertaken with the following objectives:

1) to determine the environmental parameters conducive to low voltage failure;

2) to produce large numbers of failures for electrical and physical examination;

Fig. 2. Crack extending to surface of chip.

Fig. 3. Delamination visible on outside edge of capacitor chip.

Fig. 4. SEM of probable failure site.

3) to test the effectiveness of nondestructive screening techniques.

The environments employed are 85 percent and 97 percent RH at both 85°C and room temperature, and dry 85°C and room temperature. All endurance tests are ongoing, so no de- tailed comparison can be made between the failure rat& in different environments at this time. However it should be said that failures have occurred in all of the humid environments whereas none have occurred in the dry.

In addition to the above environments, moisture resistance tests are being carried out on encapsulated components according to MIL-STD 81OC method 507.1. This type of cyclic temperature and humidity test may be a more realistic ana- logue of some actual circuit environments.

512 IEEE. TRANSACTIONS ON COMPONENTS, HYBRIDS, AND MANUFACTURING TECHNOLOGY, VOL CHMT.6, NO. 4, DECEMBER 1983

V. SCREENING TABLE I 2600 h LIFE TEST ON 100 nF CHIP CAP.4CITORS (97 PERCENT

RH, 85°C) A rapid nondestructive test has been developed that can detect the structural defects that are likely to give rise to low voltage failures [9j. The effectiveness of this test in predicting accelerated low voltage failures is demonstrated in the following sections:

-_-.

Units - - _I_.--..---

Burn-in Methanol screen Life test

The screening test is simple both in conception and imple- mentation. If a structural defect is open to the outside environment and bridges two opposing electrodes, it is possible to effect a temporary increase in electrical conductivity along the ceramic surfaces of the defect by impregnating with a volatile and mobile ionizing solvent, for example, a lower alkyl alcohol. The most convenient and effective material has been found to be methanol and all screening results given below have been obtained using methanol containing less than 0.1 percent water and having a conductivity of about 2 PLS. The following test procedure is a simple manual implementa- tion that has been found suitable for 100 nF, 100 V capacitors.

15 DaSS -<yr,= -<:“,::: 100%

50 “OH X7R 20 Off

-c 2 fail

5 Reject -i

,I0 pas 9 1%

” paSS -3, fail* 19 pass

50 Volt z5Ll --t -3 20 Off 8fail ---(I z:

1 Reject -I

,I0 pass -10 pass 100% I --c 13 pa** 100 Volt X7R 14 Off

1 Reject -i

,9 pass - 9 pass 100%

1) 10 Vdc is applied to the capacitor and the current (I,) is measured after 10 s.

2) The capacitor is preheated to 85’C for 10 min and immersed in methanol at room temperature for a period of 15 min. This immersion time is not critical and can be extended indefinitely. However immersion times of less than one minute can be insufficient to allow methanol penetration in fine cracks or porosity.

3) The capacitor is removed from the methanol, dried on a tissue, and blow-dried with air at room temperature until all traces of methanol have been removed from the ‘surface. The total drying time should be as short as possible and not exceed one minute since the methanol can evaporate from large cracks in a very short time.

rejects or life test failures. The insulation resistance of each capacitor was monitored throughout ‘the test and the failure criterion was set at 500 M.Q. The one failure that was not re- . jetted by screening was tested again after removal from the life test and was found to have developed a flaw during the life test.

The failure characteristics of capacitors in accelerating environments are similar to real time failures, exhibiting both transient and permanent low insulation resistance.

4) Step 1) is repeated immediately after drying and the current (1a) is measured.

A capacitor should be rejected if Z, exceeds I,. In prac- tice, if a significant defect is present, then the current Z, is usually greater than lo-’ A and the ratio lz/I, can be several orders of magnitude. In general, lower value capacitors give higher ratios for similar size defects. It is therefore possible, in the case of low value capacitors and those with a close insulation resistance tolerance, to omit step 1) and use a predeter- mined reference value as the failure criterion.

The technique lends itself easily to automatic testing. We have a small semi-automatic laboratory system capable of screening 2000 capacitors per hour.

Failures occurring in the 97 percent RH 85’C environment are of two types. The first, an example of which is shown in Fig. 5, has only been observed in capacitors with a Z5U dielectric. It is characterized by a gradual degradation of insulation resistance, which is reversible by drying, but is followed, by catastrophic breakdown. It is believed that this type of failure is due to an ionic current in moisture absorbed in a large surface area of linked pores. This is accompanied by den- dritjc growth of electrode materials along the pores, eventually shorting on the anode. Intermittent breakdown can also be seen in this example.

The section of a failed Z5U capacitor in Fig. 6 shows the very porous nature of the dielectric and Fig. 7 shows frit penetration into the dielectric, indicating that the dielectric is in- ‘deed permeable.

VI. CHIP CAPACITORS

Table I lists the results at 2600 hours of a test at 97 percent RH, 85°C on chip capacitors with 4.5 Vdc across the components each with 100 kSZ in series. These capacitors are not representative of typical production lots but have been selected to contain a relatively large number of screen rejects. Be- fore testing, the capacitors were subjected to a 20 h “burn in” at rated volts and 85°C. The “burn in” failures, assessed as a greater than 50 percent drop in insulation resistance, were not subjected to further life testing and are not included as screen

The second type of failure we have observed occurs mainly with the X7R dielectrbc capacitors and does not involve any noticeable degradation of the insulation resistance before complete failure. If the defect causing failure is localized, e.g., a crack, the ionic current will be much lower than that in the previous ‘example.

Fig. 8 shows how the insulation resistance remained at the initial level until a catastrophic failure occurred, followed later by a transient self-healing event. It appears that the ionic current giving rise to dendrite growth is below 5 X 10-l’ A, which is the lowest level ‘measurable on this equipment. Stresses within the capacitor or (current pulses may then burn out small

CHITTICK er al.: NONDESTRUCTIVE SCREENING FOR FAILURE IN CAPACITORS 513

Time on test hours

,0r500 1000 1500 2000 2500 3000 3500 ,

Time on test hours

I0 500 1000 1500 2000 2500 3000 3500

1 I

: 6- a

5-

4

t 10 3L

Fig. 5. Failure characteristics of 100 nF 100 V ZSU in 97 RH, 85°C with a 4.5 Vdc applied.

percent

Fig. 6. Section of 100 nF 100 V ZSU failure showing porosity.

Fig. 7. Sectiop bf 100 !F 100 V ZSU failure showing frit penetration from erid termination.

Fig. 8. Failure characteristics of 100 nF 50 V X7R in 97 percent RH, 85°C with 4.5 Vdc applied.

regions of the dendrite and temporarily return the capacitor to an open circuit condition.

VII. ENCAPSULATED CAPACITORS

Table II lists the results of a test carried out according to the MIL-C-123 test, which specifies 85°C 85 percent RH, 1.5 Vdc applied with a 100 K series resistor to each capacitor, on two lots of resindipped capacitors. The test was extended to 1200 h. Capacitors were screened at both the leaded chip stage and after epoxy dipping. Those included in the life test were specially selected to contain a large number of rejects from chip screening. The results of screening shown in Table II refer to the leaded chip stage. No screen rejects were recorded after encapsulation indicating that the test would be unlikely to detect a defective chip if the encapsulation was mechanically sound.

In this group the capacitors were screened before the “burn- in” and, although it is not claimed that screening will detect normal load test failures, it is worth noting that most of the burn-in failures had been rejected by the chip screening. All burn-in failu.res were withdrawn from the life test at the burn- in stage and are not included as life test failures in Table II.

The final group, details of which are shown in Table III, were subjected to the cyclic MIL-STD-810C Method 507-1, Procedure 1 moisture resistance’test with 1 Vdc applied. The capacitors, which were molded X7R components, were measured at 5 Vdc 24 h after removal from the test environment. Owing to circuit board leakage only currents above 10 nA were considered as a failure condition. The components on this test differ from the previous two groups in that they are from normal bought-in production lots and the chips themselves are of ‘high quality. Two of the lots had a thermoplastic encapsulant, while the remainder had the more usual thermo- setting type. The failures on this test, which were predomi- nantly in the capacitors with the thermoplastic encapsulant, were due to moisture trapped at the ceramic/encapsulant interface through which an ionic current passes between the end terminations giving rise to silver dendrite growth.

Fig. 9 is a section of one of these capacitors viewed in ultra- violet light #showing fluorescent dye penetration to the ce-’ ramic/encapsulant interface revealing the path for moisture in-

514 LEEETRANSACI-IONSON COMPONENTS,HYBRIDS, AND~UA~WJFACTURINGTECHNOI,OGY,VOL CHMT-f$NO. 4,DECEMBER1983

1200 TABLE II

~LIFETEsTON~~~V~~~~FRESIN-DIPPEDCAPACITORS (85 PERCENTRH,85"C)

-

Units

Specially selected X7R

Methanol screen’ Burn-in after at chip stage encapsulation

,48 pass ~---J

Life test

‘0°%

97 Off - / 135 Ilass

Specially selected Z5U

j49 fail ~---+ 4o pass ---(5 f.[i, e 9 Rejects 4

39 pass

g5qo

0 Rejects i 73 Off ‘5 Pass

TABLE III MIL810C LIFETESTONMOLDEDCAPACITORS

Units

Lot 1 thermo- Plastic

Methanol screen Life test

t’ 1 pass

* All capacitors that passed initial methanol screening but failed life test were shown to be methanol failures on rescreening.

gress. The dendritic growth of silver from the cathodic end termination is confirmed by Fig: 10 showing a dendrite on the ceramic surface of a failed capacitor from which the encapsulant has been removed. The four failures that had passed the screening test were found after removal from the test environment to have developed encapsulation defects.

This type of failure may be particularly important in low impedance circuits. Because the dendrite is in close contact with the encapsulant, the heat evolved from burn-out may be

Fig. 9. Flubrescent dye penetration ‘at ceramic surface X7R capacitor. \ in a molded

Fig. 10. Dendritic growth of silver on ceramic surface of 100 nF 100 V X7R molded capacitor that failed MIL-810C test.

directly transferred to the encapsulant which can be carbon- , ized and result in catastrophic burn-up of the capacitor par: titularly when sufficient energy is available from the circuit. The incidence of low circuit impedance failure reported to us has been higher in the 30-40 V range.

VIII. COMPARISONS OF LIFE TESTS ON ENCAPSULATED CAPACITORS

1) Steady-state life test MIL C123, 85 percent, 85°C (extended time). 2) Cyclic life test MIL 810C Method 507.1, Pro- cedure 1.

When encapsulated ceramic capacitors are subjected to the above testing procedures, certain important results emerge. These results tend to reflect the type of fault (if any) en- countered in the encapsulated capacitor, and it is important to identify and understand these effects which, at first sight, may appear to be conflicting.

For example, a defective chip (A) with sound encapsulation may fail an extended time steady-state (MIL C123) test but pass the cyclic test I(MIL SlOC). Conversely, a sound chip (B) badly encapsulated,, may pass an extended time steady-

CHITTICK et al.: NONDESTRUCTIVE SCREENING FOR FAILURE IN CAPACITORS

Defective encapsulation

- Pass

Fig. 11. Comparative life test behavior.

515

state test but fail the cyclic test. A properly encapsulated and sound chip (C) would of course be expected to pass both life tests. Fig. 11 illustrates these facts.

It is proposed that the differing behaviors in the steady- state and cyclic tests may be explained by considering the conditions necessary to achieve a condensed water phase. The previous data presented in Table I demonstrates that perfect chip capacitors, even at 97 percent RH, will not develop den- drites on the outer ceramic surface between end terminations. A defective chip would have been liable to fail under these conditions. It is logical to expect that for an encapsulated capacitor, given sufficient time for moisture to penetrate the encapsulation by molecular diffusion, if a steady high humidity were to exist outside the encapsulant the same high humidity would at equilibrium be achieved within the chip. Although it may be necessary to extend the duration of the MIL Cl23 85 percent RH, 85°C test compared with the bare chip conditions, a capacitor containing a defective chip would eventually be expected to fail.

An encapsulated capacitor containing a perfect chip but whose encapsulant is badly bonded to the ceramic and lead wire would also be expected to pass the steady-state life test for the same reasons as a bare chip. If, however, a “badly” encapsulated capacitor were subjected to a cyclic temperature condition then there may be a sufficient reservoir of moisture within the air space between the encapsulant and the ceramic surface (see Fig. 9) to exceed the dew point as the temperature falls, thus creating a condensed water phase between the end terminations.

IX. CONCLUSION

Based on our work to date, the following conclusions may be drawn concerning low voltage failure of multilayer ceramic capacitors.

1) Low voltage failure can occur provided certain conditions prevail. A defect site must be present in the capacitor such that a path exists between the electrodes of opposite polarity and moisture from the environment is accessible to this path. The site may be either an internal defect in +he chip or a poor bond between the encapsulant and the chip and wire where a path exists at the encapsulant/ceramic interface bridg-

ing the two end terminations (usually made from silver frit). In the case of an encapsulant defect a failure may occur even with a perfect chip. Similarly, in the case of a defective chip, a mechanically perfect encapsulation will not prevent failure.

2) STL life tests have shown that neither capacitor chips nor encapsulated capacitors fail if a low humidity is always maintained.

3) Real time failures tend to occur in periods of high ambient humidity, and accelerated failure rates can be achieved in a high humidity environment. MIL 810C Method 507.1 (Proce- dure 1) cyclic environmental test has been found particularly effective in detecting encapsulation defects. MILC-123 is rec- ommended for encapsulation capacitors and for detecting defective chips within a good unencapsulated (see Fig. 11).

4) STL have developed a critical nondestrucfive screening test which can be applied to detect defects independently in

a> chips b) encapsulation.

The screening is applicable to 100 percent production testing

and, in the case of encapsulated capacitors, would be carried out at both the chip and final capacitor stages.

5) The screening test has shown excellent correlation with MIL 8 1OC for encapsulated units and MIL-C-123 for chips.

6) The screening test when applied to an encapsulated capacitor will not detect a defective chip within a “perfect” encapsulant. Under these circumstances, if the capacitor is not

also tested at the chip stage a potential failure would escape detection.

7) Low voltage life test failures have occurred even on capacitors that passed the screening test. Rescreening after life test on these failed capacitors then indicated the presence of a screening defect. The implications of these data are that the defects actually developed in the capacitors during the life test. The cause of the apparently anomalous behavior may be due to, say, thermal, mechanical, or humidity stresses on a borderline capacitor. This could be particularly important in the case of an encapsulant which is weakly bonded to the ceramic and wire. Soldering of chips onto substrates may also in- troduce defects as a result of the induced stresses.

8) The screening test may be used by the customer to con-

516 IEEE TRANSACTIONS ON COMPONENTS, HYBRIDS, AND MANUFACDJRING TECHNOLOGY, VOL CHMT6, NO. 4, DECEMBER 1983

firm product quality, but in the case of encapsulated units he would be limited to checking encapsulation defects only (see also Sections VI and VII).

9) The incidence of low voltage failure of multilayer ceramic capacitors is very low if the entire volume of the indus- try is considered. Complete elimination of low voltage failure by screening has not yet been achieved, but a major improve- ment in product quality has been achieved.

REFERENCES [I] T. F. Brennan, “Ceramic capacitor insulation resistance failures

accelerated by low voltage,” in Proc. 16th Annu. Reliability Phys- ics Symp., Apr. 1978, pp. 68-74.

[2] A. M. Holladay, “Unstable insulation resistance in ceramic capacitors,” in Proc. Symp. Cap&or Technologies, Applicarions and Reliability, NASA Conf. Pub. 2186, 1981, pp. 27-:31.

r31

r41

ISI

I61

[71

I81

[91 IlO1

P. N. Bradley, “Ultrasonic scanning of multilayer ceramic chip capacitors, ” in Proc. Symp. Capaciror Technologies, Applicarions and Reliability, NASA Conf. Pub. 2186, 1981, pp. 105-I 10. S. J. Vahaviolos, “In-process capacit0.r flaw detection with acoustic emission,” Physical AcousticsCorp., Tech. Rep. TR-19, 1979. Cl. J. Ewe11 and D. A. Demeo, “Electrical parameters of capacitors failing the 85”C/85% RH/1.5 V dc test,” in Proc. 2nd Capacitor and Resistor Technol. Symp., 1982, pp. El-I-El-12. Murata et al., “Low voltage failures of monolithic ceramic capacitors and their screening method,” in Proc. Inr. Symp. for Tesring and Failure Analysis, 1981, pp. 105-l 10. K. Sato er al., “A low voltage screening of ceramic capacitors from leakage failures,” in Proc. Inr. Symp. for Testing and Failure Analysis, 1980, pp. 225-229. -, “Mechanism of ceramic capacitor leakage failures due to low dc stress,” in Proc. 18th Inr. Reliabiliry Physics Symp., 1980, pp. l-8. 1 Worldwide Patents Pending. D of I Contract No. RD/801/8/156.

chittick - ceramic capacitor testing

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