ceramic capacitor technology - tdk electronics...snubber capacitor dc-link capacitor filter...

Ceramic Capacitor TechnologyCeraLink® Opens New Dimensions in Power Electronics

TDK Electronics AGPiezo and Protection Devices Business GroupProduct Marketing PI AE/IE Munich, Germany

July 2020

Ceramic Capacitor Technology CeraLink® © © TDK Electronics AG 2020Product Marketing PI AE/IE 07/20 2

CeraLink in a shot - optimized for conditions under operation in power electronics

Use CeraLink when●Space requirement is tight● Temperature is demanding (+150 °C)● High current rating is vital ● Requirements for capacitance density are tough ● High switching frequencies are applied (SiC, GaN)

Main Application● Snubber capacitor ● DC-Link capacitor● Filter capacitor

CeraLink technology supports ● Increasing capacitance with DC bias and best in class

capacitance density at operating point (Vop + Top)● High current capability due to low losses at high frequencies

(up to several MHz) and high temperatures (up to +150 °C)● No limitation of dV/dt● Good self-regulating properties● Qualification based on AEC-Q200 rev. D

Main Application

Measurement condition Film capacitorClass 2 MLCC CeraLink

Typical capacitance density@ DC link voltage, 20 VRMS, 25°C

0.7 µF/cm³ 2.5 µF/cm³ 4.9 µF/cm³

Typical current rating per capacitance @ 100 kHz, 105°C < 1 A/µF < 4.5 A/µF 12 A/µF

Full Performance Potential

V

C

Vop


CeraLinks Special Behaviour

●Operating temperature up to +150 °C● Low losses at high temperature ● Low leakage current● No thermal runaway

● Generally low self-heating AND self-heating supports CeraLink to come to temperature for good performance

● Optimal frequency in the range of 100 kHz to 1 MHz● Minimal ESR due to low-loss copper electrodes

and HF-suited backend● Typ. ESR @ 25 °C, 1 MHz*: 3-45 mOhm● Typ. ESL*: 2-4 nH● Temperature decrease with rising frequency

At High Temperature At High Frequency

Measurement condition MKP film capacitorBTO Class 2

MLCC CeraLink

Typical capacitance density@ DC link voltage, 20 VRMS, 25 °C

0.7 µF/cm³ 2.5 µF/cm³ 4.9 µF/cm³

Typical current rating per capacitance @ 100 kHz, 105 °C < 1 A/µF < 4.5 A/µF 12 A/µF

Due to low losses at high temperature and high frequency, CeraLink can carry more current under these conditions

* varies with series and voltage class

Technology Insights


PZT – a highly flexible ceramic material class

Piezo actuators Capacitors


CeraLink at a first glance

CeraLinkcapacitors


Technology guideline

Film Capacitor Large MLCC Chips Stacked MLCC CeraLink

• more compact

• higher operating

temperature

• lower ESL

• higher frequency

• SMD

• higher ripple

current ratings

• more compact

/ less footprint

• lower ESL

• more robust

• higher cap-density at Vop

• higher operating temperature

• lower ESL• higher ripple

current ratings

Standard semiconductor technology

Standard semiconductor technology

Enhanced technologies / modular ceramic designs possible /

automotive

High-end and high-temperature applications / fast switching (SiC) / full

ceramic DC-link solutions


MaterialPLZT – an antiferroelectric material

P Dielectric polarization

E Electrical field strength

ε Permittivity

P

E

E

ε

P

E

E

ε

P

E

E

ε

Linear Ferroelectric Antiferroelectric

Nature of electrical polarization Electronic, ionic

Permanent dipoles form ferroelectric domains

Permanent dipoles form antiparallel zones

Material class (Ba,Nd)TiO, typ. NP0, C0G BaTiO3 (BTO), typ. X7R (Pb,La)(Zr,Ti)O3 (PLZT)

Advantages ε constant over electric field and temperature ε up to 10,000 is possibleε increases with field

Disadvantages ε < 100 ε decreases strongly with electrical field ε low at zero bias


High capacitance density at operating condition

●Due to antiferroelectric behavior, the characteristics of CeraLink are strongly non-linear and optimized for conditions under operation in power electronics

● Film capacitors and class 1 ceramics have a dielectric constant (nearly) independent on the electrical field (ε < 100)

● The permittivity of ferroelectric (e.g. X7R) MLCC capacitors is decreasing with electrical field

●CeraLink features an increasing dielectric constant up to the operating voltage

●At higher AC voltage (peaks), the material is able to provide even higher permittivities

DC bias characteristics at room temperature

4000

3000

2000

1,000

0

Die

lect

ric c

onst

ant

Electric field [V/µm]0 2 4 6 8 10 12

Film capacitor

Class 2 MLCC CeraLink

Nominal / rated capacitance 100 % 100 % 100 %

No bias voltage 0.5 VRMS 100% 100 % 35 %

DC link voltage 0.5 VRMS 100 % 35 % 60 %

DC link voltage 20 VRMS 100 % 35 % 100 %DC link (energy)Snubber


CeraLink is ideal for fast switching

Device characteristics lead to a low inductive commutation loop●High capacitance density of 2 to 5 µF/cm³●Low self-inductance (ESL) of 2.5 to 4 nH●High thermal robustness allows CeraLink to be

placed very close to the semi-conductor with operation up to 150 °C permissible

●No limitation of dV/dt


New demands for DC link capacitors

Requirements for a DC link capacitor● High capacitance density● High current density● Low parasitic values (ESR/ESL) for fast switching● Low losses in operation● High operating and peak temperatures ● High cooling efficiency due to high thermal

conductivity● Support of distributed DC link capacitor topologies

with low inductance components (modular design)

Improvements in power density and efficiency were mainly driven by semiconductor technology in the last decade.

Example: principle block picture and size comparison of a motor inverter

“Today the package of a motor inverter is mainly driven by the size of the capacitor, the bus bars, the terminal box and the filter components.”Source: Plikat, Mertens, Koch, Volkswagen AG, Corporate Research, 2013


Ceramic Chip FeaturesDesign for robustness against ceramic cracksMLSC design● Series connection of two MLCC geometries in

one component.

● MLSC design prevents short circuits caused by cracks from mechanical overstress

99

806040

20

10

532

1

Failu

re [%

] Rated voltage500 V

Voltage [V DC]15001000900800700600500400

Breakdown voltage measurementWeibull – 95% CI

Shape 21.62Scale 1331N 30AD 0.175P value >0.250

500 V Chip

zero bias maximum bias

stress in corner area scales with height of chip

MFD design● Chip is segmented in height to reduce piezoelectric stress

between active and inactive area


PackagingRobust interconnection of metallic contacts

Lead frame

10,000 cycles thermal shock test (-55 °C to +150 °C)

● Silver sinter connection between ceramic body and lead frame

● Outer contacts made of CIC (copper invar* copper), to combine high electrical and thermal conductivity with low coefficient of thermal expansion

● All materials are excellent thermal and electrical conductors (lowest thermal and electrical resistance)

● Silver layer prevents cracking of the ceramic in case of mechanical overstress or solder shock open mode!

No crack or damageafter thermal cycles

*Invar: 36Ni-Fe

Ceramic with inner electrodes (Cu)

Ag galvanic layer

Sintered silver layer


Low losses at high temperatures and frequencies

Low dielectric loss at high temperatures Minimal ESR due to low-losscopper electrodes and HF-suited backend

Comparison @ 0.1 VAC, 0 VDC, 25 °CComparison @ 1 VAC, 1 kHz, 400 VDC, 25 °C

1µF

MLCC 1µF

extrapolatedESR @ 100°C,400VDC

Temperature (°C)

Dis

sipa

tion

fact

orta

n δ

[10-

3 ]

Frequency (Hz)

Equi

vale

ntse

ries

resi

stan

ce[Ω

]

100500-50 1500

20

40

60

80 10-0

104

10-1

10-2

10-3105 106 107

BTO = barium titanate oxide = standard MLCC material


Low self-heating and high current capability

Due to low losses at high temperature and high frequency, CeraLink can carry more current under these conditions

Measurement condition MKP film capacitorBTO Class 2

MLCC CeraLink

Typical capacitance density@ DC link voltage, 20 VRMS, 25 °C

0.7 µF/cm³ 2.5 µF/cm³ 4.9 µF/cm³

Typical current rating per capacitance @ 100 kHz, 105 °C < 1 A/µF < 4.5 A/µF 12 A/µF

Comparison @ 400 VDC, 105 °C, 200 kHz Comparison @ 400 VDC, 85 °C, 5 Arms

5

0 0

Tem

pera

ture

incr

ease

[°C

]

Tem

pera

ture

incr

ease

[°C

]

Frequency [kHz]Current [Arms]0 1 2 3 4 5 6 20 40 60 80 120100

10

15

20

25

30

10

20

30

40

50

60

70

Measurements were carried out without active cooling (no forced air flow, no heat sink)


Lifetime at high temperatures –comparison of ceramic capacitors

CeraLink

CeraLink offers highest lifetime and capacitance densitycompared to conventional ceramic capacitors


Low leakage current at high temperatures

CeraLink shows stable and outstanding high isolation properties compared to all existing capacitor technologies●low leakage current at elevated temperatures

even above 150 °C●No thermal runaway observed for CeraLink

ceramic material

Comparison @ 400 VDC

1µF

1µF

Temperature [°C]

ρ[Ω

m]

1013

1012

1011

101020 40 60 80 120100 140 160


CeraLink Product portfolio – modular design

500 V(for 650 V semiconductors)



SP(20 chips)

LPL leads

LPJ leads

Basic element (chip)7.85 mm x 6.84 mm x 2.65 mm

Released

FA(2-10 chips)


Back to Example APrevious slide Next slideBack to Example B

SeriesMaximum voltage ratings

Features650 V 1000 V 1300 V

Low ProfileLP (L /J leads) 1 µF / 500 V 0.5 µF / 700 V 0.25 µF / 900 V

Innovative anti-ferroelectric ceramic material

Use CeraLink when• Temperature is demanding (+150 °C)• High current rating is vital • Requirements for capacitance density

are tough • High switching frequencies are applied

(SiC, GaN)

Qualified based on AEC-Q200 and

Flex AssemblyFA2 / FA3 2/3 µF / 500 V 1/1.5 µF / 700 V

0.5/0.75 µF / 900 V

Flex AssemblyFA10 10 µF / 500 V 5 µF / 700 V 2.5 µF / 900 V

Solder PinSP 20 µF / 500 V 10 µF / 700 V 5 µF / 900 V

V

C

Vop

CeraLink product range

Application Insights


High Voltage Application in xEV

Power Supplies for Medical Equipment Test- & Measurement

Electric Flying Down-hole Power Supplies (Mining)

Traction(SiC)

Application examples Ideal for Demanding Applications

Temper-ature

High Voltage

High Current

Capability

Low Weight

Low SizeCompact Design

Low ESL Robust Design


Application examplesIntegrated servo drive

Electronics integrated into the motor housing (outside of inverter) A lot of space Separated from main temperature driver

Electronics integrated into inverter box Tight space requirements Challenging temperaturesSiC based design Low ESL requirements

Traditional design Integrated servo drive

Temper-ature

Low ESL


CeraLink inside Automotive… some Success Stories

Target Application • OBC• DC/DC• Auxiliary inverters

• HV heater• HV pump• HV compressor

Often chosen due to

Low Weight

Low SizeTemper-

ature

Low ESL Robust Design


CeraLink as DC Link



Flex AssemblyFA10 10 µF / 500 V 5 µF / 700 V 2.5 µF / 900 V The capacitance characteristic and low

ESR of CeraLink avoid a thermal runawaySolder PinSP 20 µF / 500 V 10 µF / 700 V 5 µF / 900 V

Itot

Z4

I4

Z1

I1

Z2

I2

Z3

I3

In parallel connection, higher temperature leads to:

●Lower capacitance

● Higher impedance

● Lowest current through the hottest capacitor self-regulating properties


CeraLink as Snubber 1 per half bridge - mounted close to the semiconductor

Principle Semiconductor Overshoot

0

100

200

300

400

500

600

0 800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 9600

Time in ns

Sem

icon

duct

or S

witc

hing

Vol

tage

in V

0

10

20

30

40

50

60

70

80

90

100

Sem

icon

Col

lect

or C

urre

nt in

A

CeraLink

diV Ldt

= − ⋅Over-voltages or over-shoots occur when switching off a Semiconductor. This will cause an overvoltage according the formula (see left)The low inductance of the CeraLink enables a faster switching of the semiconductor resulting in lower switching losses, enabling a reduction of switching losses of up to 40%!



Low ProfileLP (L /J leads) 1 µF / 500 V 0.5 µF / 700 V 0.25 µF / 900 V

• Low ESL (typ. 3 nH)• Low losses at high frequencies and

high temperatures (up to +150 °C)• No limitation of dV/dtFlex AssemblyFA2 / FA3 2/3 µF / 500 V 1/1.5 µF / 700 V

0.5/0.75 µF / 900 V

Diagramm2

0000

400400400400

800800800800

1200120012001200

1600160016001600

2000200020002000

2400240024002400

2800280028002800

3200320032003200

3600360036003600

4000400040004000

4400440044004400

4800480048004800

5200520052005200

5600560056005600

6000600060006000

6400640064006400

6800680068006800

7200720072007200

7600760076007600

8000800080008000

8400840084008400

8800880088008800

9200920092009200

9600960096009600

10000100001000010000

Current (Ic Conv. Cap.)

Conventional Capacitors

CeraLink

Current (Ic CeraLink)

Time in ns

Semiconductor Switching Voltage in V

Semicon Collector Current in A


60

0

0

60

60

0

0

60

60

0

0

60

60

0

0

60

60

0

0

60

60

0

0

60

60

0

0

60

60

0

0

60

60

0

0

60

60

0

0

60

60

0

0

60

60

10

10

58

55

200

300

30

30

400

410

10

10

550

396

1

3

420

400

0

1

420

400

0

0.5

395

400

0

0

410

400

0

0

400

400

0

0

400

400

0

0

400

400

0

0

400

400

0

0

400

400

0

0

400

400

0

0

400

400

0

Tabelle1

CeraLink0000000000010300410396400400400400400400400400400400400400400400400400400400400400400400400400400400400400400400400400

Conventional Capacitors0000000000010200400550420420395410400400400400400400400400400400400400400400400400400400400400400400400400400400400400

Current (Ic CeraLink)6060606060606060606060583010100000000000000000000000000000000

Current (Ic Conv. Cap.)606060606060606060606060553010310.500000000000000000000000000000

040080012001600200024002800320036004000440048005200560060006400680072007600800084008800920096001000010400108001120011600120006200640066006800700072007400760078008000820084008600880090009200

Tabelle1

Current (Ic Conv. Cap.)

Conventional Capacitors

CeraLink

Current (Ic CeraLink)

Time in ns

Semiconductor Switching Voltage in V

Semicon Collector Current in A


Tabelle2

Tabelle3


CeraLink: Ideal Capacitors for Wide Bandgap Semiconductors

Target Application ●OBC● DC/DC● SiC Power Modules● Auxiliary inverters for xEV

(HV compressor, HV pump, HV heater)● Wireless charging of vehicle

● Suitable for designs of 400 V / 800 V xEV● Increasing capacitance with DC bias

and best in class capacitance density at operating point (Vop + Top)

● Supports miniaturization with low inductive design

High capacitance densityHigh current capability Low ESL (typ. 3 nH) Low losses at high frequencies and high temperatures (up to +150 °C)No limitation in dV/dt

Ideal as snubber or filter cap for SiC and GaN applications

Resulting Advantages

Innovative anti-ferroelectric ceramic material High cooling efficiency due to high thermal conductivityGood self-regulating properties

Unique Feature Qualification based on AECQ-200Manufacturing site in EU (Deutschlandsberg, AT)Quality management system according to IATF 16949:2016Soldering Method: Reflow

Basic Facts

V

C

Vop


SiC based DC/DC ConverterCeraLink as Snubber

Fast Power Electronics with Low Inductive Module Design

●DC/DC SiC power module: 2 phases - 800V, 100A, 130kHz each● Ultra-low inductive commutation loop - inductance in low single-digit range realized with CeraLink LP 900 V 0.25 µF (B58031U9254M062)

Source: Hochschule Landshut

Temper-ature

Low ESL Compact Design


GaN power module with integrated driver and DC-Link capacitor

CeraLink as DC-Link capacitors● Supports miniaturization with low inductive

design

● Supports fast-switching GaNand high switching frequencies

Source: Fraunhofer IZM

● 1x CeraLink LP 500 V, 1 µF low inductive commutation loop ~3nH

● 2x integrated driver for 2x GaN systems 650 V

Compact Design

Low ESL


CeraLink Outlook

CeraLink 2220500 V 250 nF

Capacitance@ 0 V DC, 25 °C 70 nF

Capacitance@ 400 V DC, 25 °C 130 nF

Capacitance@ 400 V DC, large signal, 25 °C

250 nF

Size [l x w x h] 5.7 x 5.0 x 1.4 mm

Capacitance density@ 400 V DC(400 V DC large signal)

3.4 (6.6) µF/cm³

Tmax 150 °C

Irms @ 100 kHz* 4.0 ARMS

* Tamb = 85°C / f = 100 kHz / VDC = 400V / calculated from Irms = 3 A and device temperature after 15 min

●Optimized for capacitance density (MLCC design)

●No stress-relief layer necessary for 1 mm active packet (1.4 mm chip height)

● Termination: Cu cap with Ni/Sn galvanics

And more… especially in the field of material development


Key benefits of CeraLink®

● Effective capacitance increases with rising voltage and leads to high capacitance density

● Low ESL and low inductive connection● Low ESR especially at high frequencies

and high temperatures● High current density ● High operating and peak temperatures

with temperature excursions up to 150 °C● High robustness against high temperatures● Supports fast-switching semiconductors

and high switching frequencies● Supports further miniaturization of power

electronics at the system level

Summary

www.tdk-electronics.tdk.com

Ceramic Capacitor TechnologyCeraLink in a shot - optimized for conditions under operation in power electronicsCeraLinks Special Behaviour Technology Insights�PZT – a highly flexible ceramic material classCeraLink at a first glanceTechnology guidelineMaterial�PLZT – an antiferroelectric materialHigh capacitance density at operating conditionCeraLink is ideal for fast switchingNew demands for DC link capacitorsCeramic Chip Features�Design for robustness against ceramic cracksPackaging�Robust interconnection of metallic contacts Low losses at high temperatures and frequenciesLow self-heating and high current capabilityLifetime at high temperatures – �comparison of ceramic capacitorsLow leakage current at high temperaturesCeraLink Product portfolio – modular designCeraLink product rangeApplication InsightsApplication examples �Ideal for Demanding ApplicationsApplication examples�Integrated servo driveCeraLink inside Automotive�… some Success Stories �CeraLink as DC LinkCeraLink as Snubber �1 per half bridge - mounted close to the semiconductorCeraLink: Ideal Capacitors �for Wide Bandgap SemiconductorsSiC based DC/DC Converter�CeraLink as Snubber GaN power module with integrated driver �and DC-Link capacitor CeraLink OutlookSummaryFoliennummer 31

ceramic capacitor technology - tdk electronics...snubber capacitor dc-link capacitor filter...

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