characterizing your pll-based designs · a phase-locked loop is often used to create the receiver...

PLL-Based Designs Manage System Jitter 1

Sept. 2008

Char. PLL based Designs

Characterizing Your PLL-based Designs To Manage System Jitter

Rob SleighGreg D. Le Cheminant

Agilent Technologies

Copyright © 2008 Agilent Technologies

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Outline

A review of digital communications system receiver architectures

The important role of Phase–locked Loops (PLL) and how they impact jitter performance

Characterizing performance (emphasis on PLL’s)


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Digital receivers need a clock to control the time when the ‘decision’ is made on each incoming bit

DecisionCircuit

Data Input Data Output

Clock Input

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Where does the receiver clock come from?

Clock embedded in the data stream

Clock ‘distributed’ as a lower rate reference clock

Transmitter clock sent directly to the receiver

A Phase-locked Loop is often used to create the receiver clock


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Clock Multiplier PLL converts a Reference Clock to a full-rate System Clock for the Receiver

PhaseDetector VCO

Reference ClockInput

FrequencyDivider

N

Full rate clock used at either the transmitter or the

receiver

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Receiver PLL can derive a clock from the incoming data stream

PhaseDetector VCO

D-Flip Flop



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What is the behavior of the PLL when the input signal has jitter?

)()()()(1

)(gain loop Closed sj

in

out esGsGsA

sA φ

φφ

==+

==

Phase Detector Voltage ControlledOscillator (VCO)Data Input Recovered Clock

PhaseError

Amplifier

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VCO can track the jitter of the incoming signal

The phase detector effectively extracts the jitter from the input data and ‘tunes’ the VCO allowing it to track the jittered input

)()()()(1


in

out esGsGsA

sA φ

φφ

==+

==


PhaseError

Amplifier


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Jitter tracking is frequency dependent

Loop gain A(s) is frequency dependent and generally is large at low frequencies (closed loop gain ~1) and diminishes at high frequencies (closed loop gain approaches 0)

Low frequency jitter is transferred to the clock output and high frequency jitter is not

)()()()(1


in

out esGsGsA

sA φ

φφ

==+

==


PhaseError

Amplifier

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PLL Jitter Transfer Function (JTF) indicates how the jitter on the recovered clock tracks the jitter of the input

)()()()(1


in

out esGsGsA

sA φ

φφ

==+

==

Loop Response and OJTF

0

0.2

0.4

0.6

0.8

1

1.2

1.0E+3 10.0E+3 100.0E+3 1.0E+6 10.0E+6 100.0E+6

Frequency (Hz)

Jitte

r Mul

tiplie

r


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What impact does the JTF have on a receiver and its ability to tolerate jitter?

Allowing jitter to transfer from the data to the receiver clock can be a good thing. This allows the decision circuit to ‘track’ the jittered data and still make decisions in the center of the bit period

DecisionCircuit


Clock Input

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What is the effective jitter from the perspective of the receiver decision circuit?

As the jitter frequency increases, jitter transferred to the recovered clock rolls offJitter tracking at the decision circuit is reduced


0

0.2

0.4

0.6

0.8

1

1.2

1.0E+3 10.0E+3 100.0E+3 1.0E+6 10.0E+6 100.0E+6

Frequency (Hz)

Jitte

r Mul

tiplie

r


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0

0.2

0.4

0.6

0.8

1

1.2

1.0E+3 10.0E+3 100.0E+3 1.0E+6 10.0E+6 100.0E+6

Frequency (Hz)

Jitte

r Mul

tiplie

r

From the receiver’s perspective, the PLL performs a jitter ‘high-pass’

)()(1)(-1OJTF sjesGsG φ−== All the higher frequency jitter on the data stream is observed at the decision circuitJitter observed at the decision circuit is effectively the complement of the PLL jitter transfer functionThe receiver “Observed Jitter Transfer Function”(OJTF) effectively acts like a jitter high-pass filter

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To take advantage of the PLL jitter filtering properties, it is useful to observe jitter in the frequency domain

Mag

nitu

de

Frequency

Offset frequency


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E5052B (SSA : Signal Source Analyzer) provides a wide variety of clock oscillator measurements including the phase noise/jitter spectrum

ComponentEvaluation

Oscillator/PLL Circuit Design

Verification/Test at Operating Conditions

Reference SourcePhase Noise

VCO Phase NoiseAM NoiseTuning Sensitivity

Loop Filter (PLL Response)Phase Noise RF Transient

SpursHarmonics

Microphonic

Phase-hits

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Using the hardware clock recovery system of the 86100C “DCAj” wide-bandwidth sampling oscilloscope

Phase Detector VCO

ADC

Data or Clock Input

Similar to PLL’s discussed earlier, the output of the phase detector is effectively the demodulated jitter of the input. Monitoring this signal with an analog-to-digital converter and transforming the results into the frequency domain provides the jitter spectrum


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Spectral lines indicate periodic jitter elements

Jitter Spectrum

1E-15

10E-15

100E-15

1E-12

10E-12

100E-12

1E-9

10E-9

100E-9

1E-6

1E+3 10E+3 100E+3 1E+6 10E+6 100E+6

Delta Frequency (Hz)

Sec

onds

(rm

s)

Jitter Spectrum / Phase Noise Application Rev 0.5

SSC and its odd harmonics

1 MHz PJ (and harmonics)

Jitter magnitude in seconds rms versus jitter frequency in Hz (log-log scale)

33 kHz1 MHz

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The floor of the signal (without tones) is effectively the spectrum of the random jitter

Jitter Spectrum

1E-15

10E-15

100E-15

1E-12

10E-12

100E-12

1E-9

10E-9

100E-9

1E-6

1E+3 10E+3 100E+3 1E+6 10E+6 100E+6

Delta Frequency (Hz)

Sec

onds

(rm

s)

Jitter Spectrum / Phase Noise Application Rev 0.5


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Measuring the Jitter Transfer (and Observed Jitter Transfer) Functions

Jitter transfer definition:

The amount of jitter at the output of a device compared to the jitter that was on the input of the device

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Pattern Generator

FrequencySynthesizer

(Clock)

SinusoidGenerator

(Jitter modulation)

D.U.T

Jitter receiver (clock recovery)

Clock

Data

(for calibration)

Provide a jittered signal at the DUT input and measure the jitter at the output


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Stimulus: N4903 JBERT (jittered clock or data)

Alternate: Any PG or source that can be modulated with a 33250 function generator (81134, 81142A etc.)

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Stimulus: Jittered Clock sources

OR

N5182A MXG81150A Pulse Function Arbitrary Noise Generator


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Response receiver: 86100C DCAj with 86108 or 83496B

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Examples of device types

Clock recovery circuit

Clock multiplier circuit

Transmitter with ref. clock

Repeater circuit


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Measurement result examples

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86100CU-400 PLL and Jitter Spectrum Measurement Software – controls hardware

- Measure Phase Locked Loop (PLL) Performance and Jitter Spectrum

- PCI-SIG ® Approved for PCI Express 2.0 PLL Compliance Testing

- Automated report generation

Features:

Software:• Automated PLL Bandwidth Testing• Fast, Accurate measurements• Flexible system architecture• Microsoft ® Excel based SW • Free web download www.agilent.com/find/jtf


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Increasing JTF measurement accuracy

What are the main sources of inaccuracy?

Jitter source flatness and repeatability

Jitter receiver flatness and repeatability

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Measurement calibration removes source and receiver unflatness

Since the source and receiver are used in both the input and the output measurements, the system unflatness can be determined with a through calibration

Calibration measurement response =(Jitter source)(cables)(jitter receiver)DUT measurement response =(Jitter source)(cables)(DUT jitter output response)( jitter receiver

Jitter transfer= Jitter output/jitter input =DUT measurement/Cal measurement


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Calibration when input and output rates do not match

If the input to the DUT is at one rate, and the output is another (e.g. clock multiplier) how can a valid calibration be performed?

Example: PCI-Express 5 Gb/s transmitter with a 100 MHz reference clock input

Jitter receiver needs to observe 2 rates, possible source of measurement uncertainty

Solution: Set 86100 receiver at 5 Gb/s. Create 100 MHz reference clock with 25 1’s and 25 0’s pattern from BERT

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What if DUT jitter ‘conflicts’ with jitter stimulus?

If DUT has a significant periodic jitter tone at one of the stimulus frequencies, jitter transfer result could be distorted

Solution: 86100C jitter receiver can observe the DUT un-stimulated jitter spectrum and has the opportunity to adjust stimulus frequencies to avoid a ‘collision’


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Putting the puzzle togetherKnowing both the jitter spectrum and the jitter transfer allows a system level analysis of how jitter is propagating and being controlled in a communications system

The jitter spectrum (left) combined with the JTF/OJTF results with the jitter spectrum as seen by the receiver (right). PLL OJTF performs a jitter high-pass

Measure Jitter Spectrum(from device)

Measure OJTF(e.g. clock recovery PLL)

Predict Observed Jitter Spectrum(seen by receiver)

* =

* =

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Low-jitter components contribute to overall jitter budget, but can be difficult to measure

Examples: VCO and/or divider circuits in PLL’s

Residual jitter of the oscilloscope can be larger than the jitter of the DUT


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New capabilities for analyzing very low jitter circuit elements (clock or data)Residual jitter of sampling scopes hit ~200 fs in 2002 (Agilent 86107A Precision Timebase)

When precision timebase is integrated with sampling channels and the HW clock recovery system, scope jitterfloor is below 60 fs

Allows ultra-low jitter measurements of precision devices

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86108A Precision Waveform Analyzer: A ‘gold standard’ for waveform analysis

New plug-in module for the 86100C DCAj

2 CH at >32 GHz

Low noise, ultra-low jitter (<60fs typical)

Precision waveform measurements

Integrated clock recovery for single connection measurement (no trigger required)

PLL/Jitter Transfer/Jitter Spectrum

~0 trigger to sample delay allows accurate analysis in the presence of SSC


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Conclusions

PLL’s provide opportunities to manage jitter in high-speed serial bus communications

Combining knowledge of the jitter spectrum and the jitter transfer/observed jitter transfer can lead to optimal designs

Test systems available to provide accurate analysis

characterizing your pll-based designs · a phase-locked loop is often used to create the receiver...

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