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Principles of Computer Architecture Miles Murdocca and Vincent Heuring Chapter 6: Datapath and Control. Chapter Contents. 6.1 Basics of the Microarchitecture 6.2 A Microarchitecture for the ARC 6.3 Hardwired Control 6.4 Case Study: The VHDL Hardware Description Language. - PowerPoint PPT PresentationTRANSCRIPT
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6-1 Chapter 6 - Datapath and Control
Department of Information Technology, Radford University ITEC 352 Computer Organization
Principles of Computer ArchitectureMiles Murdocca and Vincent Heuring
Chapter 6: Datapath and Control
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6-2 Chapter 6 - Datapath and Control
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Chapter Contents
6.1 Basics of the Microarchitecture
6.2 A Microarchitecture for the ARC
6.3 Hardwired Control
6.4 Case Study: The VHDL Hardware Description Language
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The Fetch-Execute Cycle
• The steps that the control unit carries out in executing a program are:
(1) Fetch the next instruction to be executed from memory.
(2) Decode the opcode.
(3) Read operand(s) from main memory, if any.
(4) Execute the instruction and store results.
(5) Go to step 1.
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High Level View of Microarchitecture• The microarchitecture consists of the control unit and
the programmer-visible registers, functional units such as the ALU, and any additional registers that may be required by the control unit.
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ARC Instruction Subset
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ARC Instruction Formats
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ARC Datapath
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ARC ALU Operations
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Block Diagram of ALU
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Gate-Level Layout of Barrel Shifter
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Truth Table for (Most of the) ALU LUTs
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Design of Register %r1
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Outputs to Control Unit fromRegister %ir
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Microarch-itecture of the ARC
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Microword Format
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Settings for the COND Field of the Microword
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DECODE Format for Microinstruction Address
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Timing Relationships for the Registers
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Partial ARC
Micro-program
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Partial ARC Microprogram
(cont’)
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Branch Decoding• Decoding tree for
branch instructions shows corresponding microprogram lines:
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Assembled ARC
Microprogram
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Assembled ARC
Microprogram (cont’)
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Example: Add the subcc Instruction• Consider adding instruction subcc (subtract) to the ARC instruction
set. subcc uses the Arithmetic format and op3 = 001100.
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Branch Table• A branch table for trap handlers and interrupt service routines:
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Microprogramming vs. Nanoprogramming
• (a) Micropro-gramming vs. (b) nano-programming.
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Hardware Description Language
• HDL sequence for a resettable modulo 4 counter.
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Circuit Derived from HDL
• Logic design for a modulo 4 counter described in HDL.
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HDL for ARC
• HDL description of the ARC control unit.
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HDL for ARC (cont’)
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HDL ARC Circuit
• The hardwired control section of the ARC: generation of the control signals.
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HDL ARC Circuit (cont’)• Hardwired
control section of the ARC: signals from the data section of the control unit to the datapath.
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Case Study: The VHDL Hardware Description Language
• The majority function. a) truth table, b) AND-OR implementation, c) black box representation.
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VHDL SpecificationInterface specification for the majority component
-- Interfaceentity MAJORITY is port
(A_IN, B_IN, C_IN: in BIT F_OUT: out BIT);
end MAJORITY;Behavioral model for the majority component -- Body
architecture LOGIC_SPEC of MAJORITY isbegin-- compute the output using a Boolean expressionF_OUT <= (not A_IN and B_IN and C_IN) or
(A_IN and not B_IN and C_IN) or(A_IN and B_IN and not C_IN) or(A_IN and B_IN and C_IN) after 4 ns;
end LOGIC_SPEC;
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VHDL Specification (cont’)-- Package declaration, in library WORKpackage LOGIC_GATES iscomponent AND3 port (A, B, C : in BIT; X : out BIT);end component;component OR4 port (A, B, C, D : in BIT; X : out BIT);end component;component NOT1 port (A : in BIT; X : out BIT);end component;-- Interfaceentity MAJORITY is port
(A_IN, B_IN, C_IN: in BITF_OUT: out BIT);
end MAJORITY;
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VHDL Specification (cont’)-- Body-- Uses components declared in package LOGIC_GATES -- in the WORK library-- import all the components in WORK.LOGIC_GATESuse WORK.LOGIC_GATES.all architecture LOGIC_SPEC of MAJORITY is-- declare signals used internally in MAJORITYsignal A_BAR, B_BAR, C_BAR, I1, I2, I3, I4: BIT;begin-- connect the logic gatesNOT_1 : NOT1 port map (A_IN, A_BAR);NOT_2 : NOT1 port map (B_IN, B_BAR);NOT_3 : NOT1 port map (C_IN, C_BAR);AND_1 : AND3 port map (A_BAR, B_IN, C_IN, I1);AND_2 : AND3 port map (A_IN, B_BAR, C_IN, I2);AND_3 : AND3 port map (A_IN, B_IN, C_BAR, I3);AND_4 : AND3 port map (A_IN, B_IN, C_IN, I4);OR_1 : OR3 port map (I1, I2, I3, I4, F_OUT);end LOGIC_SPEC;