chapter 7 memory organisation

8/13/2019 Chapter 7 Memory Organisation

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Chapter 7

Memory Organization

7.1 Memory Hierarchy

The memory unit is an essential components in any digital computer since it is needed for strong progress and data. Most general purpose computer would run more efficiently if they wereequipped with additional storage

device beyond the capacity of main memory.The main memory unit that communicates directlywith CPU is called the MAIN MEMORY . Devices that provide backup storage are calledAUXILARY MEMORY . Most common au iliary devices are magnetic disks and tapes they areused for strong system programs! large data files and other backup information. "nly programsand data currently needed by the processor resides in main memory. #ll other informations arestored in au iliary memory and transferred to the main memory when needed.

The main memory hierarchy system consists of all storage devices employed in a computersystem from the slow but high $capacity au iliary memory to a relatively faster main memory! toan even smaller and faster cache memory accessible to the high%speed processing logic. Memory&ierarchy is to obtain the highest possible access speed while minimi'ing the total cost of thememory system.

Memory Hierarchy in comp ter !y!tem

# very high speed memory is called cache memory used to increase the speed of processing by making current programs and data available to the CPU at rapid rate.The cachememory is employed in the system to compensates the speed differential between main memoryaccess time and processor logic.

7." Main Memory

The main memory is the central storage unit in a computer system. (t is a relatively large and fastmemory used to store programs and data during the computer operations. The principaltechnology used for maim memory is based on semiconductor integrated circuits. (ntegrated


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circuits )#M chips are available in two possible operating modes static and dynamic. The static)#M is easier to use and has shorter read and write cycles.

The dynamic )#M offers reduced power consumption and larger storage capacity in a singlememory chip compared to static )#M.

7.".1 RAM an# ROM Chip!

Most of main memory in a general% purpose computer is made up of )#M integrated circuitchips! but apportion of the memory may be constructed with )"M chips. "riginally )#M wasused to refer the random access memory! but now it used to designate the read*write memory todistinguish it from only read only memory! although )"M is also a random access. )#M is usedfor storing bulk of programs and data that are sub+ect to change. )"M are used to for storing

programs that are permanently resident in the computer and for tables of constants that do notchange in value once the production of computer s completed. #mong other things ! the )"M

portion is used to store the initial programs called a bootstrap loader .This is program whosefunction is used to turn on the computer software operating system. ,ince )#M is volatile its


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content are destroyed when power is turn off on other side the content in )"M remainunchanged either the power is turn off and on again.

7."." Memory A##re!! map!

The designer of computer system must calculate the amount of memory required for particularapplication and assign it to either )#M and )"M. The interconnection between memory and

processor is an established from knowledge of the si'e of memory needed and the type of )#Mand )"M chips available. The addressing of memory can be established by means of a table thatspecifies the memory address to each chip. The table! called a memory address map ! is a

pictorial representation of assigned address space for each chip in the system.

E$amp%e& '1" (yte! RAM an# '1" (yte! ROM

Memory Connection to C)U

-. )#M and )"M chips are connected to a CPU through the data and address buses.. The low%order lines in the address bus select the byte within the chips and other lines in

the address bus select a particular chip through its chip select inputs.


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7.*. A $i%iary Memory

The most common au iliary memory devices used in computer systems are magnetic disks andtapes. "ther components used! but not as frequently! are magnetic drums! magnetic bubblememory! and optical disks. To understand fully the physical mechanism of au iliary memorydevices one must have knowledge of magnetic! electronics and electronics and electromechanicalsystems.

7.*.1 Magnetic +ape!

# magnetic tape transport consists of electrical! mechanical and electronic components to providethe parts and control mechanism for magnetic $ tape unit. The tape itself is a strip of coated withmagnetic recording medium. /its are recorded as magnetic spots on the tape along tracks. Usually!seven or nine bits are recorded simultaneously to from a character together with a parity bit.)ead*write heads are mounted one in each track so that data can be recorded and read as asequence of characters.


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7.*." Magnetic ,i!-!

# magnetic disk is a circular plate constructed of metals or plastic coated with magneti'ed. "ften both sides of disk are used and several disks may be stacked on one spindle with read*write heads

available on each surface. #ll disks rotate together at high speed and are not stopped or started foraccess purposes. /its are stored in magneti'ed surface in spots along concentric circles calledtrack. The tracks are commonly divided into section called sectors. (n most systems! the minimumquality of information! which can be transferred! is a sector.

7.*.* RAI,

RAI, is an acronym first defined by David #. Patterson! 0arth #. 0ibson and )andy 1at' atthe University of California! /erkeley in -234 to describe a Re# n#ant Array o Ine$pen!i/e,i!-! a technology that allowed computer users to achieve high levels of storage reliability fromlow%cost and less reliable PC%class disk%drive components! via the technique of arranging thedevices into arrays for redundancy .More recently! marketers representing industry )#(Dmanufacturers reinvented the term to describe a Re# n#ant Array o In#epen#ent ,i!-! as ameans of disassociating a 5low cost5 e pectation from )#(D technology.


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5)#(D5 is now used as an umbrella term for computer data storage schemes that can divide andreplicate data among multiple hard disk drives. The different ,chemes*architectures are named bythe word )#(D followed by a number! as in )#(D 6! )#(D -! etc. )#(D7s various designs allinvolve two key design goals8 increased data reliability or increased input*output performance.9hen multiple physical disks are set up to use )#(D technology! they are said to be in a RAID

array. This array distributes data across multiple disks! but the array is seen by the computer userand operating system as one single disk. )#(D can be set up to serve several different purposes.

) rpo!e an# (a!ic!& Redundancy is achieved by either writing the same data to multiple drives:known as mirroring ;! or writing e tra data :known as parity data ; across the array! calculatedsuch that the failure of one :or possibly more! depending on the type of )#(D; disks in the arraywill not result in loss of data. # failed disk may be replaced by a new one! and the lost datareconstructed from the remaining data and the parity data. "rgani'ing disks into a redundant arraydecreases the usable storage capacity.


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There are three key concepts in )#(D8 mirroring! the copying of data to more than one disk>striping! the splitting of data across more than one disk> and error correction! where redundantdata is stored to allow problems to be detected and possibly fi ed :known as fault tolerance;.Different )#(D levels use one or more of these techniques! depending on the systemrequirements. )#(D7s main aim can be either to improve reliability and availability of data!

ensuring that important data is available more often than not :e.g. a database of customer orders;!or merely to improve the access speed to files :e.g. for a system that delivers video on demandT? programs to many viewers;.

7.0 A!!ociati/e memory Many data%processing application require the search of items in a table stored in memory. Theestablished way to search a table is to store all items where they can be addressed in a sequence.The search procedure is a strategy for choosing a sequence of addresses! reading the content ofmemory at each address! and comparing the information read with the item being searched untilthe match occurs.

The number of accesses to memory depends on the location of item and efficiency of the searchalgorithm.

The time required to find the item stored in memory can be reduced considerably if stored datacan be identified for access by content of the data itself rather than by an address. # memoryunit accessed by a content is called associative memory or content addressable memory:C#M;.

Compare each word in C#M in parallel with the content of #:#rgument )egister;

% (f C#M 9ord@iA B #! M:i; B -

% )ead sequentially accessing C#M for C#M 9ord:i; for M:i; B -


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% 1:1ey )egister; provides a mask for choosing a particular field or key in the argument in#:only those bits in the argument that have - s in their corresponding position of 1 arecompared;.

Organization o CAM

7.' Cache memory

The cache is a small amount of high%speed memory! usually with a memory cycle timecomparable to the time required by the CPU to fetch one instruction. The cache is usually filledfrom main memory when instructions or data are fetched into the CPU. "ften the main memorywill supply a wider data word to the cache than the CPU requires! to fill the cache more rapidly.The amount of information which is replaces at one time in the cache is called the line size forthe cache. This is normally the width of the data bus between the cache memory and the mainmemory. # wide line si'e for the cache means that several instruction or data words are loadedinto the cache at one time! providing a kind of prefetching for instructions or data. ,ince thecache is small! the effectiveness of the cache relies on the following properties of most programs8

Spatial locality %% most programs are highly sequential> the ne t instruction usually comesfrom the ne t memory location.

Data is usually structured! and data in these structures normally are stored in contiguousmemory locations.


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,hort loops are a common program structure! especially for the innermost sets of nestedloops. This means that the same small set of instructions is used over and over.

0enerally! several operations are performed on the same data values! or variables.

9hen a cache is used! there must be some way in which the memory controller determineswhether the value currently being addressed in memory is available from the cache. There areseveral ways that this can be accomplished. "ne possibility is to store both the address and thevalue from main memory in the cache! with the address stored in a type of memory calledassociative memory or! more descriptively! content addressable memory .

#n associative memory! or content addressable memory! has the property that when a value is presented to the memory! the address of the value is returned if the value is stored in thememory! otherwise an indication that the value is not in the associative memory is returned. Allof the comparisons are done simultaneously! so the search is performed very quickly. This typeof memory is very e pensive! because each memory location must have both a comparator and a

storage element. # cache memory can be implemented with a block of associative memory!together with a block of ordinary77 memory. The associative memory would hold the address ofthe data stored in the cache! and the ordinary memory would contain the data at that address.,uch a cache memory might be configured as shown in


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address! called the tag ! are stored in the cache memory along with the data. one foreach byte and one for the tag. The parity bits are used to check that a single bit error has notoccurred to the data while in the cache. # fourth bit! called the valid bit is used to indicatewhether or not a given location in cache is valid. (n the PDP%--*E6 and in many other processors!the cache is not updated if memory is altered by a device other than the CPU :for e ample whena disk stores new data in memory;. 9hen such a memory operation occurs to a location whichhas its value stored in cache! the valid bit is reset to show that the data is stale77 and does notcorrespond to the data in main memory. #s well! the valid bit is reset when power is first appliedto the processor or when the processor recovers from a power failure! because the data found inthe cache at that time will be invalid. (n the PDP%--*E6! the data path from memory to cache wasthe same si'e :-E bits; as from cache to the CPU. :(n the PDP%--*46! a faster machine! the data

path from the CPU to cache was -E bits! while from memory to cache was G bits which meansthat the cache had effectively prefetched the ne t instruction! appro imately half of the time;.The amount of information :instructions or data; stored with each tag in the cache is called theline size of the cache. :(t is usually the same si'e as the data path from main memory to thecache.; # large line si'e allows the prefetching of a number of instructions or data words. Allitems in a line of the cache are replaced in the cache simultaneously! however! resulting in alarger block of data being replaced for each cache miss.


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,traight forward design %I n entry table in memory! (nefficient storage space utili'ation L%n%m entries of the table is empty

More efficient method is m%entry Page Table. Page Table made of an #ssociative Memorythat is m words> :Page Humber8 /lock Humber;

)age a %t

-. Trap to the ",

. ,ave the user registers and program state

G. Determine that the interrupt was a page fault

F. Check that the page reference was legal and determine the location of the page on the backing store:disk;

=. (ssue a read from the backing store to a free frame

a. 9ait in a queue for this device until serviced

b. 9ait for the device seek and*or latency time

c. /egin the transfer of the page to a free frame

E. 9hile waiting! the CPU may be allocated to some other process

4. (nterrupt from the backing store :(*" completed;

3. ,ave the registers and program state for the other user

1 0 1 Line number

Page no.

Argument register

1 0 1 0 0

0 0 1 1 10 1 0 0 01 0 1 0 11 1 0 1 0

Key register

Associative memory

Page no. Block no.

Virtual address


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2. Determine that the interrupt was from the backing store

-6. Correct the page tables :the desired page is now in memory;

--. 9ait for the CPU to be allocated to this process again

- . )estore the user registers! program state! and new page table! then resume the interruptedinstruction .

)roce!!or architect re !ho %# pro/i#e the a(i%ity to re!tart any in!tr ction a ter a pagea %t.

chapter 7 memory organisation

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