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CHAPTER 5

SWITCH MODE POWER SUPPLIES

5.1 INTRODUCTION

The latest advancements in the consumer electronics market

resulted in producing high quality classy electronic equipment, but

they are compelled to work even in low-voltage power supply systems

(e.g. personal computers, laptops, televisions, CD/DVD players, etc.).

This equipments are sensitive to voltage variations and requires a

regulated dc voltage supply, usually referred to as a ‘switch-mode

power supply’ (SMPS). It is estimated that power electronic loads now

constitute for about 30% of the total demand [54] in the Indian

residential load sector, and it is predicted that their share would

increase tremendously in the times to come. In this chapter the

analysis of the SMPS in relation to the residential load sector is

emphasised, the general conclusions to a large extent are also

applicable to the other load sectors where SMPS category of loads is

prevalent, i.e. commercial load sector. The nature of the operation of

SMPS load marks the nonlinear current waveform being drawn from

the power supply system [54]. This is due to the charging/discharging

of the dc link capacitor (Cdc, Fig 5.1), which is used to reduce (i.e. to

“smooth”) the variations of the bridge rectifier dc voltage output.

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Fig 5.1 General Block diagram of SMPS load

As the SMPS devices are non-linear loads, they are significant

sources of harmonics in modern power supply systems. The

occurrence of harmonics will have negative effects on the operation of

power supply systems, including higher thermal stresses and

overloading of system components (e.g. shortening of the lifetimes of

transformers and cables), or increased neutral conductor currents.

The harmonics may also interact with supply system impedance,

leading to distortions of the supply voltage (e.g. “flat-top” voltage

waveforms). This chapter presents some of the results of the

continuous research work on providing more specific guidance (than

the regular trends) about the harmonic emission characteristics of

modern distribution system loads [55]. Even more precisely, this

chapter considers the SMPS load category; the direct effects of

harmonics on equipment have been studied extensively. The main

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objective of this chapter is to analyze if harmonics in the voltage

supply affect the sensitivity of equipment to the voltage sags.

5.2 CLASSIFICATION AND MODELLING OF SMPS LOADS

5.2.1 Classification of SMPS Loads

Harmonic legislation in [55] stipulates that the electronic loads

with rated active power less than or equal to 75 W do not need to

satisfy any of the prescribed harmonic emission limits. Therefore,

SMPS load category is divided/classified in this chapter into low-

power (≤ 75 W) and high-power (> 75 W) sub-categories (i.e. types) of

SMPS load. The general structure (i.e. circuit topology) of low-power

and high-power SMPS loads are almost similar, with an exception that

low-power SMPS’ will usually not have the power factor correction

(PFC) circuit, Fig 5.1, as they do not have to adhere to prescribed

harmonic limits. High-power SMPS loads will utilise one of the two

general variants of PFC circuits: passive-PFC (p-PFC), or active-PFC

(a-PFC). SMPS with a-PFC use an additional dc-dc converter to shape

input current into a sinusoidal waveform [56]. The devices with p-PFC,

on the other hand, include a relatively large inductor in the current

conduction path. As the inductor opposes the change of current, this

will “smooth” the input current waveform, effectively widening input

current pulses and therefore by reducing its harmonic content. The

SMPS’ with a-PFC use more sophisticated circuits, and inject only a

(very) low-level of harmonics. This assertion is additionally

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strengthened with the fact that p-PFC type of SMPS load is more

common, as it is considerably cheaper to implement [56]. It should

also be noted that as the cost of power electronic circuits falls, the

contribution of a-PFC type of SMPS load increased. In this chapter,

the term “high-power SMPS” refers to SMPS devices with p-PFC and

rated power > 75 W, while term “low-power SMPS” refers to SMPS

devices with no-PFC and rated power 75 W.

5.2.2 Equivalent Circuit Model of SMPS Load

During the steady-state operation, both low and high power

types of SMPS load can be represented by the equivalent circuit given

in Fig 5.2.

Fig 5.2 Equivalent circuit model of SMPS load

In Fig 5.2 Lsys and Rsys represent the system impedance (Zsys), while

RSMPS and LSMPS represent the sum of all resistances and inductances

in the SMPS conduction path. Resistance req is the “equivalent load

resistance”, which represents dc-dc converter and the dc load

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supplied by the SMPS. This equivalent load resistance is defined as

[57]:

rated

dceq P

vr

2

(5.1)

where vdc is the instantaneous value of the dc link voltage and Prated

is the rated power of the modelled SMPS device. Further details on the

implemented equivalent circuit model are given in [57].

5.2.3 Parameters of the Equivalent Circuit SMPS Model

Table 5.1 lists per-unit (p.u) parameters of equivalent circuit

SMPS model (based on the values identified from the actual SMPS

devices), which have been shown to represent generic SMPS load in

[58].

TABLE 5.1: SMPS GENERIC CIRCUIT/MODEL VALUES, [58]

Model Parameter

SMPS type

Low-power High-power

RSMPS [pu] 0.001420.00709

XCdc [pu] 0.0360.036

XLSMPS [pu] -0.0371

Although system impedance is not part of the model, it is used to

represent the power supply system to which SMPS load, together with

the other loads, is connected at the point of common coupling (PCC),

Fig. 5.3. The impedance of the lines/conductors connecting loads to

PCC is assumed to be negligible. The nominal and maximum values of

system impedance used in this work are taken from [58], while

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minimum system impedance value is estimated based on these two

specified values, Table 5.2.

Fig 5.3. Aggregate load connected to low-voltage network

TABLE 5.2 : SYSTEM IMPEDANCE VALUES

Value SystemImpedance [Ω]

Rsys[Ω]

Lsys[mH]

Min Z = 0.12 + j0.11 0.12 0.35Nom Z = 0.25 + j0.23 0.25 0.73Max Z = 0.46 + 0.45 0.46 1.43

5.3 PARAMETER VARIATION

Although the described generic equivalent circuit SMPS model

can be used to represent some important characteristics of the

aggregate SMPS load (e.g. their aggregate active and reactive power

demands, [58]), it does not have the ability to correct the model

harmonic cancellation between the individual SMPS loads.

5.3.1 Resistance RSMPS

The resistance of the SMPS (RSMPS) is dominated by the

resistance of the negative temperature coefficient (NTC) thermistor

used for inrush current protection. Although resistors generally have a

much smaller tolerance range, typically around ±1 %, the range

applied in the analysis is taken as ±20 %, in order to correctly

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represent different types of components and different operating

temperature regions. A uniform distribution is taken for RSMPS to allow

for a more random variance in this parameter. The influence of RSMPS

on harmonic emission of low power SMPS load is small, Fig 5.4, but

still more significant than in case of high-power SMPS’, Fig 5.5. This is

because the large inductor present in high-power SMPS with p-PFC

will dominate the high-power device input impedance.

Fig 5.4 Influence of resistance (RSMPS) on low-power SMPS:

a) Instantaneous current waveformb) Magnitudes/Amplitudes of current harmonics

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Fig 5.5 Influence of resistance (RSMPS) on high-power SMPS:a) Instantaneous current waveformb) Magnitudes/Amplitudes of current harmonics

5.3.2 Capacitance Cdc

The capacitor (Cdc) in SMPS devices must be large enough to

allow SMPS to ride-through a voltage interruption of up to 10ms [59].

However, if the voltage interruption starts just before the Cdc is about

to charge, then a 10ms interruption corresponds to a 20ms

interruption for a fully charged capacitor. A common industrial

practice is to select the value of Cdc to satisfy a hold-up time of 23ms,

which is 20ms hold-up time plus a safety margin, [59]. In order to

calculate the size of Cdc it is necessary to achieve a particular hold-up

time; the rated power of the SMPS and the minimum operational input

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voltage of the dc-dc converter in the SMPS must both be known.

Although the exact value of minimum operating voltage will be

dependent on the specific dc-dc converter, values of around 80 V are

common. Therefore, the selected value of Cdc should be large enough

to maintain dc link voltage greater than 80V. This was simulated

using full circuit SMPS model in [59], where the value of Cdc was

adjusted at each rated power to just satisfy the holdup criteria as

shown in Fig 5.6.

Fig 5.6 Range of typical values of Cdc found in SMPS load

The values of Cdc obtained in simulations with full circuit SMPS

model are compared with the values of Cdc found after the inspection

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of actual SMPS, and with data from manufacturer’s specifications in

Fig 5.5. This allowed specifying a nominal p.u value of Cdc:

puPV

wCX

ratedphase

dcC pudc

036.0)/(

/12,

(5.2)

where Vphase is the rms value of the supply voltage, Prated is the rated

power of the modelled SMPS and ω is the angular frequency of the

supply voltage. The actual values of the capacitors in SMPS circuits

may vary based on their manufacturing tolerance, which is typically

±20% for electrolytic-type capacitors used in low-voltage single-phase

SMPS devices [60].

5.3.3. Inductance LSMPS

The inductance (LSMPS) of the SMPS device is dominated by the

value of the PFC inductor selected to satisfy harmonic legislation

[55],[60]. Accordingly, this model parameter is only present in high-

power SMPS load. To determine the value of LSMPS inductor to satisfy

harmonic legislation, the inductor size was adjusted until the

harmonic limits were just met at each rated power using a detailed

full-circuit SMPS model. This was repeated for the three values of Cdc

identified in the previous section, which were found to have only a

small effect. The minimum value is given by (5.3).

puPV

wLX

ratedphase

SMPSL puSMPS

0315.0/( )

2, (5.3)

It was found that this minimum value was approximately 15% lower

than measured values. This generally agrees with typical inductor

tolerances, usually given as ±10% [13] and ±15% [61].

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5.4. Variations in SMPS Operating Conditions

The rated power of an SMPS device is the maximum power that

the device can safely provide during the normal operation. For the

majority of SMPS applications, however, it is highly unlikely that the

device will continuously provide this power. During the normal

operation, power demand of the SMPS will alter, on the basis of the

actual loading conditions at its dc output(s). It has been found that

the power consumption of a typical low-voltage SMPS (e.g. TV, PC,

monitor etc.) will depend upon the specific operating mode of the

device. Therefore, it is important to consider how loading conditions of

an SMPS device will influence harmonic content of the input current.

The most dominant type of SMPS load in residential and commercial

load sectors are PC’s and monitors. To determine the range of their

loading conditions (Pload), several of these devices were measured

during typical operations [62]. The results of the power drawn, as a

percentage of the device rated power, are shown in Fig 5.7.

Fig.5.7 Measured variations in SMPS power demand.

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During active (i.e. normal) operation, the SMPS is usually loaded at

around 50% of Prated, so nominal value of Pload is taken as 50%. A

normal distribution is taken as Pload is not constant, but is expected to

vary close to nominal.

For both SMPS types, the current pulses will become wider as power

demand of the supplied load increases [62]. As a decrease of loading of

an SMPS device reduces its harmonic emission, this indicates that

they are designed to satisfy harmonic legislation for the operation at

fully rated power.

5.5 DIVERSITY FACTORS AND HARMONIC INJECTIONS

The harmonic cancellation occurs due to phase angle dispersion

between the same-order harmonics produced by different individual

SMPS loads. Diversity factor is the ratio of the vector sum of

magnitudes of individual current harmonics in the considered

aggregate load to their algebraic sum, (5.4). In this work, aggregate

load refers to an aggregation of SMPS load.

The values of the DFh will lie between one and zero, where DFh of one

indicates no harmonic cancellation, while DFh value less than one

indicates harmonic cancellation.

N

n

nh

N

n

nhh IIDF

11

(5.4)

where: nh

nh

nh II is the harmonic current of order h injected by the

nth load, θ is the corresponding harmonic angle and N is the total

number of loads in the aggregate [62]. To determine the diversity

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factors of low and high-power SMPS loads, all model/circuit

parameters were simultaneously varied as previously described using

the Monte Carlo simulation technique to allow for random variations

of selected parameter values.

The results in Table 5.3 show that harmonic cancellation between

individual low-power SMPS loads is not as strong as the cancellation

between individual high-power SMPS’.

For high-power SMPS, the assumed variations in p-PFC

inductor values will have strongest effects among all other circuit

parameters. Additional variations in power demands will further

increase and determine resulting levels of harmonic cancellation in

practical SMPS applications. Calculated diversity factors for a mixed

aggregate of low and high-power SMPS’s are generally between the

diversity factors of same-type aggregates (Table 5.3), but cancellation

of lower order harmonics (3rd-9th) is more pronounced.

TABLE 5.3 Calculated diversity factor values

HarmonicNumber

Diversity Factor

Low-power High-power MixedAggregate

3 0.99763 0.99727 0.90869

5 0.99343 0.98846 0.66516

7 0.98714 0.9264 0.10072

9 0.97878 0.78415 0.77145

11 0.96837 0.85021 0.92453

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Table 5.4 presents the asymptotic values of magnitudes and phase

angles of current harmonics for both considered types of SMPS loads.

TABLE 5.4: Calculated current harmonics magnitudes and phase angles

HarmonicNumber

Low-power SMPS High-power SMPS

Mag.[% of fund.]

Angle[°]

Mag.[% of fund.]

Angle[°]

1 100 -81.9 100 72.2

3 98.33 103.3 76.85 -144.2

5 95.05 -71.4 43.16 -4.7

7 90.31 113.8 15.59 118.6

9 84.29 -61.2 6.79 -160.9

11 77.22 123.7 5.91 -75.4

Using the Monte Carlo method for simulations of different

aggregates of SMPS loads, it was shown that the harmonic

cancellation between high-power SMPS’ is considerably greater than

the harmonic cancellation between low-power SMPS devices. For the

realistic scenarios of mixed-type aggregation of both low and high-

power SMPS devices connected to low-voltage network with typical

system impedance values, it was shown that harmonic cancellation

effects are stronger in case of mixed-type aggregates, and that system

impedance in most of the cases, but not always, will reduce harmonic

emissions.

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5.6 SINGLE PC AS A HARMONIC SOURCE

The Power supply unit of a modern PC consists of input AC/DC

converter with capacitive filtering on DC side. Simplified electrical

scheme is shown in Fig.5.8. Current on AC side is determined with

capacitor charging/discharging and therefore is impulse in nature.

Such a wave shape is far from sinusoidal, so harmonic distortion is

high.

Fig 5.8 Simplified representation of a PC power supply unit.

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The figure 5.9 shows the internal schematic circuit of PC power

supply. The source of a PC is a nonlinear load that introduces many

harmonics. It is clear that this complicated high frequency source will

have a big influence to the power quality.

Fig 5.9 Circuit diagram of PC source practice

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5.6.1 SIMULATION RESULTS

The circuit presented in Fig.5.2 was simulated by using MAT

LAB. Fig. 5.10 and 5.11 shows an effect of non linear load (PC model)

on source voltage and harmonic spectrum respectively. The voltage

harmonics produces the total harmonic distortion (THD) i.e. 73.6%

which will affect more when a large number of PCs are connected. As

the source voltage becomes distorted sinusoidal wave, even harmonics

are present, but their magnitudes are negligible because of low

magnitude. Fig. 5.12 and 5.13 shows source current and harmonic

spectrum respectively. The current harmonics produces the total

harmonic distortion (THD) i.e. 108.53%.

Fig 5.10 Source voltage of pc model

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THDv=73.6%

Fig 5.11 Harmonic spectrum of source voltage of PC model

Fig. 5.12 Source current of PC model

THD=108.53%.

Fig. 5.13 Harmonic spectrum of source current of PC model