chapter 3 cmos(class2)

1

CMOS Digital Integrated

Circuits Analysis and Design

Chapter 3

MOS Transistor

2

The Metal Oxide Semiconductor (MOS) structure

• The structure consists of three layer– The metal gate

electrode– The insulating oxide

(SiO2) layer– The p-type bulk

semiconductor

• The basic properties of the semiconductor

ApA

in

A

i

Np,N

neconcptronandholibriumelecthen equil

n Nncentratio doping co substrateAssume the

npnction law:The mass a

0

2

0

2

n=mobile carrier concentration of electron

P=mobile carrier concentration of hole

3

Energy band diagram of a p-type silicon substrate

4

qx.

bygiven is and level vacuum theand Level

band conduction ebetween th Difference

potential theissilicon ofaffinity Electron

int

ln

ln

) -E(Eqχqφ

k functioned the worce is callo free spal Fermi leve

he ove from tctron to mfor an ele required The energy

n

N

q

kTductor, φpe semiconFor a n-ty

N

n

q

kTductor, φpe semiconFor a p-ty

q

-EEφpotential The Fermi

Fcs

i

DFn

A

iFp

iFF

6

Energy diagram of the combined MOS system

• The equilibrium Fermi levels of the semiconductor (Si) substrate and the metal gate are at the same potential

• The bulk Fermi level is not significantly affected by the bending• The surface Fermi level moves closer to the intrinsic Fermi level

7

Example 1

8

The MOS System under External Bias - accumulation

• A negative voltage VG is applied to the gate electrode.– The holes in the p-type substrate are attracted to the semiconductor-oxide surface– The majority carrier concentration > the equilibrium hole concentration

• The electron concentration (minority carrier) decreases as the negatively charged electron are pushed deeper into the substrate

– The oxide electric field is directed towards the gate electrode– Causing the energy bands bend up-ward near the surface

9

The MOS System under External Bias – depletion

• A small positive gate bias VG is applied to the gate electrode– The oxide electric field will be directed towards the substrate– Causing the energy bands to bend downward near the surface– The majority carrier (hole) will be repelled back into the substrate

• Leaving negatively charged fixed acceptor ions behind (depletion region)

10

FsSiAdA

A

FsSid

Si

dAFs

x

Si

As

Si

A

Sis

A

NqxNqQ

Nqx

xNq

dxxNq

d

dxxNqdQ

xd

dxNqdQ

s

F

d

2

2

2

2

0

Assume that the mobile hole charge in a thin horizontal layer parallel to

the surface isThe change in surface potential

Required to displace this charge

sheet dQ by a distance xd away

from the surface can be found by

using Poisson equationIntegrating along the vertical dimension

gives

Thus, the depth of the depletion region is

And the depletion region charge density is

given by

11

The MOS System under External Bias – inversion• A further increase in the positive gate bias

– Increasing surface potential the downward bending of the energy bands will increase– The mid-gap energy level Ei becomes smaller than the Fermi level EFp on the surface

• The substrate semiconductor in this region become n-type• The electron density is larger than the majority hole density• Inversion layer, surface inversion • Can be utilized for conducting current between two terminal of the MOS transistor

– The surface is said to be inverted• The density of mobile electrons on the surface becomes equal to the density of holes in the bulk

substrate• Requiring the surface potential has the same magnitude, but the reverse polarity, as the bulk Fermi

potential F

• Further increase gate voltage electron concentration but not to an increase of the depletion depth

A

FSidm Nq

x

22

12

The physical structure of a n-channel enhancement-type MOSFET

• MOS structure– polysilicon gate, thin oxide layer, semiconductor

• Source, drain n+-region– The current conducting terminals of the device

• Conducting channel, channel length L, channel width W– The device structure is completely symmetrical with respect to the drain and source

• The simple operation of this device– Controlling the current conduction between the source and the drain, using the electric field

generated by the gate voltage as a control variable

13

Circuit symbols for enhancement-type MOSFET

• Enhancement-mode MOSFET– No conducting region at zero gate bias

• Depletion-mode MOSFET– A conducting channel already exists at zero gate bias

• The abbreviations used for device terminals are– G for the gate, D for the drain, S for the source, and B for the substrate

• The small arrow always marks the source terminal

14

Formation of a depletion region

• For small gate voltage level– The majority carriers (holes) are repelled back into the

substrate– The surface of the p-type substrate is depleted– Current conduction between S and D is not possible

15

Formation of an inversion layer

• As the gate-to-source voltage is further increased– The surface potential reaches -Fp surface inversion will be established conducting

channel between S and D – Allowing current flow, as log as there is a potential difference between S and D– VGS<VT0 (threshold voltage)

• Not sufficient to establish an inversion layer• No current between S and D

– VGS>VT0 (threshold voltage)• Electrons are attracted to the surface

– Contributing to channel current conduction

– Further increase gate voltage• Not affect the surface potential and the depletion region depth

16

The threshold voltage • Four physical components of VT0

– The work function difference between gate and the channel GC= F(substrate)- M for metal gate GC= F(substrate)- F(gate) for polysilicon gate

– The gate voltage component to change the surface potential(to achieve surface inversion) .To change the surface potential by -2F

– The gate voltage component to offset the depletion region charge• -QB/Cox

•

– The voltage component to offset the fixed charge in the gate oxide and in the silicon-oxide interface(due to impurities and/or lattice imperfections at the interface)

• -Qox/Cox

•

ox

oxox

SBFSiAB

tC

VNqQ

22The depletion region charge

Density is given as

17

tcoefficieneffectbodybiassubstrate

C

Nq

VVV

C

Q

C

QV

ox

SiA

FSBFTT

ox

ox

ox

BFGCT

)(

2 e wher

effect)body (with 22

effect)body (no 2

0

00

• Compared with the p-MOSFET

– The substrate Fermi potential F is negative in NMOS, positive in pMOS– The depletion region charge densities QB0 and QB are negative in

nMOS, positive in pMOS– The substrate bias coefficient is positive in nMOS, negative in pMOS– The substrate bias voltage VSB is positive in nMOS, negative in pMOS

• Threshold voltage adjustment

• For n-channel MOS

– Implanting p-type impurity VT increased– Implanting n-type impurity VT decreased– The amount of change in the threshold voltage as a result of extra

implant• qNI/Cox where Ni is the density of implanted impurities

18

19

Example 2

21

Circuit symbols for n-channel depletion-type MOSFETs

• Using selective ion implantation into the channel– The threshold voltage for nMOSFET can be made

negative

– Having a conducting channel at VGS=0

23

Example 3

24

MOSFET operation: linear region• The MOSFET consists

– A MOS capacitor, two pn junction adjacent to the channel– The channel is controlled to the MOS gate

• The carrier (electron in nMOSFET)– Entering through source, controlling by gate, leaving through drain

• To ensure that both p-n junctions are reverse-biased initially– The substrate potential is kept lower than the other three terminal potentials

• When 0<VGS<VT0

– G-S region depleted, G-D region depleted– No current flow

• When VGS>VT0

– Conduction channel formed– Capable of carrying the drain current– As VDS=0

• ID=0– As VDS>0 and small

• ID proportional to VDS

• Flowing from S to D through the conducting channel• The channel act as a voltage controlled resistor• The electron velocity much lower than the drift velocity limit• As VDSthe inversion layer charge and the channel depth at the drain end start to

decrease

25

MOSFET operation: saturation region

• For VDS=VDSAT

– The inversion charge at the drain is reduced to zero

– Pinch off point

• For VDS>VDSAT

– A depleted surface region forms adjacent to the drain

– As further increases VDS this depletion region grows toward the source

– The channel-end voltage remains essentially constant and equal to VDSAT

– The pinch-off (depleted) section• Absorbs most of the excess voltage drop,

VDS-VDSAT • A high-field region forms between the

channel-end and the drain boundary– Accelerating electrons, usually reaching

the drift velocity limit

26

MOSFET current-voltage characteristics-gradual channel approximation (GCA)(1)• Considering linear mode operation

– VS=VB=0, the VGS and VDS are the external parameters controlling the drain current ID

– VGS > VT0 (assume constant through the channel) to create a conducting inversion layer– Defining

• X-direction: perpendicular to the surface, pointing down into the substrate• Y-direction: parallel to the surface

– The y=0 is at the source end of the channel– Channel voltage with respect to the source, Vc(y)

– Assume the electric field Ey is dominant compared with Ex• This assumption reduced the current flow in the channel to the y-direction only

– Let QI(y) be the total mobile electron charge in the surface inversion layer• QI(y)=-Cox[VGS-Vc(y)-VT0]

28

MOSFET current-voltage characteristics-gradual channel approximation (GCA)(2)

L

Wk where kVVVV

kI

Cμ where kVVVVL

WkI

VVVVL

WCI

dVVVVCWLI

dVyQWdyI

dy(y)QμW

I-dRIdV

yisdropalongdThevoltage

μ

Q(y)QμW

dydR

cesislincrementa

Theμ

'DSDSTGSD

oxn'

DSDSTGSD

DSDSTGSoxn

D

V

CTCGSoxnD

V

CI

L

D

In

DDC

n

IIn

n

DS

DS

20

20

'

20

0 0

0n0

22

22

22

)(

mobilityelectron bulk theof that of half-oneabout typicallyis magnitude its and

region, channel theofion concentrat doping on the dependents mobility surfaceelectron The

) chargelayer inversion theofpolarity negative the todue issign (mimus

tanRe

mobility surfaceconstant a haslayer inversion in the electrons mobile all that Assumeing

29

Example 4

30

MOSFET current-voltage characteristics-gradual channel approximation (GCA)-saturation region

• For VDSVDSAT=VGS-VT0

–

– The drain current becomes a function only of VGS, beyond the saturation boundary

20

2

000)(

2

22

TGSoxn

TGSTGSTGSoxn

satD

VVL

WC

VVVVVVL

WCI

31

Channel length modulation

DSTGSoxn

D(sat)

DS

DS

DSATDS

TGSoxn

D(sat)

TGS'oxn

D(sat)

I

'

I

TGSDSATDS

DSTGSoxI

TGSoxI

λV VVL

WCμ I

λλ

, λ VλL

ΔL

VVΔL

VVL

WCμ

LΔL

I

VVL

WCμI

Q Δ

L-ΔL

L)(yQ

-VVV, V

V-VV-CL)(yQ

-VV-C)(yQ

12

1 thatAssuming

tcoefficien modulationlength channel 11use We

21

1

2

0thsegment wi channel theoflength theis Lwhere

L

length channel effective The

0

small very become enddrain at the chargelayer inversion The

saturation of edge at the that Note

is channel theof enddrain at the chargelayer inversion theand

0

is channel theof end source at the chargelayer inversion The

20

20

20

0

0

0

32

Substrate bias effect• The discussion in the previous has been done under the assumption

– The substrate potential is equal to the source potential, i.e. VSB=0• On the other hand

– the source potential of an nMOS transistor can be larger than the substrate potential, i.e. VSB>0

–

DSSBTGSoxn

satD

DSDSSBTGSoxn

linD

FSBFTSBT

VVVVL

WCI

VVVVVL

WCI

VVVV

1)(2

)(22

22)(

2)(

2)(

0

33

Current-voltage equation of n-, p-channel MOSFET

TGSDS

TGSDSTGSoxp

satD

TGSDS

TGSDSDSTGSoxp

linD

TGSD

TGSDS

TGSDSTGSoxn

satD

TGSDS

TGSDSDSTGSoxn

linD

TGSD

-VVV

VVVVVL

WCI

-VVV

VVVVVVL

WCI

VVI

-VVV

VVVVVL

WCI

-VVV

VVVVVVL

WCI

VVI

and

for 12

and

for 22

for ,0

MOSFET channel-pFor

and

for 12

and

for 22

for ,0

MOSFET channel-nFor

2)(

2)(

2)(

2)(

34

Measurement of parameters- kn, VT0, and

• The VSB is set at a constant value– The drain current is measured for different values of VGS

– VDG=0 • VDS>VGS-VT is always satisfied saturation mode

• Neglecting the channel length modulation effect–

– Obtaining the parameters kn, VT0, and –

02

0)( 2,

2 TGSn

DTGSn

satD VVk

IVVk

I

FSBF

TSBT

V

VVV

22

)( 0

36

Measurement of parameters- • The voltage VGS is set to VT0+1

• The voltage VDS is chosen sufficiently large (VDS>VGS-VT0) that the transistor operates in the saturation mode, VDS1, VDS2 – ID(sat)=(kn/2)(VGS-VT0)2(1+VDS)

• Since VGS=VT0+1 ID2/ID1=(1+VDS2)/ (1+VDS1)

• Which can be used to calculate the channel length modulation coefficient • This is in fact equivalent to calculating the slope of the drain current versus drain voltage curve in the saturation

region– The slope is kn/2

38

Example 5

39

MOSFET scaling and small-geometry effects• High density chip

– The sizes of the transistors are as small as possible– The operational characteristics of MOS transistor will change with the reduction of its

dimensions• There are two basic types of size-reduction strategies

– Full scaling (constant-field scaling)– Constant-voltage scaling

• A new generation of manufacturing technology replaces the previous one about – every two or three years– The down-scaling factor S about 1.2 to1.5

• The scaling of all dimensions by a factor of S>1 leads to the reduction of the area occupied by the transistor by a factor of S2

40

Full scaling (constant-field scaling)

sresistance abd escapacitanc parasitic variousofreduction A

improved down time-charge and up,-charge the offactor aby down scaled is

unchanged virtuallyremaining areaunit per The

scaling full of features attractivemost theof one isn dissipatiopower theofreduction t significan The

1

ndissipatiopower The

1

22

currentdrain mode saturation The

21

2

22

currentdrain modelinear The

offactor aby scaled also will the unchanged ratioaspect The

C

areaunit per ecapacitanc oxide gate The

density doping scaled by the affectedtly significannot is mobility surface theAssuming

factor scaling same by the ally,proportiondown scaled bemust potentials all goal, thisachieve To

22

2

2

2

22

2

''ox

SC

itypower dens

S

PVI

SVI P

S

IVV

S

kSVV

k(sat) I

S

IVVVV

S

kS

VVVVk

(lin) I

SkW/L

CSt

St

μ

g

DSD'DS

'D

'

D(sat)TGS

n'T

'GS

'n'

D

D(lin)DSDSTGS

n

'DS

'DS

'T

'GS

'n'

D

n

oxox

ox

ox

ox

n

43

Constant-voltage scaling

stress-over electrical and breakdown, oxide n,degradatiocarrier hot ration,electromig

densitypower density,current increasing Disadv.

s.constraint level- voltageexternal theof because

cases practicalmamy in scaling fullover preferred bemay scaling voltage-constant ,summarized To

offactor aby incresaeddensity power The

ndissipatiopower The

offactor aby increaseddensity current drain The

22

currentdrain mode saturation The

22

22

currentdrain modelinear The

by increased also isparameter uctance transcondThe

offactor aby increased is areaunit per ecapacitanc oxide gate The

relations field-charge thepreserve order toin offactor aby increased bemust densities doping The

unchanged. remained voltages terminal theand tagesupply volpower The

.offactor aby reduced MOSFETare theof dimensions All

3

3

22

2

2

2

S

PSV)I(SVI P

S

(sat)ISVVkS

VVk

(sat)I

(lin)ISVVVVkS

VVVVk

(lin) I

S

SC

S

S

DSD'DS

'D

'

DTGSn'

T'

GS

'n'

D

DDSDSTGSn

'DS

'DS

'T

'GS

'n'

D

ox

45

Short-channel effects

• A MOS transistor is called a short-channel device– If its channel length is on the same order of magnitude as

the depletion region thickness of the S and D junction– The effective channel length Leff S, D junction depth xj

– Two physical phenomena arise from short-channel effects• The limitations imposed on electron drift characteristics in the

channel– The lateral electric field Ey increased, vd reached saturation velocity–

» No longer a quadratic function of VGS, virtually independent of the channel length

DSAToxsatd

L

IsatdsatdsatD VCvWQvWdxxnqvWIeff )(0 )()()( )(

46

TGS

no

cGSSiox

ox

nonon VVyVV

tEx

eff

1)(11

)(

The carrier velocity in the channel is also a function of Ex Influence the scattering of carriers in the surface

The modification of the threshold voltage due to the shortening channel length

47

Short-channel effects-modification of VT

• The n+ drain and source diffusion regions in p-type substrate induce a significant amount of depletion charge

– The long channel VT, overetimates the depletion charge support by the gate voltage

– The bulk depletion region asymmetric trapezoidal shape• A significant portion of the total depletion region charge is due the S and D junction

depletion

12

112

12

221

12

1

12

12

022

ln22

222

1

ΔV-V

0

222

222

222

2000

0

T0T00

j

dS

j

dDjFASi

oxT

j

dSjS

j

dDjdDjdDdmjjD

dDjdDdmDjD

DjdmdDj

i

ADDS

A

SidD

A

SidS

FASiDS

B

T

x

x

x

x

L

xφNεq

CΔV

x

xxΔL

x

xxxxxxxxΔL

xxxxΔLxΔL

ΔLxxxx

n

NN

q

kT, φVφ

Nq

ε, xφ

Nq

εx

φNεqL

ΔLΔLQ

nnel)(short chaV

50

12

112

12

221

12

1

12

12

,022

ln22

Re,222

1

)(arg,ΔV-V

0

222

222

222

2000

0

T0T00

j

dS

j

dDjFASi

oxT

j

dSjS

j

dDjdDjdDdmjjD

DdDjdDdmDjD

DjdmdDj

i

ADDS

A

SidD

A

SidS

FASiDS

B

T

x

x

x

x

L

xφNεq

CΔV

x

xxΔL

x

xxxxxxxxΔL

ΔLSolvingForxxxxΔLxΔL

ΔLxxxx

n

NN

q

kT, φVφ

Nq

ε, xφ

Nq

εx

gionDepthpletionjunctionDeφNεqL

ΔLΔLQ

lregiontrapizoidaeegionchDepletionrnnel)(short chaV

51

Example 6 (1)

52

Example 6 (2)

53

Example 6 (3)

54

Narrow-channel effect

• Channel width W on the same order of magnitude as the maximum depletion region thickness xdm

• The actual threshold voltage of such device is larger than that predicted by the conventional threshold voltage

• Fringe depletion region under field oxide–

arcscircular -quarterby modeledregion depletion for 2

221

V

VVchannel) narrow(

T0

T0T00

W

xNq

C

V

dmFASi

ox

T

55

Other limitations imposed by small-device geometries• The current flow in the channel are controlled by two dimensional electric field vector• Subthreshold conduction

– Drain-induced barrier lowering (DIBL)– A nonzero drain current ID for VGS<VT0

–

• Punch-through– The gate voltage loses its control upon the drain current, and the current rises sharply

• Gate oxide thickness tox scaled to tox/S, is restricted by processing difficulties – Pinholes, oxide breakdown

• Hot-carrier effect

DSGSr VBVA

kT

q

kT

q

B

cnD ee

L

nWxqDldsubthreshoI

0)(

56

MOSFET capacitances

• L=LM-2LD

– L: the actual channel length– LM: the mask length of the

gate– LD: the gate-drain, the gate-

source overlap• On the order of 0.1m

57

Oxide related capacitance(1)

• The gate electrode overlap capacitance– CGD(overlap)=CoxWLD

– CGS(overlap)=CoxWLD

• With Cox=ox/tox

– Both capacitance do not depend on the bias condition, they are voltage-independent

• The capacitances result from the interaction between the gate voltage and the channel charge– Cut-off mode

• Cgs=Cgd=0• Cgb=CoxWL

– Linear mode• Cgb=0• CgsCgd (1/2) CoxWL

– Saturation mode• Cgb= Cgd =0• Cgs (2/3) CoxWL

58

Oxide related capacitance(2)• The sum of all three voltage-dependent (distributed) gate oxide

capacitances (Cgb+Cgs+Cgd)– A minimum value of 0.66CoxWL, in saturation mode– A maximum value of CoxWL, in cut off and linear modes– For simple hand calculation

• The three capacitances can be considered to be in parallel• A constant worst-case value of CoxW(L+2LD) can be used for the sum of

MOSFET gate oxide capacitances

59

Junction capacitance(1)

102012

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0

0

1

0

2

2

00

1

0

1

1

0

2

2

00

1212

12

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20

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2

112

junctions-pnabrupt of case special For the

111

1

as defined becan ecapacitanc signal-large equivalent The

1

2 areaunit per ecapacitancjunction bias zero The

tcoefficien grading is mparameter the,

1

1

2 ecapacitancjunction The

2 chargeregion depletion The

ln potentialin -built The

2cknessregion thidepletion The

2

1

VVVV

K

KCAC

VV

VV

φCAC

VV

mVV

CA

(V)dVCVVVV

)(VQ)(VQ

ΔV

ΔQC

φNN

NNqεC

φ

V

AC(V)C

VφNN

NNqεA

dV

dQC

VφNN

NNqεAx

NN

NNqAQ

n

NN

q

kTφ

VφNN

NN

q

ε x

eq

eqjeq

jeq

mm

j

V

V jjj

eq

DA

DASij

m

jj

DA

DASijj

DA

DASid

DA

DAj

i

DA

DA

DASid

61

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0

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112


111

1


1



1

1





2

1

VVVV

K

KCAC

VV

VV

φCAC

VV

mVV

CA

(V)dVCVVVV

)(VQ)(VQ

ΔV

ΔQC

φNN

NNqεC

φ

V

AC(V)C

VφNN

NNqεA

dV

dQC

VφNN

NNqεAx

NN

NNqAQ

n

NN

q

kTφ

VφNN

NN

q

ε x

eq

eqjeq

jeq

mm

j

V

V jjj

eq

DA

DASij

m

jj

DA

DASijj

DA

DASid

DA

DAj

i

DA

DA

DASid

62

00

0

0

0

0

20

0

1



1

1





φNN

NNqεC

φ

V

AC(V)C

VφNN

NNqεA

dV

dQC

VφNN

NNqεAx

NN

NNqAQ

n

NN

q

kTφ

VφNN

NN

q

ε x

DA

DASij

m

jj

DA

DASijj

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DASid

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DAj

i

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63

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111

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2

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VVVV

K

KCAC

VV

VV

φCAC

VV

mVV

CA

(V)dVCVVVV

)(VQ)(VQ

ΔV

ΔQC

eq

eqjeq

jeq

mm

j

V

V jjj

eq

64

Example 7

65

Junction capacitance(2)

eq(sw)jsweq(sw)

eq(sw)

swswsw

sweq

jswjjsw

swDA(sw)

DA(sw)Siswj

A(sw)

A

KCPC

P

C

VVVV

K

xCC

φNN

NNqεC

N

N

p

becan )(perimeterlength of sidewall a

for ecapacitancjunction signal-large equivalent The

2

factor eequivalenc voltagesidewall The

1

2

as found becan areaunit per ecapacitanc bias-zero the

,by given isdensity doping sidewall theAssume

density doping substrate than the

density dopinghigher a with implant, stop-channel aby surrounded are

region diffusion drain or source MOSFET typicala of sidewalls The

102012

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0

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66

Example 8 (1)

67

Example 8 (2)

chapter 3 cmos(class2)

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