chapter 3. boolean algebrasoc.yonsei.ac.kr/class/material/logic/ch3.pdf · 3 -2 boolean algebra...
TRANSCRIPT
Chapter 3. Boolean Algebra(continued)
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Boolean Algebra
Algebraic structure consisting of:
set of elements B
binary operations {+, -}
unary operation {'}
such that the following axioms hold:
1. B contains at least two elements, a, b, such that a = b
2. Closure a,b in B,
(i) a + b in B
(ii) a • b in B
3. Commutative Laws: a,b in B,
(i) a + b = b + a
(ii) a • b = b • a
4. Identities: 0, 1 in B
(i) a + 0 = a
(ii) a • 1 = a
5. Distributive Laws:(i) a + (b • c) = (a + b) • (a + c)(ii) a • (b + c) = a • b + a • c
6. Complement:(i) a + a' = 1(ii) a • a' = 0
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YZXZXYXXZXYZYX+=++
+=+))((
)(
(3-3)YXXZZXYX ')')(( +=++44 344 21
876
)')(('
:factoringfor 3)-(3TheoremofusethesillustrateexamplefollowingThevalid.alwaysisit 1,Xand0Xboth for validisequation thebecause
Z.or ZY0ZY)Z(1toreduces3)-(30,XIfY.Yor Y10Z)Y(1toreduces3)-(30,XIf
BACACABA ++=+
===∗+=+==∗+=+=
43421
876
To obtain a sum-of-product form Multiplying out using distributive lawsTo obtain a sum-of-product form Multiplying out using distributive laws
Theorem for multiplying out: Theorem for multiplying out:
Theorem for factoring: Theorem for factoring:
Theorem for Multiplying Out and Factoring
3.1 Multiplying Out and Factoring Expressions
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Multiplying Out
''')'')('( ABQDQCQDCABQ +=++
'''''')'')('( QABDCABQQDQCQDCABQ +++=++
)')(')()()('( CAEDAEBADBACBA +++++++++
)]'(')[)('( EDAACEBADCBA ++++++=
)''')('( EADAACDECBA ++++=
DECABEABDAABCAC ''''' ++++= (3-4)
Theorem for multiplying out:
Multiplying out using distributive laws
Redundant terms
multiplying out: (1) distributive laws (2) theorem(3-3)
What theorem was applied to eliminate ABC ?
3.1 Multiplying Out and Factoring Expressions
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(A+B+C’) (A+B+D) (A+B+E) (A+D’+E)(A’+C)
Let X=A+B, Y=C’, Z=D (X+Y)(X+Z) = X+YZ
=(A+B+C’D) (A+B+E) (A+D’+E) (A’+C)
Let X=A, Y=D’+E, Z=C, (X+Y)(X’+Z) = XZ+X’Y
=(A+B+C’D)(A+B+E) (AC+A’(D’+E))
=(A+B+C’D)(A+B+E) (AC+A’D’+A’E)) by distr. law
Let X=A+B, Y=C’D, Z=E, (X+Y)(X+Z) = X+YZ
=(A+B+C’DE) (AC+A’D’+A’E))
Mult. out by distr. law and eliminate terms such as AA’D’ =AAC+AA’D’+AA’E +ABC+A’BD’+A’BE +C’DEAC+C’DEA’D+C’DEA’E
= AC + ABC + A’BD + A’BE + A’C’DE
Let X=AC, Y=B X+XY = X
= AC + A’BD’ + A’BE + A’C’DE
EXAMPLE: CONVERT to SOP FORM
3.1 Multiplying Out and Factoring Expressions
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AC + A’BD’ + A’BE + A’C’DE (A’ is common to three terms)
= AC + A’(BD’ + BE + C’DE) by distr. law
Let X=A, X’=A’, Y=BD’ + BE + C’DE, Z=C XZ+X’Y=(X+Y)(X’+Z)
=(A+BD’+BE+C’DE)(A’+C)=(A+C’DE+BD’+BE)(A’+C) -re-arranging
= A+C’DE +B(D’+E ) (A’+C) by distr. law
Let X= A+C’DE, Y=B, Z=D’+E X+YZ=(X+Y)(X+Z) (8D)
= (A+B+C’DE)(A+C’DE +D’+E)(A’+C)
But E+C’DE = E (using X+XY=X) so C’DE is redundant
= (A+B+C’DE) (A+D’+E)(A’+C)
Let X=A+B, Y=C’, Z=DE X+YZ=(X+Y)(X+Z)
=(A+B+C’)(A+B+DE) (A+D’+E)(A’+C)
Let X=A+B, Y=D, Z=E X+YZ=(X+Y)(X+Z)
=(A+B+C’) (A+B+D)(A+B+E) (A+D’+E)(A’+C)
EXAMPLE: CONVERT to POS FORM
3.1 Multiplying Out and Factoring Expressions
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XOR: X or Y but not both ("inequality", "difference")
XNOR: X and Y are the same ("equality", "coincidence")
X ⊕ Y = X Y' + X' Y X ⊕ Y = X Y + X' Y'
(a) XOR (b) XNOR
Description Z = 1 if X has a different value than Y
Gates
T ruth T able
X
Y Z
X 0 0 1 1
Y 0 1 0 1
Z 0 1 1 0
Description Z = 1 if X has the same value as Y
Gates
T ruth T able
X
Y Z
X 0 0 1 1
Y 0 1 0 1
Z 1 0 0 1
XOR, XNOR
3.2 Exclusive-OR and Equivalence Operations
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Theorems for Exclusive-OR
◈Theorems for Exclusive-OR
XX =⊕ 0'1 XX =⊕
0=⊕ XX1'=⊕ XX
law) ecommutativ(XYYX ⊕=⊕
law) eassociativ( )()( ZYXZYXZYX ⊕⊕=⊕⊕=⊕⊕
law) vedistributi( )( XZXYZYX ⊕=⊕
X'Y'XYYX'Y'X'YX +=⊕=⊕=⊕ )(
3.2 Exclusive-OR and Equivalence Operations
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XOR and Equivalence Operations
1)00( =≡ 0)10( =≡
0)01( =≡ 1)11( =≡
1001
0 00 11 01 1
XY YX ≡
Equivalence operation(Exclusive-NOR)
Equivalence operation(Exclusive-NOR)
Truth TableTruth Table
SymbolSymbol
3.2 Exclusive-OR and Equivalence Operations
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Waveform View
3.2 Exclusive-OR and Equivalence Operations
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Consensus theorem states:
XY + X’Z + YZ = XY + X’Z
The YZ term is called the consensus term and is redundant. The consensus term is formed from a PAIR OF TERMS in which a variable (X) and its complement (X’) are present; the consensus term is formed by multiplying the two terms and leaving out the selected variable and its complement.
The consensus of XY, X’Z is YZ .
Consensus Theorem
3.3 The Consensus Theorem
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Consensus Theorem Proof:
XY + X’Z + YZ = XY + X’Z + (X + X’)YZ= XY + X’Z + XYZ + X’YZ= (XY + XYZ) + (X’Z + X’YZ)= XY (1 + Z) + X’Z (1 + Y)= XY + X’Z
You could also use a truth table to prove this.
Prove The Consensus Theorem
3.3 The Consensus Theorem
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(X + Y) (X’ + Z) (Y + Z) = (X + Y) (X’ + Z)
The consensus of (X + Y)(X’+ Z) is (Y + Z) .
How do you use the consensus theorem? Simply be suspicious anytime you have two terms that have a variable and its complement. Form the consensus term and see if it is present; if consensus term is present, just get rid of it.
Dual Of Consensus Theorem
3.3 The Consensus Theorem
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'''' ACDABCBCDBDADCA ++++
'''' ACDABCBCDBDADCA ++++
'''' BCEBACDEBABCDF +++=
ACDEBCEBACDEBABCDF ++++= ''''
ACDEBCEBAF ++= '''
Example: eliminate BCDExample: eliminate BCD
Example: eliminate A’BD, ABCExample: eliminate A’BD, ABC
Example: Reducing an expressionby adding a term and eliminate.
Example: Reducing an expressionby adding a term and eliminate.
Consensus
Term addedFinal expressionFinal expression
Consensus Theorem
3.3 The Consensus Theorem
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◈Goal is to find an equivalent of an original logic expression that:
a) has fewer variables per term
b) has fewer terms
c) needs less logic to implement
◈There are three main manual methods
Algebraic minimization
Karnaugh Map minimization
Quine-McCluskey (tabular) minimization
Logic Expressions Minimization
3.4 Algebraic Simplification of Switching Expressions
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◈ Logic Minimization: reduce complexity of the gate level implementation
reduce number of literals (gate inputs)
reduce number of gates
reduce number of levels of gates
◈ fewer inputs implies faster gates in some technologies
◈ fan-ins (number of gate inputs) are limited in some technologies
◈ fewer levels of gates implies reduced signal propagation delays
◈ minimum delay configuration typically requires more gates
◈ number of gates (or gate packages) influences manufacturing costs
Traditional methods: reduce delay at expense of adding gates
New methods: trade off between increased circuit delay and reduced gate count
Traditional methods: reduce delay at expense of adding gates
New methods: trade off between increased circuit delay and reduced gate count
Rationale for Simplification
3.4 Algebraic Simplification of Switching Expressions
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◈Process is to apply the switching algebra postulates, laws, and theorems to transform the original expression
Hard to recognize when a particular law can be applied
Difficult to know if resulting expression is truly minimal
Very easy to make a mistakeIncorrect complementation
Dropped variables
Algebraic Minimization
3.4 Algebraic Simplification of Switching Expressions
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Combining Terms by Adjacency:Example:
abc’d’ + abcd’ = abd’
Example: (duplicating abc first then eliminating by adjacency)
ab’c + abc +a’bc = ab’c + abc + abc + a’bc= ac + bc
XY + XY’ = X (X+Y) (X+Y’)=X
Look for two terms that are identical except for compl. in one variable.-Application removes one term and one variable from the remainingterm.
Adjacency
3.4 Algebraic Simplification of Switching Expressions
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Eliminating Terms by Absorption:
Example:
a’b + a’bc = a’b
X + XY = X X (X+Y) = X
Look for two terms that are the same except for an extra variable
Absorption
3.4 Algebraic Simplification of Switching Expressions
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Eliminating Literals by Simplification:
Example:
A’B +A’B’C’D’+ ABCD’= A’(B+B’C’D’)+ABCD’ (factored)= A’(B+C’D’) + ABCD’ (simplification)= A’B+A’C’D’ + ABCD’ (distributed A’)= B(A’ + ACD’) + A’C’D’ (factored out B)= B(A’ + CD’) + A’C’D’ (simplification)
X + X’Y = X + Y X (X’+Y) = XY
Simplification
3.4 Algebraic Simplification of Switching Expressions
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1. Construct Truth Table and evaluate both sides of eqn.
2. Make L.S. equal R.S. or R.S. equal L.S. by algebraic manipulation.
3. Reduce both L.S. and R.S. independently to the same expression.
To show an equation is NOT Valid
Give one combination of values (‘0’, ‘1’) of the variables for
which L.S. != R.S.
(This is equivalent to finding one line in a truth table for
which L.S. and R.S. have different values.)
Proving Validity of an Equation
3.5 Proving Validity of an Equation
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When attempting to prove that an equation. is valid:It is permissible to perform the same operation on on both sides of the eqn. as long as the operation is reversible (has an inverse) within Boolean Algebra..
Complement both sides -- Allowed
Mult. both sides by same expression -- Not Allowed
Add same term to both sides --- Not Allowed
Valid Operations
3.5 Proving Validity of an Equation
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BCAADDBCDABABCBCDBDA ''''''' ++=+++
ABDBCADBCDABABCBCDBDA ++++++= '''''''
(add consensus of A’BD’ and ABC’)(add consensus of A’BD’ and BCD)(add consensus of BCD and ABC’)
BCAADDBCBCADBCABCBCDBDAAD ''''''''' ++=+++++=
(eliminate consensus of BC’D’ and AD)(eliminate consensus of AD and A’BC)
(eliminate consensus of BC’D’ and A’BC)
Prove :
Proving Validity of an Equation
3.5 Proving Validity of an Equation
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zyzxyx =+=+ then , If
10but 1101 ≠+=+
zyxzxy == then , If
zxy then , If +=+= xzy
xzy then , If == xzy
Some of Boolean Algebra are not true for ordinary algebra
Example: True in ordinary algebra
Not True in Boolean algebra
Example:
True in ordinary algebra
Not True in Boolean algebraExample:
True in ordinary algebra
True in Boolean algebra
Proving Validity of an Equation
3.5 Proving Validity of an Equation
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Positive and Negative Logic
◈General ConceptPositive Logic
High Voltage => Logic 1Low Voltage => Logic 0
Negative LogicHigh Voltage => Logic 0Low Voltage => Logic 1
Positive and Negative Logic
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◈Implication
Positive Logic High Voltage => Logic 1
Low Voltage => Logic 0
VoltageA B F
Low Low LowLow High LowHigh Low LowHigh High High
LogicA B F0 0 00 1 01 0 01 1 1
- Equivalent gate: AND
Positive and Negative Logic (cont’d)
Positive and Negative Logic
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◈Implication
Negative Logic High Voltage => Logic 0
Low Voltage => Logic 1
VoltageA B F
Low Low LowLow High LowHigh Low LowHigh High High
LogicA B F1 1 11 0 10 1 10 0 0
- Equivalent gate: OR
Positive and Negative Logic (cont’d 2)
Positive and Negative Logic
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◈Implication
Positive Logic High Voltage => Logic 1
Low Voltage => Logic 0
VoltageA B F
Low Low LowLow High HighHigh Low HighHigh High High
LogicA B F0 0 00 1 11 0 11 1 1
- Equivalent gate: OR
Positive and Negative Logic (cont’d 3)
Positive and Negative Logic
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◈Implication
Negative Logic High Voltage => Logic 0
Low Voltage => Logic 1
VoltageA B F
Low Low LowLow High HighHigh Low HighHigh High High
LogicA B F1 1 11 0 00 1 00 0 0
- Equivalent gate: AND
Positive and Negative Logic (cont’d 4)
Positive and Negative Logic
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Normal Convention: Positive Logic/Active High
Low Voltage = 0; High Voltage = 1
Alternative Convention sometimes used: Negative Logic/Active Low
Behavior in termsof Electrical Levels
Two Alternative Interpretations
Positive Logic ANDNegative Logic OR
Dual Operations`
Negative Logic Positive Logic V oltage T ruth T able
F low low low high
F 0 0 0 1
F 1 1 1 0
A low low high high
B low high low high
B 0 1 0 1
A 0 0 1 1
A 1 1 0 0
B 1 0 1 0
F
Positive vs. Negative Logic
Positive and Negative Logic
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Conversion from Positive to Negative Logic
Positive Logic NOR: A + B = A • B
Negative Logic NAND: A • B = A + B
Dual operations: AND becomes OR, OR becomes ANDComplements remain unchanged
V oltage T ruth T able
F high low low low
F 1 0 0 0
F 0 1 1 1
A low low high high
B low high low high
B 0 1 0 1
A 0 0 1 1
A 1 1 0 0
B 1 0 1 0
F
Negative Logic Positive Logic
Positive vs. Negative Logic
Positive and Negative Logic
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(c)
Change Request
(active low)
T imer Expired
(active low)
Change Lights
(active low)
Bubble Mismatch
(d)
(a)
Change Request
(active high)
T imer Expired
(active high)
Change Lights
(active high)
Active High
(b)
Change Request
(active low)
T imer Expired
(active low)
Change Lights
(active low)
Active Low
Change Request
(active low)
T imer Expired
(active low)
Change Lights
(active low)
Bubble Match
Practical Example
Mismatch betweeninput and outputlogic polarities
Use NAND w/ invertedinputs if negative logic
Use OR gate if inputpolarities are neg. logic
Use AND gateif active high
Positive vs. Negative Logic
Positive and Negative Logic