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Chapter 2

MOSFETs

2.1 Why MOSFET?

Much of this book is concerned with the application of the so-called Metal-

Oxide-Semiconductor Field-Effect Transistor (MOSFET) toward implementing

signal processing circuitry. There are many other devices that could be used

to do much the same operations, so why are we concentrating on MOSFETS?

Mainly for reasons of:

• Cost – with CMOS technology we take advantage of economy of scale

and the price per device can be extremely small. Consider that one can

purchase an AMD processor for about $300 CAD, and the processor con-

tains roughly 100 million transistors. That’s only 3 “micro-dollars” per

transistor.

• Availability – it is possible to run a “fabless” design company these days

due to the accessibility of fabrication facilities. The most accessible tech-

nology is currently Complementary Metal-Oxide-Semiconductor (CMOS).

The best technology choice for an integrated application must weigh the

consequences of wafer cost, level of integration, performance, economics, and

5

CHAPTER 2. MOSFETS 6

time to market. These requirements often lead designers into using several tech-

nologies within a system. For example, commercial implementations of highly-

integrated high-performance wireless transceivers use a mixture of technologies,

including CMOS, BiCMOS, BJTs, GaAs FETs, and HBTs.

Partitioning of functionality according to technology implies that signals

must go on-chip and off-chip at several locations. Recent trends apply CMOS to

entire system-on-chip (SoC) designs, since CMOS excels in its level of integra-

tion. The level of integration offered by a particular technology determines the

required die size, which in turn affects both the cost and the physical size of the

final packaged circuitry.

2.2 Some MOSFET History

The insulated-gate field-effect transistor was conceived in the 1930’s by Lilien-

feld and Heil. An insulated-gate transistor is distinguished by the presence of

an insulator between the main control terminal and the remainder of the device.

If you are used to BJTs, then this concept might seem strange to you, since in

BJTs, a small current is used to control a larger current. In the case of insulated-

gate devices, this controlling current does not exist (well, almost). Ideally, the

transistor draws no current through its gate (in practice a small leakage current

on the order of10−18 A to 10−16 A exists). This is in sharp contrast to bipolar

junction transistors which require a significant base current to operate.

Unfortunately, the concept of the insulated-gate field effect transistor took

nearly 30 years to become a practical reality. Since the 1960’s, the explosive

growth of MOSFET utilization in every aspect of electronics is phenomenal.

The use of MOSFETs in electronics became ever more prevalent when “com-

plementary” types of MOSFET devices were combined by Wanlass in the early

1960’s to produce logic that required virtually no power except when chang-

ing state. MOSFET processes that offer complementary types of transistors are

known as Complementary Metal Oxide Semiconductor (CMOS) processes, and


are the foundation of the modern commodity electronics industry.

Advantages of MOSFETs

Primary advantages of MOSFET technology over other types of integrated de-

vices include:

• its mature fabrication technology,

• its high integration levels,

• its mixed analog/digital compatibility,

• its capability for low voltage operation,

• its successful scaling characteristics,

• and the combination of complementary MOSFETs yielding low power

CMOS circuits.

2.3 MOSFET Fundamentals

The physical structure of the MOSFET is illustrated in Figure 2.1. Visible in the

figure are the various materials used to construct a MOSFET. These materials

appear in layers when the MOSFET cross-section is viewed; this is a direct con-

sequence of the processes of "doping", deposition, growth, and etching which

are fundamental in conventional processing facilities.

The fabrication process of silicon MOSFET devices has evolved over the last

30 years into a reliable integrated circuit manufacturing technology. Silicon has

emerged as the material of choice for MOSFETs, largely because of its stable

oxide, SiO2, which is used as a general insulator, as a surface passivation layer,

and as a gate dielectric.


Figure 2.1: A MOSFET view showing the physical configuration of the MOS-FET and the terminal connections.

Full appreciation of the MOSFET structure and operation requires some

knowledge of silicon semiconductor properties and “doping”. These topics are

briefly reviewed next.

2.4 Semiconductors and Doping

On the scale of conductivity that exists between pure insulators and perfect con-

ductors, semiconductors fall in between the extremes. The semiconductor ma-

terial commonly used to make MOSFETs is silicon. Pure, or “intrinsic” silicon

exists as an orderly three-dimensional array of atoms, arranged in a crystal lat-

tice. The atoms of the lattice are bound together by covalent bonds containing

silicon valence electrons. At absolute-zero temperature, all valence electrons are

locked into these covalent bonds and are unavailable for current conduction, but

as the temperature is increased, it’s possible for an electron to gain enough ther-

mal energy so that it escapes from its covalent bond, and in the process leaves

behind a covalent bond with a missing electron, or “hole”. When that happens

the electron that escaped is free to move about the crystal lattice. At the same


time, another electron which is still trapped in nearby covalent bonds because

of its lower energy state can move into the hole left by the escaping electron.

The mechanism of current conduction in intrinsic silicon is therefore by hole-

electron pair generation and the subsequent motion of free electrons and holes

throughout the lattice.

At normal temperatures, intrinsic silicon behaves as an insulator because the

number of free hole-electron pairs available for conducting current is very low.

The number of free hole-electron pairs available for conducting current is called

the intrinsic carrier concentration density, and is denoted byni. At room tem-

perature, let’s say 300 K (that’s 300 degrees Kelvin), the value ofni for silicon

is 0.0145µm−3. Since there are5× 1010 silicon atoms in a cubic micrometer of

pure silicon, the small intrinsic carrier concentration density of intrinsic silicon

means that only about three silicon atoms out of1013 will contribute an hole-

electron pair at any given time at room temperature. No wonder pure silicon

isn’t much of a conductor!

The conductivity of silicon can be adjusted by adding foreign atoms to the

silicon crystal. This process is called “doping”, and a “doped” semiconductor

is referred to as an “extrinsic” semiconductor. Depending on what type of ma-

terial is added to the pure silicon, the resulting crystal structure can either have

more electrons than the normal number needed for perfect bonding within the

silicon structure, or less electrons than needed for perfect bonding. When the

dopant material increases the number of free electrons in the silicon crystal, the

dopant is called a “donor”. The donor materials commonly used to dope sil-

icon are phosphorus, arsenic, and antimony. In a donor-doped semiconductor

the number of free electrons is much larger than the number of holes, and so

the free electrons are called the “majority carriers” and the holes are called the

“minority carriers”. Since electrons carry a negative charge and they are the ma-

jority carriers in a donor-doped silicon semiconductor, any semiconductor which

is predominantly doped with donor impurities is known as “n-type”. Semicon-

ductors with extremely high donor doping concentrations are often denoted “n+


type”.

Dopant atoms which accept electrons from the silicon lattice are also used

to alter the electrical characteristics of silicon semiconductors. These types of

dopants are known as “acceptors”. The introduction of the acceptor impurity

atoms creates the situation in which the dopant atoms have one less valence

electron than necessary for complete bonding with neighbouring silicon atoms.

The number of holes in the lattice therefore increases. The holes are therefore

the majority carriers and the electrons are the minority carriers. Semiconductors

doped with acceptor impurities are known as “p-type”, since the majority carriers

effectively carry a positive charge. Semiconductors with extremely high acceptor

doping concentrations are called “p+ type”. Typical acceptor materials used to

dope silicon are boron, gallium, and indium.

A general point that can be made concerning doping of semiconductor ma-

terials is that the greater the dopant concentration, the greater the conductivity

of the doped semiconductor. A second general point that can be made about

semiconductor doping is that n-type material exhibits a greater conductivity than

p-type material of the same doping level. The reason for this is that electron mo-

bility within the crystal lattice is greater than hole mobility, for the same doping

concentration.

2.5 MOSFET Structure and Operation

Returning to the typical n-type MOSFET, or “NFET”, shown in Figure 2.1,

one can see that the MOSFET consists of two highly conductive regions (the

“source” and the “drain”) separated by a semi-conducting channel. The channel

is typically rectangular, with an associated length (L) and width (W). The ratio

of the channel width to the channel length,W/L, is an important determining

factor for MOSFET performance.

The MOSFET is considered a four terminal device. This is illustrated schemat-

ically in Figure 2.2. The MOSFET terminals are known as the gate (G), the bulk


(B), the drain (D), and the source (S), and the voltages present at these terminals

collectively control the current that flows within the device. For most circuit

designs, the current flow from drain to source is the desired controlled quantity.

Figure 2.2: The MOSFET viewed as a four terminal device.

The operation of field-effect transistors (FETs) is based upon the principal of

capacitively-controlled conductivity in a channel. The MOSFET gate terminal

sits on top of the channel, and is separated from the channel by an insulating

layer of SiO2. The controlling capacitance in a MOSFET device is therefore due

to the insulating oxide layer between the gate and the semiconductor surface of

the channel. The conductivity of the channel region is controlled by the volt-

age applied across the gate oxide and channel region to the bulk material under

the channel. The resulting electric field causes the redistribution of holes and

electrons within the channel. For example, when a positive voltage is applied

to the gate, it’s possible that enough electrons are attracted to the region under

the gate oxide such that this region experiences a local inversion of the majority

carrier type. Although the bulk material is p-type (the majority carriers are holes

and minority carriers are electrons), if enough electrons are attracted to the same

region within the semiconductor material the region becomes effectively n-type.


Then the electrons are the majority carriers and the holes are the minority carri-

ers. Under this condition electrons can flow from the n+ type drain to the n+ type

source if a sufficient potential difference exists between the drain and source.

When the gate-to-source voltage exceeds a certain threshold, typically de-

noted byVT , the conductivity of the channel increases to the point where current

may easily flow between the drain and the source. The value of required for this

to happen is determined largely by the dopant concentrations in the channel, but

it also depends in part upon the voltage present on the bulk. This dependence of

the threshold voltage upon the bulk voltage is known as the “body effect” and is

of particular concern for analog design.

Holes and Electrons

In MOSFETs, both holes and electrons can be used for conduction. MOSFET

devices can be constructed on a p-type or an n-type silicon substrate. Since

both the n-type and p-type MOSFETs require substrate material of the opposite

type of doping, two distinct CMOS technologies exist, defined by whether the

bulk is n-type or p-type. If the bulk material is p-type substrate, then n-type

MOSFETs can be built directly on the substrate while p-type MOSFETs must

be placed in an n-well. This type of process is illustrated in Figure 2.3(a). An-

other possibility is that the bulk is composed of n-type substrate material, and in

this case the p-type MOSFETs can be constructed directly on the bulk, while the

n-type MOSFETs must be placed in a p-well, as in Figure 2.3(b). A third type

of process known as twin-well or twin-tub CMOS enables both the p-type and

n-type MOSFETs to be placed in wells of the opposite type of doping. Other

combinations of substrate doping and well types are in common use. For exam-

ple, some processes offer a “deep-well” capability, which is useful for threshold

adjustments and circuitry isolation.

When a MOSFET sits in a well, the well material forms the “local bulk” for

the MOSFET. This has important and useful consequences when body effect is

a concern. If a device sits in a well it’s possible to electrically contact the well


(a) PFET and NFET in an n-well technology.

(b) PFET and NFET in a p-well technology.

Figure 2.3: MOSFETs can be constructed on either p-type or n-type substrates.

to the source, making the bulk-to-source voltage zero. In turn, the body effect is

avoided.

2.6 The Gate Material

Modern MOSFETs differ in an important respect from their counterparts de-

veloped in the 1960’s. While the gate material used in the field effect transis-

tors produced thirty years ago was made of metal, the use of this material was

problematic for several reasons. At that time, the gate material was typically alu-

minum and was normally deposited by evaporating an aluminum wire by placing

it in contact with a heated tungsten filament. Unfortunately, this method leads

to sodium ion contamination in the gate oxide, which caused the MOSFET’s

threshold voltage to be both high and unstable. A second problem with the ear-


lier methods of gate deposition was that the gate was not necessarily correctly

aligned with the source and drain regions. Matching between transistors was

then problematic because of variability in the gate location with respect source

and drain for the various devices. Parasitics (e.g. capacitive) also varied greatly

between devices because of this variability in gate location with respect to the

source and drain regions. In the worst-case, a non-functional device was pro-

duced because of the errors associated with the gate placement.

Devices manufactured today employ a different gate material, namely “polysil-

icon”∗, and the processing stages used to produce a field-effect transistor with

a poly-gate are different than the processing stages required to produce a field-

effect transistor with a metal gate. In particular, the drain and source wells are

patterned using the gate and field oxide as a mask during the doping stage. Since

the drain and source regions are defined in terms of the gate region, the source

and drain are automatically aligned with the gate. CMOS manufacturing pro-

cesses are referred to as self-aligning processes when this technique is used.

Certain parasitics† are minimized using this method. The use of a polysilicon

gate tends to simplify the manufacturing process, reduces the variability in the

threshold voltage, and has the additional benefit of automatically aligning the

gate material with the edges of the source and drain regions.

The use of polysilicon for the gate material has one important drawback:

the sheet resistance of polysilicon is much larger than that of aluminum and so

the resistance of the gate is larger when polysilicon is used as the gate mate-

rial. Typical polysilicon gate resistances are 20-50Ω/, while aluminum sheet

resistance is normally about 0.03Ω/. High-speed digital processes require fast

switching time from the MOSFETs used in the digital circuitry, yet a large gate

resistance hampers the switching speed of a MOSFET. One method commonly

used to lower the gate resistance is to add a layer of silicide on top of the gate

material. A silicide is a compound formed using silicon and a refractory metal,∗Often called “poly”.†Specifically the overlap parasitics encountered in Section 5.1.


for example TiSi2. In general, the use of silicide gates is required for reasonable

high frequency MOSFET performance.

Although the metal-oxide-semiconductor sandwich is no longer regularly

used at the gate, the devices are still called MOSFETs. The term IGFET is

also in common usage.

2.7 MOSFET Large Signal Current-Voltage

Characteristics

When a bias voltage in excess of the threshold voltage is applied to the gate

material, a sufficient number of charge carriers are concentrated under the gate

oxide such that conduction between the source and drain is possible. Recall that

the majority carrier component of the channel current is composed of charge

carriers of the opposite type to that of the substrate. If the substrate is p-type

silicon then the majority carriers are electrons. For n-type silicon substrates,

holes are the majority carriers.

The threshold voltage of a MOSFET depends on several transistor properties

such as the gate material, the oxide thickness, and the silicon doping levels. The

threshold voltage is also dependent upon any fixed charge present between the

gate material and the gate oxide. MOSFETs used in most commodity products

are normally the “enhancement mode” type. Enhancement mode n-type MOS-

FETs have a positive threshold voltage and do not conduct appreciable charge

between the source and the drain unless the threshold voltage is exceeded. In

contrast, “depletion mode” MOSFETs exhibit a negative threshold voltage and

are normally conductive. Similarly, there exists enhancement mode and deple-

tion mode p-type MOSFETs. For p-type MOSFETs the sign of the threshold

voltage is reversed.


Body Effect

Equations which describe how MOSFET threshold voltage is affected by sub-

strate doping, source and substrate biasing, oxide thickness, gate material, and

surface charge density have been derived in the literature.1−4 Of particular im-

portance is the increase in the threshold voltage associated with a non-zero

source-to-bulk voltage. This is known as the “body effect” and is quantified

by the equation,

VTH = VTH0 + γ(√

|2ΦF + VSB| −√|2ΦF |

)(2.7.1)

whereVTH0 is the zero-bias threshold voltage,γ =√

2qεsiNsub/Cox is the body

effect coefficient or body factor,VSB is the bulk-to-source voltage, andΦF is is

the bulk surface potential, or the Fermi potential∗. It can be shown thatΦF is

given by

ΦF =kT

qln

(Nsub

ni

)(2.7.2)

in which k = 1.3809 × 10−23 C·VK is Boltzmann’s constant,T is the temperature

in Kelvin, q = 1.6022 × 10−19C is the electronic charge,Nsub is the dopant

concentration, andni is the intrinsic carrier concentration of silicon.

The zero-bias threshold voltage,VTH0, appearing in (2.7.1) is given by

VTH0 = ΦMS + 2ΦF +Qdep

Cox

(2.7.3)

whereΦMS is the difference between the work function of the silicon substrate

and the gate material, andQdep is the charge in the depletion region. It can be

shown that the charge in the depletion region,Qdep, is given by

Qdep =√

4qεsi |ΦF |Nsub (2.7.4)∗The Fermi potentialΦF of extrinsic silicon is the theoretical contact potential that would

develop between intrinsic and extrinsic silicon under conditions of thermal equilibrium.


in which εsi is the dielectric constant of silicon.

2.8 MOSFET Operating Regions

MOSFETs exhibit fairly distinct regions of operation depending upon their bi-

asing conditions. In the simplest treatments of MOSFETs the three operating

regions considered are subthreshold, triode, and saturation.

Subthreshold MOSFET Operation

When the applied gate-to-source voltage is below the device’s threshold voltage,

the MOSFET is said to be operating in the subthreshold region. For gate voltages

below the threshold voltage, the current decreases exponentially towards zero

according to the equation

iDS = IDS0W

Lexp

(vGS

nkT/q

)(2.8.1)

in whichn is given by

n = 1 +γ

2√

φj − vBS

(2.8.2)

In (2.8.2),γ is the body factor,φj is the channel junction built-in voltage, and

vBS is the source-to-bulk voltage.

MOSFET Triode Operation

A MOSFET operates in its triode, also called “linear”, region when bias condi-

tions cause the induced channel to extend from the source to the drain. When

VGS > VT the type of the majority carriers at the surface under the oxide is in-

verted and ifVDS > 0 a drift current will flow from the drain to the source. The

drain-to-source voltage is assumed small so that the depletion layer is approx-

imately constant along the length of the channel. Under these conditions, the


drain source current for an NMOS device is given by the relation,

ID = µnC′ox

W

L

((VGS − VTn) VDS −

V 2DS

2

)∣∣∣∣ VGS > VTn

VDS 6 VGS − VTn

(2.8.3)

whereµn is the electron mobility in the channel andC ′ox is the per unit area

capacitance over the gate area. Similarly, for PMOS transistors the current rela-

tionship is given as,

ID = µpC′ox

W

L

((VSG − |VTp|) VSD −

V 2SD

2

)∣∣∣∣ VSG > |VTp|VSD 6 VSG − |VTp|

(2.8.4)

in which µp is the hole mobility andVTp is the threshold voltage of the pmos

device.

If VDS in (2.8.3) is small, then the term containingV 2DS may be negligible.

Under this condition, (2.8.3) reduces to a linear equations inVDS, and hence the

region of operation is often called “linear”. A similar analysis can be made for

the pmos equation.

MOSFET Saturation Operation

The conditionsVDS 6 VGS − VT in (2.8.3) andVSD 6 VSG − VT in (2.8.4)

ensure that the inversion charge is never zero for any point along the channel’s

length. However, whenVDS = VGS − VT (or VSD = VSG − VT in PMOS

devices) the inversion charge under the gate at the channel-drain junction is zero.

The required drain-to-source voltage is calledVDS,sat for NMOS andVSD,sat for

PMOS.

ForVDS > VDS,sat (VSD > VSD,sat for PMOS), the channel charge becomes

“pinched off”, and any increase inVDS increases the drain current only slightly.

The reason that the drain currents will increase for increasingVDS is because the

depletion layer width increases for increasingVDS. This effect is called channel


length modulation and is accounted for byλ, the channel length modulation

parameter. The channel length modulation parameter ranges from approximately

0.1 for short channel devices to 0.01 for long channel devices. Since MOSFETs

designed for high frequency operation normally use minimum channel lengths,

channel length modulation is an important concern for high frequency circuit

implementations in CMOS.

When a MOSFET is operated with its channel pinched off, in other words

VDS > VGS − VT andVGS > VT for NMOS (orVSD > VSG − VT andVSG >

VT for PMOS), the device is said to be operating in the saturation region. The

corresponding equations for the drain current are given by,

ID =1

2µnC

′ox

W

L(VGS − VTn)2 (1 + λ (VDS − VDS,sat)) (2.8.5)

for long-channel NMOS devices and by,

ID =1

2µpC

′ox

W

L(VSG − |VTp|)2 (1 + λ (VSD − VSD,sat)) (2.8.6)

for long-channel PMOS devices.

Figure 2.4 illustrates a surface representing a MOSFET’s drain current as a

function of its terminal voltages. The drain-to-source voltage and gate-to-source

voltage are swept over the operating region while the bulk-to-source voltage has

been taken as zero. Figure 2.4 demonstrates that the drain current is always a

function of bothVDS andVGS. Otherwise, there would be regions on theIDS

surface that were flat with respect to eitherVDS or VGS.

Figure 2.5 represents the data given in Figure 2.4 using families of curves.

In Figure 2.5(a), the drain current is plotted againstVDS for several values of

VGS. One can see that asVDS is increased, the device goes from triode into

saturation and the output current is less dependent uponVDS. The slope is not

identically zero however, as the drain-to-source voltage does have some effect

upon the channel current due to channel modulation effects.

Figure 2.5(b) illustrates the drain current versusVGS for increasing values of


Figure 2.4: The MOSFET drain to source current as a function ofVGS andVDS.The bulk-to-source voltage was fixed as 0V.

VDS. For large values ofVDS the square-law characteristic of the MOSFET is

evident in the shape of the curve.

2.9 Non-Ideal and Short Channel Effects in

MOSFETs

The equations presented for the subthreshold, triode, and saturation regions

of the MOSFET operating characteristic curves do not include the many non-

idealities exhibited by MOSFETs. Most of these non-ideal behaviours are more

pronounced in deep submicron devices such as those employed in radio fre-

quency designs, and so it is important for a designer to be aware of these non-

idealities.


(a) MOSFET IDS versusVDS for varyingVGS .

(b) MOSFET IDS versusVGS for varyingVDS .

Figure 2.5: MOSFETs can be constructed on either p-type or n-type substrates.

Velocity Saturation

Electron and hole mobility are not constants; they are a function of the applied

electric field. Above a certain critical electric field strength the mobility starts

to decrease, and the drift velocity of carriers does not increase in proportion to

the applied electric field. Under these conditions the device is said to be velocity

saturated. Velocity saturation has important practical consequences in terms of

the current-voltage characteristics of a MOSFET acting in the saturation region.

In particular, the drain current of a velocity saturated MOSFET operating in the

saturation region is a linear function ofVGS. This is in contrast to the results

given in equations (2.8.5) and (2.8.6). The drain current for a short channel

device operating under velocity saturation conditions is given by

IDS = µcritC′oxW (VGS − VT ) (2.9.1)

whereµcrit is the carrier mobility at the critical electric field strength.


Drain Induced Barrier Lowering

A positive voltage applied to the drain terminal helps to attract electrons under

the gate oxide region. This increases the surface potential and causes a thresh-

old voltage reduction. Since the threshold decreases with increasing VDS, the

result is an increase in drain current and therefore an effective decrease in the

MOSFET’s output resistance. The effects of drain induced barrier lowering are

reduced in modern CMOS processes by using lightly-doped-drain (LDD) struc-

tures.

Hot carriers

Velocity saturated charge carriers are often called hot carriers. Hot carriers can

potentially tunnel through the gate oxide and cause a gate current, or they may

become trapped in the gate oxide. Hot carriers that become trapped in the gate

oxide change the device threshold voltage. Over time, if enough hot carriers

accumulate in the gate oxide the threshold voltage is adjusted to the point that

analog circuitry performance is severely degraded. Therefore, depending upon

the application, it may be unwise to operate a device so that the carriers are

velocity saturated since the reliability and lifespan of the circuit is degraded.

Chapter 3

Small Signal Modeling

Small signal equivalent circuits are useful when the voltage and current wave-

forms in a circuit can be decomposed into a constant level plus a small time-

varying offset. Under these conditions, a circuit can be linearized about its DC

operating point. Nonlinear components are replaced with linear components that

reflect the characteristics of the devices at the DC bias condition.

Why do we need to do this? Well, the use of small signal models is motivated

by several factors:

• Using the “real” equations for currents can lead to an analytically unsolv-

able problem.

• Mathematical operations on linear equations can be done quickly. Simu-

lators take less time to simulate the circuit of interest.

• There is a wide body of technical literature on how to design systems based

on linear superposition.

The last point should not be overlooked. When we represent complicated

device models using linearized small signal models, we ignore the nonlinearities

inherent in the device that we are modeling. Depending on the circuit, the inputs

to the circuit, and the quantity of interest, it may turn out that using small signal

models is entirely erroneous.

23

CHAPTER 3. SMALL SIGNAL MODELING 24

Total Signal = Static + Dynamic

Small-signal modeling can get confusing unless a notation is adopted for the

various types of signals. We shall adopt the following notation:

• A quantity with the main variable in lower case and the subscript letters

in upper case means that value includes both the static quantity and the

dynamic quantity. An example isvGS.

• A quantity with the main variable in upper case and the subscripts in upper

case denotes a static quantity. An example isVGS.

• A quantity written using all lower case is a dynamic quantity. An example

is vgs.

• The total quantity is composed of the addition of the fully static and fully

dynamic quantities. An example isvGS = VGS + vgs.

Note that this notation makes it easy to see if a given variable is DC, AC, or

AC+DC. If the notation is adopted then any variable that is written using all

upper case letters is fully static (DC), any variable written using all lower case

letters is fully dynamic (AC), and any variable written using a combination of

upper case and lower case is a total quantity and represents a static signal with a

dynamic offset (AC+DC).

For a small change in VGS, the output current changes in an essentially linear

fashion. If we know the slope of IDS as a function of VGS, we can predict

changes in the output current for small changes in the VGS value. Similarly for

IDS versus VDS.

Chapter 4

Low Frequency Small Signal

MOSFET Models

The low-frequency small signal model for a MOSFET is shown in Figure 4.

Only the intrinsic portion of the transistor is considered for simplicity. As shown,

the small signal model consists of three components: the small signal gate transcon-

ductance,gm; the small signal substrate transconductance,gmb; and the small

signal drain conductance,gd.

If we consider that each of these small signal parameters describe how the

MOSFET drain-to-source current changes with respect to changes in the termi-

nal voltages, we can write the definitions of these parameters as follows:

gm =∂IDS

∂VGS

∣∣∣∣VBS ,VDS constant

(4.0.1)

gmb =∂IDS

∂VBS

∣∣∣∣VGS ,VDS constant

(4.0.2)

gd =∂IDS

∂VDS

∣∣∣∣VGS ,VBS constant

(4.0.3)

Depending on the large signal current expressions used to model the MOSFET

operation, each of equations (4.0.1), (4.1.6) and (4.0.3) results in different ex-

25

CHAPTER 4. LOW FREQUENCY SMALL SIGNAL MOSFET MODELS 26

pressions forgm, gmb andgd.

4.1 MOSFET Small Signal Models in the

Saturation Region

In order to illustrate the concepts of small signal models as they apply to MOS-

FET modeling, we consider the MOSFET current expressions in the saturation

region. The current expressions we consider are best for long-channel MOS-

FETs. We’ll use these expressions since they are reasonably easy to understand

and to manipulate. However, one should be careful when applying these formu-

las to short-channel devices.

Recall that the MOSFET current expression in the saturation region for an

NMOS device is given by

IDS =1

2µnCox

W

L(VGS − VT )2 (1 + λVDS) (4.1.1)

in which µn is the electron mobility,Cox is the per-unit-area gate oxide capac-

itance,W is the width of the gate,L is the length of the gate,VGS is the total

voltage between the gate and the source,VT is the threshold voltage (which

depends upon the bulk-to-source voltage),λ is the channel length modulation

coefficient, andVDS is the voltage from the drain to the source.

An Analytical Expression for gm

If we apply the definition ofgm given by equation (4.0.1) to equation (4.1.1),

we can arrive at an analytical expression forgm in terms of the parameters in


equation (4.1.1) as follows:

gm =∂IDS

∂VGS

∣∣∣∣VBS ,VDS constant

(4.1.2)

=∂

∂VGS

(1

2µnCox

W

L(VGS − VT )2 (1 + λVDS)

)(4.1.3)

= µnCoxW

L(VGS − VT ) (1 + λVDS) (4.1.4)

An alternative expression forgm can be written if we solve (4.1.1) for(VGS − VT )

and substitute the resulting expression in (4.1.4). Using these manipulations

givesgm in terms ofIDS as,

gm =

√2µnCox

WL

IDS

1 + λVDS

(4.1.5)

Interestingly, from (4.1.5) we see thatgm ∝√

IDS. Later we will see thatgm

appears in many of our circuit small signal gain formulas. So from now we can

anticipate that the small signal gain of our circuits will be proportional to the

square root of the bias current.

An Analytical Expression for gmb

The effect on the drain to source current due to changes in the bulk-to-source

voltage,vBS is encapsulated in the definition ofgmb. The bulk-to-source voltage

can be used to create a number of interesting analog processing circuits. First,

we need to derive an analytical expression forgmb.

Application of the definition ofgmb given by equation (4.1.6) to equation (4.1.1)

yields an analytical expression forgmb in terms of the parameters in equation (4.1.1).

There are a few mathematical tricks that are used to arrive at the final expression.


Starting with the basic definition,

gmb =∂IDS

∂VBS


(4.1.6)

the chain rule is used to express the partial derivative given in (4.1.6) as the

product of two partial derivatives:

gmb =∂IDS

∂VTH

∂VTH

∂VBS


(4.1.7)

If channel length modulation is negligible, thenλ ≈ 0 and the term∂IDS

∂VTHcan be

evaluated using (2.8.5) giving

gmb = −µCoxW

L(VGS − VTH)

∂VTH

∂VBS


(4.1.8)

in which VTH is given by (2.7.1). Furthermore, since∂VTH

∂VBS= −∂VTH

∂VSB, we can

evaluate the remaining partial derivative term using (2.7.1), yielding,

gmb = µCoxW

L(VGS − VTH)

γ

2√

2ΦF + VSB

(4.1.9)

Some noteworthy points on (4.1.9) include:

• The small-signal substrate transconductance is proportional to the body

effect coefficientγ.

• As the bulk-to-source voltage increases (VBS increases), more current will

flow from the drain to the source sincegmb is positive. For this reason, the

substrate is often called theback gatesince in effect it acts as a second

gate.

• From (4.1.9), a decrease inVSB implies thatgmb increases∗.∗Interestingly, (4.1.9) implies that ifVSB = −2ΦF , the small-signal substrate transconduc-

tance is infinite. It would be an interesting exercise to explain this apparent discrepancy.


Substitutinggm from (4.1.5) into (4.1.9), under the assumption thatλ ≈ 0,

gives a common expression forgmb,

gmb = ηgm (4.1.10)

in whichη = γ2(2ΦF + VSB)−

12 .

An Analytical Expression for gd

Judging from the finite slope in theIDS versusVDS curve, even in the saturation

region, as shown in Figure 2.5, we can anticipate thatIDS is affected by changes

in VDS. This relation is captured by the small signal drain conductancegd as

defined in (4.0.3). An analytical expression forgd in terms of the parameters in

equation (4.1.1) is found as

gd =∂IDS

∂VDS

∣∣∣∣VBS ,VGS constant

(4.1.11)

=∂

∂VDS

(1

2µnCox

W

L(VGS − VT )2 (1 + λVDS)

)(4.1.12)

=1

2µnCox

W

L(VGS − VT )2 λ (4.1.13)

≈ IDSλ (4.1.14)

where the final approximation is made assuming thatλVDS 1. As could

be expected, the small signal drain conductance is directly proportional to the

channel modulation coefficientλ. A second interesting observation is that the

small signal drain conductance is also proportional to the drain to source current

IDS.

The small signal drain conductance is often modeled as a resistor between


the drain and the source. The resistance is given by

ro =1

gd

(4.1.15)

=1

12µnCox

WL

(VGS − VT )2 λ(4.1.16)

≈ 1

IDSλ(4.1.17)

Note that as the channel modulation coefficient increases, the MOSFET small

signal drain resistance decreases. This can be a problem in deep sub-micron

designs with large values ofλ. Also, as the device bias current increases the

output resistance drops. This trade-off will gain significance in the expressions

for small-signal gain encountered later for various analog processing blocks.

Building a Small Signal Model: Adding gm.

At this point, having evaluatedgm, we can think about what this quantity really

means and how we might use it in a circuit analysis. What (4.0.1) is telling us is

that if VGS changes we can expect some sort of a change in the currentIDS due

to this change. If we assume that a small change inVGS gives us a small change

in IDS that is linearly proportional to the small change inVGS, we can estimate

how muchIDS changes by using a simple linear expession of the form,

∆IDS = κ∆VGS (4.1.18)

in which ∆IDS is the estimated change inIDS, ∆VGS is the small change in

VGS, andκ is the proportionality constant relating the small change inVGS to the

estimated linearly proportional change inIDS. Solving (4.1.18) forκ gives,

κ =∆IDS

∆VGS

(4.1.19)


If you compare (4.1.19) to (4.0.1), you can see that if we make∆VGS small,

(4.1.19) approaches the definition ofgm given in (4.0.1). In other words, for

small∆VGS we have

∆IDS = gm∆VGS (4.1.20)

We can represent (4.1.20) using a voltage-controlled current source, as shown

in XXX. We can use the circuit shown in XXX if we understand that certain

conditions apply, namely,

• Any change inVGS is represented by∆VGS.

• ∆VGS should be small.

• Except forVGS, all other terminal voltages are held constant.

It is important to recognize that the circuit in XXX gives us∆IDS in terms of

∆VGS. It does not give usIDS in terms ofVGS. In order to get the actual value of

IDS, we need to add the “original value” ofIDS plus the change inIDS (which

is given by∆IDS).

The expression forIDS is therefore given by

IDS = IDS (4.1.21)

the change in can be evaluated using the large signal IDS equations for each

region of operation of the MOSFET. Saturation Region: For the saturation re-

gion, the small signal transconductances and the drain conductance are given by,

(1.4) (1.5) and (1.6) where in (1.5) is a factor that describes how the threshold

voltages changes with reverse body bias. For small , . Triode Region: For the

saturation region, the small signal transconductances and the drain conductance

are given by, (1.7) (1.8) and (1.9) where in (1.5) is a factor that describes how

the threshold voltages changes with reverse body bias. For small , . Subthresh-

old Region: For the saturation region, the small signal transconductances and

the drain conductance are given by, (1.10) (1.11) and (1.12) where in (1.5) is a


factor that describes how the threshold voltages changes with reverse body bias.

For small , .

The small signal model shown in XXX is only valid at very low frequencies.

At higher frequencies capacitances present in the MOSFET must be included

in the small signal model, and at radio frequencies distributed effects must be

taken into account. In the next section these two factors are explored and the

small signal model is revised.

The Link Between Large Signal and Small Signal Models

Large signal and small signal models are linked together by device current.

The small signal model represents the linearized MOSFET operating around

some bias point. We are free to choose the bias points. Normally we choose the

bias point such that certain performance specifications are realized. For example,

if we are designing an amplifier we might choose the bias points that will give

us sufficient gain. Often the bias point is called the Q-point or quiescent point.

[page 25 figure] Note that there is some distortion in the output. The amount of

distortion depends on the amplitude of the input, and the linearity of the circuit.

When we use linear small signal models, we ignore the nonlinear characteristics

of the devices in our circuits. Simulations that use such linearized models do

not give any indication of the distortion caused by the circuit. An example of

a simulation that would not show distortion is an AC analysis in SPICE. Also

noteworthy in XXX is that the output is inverted compared to the input. How did

this happen? To see how, consider that as the input voltage increases, the gate-to-

source voltage of M1 also increases. Recall that the current in the mosfet varies

according to (1.13)

Chapter 5

MOSFET Capacitances

At high operating frequencies the effects of parasitic capacitances on the oper-

ation of the MOSFET cannot be ignored. Transistor parasitic capacitances are

subdivided into two general categories; extrinsic capacitances and intrinsic ca-

pacitances. The extrinsic capacitances are associated with regions of the transis-

tor outside the dashed line shown in Figure 5.1, while the intrinsic capacitances

are all those capacitances located within the region illustrated in Figure 5.1.

Figure 5.1: The MOSFET intrinsic region.

33

CHAPTER 5. MOSFET CAPACITANCES 34

5.1 Extrinsic Capacitances

Extrinsic capacitances are modeled by using lumped capacitances, each of which

is associated with a region of the transistor’s geometry. Seven small-signal ca-

pacitances are used, one capacitor between each pair of transistor terminals, plus

an additional capacitor between the well and the bulk if the transistor is fabri-

cated in a well. Figure 5.2 demonstrates the location of each capacitance within

the transistor structure for an nmos MOSFET.

Figure 5.2: The MOSFET extrinsic capacitances. Note that there is no well-to-bulk capacitance in this case.

Gate Overlap Capacitances

Although MOSFETs are manufactured using a self-aligned process, there is still

some overlap between the gate and the source and the gate and the drain. This

overlapped area gives rise to the gate overlap capacitances denoted byCGSO and

CGDO for the gate-to-source overlap capacitance and the gate-to-drain overlap

capacitance respectively. Both capacitancesCGSO andCGDO are proportional to

the width,W , of the device and the amount that the gate overlaps the source and


the drain, typically denoted as “LD” in SPICE parameter files. The overlap ca-

pacitances of the source and the drain are often modeled as linear parallel-plate

capacitors, since the high dopant concentration in the source and drain regions

and the gate material implies that the resulting capacitance is largely bias inde-

pendent. However, for MOSFETs constructed with a lightly-doped-drain (LDD-

MOSFET), the overlap capacitances can be highly bias dependent and therefore

non-linear. For a treatment of overlap capacitances in LDD-MOSFETs, refer to

Park7. For non-lightly-doped-drain MOSFETs, a rough estimation of the gate-

drain and gate-source overlap capacitances can be made using the the expression

CGSO = CGDO = W LD Cox (5.1.1)

whereLD is the lateral diffusion distance,W is the gate width, andCox is the

per-unit-area gate oxide capacitance.

The overlap distance,LD, is typically small, and so fringing field lines add

significantly to the total capacitance rendering (5.1.1) inaccurate. Since the exact

calculation of the fringing capacitance requires an accurate knowledge of the

drain and source region geometry, estimates of the fringing field capacitances

based on measurements are normally used. The gate-to-source and gate-to-drain

overlap capacitances are normally calculated using measured parameters given

in the MOSFET model files. Since the lateral diffusion distance is different for

an NMOS device compared to a PMOS device, there are separate values given

for NMOS MOSFETs and PMOS MOSFETs. These values are per-unit-width

quantities, typically given in F/m, and hence the overlap capacitances may be

calculated as

CGSO = W CGSO (5.1.2)

CGDO = W CGDO (5.1.3)

in whichCGDO is the per-unit-width overlap capacitance for the drain area and

CGSO is the per-unit-width overlap capacitance for the source area.


Extrinsic Junction Capacitances

When a reverse voltage is applied to a PN junction , the holes in the p-region

are attracted to the anode terminal and electrons in the n-region are attracted to

the cathode terminal. The resulting region contains almost no carriers, and is

called the depletion region. The depletion region acts similarly to the dielectric

of a capacitor. The depletion region increases in width as the reverse voltage

across it increases. If we imagine that the diode capacitance can be likened to a

parallel plate capacitor, then as the plate spacing (i.e. the depletion region width)

increases, the capacitance should decrease. Increasing the reverse bias voltage

across the PN junction therefore decreases the diode capacitance.

At the source region there is a source-to-bulk junction capacitance,CjBS,e,

and at the drain region there is a drain-to-bulk junction capacitance,CjBD,e.

These capacitances can be calculated by splitting the drain and source regions

into a “side-wall” portion and a “bottom-wall” portion. The capacitance associ-

ated with the side wall portion is found by multiplying the length of the side-wall

perimeter (excluding the side contacting the channel) by the effective side-wall

capacitance per unit length. Similarly, the capacitance for the bottom-wall por-

tion is found by multiplying the area of the bottom-wall by the bottom-wall

capacitance per unit area. Additionally, if the MOSFET is in a well, a well-

to-bulk junction capacitance,CjBW,e, must be added. The well-bulk junction

capacitance is calculated similarly to the source and drain junction capacitances,

by dividing the total well-bulk junction capacitance into side-wall and bottom-

wall components. If more than one transistor is placed in a well, the well-bulk

junction capacitance should be included only once in the total model.

Both the effective side-wall capacitance and the effective bottom-wall capac-

itance are bias dependent. Normally the per unit length zero-bias side-wall ca-

pacitance and the per unit area zero-bias bottom-wall capacitance are estimated

from measured data. The values of these parameters for nonzero reverse-bias

conditions are then calculated using the formulas given in Table 5.1.


Ext

rinsi

cS

ourc

eC

apac

i-ta

nce

CjB

S,e

=C

′ jBSA

S+

C′′ js

wB

SP

S

C′ jB

S=

C′ j

( 1−

VB

Sφ

j

) m jC

′′ jsw

BS

=C

′′ jsw

( 1−

VB

Sφ

jsw

) m jsw

Ext

rinsi

cD

rain

Cap

acita

nce

CjB

D,e

=C

′ jBDA

D+

C′′ js

wB

DP

D

C′ jB

D=

C′ j

( 1−

VB

Dφ

j

) m jC

′′ jsw

BD

=C

′′ jsw

( 1−

VB

Dφ

jsw

) m jsw

Ext

rinsi

cW

ellC

apac

itanc

eC

jBW

,e=

C′ jB

WA

W+

C′′ js

wB

WP

W

C′ jB

W=

C′ j

( 1−

VB

Wφ

j

) m jC

′′ jsw

BW

=C

′ jsw

( 1−

VB

Wφ

jsw

) m jsw

Not

es:

mjan

dm

jsw

are

proc

ess

depe

nden

t,ty

pica

lly1/3..

.1/2

.

C′ j=

√ ε siqN

B

2φ

j

C′′ js

w=

√ ε siqN

B

2φ

jsw

Whe

re:φ

jan

dφ

jsw

are

the

built

-inju

nctio

npo

-te

ntia

lan

dsi

de-w

all

junc

tion

pote

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ls,

resp

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diel

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icco

nsta

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AS,A

D,a

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eth

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Tabl

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OS

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TE

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Junc

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Cap

acita

nces


Extrinsic Source-Drain Capacitance

Accurate models of short channel devices may include the capacitance that exists

between the source and drain region of the MOSFET. The source-drain capac-

itance is denoted asCsd,e. Although the source-drain capacitance originates in

the region within the intrinsic region as shown in Figure 5.1, it is still referred to

as an extrinsic capacitance.1 The value of this capacitance is difficult to calculate

because its value is highly dependent upon the source and drain geometries. For

longer channel devices,Csd,e is very small in comparison to the other extrinsic

capacitances, and is therefore normally ignored.

Extrinsic Gate-Bulk Capacitance

As with the gate-to-source and gate-to-drain overlap capacitances, there is a

gate-to-bulk overlap capacitance caused by imperfect processing of the MOS-

FET. The parasitic gate-bulk capacitance,CGB,e, is located in the overlap region

between the gate and the substrate (or well) material outside the channel region.

The parasitic extrinsic gate-bulk capacitance is extremely small in comparison

to the other parasitic capacitances. In particular, it is negligible in comparison to

the intrinsic gate-bulk capacitance. The parasitic extrinsic gate-bulk capacitance

has little effect on the gate input impedance and is therefore generally ignored in

most models.

5.2 Intrinsic Capacitances

Intrinsic MOSFET capacitances are significantly more complicated than extrin-

sic capacitances because they are a strong function of the voltages at the termi-

nals and the field distributions within the device. Although intrinsic MOSFET

capacitances are distributed throughout the device, for the purposes of simpler

modeling and simulation the distributed capacitances are normally represented

by lumped terminal capacitances. The terminal capacitances are derived by con-


sidering the change in charge associated with each terminal with respect to a

change in voltage at another terminal, under the condition that the voltage at

all other terminals is constant. The five intrinsic small-signal capacitances are

therefore expressed as,

Cgd,i =∂QG

∂VD

∣∣∣∣VG,VS ,VB

(5.2.1)

Cgs,i =∂QG

∂VS

∣∣∣∣VG,VD,VB

(5.2.2)

Cbd,i =∂QB

∂VD

∣∣∣∣VG,VS ,VB

(5.2.3)

Cbs,i =∂QB

∂VD

∣∣∣∣VG,VD,VB

(5.2.4)

and,

Cgb,i =∂QG

∂VB

∣∣∣∣VG,VS ,VD

(5.2.5)

These capacitances are evaluated in terms of the region of operation of the

MOSFET, which is a function of the terminal voltages. Detailed models for each

region of operation were investigated by Cobbold.8 Simplified expressions are

given here in Table 5.2, for the triode and saturation operating regions.

Operating Re-gion

Cgs,i Cgd,i Cgb,i Cbs,i Cbd,i

Triode ≈ 12Cox ≈ 1

2Cox ≈ 0 k0Cox k0Cox

Saturation ≈ 23Cox ≈ 0 k1Cox k2Cox ≈ 0

Notes:Triode region approximations are forVDS = 0.k0, k1,andk2are bias dependent. See1.

Table 5.2: Intrinsic MOSFET Capacitances

The total terminal capacitances are then given by combining the extrinsic

capacitances and intrinsic capacitances according to,


Cgs = Cgs,i + Cgs,e = Cgs,i + Cgso

Cgd = Cgd,i + Cgd,e = Cgd,i + Cgdo

Cgb = Cgb,i + Cgb,e = Cgb,i + Cgbo

Csb = Cbs,i + Csb,e = Cbs,i + Cjsb

Cdb = Cbd,i + Cdb,e = Cbd,i + Cjdb

(5.2.6)

in which the small-signal form of each capacitance has been used.

The contribution of the total gate-to-channel capacitance, CGC , to the gate-

to-drain and gate-to-source capacitances is dependent upon the operating region

of the MOSFET. The total value of the gate-to-channel capacitance is deter-

mined by the per unit area capacitance Cox and the effective area over which the

capacitance is taken. Since the extrinsic overlap capacitances include some of

the region under the gate, this region must be removed when calculating the gate

to channel capacitance. This is shown schematically in Figure 5.3, in which the

gate overlap distances are exaggerated for visibility.

Figure 5.3: MOSFET processing involves diffusion of dopants into the sub-strate. This diffusion is caused by baking the wafer containing the ion-implanteddopants. The ion-implanted dopants are initially close to the surface, but whenheated tend to diffuse deeper into the substrate. Unfortunately, the dopants alsodiffuse under the gate region, giving rise to the gate overlap areas.

The effective channel length, Leff, is given byLeff = L − 2LD so that the

gate to channel capacitance can be calculated by the formulaCGC = CoxW Leff.


The total value of the gate to channel capacitance is split between the drain and

source terminals according to the operating region of the device. When the de-

vice is in the triode region, the capacitance exists solely between the gate and the

channel and extends from the drain to the source. Its value is therefore evenly

split between the terminal capacitances Cgs and Cgd as shown in??. When the

device operates in the saturation region, the channel does not extend all the way

from the source to the drain. No portion of CGC is added to the drain terminal

capacitance under these circumstances. Again, as shown in??, analytical calcu-

lations demonstrated that an appropriate amount of CGS to include in the source

terminal capacitance is 2/3 of the total.1

Finally, the channel to bulk junction capacitance, CBC , should be considered.

This particular capacitance is calculated in the same manner as the gate to chan-

nel capacitance. Also similar to the gate to channel capacitance proportioning

between the drain in the source when calculating the terminal capacitances, the

channel to bulk junction capacitance is also proportioned between the source to

bulk and drain to bulk terminal capacitances depending on the region of opera-

tion of the MOSFET.

5.3 Wiring Capacitances

Referring to Figure 2.1, one can see that the drain contact interconnect over-

lapping the field oxide and substrate body forms a capacitor. The value of this

overlap capacitance is determined by the overlapping area, the fringing field, and

the oxide thickness. Reduction of the overlapping area will decrease the capaci-

tance to a point, but with an undesirable increase in the parasitic resistance at the

interconnect to MOSFET drain juncture. The parasitic capacitance occurring at

the drain is particularly troublesome due to the Miller effect, which effectively

magnifies the parasitic capacitance value by the gain of the device. The intercon-

nects between MOSFET devices also add parasitic capacitive loads to the each

device. These interconnects may extend across the width of the IC in the worst


case, and must be considered when determining the overall circuit performance.

Modern CMOS processes employ thick field-oxides that reduce the parasitic

capacitance that exists at the drain and source contacts, and between intercon-

nect wiring and the substrate. The thick field-oxide also aids in reducing the

possibility of unintentional MOSFET operation in the field region.

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