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Chapter 12

Additional Design Examples

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Design of a Wristwatch 1

� Timekeeping, alarm, and stopwatch functions.

� Three buttons (B1, B2, and B3):

� B1 changes the mode from Time to Alarm.

� B2 and B3 vary depending on the mode.

� Operation in time mode:

� Display time and A.M./P.M. (hh:mm:ss (A or P)).

� B3 shuts off the alarm manually.

� B2 changes the state to Set Hours, Set Minutes, and back to Time.

� In Set Hours and Set Minutes, B3 advances the hours or minutes by 1.

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Design of a Wristwatch 2

� Operation in alarm mode:� Display alarm time and A.M./P.M. (hh:mm (A or P)).� B3 sets or resets the alarm.� B2 changes the state to Set Alarm Hours or Set Alarm

Minutes and then back to Alarm.� In Set Alarm mode, B3 advances hours or minutes by 1.� The alarm will ring for 50 seconds if not shut off

manually.

� Operation in stopwatch mode:� Display stopwatch time (mm:ss.cc), where cc is

hundredths of a second.� B2 starts and stops the time counter.� B3 resets the time counter.� Stopwatch will keep running in Time and Alarm modes.

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Design of a Wristwatch 3

� Block diagram:

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State Graph of Wristwatch Module

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Wristwatch Module 1

� The wristwatch module contains:

� Main control

� Clock module (implements timekeeping and alarm functions)

� Stopwatch module (implements stopwatch functions)

� The 100-Hz clock synchronizes operation of the control unit and time registers.

� The VHDL code for the wristwatch module instantiates clock and stopwatch modules, and implements the state machine.

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Wristwatch Module 2

� The clock module contains the counters that keep track of time as well as the counters that are used to store the alarm time.

� It contains a counter that divides the 100-Hz clock by 100 and provides a signal to increment the seconds counter.

� The clock VHDL code also implements the alarm functions.

� Stopwatch VHDL code instantiates counters for hundredths of a second, seconds, and minutes.

� Divide-by-60 counter counts to 59 and resets.� Hours counter counts to 12 and toggles A.M./P.M.

when the count changes from 11 to 12.

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Testing the Wristwatch

� Testing the Wristwatch:� Test bench takes the place of the input and display modules.� Two procedures:

� wait1(N1) waits for N1 clocks.� push(button, N) simulates pushing a button N times.

� Test sequence used:1. Set the time to 11:58 P.M.2. Set the alarm time to 12:00 A.M.3. Set the alarm and change to time mode, and wait until the time

rolls over at midnight.4. Turn off the alarm 5 seconds later.5. Change to stopwatch mode and start the stopwatch.6. Switch to time mode and wait for 10 seconds (stopwatch keeps

running).7. Switch back to stopwatch mode and wait until it reads 1 minute

and 2 seconds.8. Stop the stopwatch, reset it, and return to time mode.

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Memory Timing Models

� Must develop accurate timing models for components in order to simulate a complex system.

� We will develop a timing model for a small static RAM.

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Block Diagram of 6116 static RAM

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Universal Asynchronous Receiver Transmitter 1

� By using a modem connected to a serial port, serial data can be transmitted and received via telephone lines.

� The serial communication interface is often called a UART (universal asynchronous receiver-transmitter).

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Universal Asynchronous Receiver Transmitter 2

� There is no clock line, so data (D) is transmitted asynchronously, one byte at a time.

� When no data is being transmitted, D remains high.

� D goes low for one bit time to mark the start of transmission (start bit).

� Eight data bits are transmitted, with the least significant bit first. 8th bit may be used as a parity check.

� After 8 bits are transmitted, D must go high for at least one bit time.

� The number of bits transmitted per second is the baud rate.

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Universal Asynchronous Receiver Transmitter 3

� Standard serial data format:

� When transmitting, the UART takes 8 bits of parallel data and converts the data to a serial data format.

� When receiving, the UART detects the start bit, receives the 8 data bits, and converts the data to parallel form when it detects the stop bit.

� The UART must synchronize the incoming bit stream with the local clock.

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UART Block Diagram

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UART Main Components

� Main components (besides registers):

� Baud rate generator – divides down the system clock to provide the bit clock.

� Receiver controller.

� Transmitter controller.

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SM Chart for the UART Transmitter

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VHDL Code for the UART Transmitter 1

� VHDL code for the UART transmitter:

� Based on previous SM chart.

� First process represents the combinational network, which generates the nextstate and control signals.

� Second process updates the registers on the rising edge of the clock.

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VHDL Code for the UART Transmitter 2

� The bit stream coming in on RxD is not synchronized with the local bit clock, so we sample RxD eight times during each bit time.

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SM Chart for UART Receiver

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VHDL Code for the UART Receiver 1

� VHDL code for the UART receiver:

� Based on previous SM chart.

� First process represents the combinational network, which generates the nextstate and control signals.

� Second process updates the registers on the rising edge of the clock.

� Resulting implementation of the receiver requires 26 flip-flops, 21 slices, and 32 4-input LUTs.

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VHDL Code for the UART Receiver 2

� Programmable baud rate generator: select any one of eight baud rates.

� Block diagram:

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VHDL Code for Baud Rate Generator 1

� VHDL code for baud rate generator:

� First process increments the divide-by-13 counter on the rising edge of the system clock.

� Second process increments the divide-by-256 counter on the rising edge of Clkdiv13. A concurrent statement generates the MUX output, BclkX8.

� Third process increments the divide-by-8 counter on the rising edge of BclkX8 to generate Bclk.

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VHDL Code for Baud Rate Generator 2

� To complete the UART design, we need to interconnect the three components, connect them to the control and status registers, and add the interrupt generation logic and the bus interface.

� When synthesized with the Xilinx SPARTAN 3, the resulting implementation required 62 slices, 109 4-input LUTs, and 74 flip-flops.

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