Chapter 10Chapter 10

Fundamentals of Wafer-Level Fundamentals of Wafer-Level PackagingPackaging

Jason MucilliJason Mucilli

Vincent WuVincent Wu

October 1, 2007October 1, 2007

What is Wafer-Level What is Wafer-Level Packaging?Packaging?

IC packaging formed at the wafer level on the wafer in IC packaging formed at the wafer level on the wafer in the wafer foundrythe wafer foundry Front end IC fabrication and back end IC assembly performed Front end IC fabrication and back end IC assembly performed

at wafer foundryat wafer foundry CSP (chip-scale package)CSP (chip-scale package)

20% larger than IC’s-done ass single chip packages at IC level, 20% larger than IC’s-done ass single chip packages at IC level, assembled by standard SMT, encapsulated and testedassembled by standard SMT, encapsulated and tested

Flip ChipFlip Chip Done at wafer level and solder bonded with face downDone at wafer level and solder bonded with face down

Wafer level packagingWafer level packaging Goes extra step in forming electrical connections on the wafer, Goes extra step in forming electrical connections on the wafer,

assembled face down but with SMT equipment, then assembled face down but with SMT equipment, then encapsulating, testing and singulating as packaged IC’sencapsulating, testing and singulating as packaged IC’s

What is Wafer-Level What is Wafer-Level Packaging? Cont.Packaging? Cont.

Today’s wafer and IC packaging vs. new Today’s wafer and IC packaging vs. new wafer level packaging process:wafer level packaging process:

Why Wafer-level Why Wafer-level packaging?packaging?

Possible benefitsPossible benefits Smallest system sizeSmallest system size Enabling interconnect continuum from IC to PWB Enabling interconnect continuum from IC to PWB

because of thin-film processingbecause of thin-film processing Reduced cost of packaging, testing and burn-in Reduced cost of packaging, testing and burn-in

because all done at the wafer levelbecause all done at the wafer level Elimination of underfill because compliancy of leads Elimination of underfill because compliancy of leads

or other ways to achieve reliabilityor other ways to achieve reliability Improved electrical performance due to short lead Improved electrical performance due to short lead

lengthslengths

Why Wafer-level Why Wafer-level packaging? Cont.packaging? Cont.

Size benefitsSize benefits Shrinking size of portable and hand-held Shrinking size of portable and hand-held

electronic deviceselectronic devices Ultimate IC packaging option-the package Ultimate IC packaging option-the package

and the area it occupies on the PWB are and the area it occupies on the PWB are equal to the size of an ICequal to the size of an IC

Why Wafer-level Why Wafer-level packaging? Cont.packaging? Cont.

Cost benefits-achieved by 2 techniques:Cost benefits-achieved by 2 techniques: Increasing wafer size results in more IC’s per waferIncreasing wafer size results in more IC’s per wafer Decreasing feature size on the IC- causes “die-Decreasing feature size on the IC- causes “die-

shrinks” which result in more IC’s for a given wafer shrinks” which result in more IC’s for a given wafer sizesize

Equipment CostsEquipment Costs As wafer gets larger, the cost of the equipment also As wafer gets larger, the cost of the equipment also

goes upgoes up Cost increase is more than offset by increased production Cost increase is more than offset by increased production

capacitycapacity

DisadvantagesDisadvantages Incompatibility of PWBIncompatibility of PWB

Very high I/O IC’s would require very small solder Very high I/O IC’s would require very small solder balls on a very tight pitchballs on a very tight pitch

Requires very high density PWB to interconnect-Requires very high density PWB to interconnect-expensiveexpensive

Why Wafer-level Why Wafer-level packaging? Cont.packaging? Cont.

Disadvantages Cont.Disadvantages Cont. ALL the IC’s (good and bad) are packaged ALL the IC’s (good and bad) are packaged

at the wafer levelat the wafer level Results in bad IC’s packaged early on when Results in bad IC’s packaged early on when

yields are lowyields are low

WLP TechnologiesWLP Technologies Evolution of the Silicon wafer in sizeEvolution of the Silicon wafer in size

30 years ago-82.5mm30 years ago-82.5mm Now-300mmNow-300mm Factor of 10 in IC productivity-also drives down costFactor of 10 in IC productivity-also drives down cost

WLP Technologies Cont.WLP Technologies Cont.

More than a dozen different ways of More than a dozen different ways of forming wafer-level packages: 3 forming wafer-level packages: 3 categoriescategories Redistributing WLPRedistributing WLP Encapsulated WLPEncapsulated WLP Flex/Tape WLPFlex/Tape WLP

Redistribution of WLP Redistribution of WLP TechnologiesTechnologies

WLP ProcessesWLP Processes RedistributionRedistribution Flip-Flop technologyFlip-Flop technology

Figure 10.10Figure 10.10

Redistribution of WLP Redistribution of WLP Technologies cont.Technologies cont.

Redistribution of WLP Redistribution of WLP Technologies cont.Technologies cont.

Redistribution of WLP Redistribution of WLP Technologies cont.Technologies cont.

Redistribution of WLP Redistribution of WLP Technologies cont.Technologies cont.

Redistribution technology offers Redistribution technology offers protectionprotection

WLP technology use same technology as WLP technology use same technology as flip chip or bare die direct chip flip chip or bare die direct chip attachment to organic boardattachment to organic board Difference in solder balls sizeDifference in solder balls size

Encapsulated WLP Encapsulated WLP TechnologiesTechnologies

Encapsulated technologyEncapsulated technology Seals the chip between glass plates.Seals the chip between glass plates.

Peripheral PadsPeripheral Pads Technology and material similar to redistribution. Technology and material similar to redistribution.

Wafer Wafer Front and BacksideFront and Backside ThicknessThickness lithography lithography

Encapsulated WLP Encapsulated WLP TechnologiesTechnologies

Flex Tape WLP Technologies Flex Tape WLP Technologies

Flex Tape WLPFlex Tape WLP Conventional flex tapeConventional flex tape

Copper-polyimide flex tapeCopper-polyimide flex tape WaferWafer

IC IC Connected by wirebondingConnected by wirebonding

Liquid encapsulantLiquid encapsulant protectionprotection

Flex Tape WLP Technologies Flex Tape WLP Technologies cont. cont.

WLP ReliabilityWLP Reliability

Fundamentals of reliabilityFundamentals of reliability Coffin-MasonCoffin-Mason Modified EquationModified Equation

Reliable connectionReliable connection Four WaysFour Ways

WLP Reliability cont.WLP Reliability cont.

Has been used for over 30 years.

Need for Underfill in WLPNeed for Underfill in WLP

WLP WLP IC packaging technology at wafer level w/o uIC packaging technology at wafer level w/o u

nderfill is reliable.nderfill is reliable.

But…But… Interconnection b/w IC board rigid connectioInterconnection b/w IC board rigid connectio

nn Ex. Solder Ex. Solder

Need for Underfill in WLP cont.Need for Underfill in WLP cont.

UnderfillUnderfill Distributes stress across the substrate and PDistributes stress across the substrate and P

WBWB Minimize stress concentration in solder ballsMinimize stress concentration in solder balls

Increase Lifetime in thermal shock Increase Lifetime in thermal shock

Need for Underfill in WLP cont.Need for Underfill in WLP cont.

Need for Underfill in WLP cont.Need for Underfill in WLP cont.

Wafer-Level Burn-In and TestWafer-Level Burn-In and Test

Low-cost WLPLow-cost WLP Wafer-level and Tests (necessity)Wafer-level and Tests (necessity)

Non-destructive probing and Non-destructive probing and technologiestechnologies

Wafer-Level Burn-in and TestWafer-Level Burn-in and Test

Summary and Future TrendsSummary and Future Trends

Wafer-level Packaging technologyWafer-level Packaging technology Fundamental advantageFundamental advantage

Cost, Size, electrical performance, and Reliability.Cost, Size, electrical performance, and Reliability.

Ultimate IC packaging technologyUltimate IC packaging technology So far…So far…

Mostly small I/O ICs.Mostly small I/O ICs. High I/O with very high pitch. (still needs to High I/O with very high pitch. (still needs to

be worked on)be worked on)

Summary and Future Trends Summary and Future Trends cont.cont.

Summary and Future Trends Summary and Future Trends cont.cont.