ch.7 layout design
DESCRIPTION
Standard Cell Design. Ch.7 Layout Design. TAIST ICTES Program VLSI Design Methodology Hiroaki Kunieda Tokyo Institute of Technology. Layout Design. Netlist. Layout Design. Functional Verification. Layout Netlist. Gate Level Simulatior. ATPG. Mask Data. DRC/LVS. Test Pattern. - PowerPoint PPT PresentationTRANSCRIPT
Ch.7 Layout Design
Standard Cell Design
TAIST ICTES ProgramVLSI Design Methodology
Hiroaki Kunieda
Tokyo Institute of Technology
Layout Design
Gate Level Simulatior
Layout Design
Netlist
Mask Data
Layout Netlist
DRC/LVS
Functional Verification
ATPG
TestPattern
Layout Procedure
Floorplaning
Placement
Clock Tree Generation
Routing
Whole picture
Assign standard cells on a column in a row so as to minimize the total wiring lengths.
Inverters are inserted Clock Distribution Not to get clock skew
Assign interconnection wires to tracks inrouting channels.
7.1 Floor Planning
1.Floor Planning Floorplanning is chip-
level layout design. Blocks or cells of a
variety of shapes and sizes, estimated.
Purpose is to derive interface requirement and to estimate budget for each block design.
Standard Cell Floor Plan
Cell Model
7.2 Placement
Min-cut Placement
Step 1. Cut the placement area into two pieces.
Step 2. Swap the logic cells to minimize the cut cost.
Step 3. Repeat the process from step 1, cutting smaller pieces until all the logic cells are placed.
(a) Divide the chip into bins using a grid. (b) Merge all connections to the center of each bin. (c) Make a cut and swap logic cells between bins to minimize the cost of the cut. (d) Take the cut pieces and throw out all the edges that are not inside the piece. (e) Repeat the process with a new cut and continue until we reach the individual bins.
Placement Result
Filler Cell
The purpose of filler cells is to maintain continuity in the rows by adding vdd! and gnd! lines and an n-well. The filler cells also contain substrate connections to improve substrate biasing.
7.3 Timing and Clock
Timing Problem
dssuskewd t t ttodclock peri td: Longest path through combinational logictskew: Clock skewtsu: Setup time of the synchronizing elementstds: Propagation delay within the synchronizing element
Zero Skew Routing
1. FF Clustering Adjacent FF into the same cluster Load balance among clusters Limit to the maximum load
2. Buffer insertion Zero skew joint by bottom up
3. Equi-delay clock tree routing Binary Tree by bottom up
Clock Insertion Algorithm
Cluster 3
Cluster 4
Cluster 5
Cluster 6
Cluster 1Cluster 2
1. Cluster a group of close FFs 2. Binary tree routing for clusters3. Insert optimum number of
buffers at bifurcation points.4. Equi-distant routing in each
cluster.
1. Cluster Routing
2. Buffer Insertion for Zero Skew
3. Equi-distant routing in Cluster
7.4 Routing
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Routing
Special Route
Clock Route
Global Route
Search and Repair
Warp Route
Final Route
or
layout
connect power /ground net : ring , stripe, block, IO pad , IO ring and standard cell
connect clock net
connect all regular net G/FRoute : classic router WRoute : super high speed router (use area based algorithm)
search and repair routing violation
Channel Router for Standard Cells
1. Global Router2. Channel Router3. Switch Box Wiring
Simple Channel Routing
Horizontal constraint
do not assign overlapping nets into the same horizontal track
Horizontal constraint graph
Color nodes with the minimum number with different colors for nodes which has edge between them.
Vertical constraint graph
Vertical constraint graph
The direction of edge indicates that the track number of the node with outgoing edge must be younger than nodes with incoming edge
Optimum under assumption that only one horizontal wire segment per net.
Left-edge channel routing
Channel that cannot be routed by the left edge algorithm(Vertical constraint)
A dogleg wire
Layout after Routing
7.5 Pad
5. I/O Architecture
Output design
Output Pad
Input Pad ElectroStatic Discharge
(ESD) Protection npn tr. limits VSS-0.7V pnp tr limits VDD+0.7V
Input Pad
Pad Layout Design
7.6 Package
Packages
Before bonding
DIP (Dual in-line)
PLCC (plastic leadless chip carrier)
PGA(Pin Grid array)
TAB(Tape Automated Bonding)
Packages