ch02 - system interconnection

8/3/2019 Ch02 - System Interconnection

1/29

Phm Tun Sn [email protected]: Computer Organization and Architecture 6th Edition - William Stallings

Chapter 2:System Interconnection
mailto:[email protected]:[email protected]


2/29

Content

Interconnection Structure

Bus Interconnection


3/29

Interconnection Structure

All the modules

(components) must beconnected: Memory

Input/Output

CPU

Interconnection structureincludes collection of pathsconnecting variousmodules

The design ofinterconnection structuredepends on the exchangesbetween modules

Main

Memory

InputOutput

Systems

Interconnection

Central

Processing

Unit

Computer


4/29

Types of Exchange of Computer Modules


5/29

Memory Connection

Receives and sends data

Receives addresses (of locations)

Receives control signals

Read

Write

Timing


6/29

Input/Output Connection

Similar to memory from computers viewpoint

Write (Output) Receive data from computer

Send data to peripheral

Read (Input) Receive data from peripheral

Send data to computer

Receive control signals from computer

Send control signals to peripherals

Receive addresses from computer e.g. port number to identify peripheral

Send interrupt signals (control) to the processor


7/29

CPU Connection

Reads instruction and data

Writes out data (after processing)

Sends control signals to other units

Receives (& acts on) interrupts


8/29

Bus Interconnection

A communication pathway connecting two or more

devices Usually broadcast

Must insure only 1 device places information onto a busat any given time

Typical buses consist of 50-100 lines Often grouped

A number of channels in one bus

e.g. 32 bit data bus is 32 separate single bit channels


9/29

Data Bus

Carries data

Remember that there isno difference betweendata and instructionat this level

Widthis a keydeterminant ofperformance

8, 16, 32, 64 bit


10/29

Address bus

Identify the source or destination of data

e.g. How CPU can read a word of data from a givenlocation in memory ?

Bus width determines maximum memory

capacityof systeme.g. 8080 has 16 bit address bus giving 64k address

space


11/29

Control Bus

Controls access to and use of the address anddata bus

Control and timing information

Memory read/write signal

Interrupt requestClock signals


12/29

Single Bus Problems

Lots of devices on one bus leads to:

Propagation delays

Long data paths mean that co-ordination of bus use canadversely affect performance

Bottleneck

If aggregate data transfer approaches bus capacity

Most systems use multiple buses to overcomethese problems

Hierarchy High-speed limited access buses close to the processor Slower-speed general access buses farther away from the

processor


13/29

Traditional (ISA) (with cache)


14/29

High Performance Bus


15/29

Elements of Bus Design

Bus Width

Bus Types

Method of Arbitration

Data Transfer Type

Timing


16/29

Bus Types

Dedicated

Separate data & address lines

Multiplexed

Shared lines

Address valid or data valid control lineAdvantage - fewer lines

Disadvantages

More complex control

Reduce performance


17/29

Bus Arbitration (1)

Process of insuring only 1 devices places

information onto the bus at a time

More than one module controlling the bus

e.g. CPU and DMA controller

Only one module may control bus at one time Arbitration may be centralized or distributed


18/29

Bus Arbitration (2)

Centralised

Single hardware device controlling bus access

Bus Controller

Arbiter

May be part of CPU or separate

Distributed

Each module may claim the bus

Control logic on all modules

Master - slave mechanismMaster is given control of the bus and can place

information onto it

Slave receives the information from the master


19/29

Data Transfer Type


20/29

Timing

Co-ordination of events on bus

Synchronous

Events determined by clock signals

Control Bus includes clock line

A single 1-0 is a bus cycle(clock cycle)All devices can read clock line

Usually sync on leading edge

Usually a single cycle for an event

E.g. PCI bus


21/29

Synchronous Timing Diagram


22/29

Asynchronous Timing

The occurrence of one event follows and

depends on the occurrence of a previous event

More flexible than synchronous bus but morecomplicated as well

Accomodates wider range of device speeds


23/29

Asynchronous Timing Read Diagram


24/29

Asynchronous Timing Write Diagram


25/29

PCI Bus

Peripheral Component Interconnection

High-bandwidth bus

Intel released to public domain

32 or 64 bit

50 lines

66 MHz ~ 4.224 Gbps


26/29

PCI Bus Lines (required)

Systems lines

Including clock and reset

Address & Data

32 time mux lines for address/data

Interpret & validate lines Interface Control

Arbitration

Not shared

Direct connection to PCI bus arbiter

Error lines


27/29

Typical Desktop System


28/29

Excercises (1)

1. Consider a hypothetical microprocessor having 16-bit

address bus. What is the maximum memory addressspace that the processsor can directly if it connected toa 16-bit memory?

2. A microprocessor is clocked at a rate of 5 GHz

a. How long is a clock cycle?b. What is the duration of a synchronous memory read operation

in the lesson?

3. Consider a microprocessor with a 16-bit external data

bus, driven by an 8 MHz input clock. Assume that thismicroprocessor has a bus cycle whose minimumduration equals 4 input clock cycle. What is themaximum data transfer rate across the bus that thismicroprocessor can sustain, in bytes/s?


29/29

Exercises (2)

4. For a synchronous read operation (in the lesson), the

memory module must place the data on the bussufficiently ahead of the falling edge of the Read signalto allow for signal settling. Assume a microprocessorbus is clocked at 10 MHz and the Read signal begins tofall in the middle of the second half of T3a. Determine the length of the memory read instruction cycleb. When, at the latest, should memory data be place on the bus?

Allow 20 ns for the settling of the data lines

4. Consider the microprocessor that has a memory readtiming as shown in the lesson. Affter some analysis, adesigner determine that the memory fall short ofproviding read data on time by about 180 ns. Howmany waiting states (clock cycles) need to be insertedfor the proper system operation if the bus clock rate is 8MHz?

ch02 - system interconnection

Documents