cern, 18 december 2003coincidence matrix asic prr coincidence asic modifications e.petrolo, r.vari,...

CERN, 18 december 2003

Coincidence Matrix ASIC PRR

Coincidence ASIC modifications

E.Petrolo, R.Vari, S.VenezianoINFN-Rome



Main functional modifications

• Two main problems have been found, one of which would compromise the High Pt trigger of the experiment:– Input signal Pipeline length is too

short to make a High Pt Coincidence– BCID counter reset procedure limits

the reset of the counter to specific LHC orbit bunches.



Pipeline length

– Due to final cable lenghts estimations, the required length of the input delay line increases from 75 to 210 ns (see LVL1 barrel latency table), 250 ns including safety margin.

– Current implementation is done with FF cells and muxes, 3X8-step programmable blocks. It uses 22% of the die area

– Required values are:• 0-75 ns in I inputs• 0-250 ns on J inputs.

– Die size might increase from 22 to 33 mm2 (5x5 mm2 is a critical size for this process.



BCID counter

– 40 MHz counter is currently used for tagging event fragments (BCID) and in the hit removal mechanism of the LVL1 derandomizers. • Reset procedure has to be done during

specific empty bunches of the LHC orbit, otherwise we have data loss.

– The solution is to implement two counters running at 40 MHz, only one being reset by TTC BC Reset signal.



Other functional modifications

• Synchronization of trigger block– In noisy conditions, TTC signal edges can be

corrupted. Trigger block can be very sensitive to time of arrival of BCRST, L1A, L1RST.

– Double edge synchronizations is the good solution to the problem met in H8.

• I2C input signal filtering– In noisy conditions, I2C signals can get

corrupted.– Digital filtering, asking for the signal being

stable for 8 25 ns period clock cycles can be applied without limiting I2C bandwidth.



Minor functional modifications II

• SEU output on threshold registers– Problem found in SEU measurements, where

SEUs were observed in ASIC registers, but SEU ouput pin was not active.

– SEU output needs to be implemented on threshold registers

• SEU handling on triple redundancy registers– SEUs were observed in redundant

configuration registers, even if actual register value was still correct.

– Different handling mechanism is required. SEU output signal active on two bits failing.



Minor functional modifications III

• RAM scan chain.– RAM cell test chain has been hand-made.– Current solution serializes all RAM inputs,

test procedure is very long, with many empty cycles for positioning patterns to the RAM-under-test inputs

– WEN and REN signals can be parallel, so multiple RAMs can be tested at once.

• Status register readable in run mode– Status register is available on-chip to test

readout buffer status (fill level of all FIFOs)– Status register should be driven from

external clock, so that it can be read when CMA is in running mode.



Functional modifications IV

• Derandomizer state machines– Derandomizers state machines are

only checking FIFO full.– Check on almost full flag is required,

to allow for uncorrupted data transfer on nearly buffer full state.

• Status/error flags in CM frame data– Status and error flags should be

included in the CMA frame footer, to monitor during data taking.



Layout modifications

• Die size increase– Considering 75 ns pipeline depth for

the I signals and 250 ns for the J signals, the die size might increase from the current 22 mm2 to 33 mm2.

– A different architecture for the input pipelines is required (RAM-based delays). Under investigation.

• RAM cell sizes– One RAM cell area is decreased, new

floorplan is required.



Layout modifications II

• I2C register access reduced.– Widespread I2C register access has not

been used during ASIC tests and data taking. It can be removed (also test counter logic).

• SEU tree clocking– SEU tree is currently clocked with local clock– Either external clock or false_path has to be

introduced in the SEU signal timing path.• Clock tree generation

– Violation of max_capacitance from clock tree generation

– Deeper clock tree has to be developped.



Layout modification III

• JTAG chain redefinition– JTAG chain was implemented before

knowing final die pin-out– Reordering of scan cell can be done

now.• Unused pins

– DEVID[7], MSB of Device ID inputs is never used. It can be removed.



Timescale

• Current checklist does not have a detailed schedule yet– Two designers: RV, SV.

• ASIC is required when PAD production starts (end 2004).

• Final design needs to be validated on extensive slice tests (Frascati, BB5, H8)

• Aim at Foundry submission in March.• First prototypes in June.



Conclusions

• First prototype has been tested successfully during second half of 2002, then in lab slice and finally on the H8 test beam in summer 2003.– Data analysys of H8 data is still in progress.

• Irradiation tests show that the technology can be used in the Barrel Spectometer.

• Current modifications required in the final version of the prototype are understood and solutions are known for all of them.

cern, 18 december 2003coincidence matrix asic prr coincidence asic modifications e.petrolo, r.vari,...

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