CEC 220 Digital Circuit DesignTiming Analysis of State Machines

Monday, November 9 CEC 220 Digital Circuit Design Slide 1 of 17

Lecture Outline

Monday, November 9 CEC 220 Digital Circuit Design

• Analysis from Timing Diagrams• Analysis from sequential circuits

Slide 2 of 17

Timing Analysis of State Machines1. Reverse Engineering from a Timing Diagram

Monday, November 9 CEC 220 Digital Circuit Design

• Given the timing diagram for a clocked sequential circuit (i.e., “state machine”) determine the state transition graph

StateMachinex z

Clk

• How many Flip-Flops?

• Rising or falling edge triggered?

• Moore or Mealy machine?

ClockInput

OutputStateFFAFFB

Slide 3 of 17

Timing Analysis of State Machines1. Reverse Engineering from a Timing Diagram

Monday, November 9 CEC 220 Digital Circuit Design

ClockInput

OutputStateFFAFFB

S0Z=0

x=0

falling edge triggered

0 0 0 1

S1Z=0

x=1

1

x=1

0 1

S3Z=0

x=0

1

S2Z=1

x=1

x=1

0 0

x=0Is the state machine completely defined?

x=0

Let’s assume that S2 S3 if x=0.

Moore Machine

Slide 4 of 17

Timing Analysis of State Machines1. Reverse Engineering from a Timing Diagram

Monday, November 9 CEC 220 Digital Circuit Design

• Develop the State Transition Table

S0Z=0

S1Z=0

S3Z=0

x=0

S2Z=1

x=1

x=0x=0

Present State

Next State Present Output (Z)x=0 x=1

S0S1S2S3

Present State

Next State Present Output (Z)w=0 w=1

00 00 01 001 11 01 010 11 01 111 00 10 0

S0 S1

S3 S1

S3 S1S0 S2

0

0

10

QAQB

S0 = 00

S1 = 01

S2 = 10

S3 = 11

State Encoding

Slide 5 of 17

Timing Analysis of State Machines2. Reverse Engineering from a Circuit

Monday, November 9 CEC 220 Digital Circuit Design

• Given the sequential circuit determine the state transition table & graph

Input Logic Flip-Flops Output Logic

A A B A B A BD Q Q X Q Q X Q Q X

Clk

Z

AQ

BQ

AQ

BQ

AQ

BQ

AQ

AQ

BQ

xB A A BD Q X Q Q

A BZ Q Q

• How many states?

• Moore or Mealy machine?

Slide 6 of 17

Timing Analysis of State Machines2. Reverse Engineering from a Circuit

Monday, November 9 CEC 220 Digital Circuit Design

• Develop the State Transition TableA A B A B A BD Q Q X Q Q X Q Q X

B A A B A BD Q X Q Q Q Q

A BZ Q Q

Present State

Next State Present Output (Z)

Flip-Flop Inputs

X=0 X=1 X=0DA DB

X=1DA DB

00011011

Moore Machine

Four States

Present State

Next State Present Output (Z)

Flip-Flop Inputs

X=0 X=1 X=0DA DB

X=1DA DB

00 0

01 0

10 1

11 0

Present State

Next State Present Output (Z)

Flip-Flop Inputs

X=0 X=1 X=0DA DB

X=1DA DB

00 0 0 0 0 1

01 0 1 1 0 1

10 1 1 1 0 1

11 0 0 0 1 0

Present State

Next State

Present Output (Z)

Flip-Flop Inputs

X=0 X=1 X=0DA DB

X=1DA DB

00 00 01 0 0 0 0 1

01 11 01 0 1 1 0 1

10 11 01 1 1 1 0 1

11 00 10 0 0 0 1 0

Slide 7 of 17

Could use the FF Excitation EqnsAnd go directly to Next State Cols!!

Timing Analysis of State Machines2. Reverse Engineering from a Circuit

Monday, November 9 CEC 220 Digital Circuit Design

• Develop the state transition graph

x=0

x=1

x=1

x=0

S00Z=0

S01Z=0

S11Z=0

S10Z=1

x=1

x=1

x=0x=0

PresentState

Next StatePresent

Output (Z)

Flip-Flop Inputs

X=0 X=1 X=0DA DB

X=1DA DB

00 00 01 0 0 0 0 1

01 11 01 0 1 1 0 1

10 11 01 1 1 1 0 1

11 00 10 0 0 0 1 0

Compare this graph with the one obtained from the prior waveform

example.

Slide 8 of 17

Timing Analysis of State Machines3. Reverse Engineering from a Timing Diagram

Monday, November 9 CEC 220 Digital Circuit Design

• Given the timing diagram for a clocked sequential circuit (i.e., “state machine”) determine the state transition graph

StateMachinex z

Clk

• How many Flip-Flops?

• Rising or falling edge triggered?

• Moore or Mealy machine?

ClockInput

OutputStateFFAFFB

Slide 9 of 17

ClockInput

OutputStateFFAFFB

Timing Analysis of State Machines3. Reverse Engineering from a Timing Diagram

Monday, November 9 CEC 220 Digital Circuit Design

0 0 0 1 1 0 1 1 0 0

S0

x=0 /

S1

x=1 /

x=1 /

falling edge triggered

Mealy Machine

S2

x=0 /

x=1 /

x=0 /

0

0

0

0

0

1

Slide 10 of 17

Timing Analysis of State Machines3. Reverse Engineering from a Timing Diagram

Monday, November 9 CEC 220 Digital Circuit Design

• Develop the State Transition TablePresent

State

Next State Present Output (Z)X=0 X=1 X=0 X=1

S0S1S2

QAQB

S0 = 00

S1 = 01

S2 = 10

State Encoding

S0

S1S2

x=0 /

x=1 /

0

1

0 0S0 S1

0 0S2 S1

0 1S0 S1

Present State

Next State Present Output (Z)

X=0 X=1 X=0 X=1

00 0 0

01 0 0

10 0 1

11 X X

Present State

Next State Present Output (Z)

X=0 X=1 X=0 X=1

00 00 01 0 0

01 10 01 0 0

10 00 01 0 1

11 XX XX X XSlide 11 of 17

Timing Analysis of State Machines4. Reverse Engineering from a Circuit

Monday, November 9 CEC 220 Digital Circuit Design

• Given the sequential circuit determine the state transition table & graph

Input Logic Flip-Flops Output Logic

A BD Q X

BD X

AZ Q X

• How many states?

• Moore or Mealy machine?

Clk

Zx

Slide 12 of 17

Timing Analysis of State Machines4. Reverse Engineering from a Circuit

Monday, November 9 CEC 220 Digital Circuit Design

• Develop the State Transition Table

Mealy Machine

Four States

Present State

Next State Present Output (Z) Flip-Flop Inputs

X=0 X=1 X=0 X=1X=0

DA DB

X=1DA DB

00

01

10

11

A BD Q X

BD X

AZ Q X Present State

Next State Present Output (Z) Flip-Flop Inputs

X=0 X=1 X=0 X=1X=0

DA DB

X=1DA DB

00 0 0

01 0 0

10 0 1

11 0 1

Present State

Next State Present Output (Z) Flip-Flop Inputs

X=0 X=1 X=0 X=1X=0

DA DB

X=1DA DB

00 0 0 0 0 0 1

01 0 0 1 0 0 1

10 0 1 0 0 0 1

11 0 1 1 0 0 1

Present State

Next State Present Output (Z) Flip-Flop Inputs

X=0 X=1 X=0 X=1X=0

DA DB

X=1DA DB

00 0 0 0 1 0 0 0 0 0 1

01 1 0 0 1 0 0 1 0 0 1

10 0 0 0 1 0 1 0 0 0 1

11 1 0 0 1 0 1 1 0 0 1

Slide 13 of 17

Could use the FF Excitation EqnsAnd go directly to Next State Cols!!

DFF Excitation Eqn:

Q D

Timing Analysis of State Machines4. Reverse Engineering from a Circuit

Monday, November 9 CEC 220 Digital Circuit Design

• Develop the state transition graph

x=0 / 0

x=1 / 0

x=1 / 0

x=0 / 0

x=1 /

x=0 / 0

1

Present State

Next State Present Output (Z)

X=0 X=1 X=0 X=1

00 0 0 0 1 0 0

01 1 0 0 1 0 0

10 0 0 0 1 0 1

11 1 0 0 1 0 1

S00

S01S10

S11

If we start at S00, S01, or S10 we will never reach S11

x=0 / 0 x=1 /1 Compare this graph with the one obtained from the prior waveform

example.

We can effectively ignore S11

Slide 14 of 17

Clk

Zx

Clk

Z

AQ

BQ

AQ

BQ

AQ

BQ

AQ

AQ

BQ

x

Timing Analysis of State MachinesMethod#1: VHDL Code to generate these Examples

Monday, November 9 CEC 220 Digital Circuit Design

Moore State Machine:Cases 1 & 2

Mealy State Machine:Cases 3 & 4

See course webpage for VHDL codeSlide 15 of 17

S0

S1S2

x=0 /

x=1 /

0

1

Timing Analysis of State MachinesMethod#2: VHDL Code to generate these Examples

Monday, November 9 CEC 220 Digital Circuit Design

S0Z=0

S1Z=0

S3Z=0

x=0

S2Z=1

x=1

x=0x=0

Moore State Machine:

See

cour

se w

ebpa

ge fo

r VH

DL

code

Mealy State Machine:

Slide 16 of 17

Next Lecture

Monday, November 9 CEC 220 Digital Circuit Design

• Sequence Detector design

Slide 17 of 17