catrene design technology conference - … · ms. maren sperber [email protected] fon: +49 511...

Program

Dresden (Germany), May 19 – 21, 2015www.edacentrum.de/edaworkshop

Location

CATRENEDesign Technology Conference

edaWorkshop 15

jointly organized

Dresden, the capital of Saxony and the former residence of the Wettin dynasty, is a city of art and culture with magnificent buildings, many world-class museums as well as a rich tradition of theatre and music. No book about the history of architecture can forget to men-tion Dresden’s Zwinger Palace (s. picture on the left). The recon-structed Frauenkirche, the Semper Opera House and the Royal Palace as well as many other historical monuments and collections define the image of the city. See also: www.dresden.de

The participation fee includes 3 days conference, 3x lunch, 2x dinner, conference beverages and conference documents. This is an all-inclusive package. Items are not available separately.

Registration (Deadline: May 11, 2015) until April 27, 2015 after April 28, 2015

Participation fee (All prices plus 19 % VAT) EUR 350,– EUR 400,–

To register choose the registration online (https://www.edacentrum.de/edaworkshop/online-registration) or fax the registration form to +49 511 762-19695. For further details, i.e. cancellation policy see registration form.

Registration and Accomodation Contact

edacentrum Schneiderberg 32 30167 Hannover Germany Ms. Maren Sperber [email protected]

fon: +49 511 762-19699 fax: +49 511 762-19695 [email protected] www.edacentrum.de

The event takes place at the 4-star Dorint Hotel Dresden which is located close to the Old Town. For attendees of the edaWorkshop15 and CATRENE DTC edacentrum has arranged special room rates, valid from May 19 – 21, 2015.

Dorint Hotel Dresden Grunaer Straße 14 01069 Dresden Germany Fon +49 351 4915-0 Fax +49 351 4915-100 www.dorint.com/en/hotel-dresden

Special Room Rates at Dorint Hotel Dresden (including Breakfast)

Single room: EUR 110,- Double room: EUR 140,- Fon +49 351 4915-774 [email protected]

For alternative hotels see www.edacentrum.de/edaworkshop/location

Please book your room by April 20, 2015, and mention “edaWorkshop15” as the key-word. After April 20, the fixed quota of rooms for the event will be closed. All participants are kindly asked to make their own hotel reservations directly.

Social Event Locations

From the airportBy taxi: The taxi fare to the hotel is about EUR 22.By public transportation: Take S2 local train (direction “Heidenau”), get off at “Dresden Hauptbahn-hof” and proceed as written below. See also: www.dresden-airport.de

From the main railway stationTake tram no. 3 or 7 (direction “Dresden Wilder Mann” or “Weix-dorf”), get off at “Pirnaischer Platz”. Take tram 2 or 12 (direction “Dres-den Kleinzschachwitz Freystraße” or “Dresden Ludwig-Hartmann-Straße”), get off at “Deutsches Hygiene-Museum”. See also: www.dvb.de

Using a navigation systemChoose “Pirnaische Vorstadt” as district when you enter “Grunaer Strasse 14”.

Restaurant “Dresden 1900” With the era of Empire to Art Nou-veau Dresden provides another heyday apart from the time of Au-gustus the Strong. It was a period of entrepreneurs and inventors, the rising bourgeoisie and of basic development in public transport. The museum restaurant “Dresden 1900” provides a glimpse into the lives of Dresdens’ cirizens and their traffic history(ies) about 1900 showing one of the most beautiful squares of the past - the post office square – in 1900. The restaurant offers a good Saxonian kitchen from around 1900 and also creations of the modern German cuisine. Dresden 1900 is located vis-a-vis to the Frauenkirche, within walking distance to the Dorint hotel (15 min). Adress: An der Frauenkirche 20 www.dresden1900.de

Restaurant “Alte Meister” The Alte Meister café & restaurant was opened in October 2001 on the premises of Albert Braun’s former studio. Braun directed the artistic renovation of the Zwinger after World War II. In the museum café of the world-famous gallery of the same name, freshly made delicacies of creative seasonal kitchen are offered. A café durng the day, the “Alte Meister” turns into a stylish restaurant in the evening where dining between Rubens and Rossini becomes possible. The restaurant “Alte Meister” is located in the lavishly renovated Braun Atelier of the Dresden Zwinger next to the Sem-per Opera House. From the Dorint Hotel it located within walking distance (20 min). Adress: Theaterplatz 2 www.altemeister.net

Directions to Dorint Hotel

About edaWorkshop and CATRENE DTC

The edaWorkshop is the premier German event on “Electronics, Design and Applications” (EDA). It offers excellent opportunities for the publication and discussion of application-oriented EDA research results. The mix of participants from industry and academia creates ideal opportunities for a professional exchange of ideas on a scientific basis. This interac-tion paves the way for industry to benefit from research results.

The edaWorkshop is also the pri-mary platform for presenting and exchanging solution approaches and results of those research projects in the area of “Electronics,

Design and Applications”, which are funded by the BMBF (Fed-eral Ministry of Education and Research, Germany). It promotes

communication between experts and public authorities, and sup-ports the dissemination of the results of publicly-funded projects.

The edaWorkshop is organized jointly by the edacentrum and the GI/GMM/ITG RSS Steering Group

for “Computer-aided Circuit and System Design” and is supported by the BMBF. Like in 2009, 2011 and 2013, the edaWorkshop15 will co-locate and share a com-mon day – including keynotes, sessions and the social event – with the annual CATRENE Design Technology Conference (DTC).

The CATRENE DTC is the meeting point of Europe’s scientists and experts in application-oriented design. Both events are attracting European experts in industry and academia and consequently the organizers decided to co-locate the workshop and the conference every two years.

edaWorkshop 15edaWorkshop 15

The three-day event is a balanced combination of information and communication. It offers not only a wide range of discussions on specialized subjects and EDA research projects, but also provides plenty of networking op-portunities. This is supported by a comprehensive poster exhibition, where also demonstrations and prototypes will be presented.

Looking forward to seeing you in Dresden!

Prof. Dr. W. Rosenstiel Prof. Dr. W. Nebel General Chairs

Wed

nesd

ay, May 20, 2015

Keyn

ote M

oderator: W. R

osenstiel (edacentrum, D

)

9:00S

ystem o

f System

s – Th

e Key E

nab

ler for Fu

ture A

pp

lication

s A

. Schöllhorn (Intel M

obile Com

munications, D

)

Techn

ical Sessio

n: M

od

eling

and

Sim

ulatio

nM

oderator: M. D

ietrich (Fraunhofer IIS/E

AS, D

)

9:30

Virtu

al Pro

totyp

ing

with

IP R

euse fo

r a ME

MS

Ap

plicatio

n w

ith

IP-X

AC

T an

d S

ystemC

-AM

S M

DV

PO

. Guillaum

e, F. Cenni, (ST M

icroelectronics, F), E. Vaum

orin, J.-M. Fernandez (M

AG

IL-LE

M, F), F. R

ahim (ATR

EN

TA, F), G

. Schröpfer, B

. Vernay (CO

VE

NTO

R, F)

10:05Leverag

ing

Verificatio

n o

f System

C w

ith U

VM

S. Schulz, T. Voertler (Fraunhofer IIS

/EA

S, D)

10:30Q

&A

M. D


AS, D

)

10:35 C

offee B

reak

Techn

ical Sessio

n: FD

SO

I Eco

systems

Moderator: P. B

louet (ST Microelectronics, F)

11:05FD

SO

I Device Param

eter Op

timizatio

n w

ith T

CA

DE

l Medi B

azizi (GLO

BA

LFOU

ND

RIE

S, D)

11:40FD

SO

I Silico

n E

nab

lemen

t Desig

n C

enter

O. Thom

as (CE

A-LETI, F)

12:05FD

SO

I and

AD

AS

Ap

plicatio

n fo

r Au

tom

otive

J. Benndorf (D

reamchip, D

)

12:30Q

&A

P. Blouet (ST M

icroelectronics, F)

Poster S

ession

Moderator: R

. Popp (edacentrum, D

)

12:35In

trod

uctio

n o

f the Po

ster Exh

ibitio

nC

omprising accepted scientific contributions and an overview

of project posters.

Poster E

xhib

ition

12:50For the titles and authors of the scientific posters see bottom

of next page.

13:20Lu

nch

and

Poster E

xhib

ition

Techn

ical Sessio

n: S

ecurity, S

afety and

Privacy – C

hallen

ges and

D

esign

So

lutio

ns fo

r Tom

orrow

´s Ap

plicatio

ns

Moderator: J. H

aase (edacentrum, D

)

14:35S

ecurity, S

afety and

Privacy b

ut w

hat fo

r and

how

…C

. Dietrich (G

emalto, F)

15:10N

ew Tru

sted H

ardw

are and

Firmw

are Co

mp

utin

g M

echan

isms

Ap

plicab

le to E

mb

edd

ed S

ystems

B. C

andaele (Thales, F)

15:35Q

&A

J. Haase (edacentrum

, D)

15:40C

offee B

reak

Techn

ical Sessio

n: V

2X: C

ar to E

nvirom

ent C

om

mu

nicatio

nM

oderator: R. H

oofman (N

XP, N

L)

16:10H

ow V

2X Lead

s to S

afe and

Secu

re Mo

bility

P. Pype (N

XP, B

E)

16:45V

AM

OS

– Th

e Traffic Man

agemen

t System

of D

resden

M. K

rumnov (TU

Dresden, D

)

17:10Q

&A

R. H

oofman (N

XP, N

L)

17:15B

reak

So

cial Even

t (Dinner Location: R

estaurant “Alte M

eister“, adress below)

17:45M

eeting point at hotel reception for guided tours

18:00Public organ prayer and explanations at „Frauenkirche“ (in G

erman only) or

Guided tour through D

resden‘s old town

19:00M

eeting point at hotel reception (in case of not participating guided tours)

19:15A

rrival at "Alte M

eister" (Theaterplatz 1a, 01067 Dresden)

19:30C

on

fermen

t of "E

DA

-Med

aille 2015" W. R


)

20:00D

inn

er

23:00E

nd of 2nd day

Th

ursd

ay, May 21, 2015

Keyn

ote

Moderator: W

. Nebel (edacentrum

, D)

9:00D

esign

of S

ecure C

hip

sG

. Sigl (TU

München, D

)

9:30D

esign

for M

anu

facturin

g in

Extrem

e Scalin

g an

d B

eyon

dD

. Pan (U Texas at A

ustin, US

)

10:00C

on

fermen

t of “E

DA

Ach

ievemen

t Aw

ard 2015”

W. N

ebel (edacentrum, D

)

10:20C

offee B

reak

Techn

ical Sessio

n: M

EM

S an

d A

nalo

gM

oderator: U. S

chlichtmann (TU

München, D

)

10:50M

EM

S2015 Paves th

e Way to

Sch

ematic D

riven M

EM

S D

esign

T. Maier (B

osch, D), R

. Som

mer (IM

MS, D

) (tbc)

11:10D

esign

of A

cceleration

Sen

sors U

sing

a System

atic ME

MS

-AS

IC

Desig

n Flow

R

. Pevgonen, J. Klaus, R

. Som

mer (IM

MS, D

)

11:35B

ehavio

ral Mo

delin

g o

f an A

nalo

g N

eural R

ecord

ing

Fron

t-En

d fo

r S

ystem S

imu

lation

and

Reliab

ility An

alysisN

. Heidm

ann, N. H

ellwege, D

. Peters-Drolshagen (U

Brem

en, D)

12:00S

ymb

olic S

imu

lation

of M

ixed-S

ign

al System

s with

Exten

ded

Affin

e A

rithm

etic C. R

adojicic, C. G

rimm

, T. Purusothaman (TU

Kaiserslautern, D

)

Poster E

xhib

ition

12:25For the titles and authors of the scientific posters see below

.

12:55Lu

nch

and

Poster E

xhib

ition

Techn

ical Sessio

n: S

trategy, An

alysis and

Diag

no

sis M

oderator: W. N

ebel (edacentrum, D

)

14:10N

ation

al Agen

da P

rocess to

develo

p S

trategies fo

r Micro

electron

ics C

. Martin (B

MB

F, D)

14:25Fro

m M

aterial via SO

C to

System

s/Platfo

rms: T

he D

esign

Ro

adm

ap in

E

CS

EL M

AS

P

H. D

aembkes (A

irbus, D), J. N

iehaus (SafeTrans, D

), R. Popp (edacentrum

, D)

15:45E

valuatio

n o

f circuit p

erform

ance an

d co

nfig

uratio

n red

uctio

n co

nsid

-erin

g p

ost-silico

n clo

ck skew tu

nin

g

B. Li, U

. Schlichtm

ann (TU M

ünchen, D)

15:10E

ffective Finite E

lemen

t Meth

od

for E

lectrom

igratio

n A

nalysis in

C

om

plex IC

Desig

n

M. Thiele, J. Lienig (TU

Dresden, IFTE

, D)

15:35K

now

ledge-B

ased O

n-C

hip

Diag

no

sis for M

ulti-C

ore S

ystems-o

n-C

hip

P. W

agner (TU M

ünchen, D), L. Li, A

. Mayer, (Infineon D

), T. W

ild, A. H

erkersdorf (TU M

ünchen, D)

16:00C

losin

g W

. Nebel (edacentrum

, D)

16:10E

nd of 3rd day

A Fram

ewo

rk for au

tom

ated V

erification

of u

ser-defin

ed M

BIS

T-A

lgorith

ms

J. Kinseher, M

. Richter (Intel M

obile Com

munications, D

), I. Polian (U Passau, D

)

A C

om

plete C

yber-P

hysical System

for M

ovemen

t Related

Poten

tials Detectio

n

by Syn

chro

nized

EE

G an

d E

MG

D

. De Venuto, V. F. A

nnese, (Politechnico Bari, IT)

ES

D p

rotectio

n m

etho

do

logy o

n system

level and

con

cept o

n d

evice level G

. Noterm

ans, S. Holland (N

XP, D

), C. S

ohrmann (Fraunhofer IIS, D

)

C++ P

rocesso

r Mo

dels fo

r Accelerated

Mu

lti-level Erro

r Effect S

imu

lation

M

. Greim

, D. M

ueller-Gritschneder, U

. Schlichtm

ann (TU M

ünchen, D)

Besides these review

ed contributions to edaWorkshop15, the poster exhibi-

tion will show

results of all ED

A projects funded by B

MB

F within IK

T 2020.

Wo

rksho

p C

on

tribu

tion

s Accep

ted as Po

ster

edacentrum

The design of integrated circuits and systems places enormous de-mands on R&D engineers and de-sign methods and tools that they use. It requires the efficient and manufacturing-aware development of safe, economical, robust and reliable systems of high complex-ity with very small structures and the design of analog and mixed-signal circuits.

In addition, most integrated circuits today contain not only a ‘system on chip’ (SoC), they also comprise large systems which are essential parts of applications. A new (product) design concept along the entire value chain with close interaction between elec-

tronics, design and applications (EDA) is necessary to speed-up innovation. This requires the integration of application domain knowledge into the design pro-cess, including design method-ologies and tools. It comprises management of requirements, design along all levels of abstrac-tion and the consideration of extra-functional properties.

Within the scope of its funding programme for information and communication technologies (ICT 2020) the BMBF (Federal Ministry of Education and Research, Ger-many) supports research activities in the area of “Electronics, Design and Applications”. Currently fun-

ded projects predominantly aim at developing application-specific design platforms for complex systems and circuits. The EDA-industry forms an important link between semiconductor manufac-turers and OEMs, and EDA-related research projects within ICT2020 foster collaboration along the value chain. ICT2020 focuses on fields of application that play a de-cisive role for the future strength of the German economy, such as automotive/mobility, automation and medical technology. Some projects within ICT 2020 are part of European collaborations, for example within the programme EUREKA-CATRENE.

The edaWorkshop and CATRENE DTC – Catalyst of EDA Research

This event is a central platform for exchanging information concern-ing the approaches and results of projects from ICT 2020 and CATRENE (www.catrene.org) as well. Experts involved in the projects will be invited to present their results by means of talks and posters. At the heart of these presentations on electronics, design and applications will be the relevance of the applications to topics affecting society (as defined by ICT 2020 and CATRENE White Book B). As a second essential part of the event, project presenta-tions will be supplemented by a selection of peer-reviewed scien-tific papers on R&D results.

Committees of the CATRENE DTC and edaWorkshop

W. Nebel, OFFIS, edacentrum

J. Haase, edacentrum

W. Rosenstiel, U Tübingen, edacentrum

General Chairs of the edaWorkshop

Organization Committee

R. Popp, edacentrum

D. Treytnar, edacentrum V. Schanz, ITG in VDE R. Schnabel, VDE/ VDI-GMM

Technical Program Chair U. Schlichtmann, TU München

P. Federer, GI

P. Blouet, ST, F M. Barnasconi, NXP, NL J.L. Conesa, ALPHSIP, E B. Candaele, Thales Group, F M. Coenen, EMC MCC, NL M. Coppola, ST, F M. Diaz-Nava, ST, F M. Dietrich, Fraunhofer IIS, D A. Fritsch, Thales Group, F C. Grimm, FhG-UKL, D J. Haase, edacentrum, D P. Koch, CATRENE, EU P. Merkus, Philips, NL F. Petrot, TIMA, F R. Pferdmenges, Infineon, D D. Rousset, ST, F F. Schenkel MunEDA, D E. Villar, U Cantabria, E

W. Rosenstiel, U Tübingen, edacentrum, D

A. Jerraya, CEA-LETI, F

Technical Program Chair

General Chair of the DTC

Steering Committee Program Committee W. Anheier, U Bremen

G. Teepe, GLOBALFOUNDRIES

O. Bringmann, FZI W. Daehn, FH Magdeburg-Stendal M. Dietrich, Fraunhofer IIS R. Drechsler, U Bremen

W. Ecker, Infineon R. Ernst, TU Braunschweig

G. Kornmann, Intel Mobile Communications

W. Glauert, U Erlangen-Nürnberg H. Gräb, TU München

K. Hahn, U Siegen

L. Hedrich, U Frankfurt A. Herkersdorf, TU München

P. Haspel, Cadence

W. Kunz, TU Kaiserslautern

S. Kern, Atmel

R. Pferdmenges, Infineon

H. Schmidt-Habich, Infineon S. Sattler, U Erlangen-Nürnberg

M. Reuter, Mentor M. Schächtele, Bosch

V. Meyer zu Bexten, Infineon

J. Kampe, FH Jena

M. Olbrich, U Hannover

H.-J. Wunderlich, U Stuttgart N. Wehn, TU Kaiserslautern

J. Doblaski, X-Fab

J. Teich, U Erlangen-Nürnberg R. Sommer, IMMS

P. v. Staa, Bosch

K. Schneider, TU Kaiserslautern

A. Hoffmann, Synopsys

Abstract:By 2050, 70 percent of the world’s population will live in cities. And, as cities grow and ex-pand their services, the manage-ment, operations and governance across the city becomes increas-ingly complex. To manage this increasing complexity, it becomes necessary to make cities »smart«. ‘Smart Cities’ have been defined as cities that use information and communications technology to make their critical infrastructure and its components and utilities more interactive and efficient. ‘Smart Cities’ are built on ‘smart and intelligent’ solutions and technologies that will lead to the adoption of at least 5 of the 8 fol-lowing smart parameters – smart energy, smart building, smart

mobility, smart healthcare, smart infrastructure, smart technology, smart governance, and smart education & citizens.

Surprisingly, although ‘Smart Cit-ies’ is a hot topic today, a continu-ous semiconductor value chain for Smart Cities does not exist yet. Whereas smart city planners and operators think and act mainly on a conceptual level and utilize microelectronics off the shelves only, technological opportunities, although available and offered, are not really recognized within this community. In addition, Smart Cit-ies Applications today are more or less singular application solutions, because no unified Smart City approach exists yet.

Nevertheless, ‘Smart Cities’ will be one exciting application of the ‘Internet of Things’ (IoT) with an enormous demand for nano-electronics and smart systems. A huge increase in markets is expected for the next years described best by the ‘The Trillion Sensor Vision’.

Curriculum Vitae: Dr. Joachim Pelka is the Managing Director of the business office for the Fraunhofer Group for Micro-electronics. He studied electrical engineering, with an emphasis on semiconductor technology, at Berlin’s Technical University and was awarded a doctorate there for his work on semiconductor components. He has been with

the Fraunhofer-Gesell-schaft since 1983.

Today, following many years in the organiza-tion, Dr. Pelka is the Managing Director of the Fraunhofer Group for Microelectronics. As managing direc-tor he is responsible for strategic planning and for the coordination of work in the microelectronic institutes of the Fraunhofer-Gesellschaft. In keeping with deepening European integration, Dr. Pelka today functions more and more as a contact person for other European research facilities such as CEA-Leti, CSEM, IMEC and VTT and is a member of the CATRENE Scientific Committee.

Tuesday Keynote: Joachim Pelka: “Semiconductor Technologies & Smart Cities –Technology Push or Application Pull?”

“The only thing more amazing than our technology is what the world does with it.” - Intel

Abstract:As more and more diverse mobile devices are connected to the cloud computing technology continues to advance a faster merge of multiple communication technologies. Manifold new applications such as in health care or automotive connect and enrich the lives of every person on earth. “Internet of Things”, “Smart Everything”, or “Always Connected” are the new keywords characterizing the ap-plications.

More than ever, we face unan-ticipated challenges in System of Systems development. Today,

Wednesday Keynote: Angela Schöllhorn: “System of Systems – The Key Enabler for Future Applications”

components are sophisticated systems themselves. As soon as such integrate into an even more complex product their interaction becomes as important as the individual systems. Rather than the most advanced technology the user experience in the ecosystem defines the success of a product. To make matters worse, the pace of innovation in the ecosystem continuously accelerates. All that is accompanied with having to serve all price segments allowing network access for everybody.

Only a new design philosophy tying all elements together will allow to reconcile these extremely diverging requirements. While System-on-Chip solutions providing the compute power for a tremen-

dous amount of SW/FW remain essential, the System of Systems architecture itself is defined by the user experiences and must cover the interaction of the sys-tems and related communication protocols. The road to success are end to end accountability for each use case as well as traceability of its implementation status. Combining user experi-ences with technology needs to be adhered in the next EDA generation.

This keynote will cover: 1) the System of Systems challenge in computing ecosystems, 2) the evolution in product development and their challenges, and 3) the requirements for the next EDA generation.

Curriculum Vitae:Angela Schöllhorn studied solid state physics at the Uni-versity of Duisburg-Essen. In 1984 she started her career in semiconductor business. Since then she has held several top-management R&D positions in the industry (Siemens, Infi-neon, INTEL) delivering Mobile Communication Solutions to leading providers such as Apple, Samsung and Nokia.

Abstract:In the era of the Internet of Things more and more connected embedded systems are accessible to physical attacks jeopardizing the systems’ security. Thus security critical parts of the embedded

systems, which are often realized as single systems-on-chips, have to be hardened against such attacks.The hardening of chips against hardware attacks requires specific add-ons to standard design flows usually only known in the world of smart cards. This talk will first moti- vate the need for more hardware security and present the different kinds of hardware attacks with a focus on side channel and fault

attacks. These attacks can be per- formed with low budget equip-ment and standard engineering knowledge. Therefore counter-measures have at least to cover those attacks. Countermeasures may be implemented on the architecture, microarchitecture, RTL, gate, or transistor level. No matter on which level they are implemented, they must both be designed properly and verified before tape-out. Otherwise long redesign cycles are encountered if security weaknesses are detected during silicon or system verifica-tion. The talk will give examples of design measures against side channel and fault attacks and discuss verification against these design measures. Security is an additional parameter in the design

space which is currently mostly neglected. In the future it will be of increasing importance and hopefully be supported by better design and verification tools.

Curriculum Vitae: Georg Sigl is director at Fraun- hofer Research Institute for Applied and Integrated Security AISEC and head of the chair for Security in Electrical Engineering and Information Technology at Technische Universität München (TUM). After several stations in semiconductor industry, he was responsible for the development of security controllers for Infi-neon from 2000 to 2010. In 1992 he earned his PhD at the institute for Electronic Design Automation at TUM.

Abstract: As the nanometer IC critical dimension enters the era of extreme scal-ing (14nm, 11nm and beyond), manufactur-ability challenges are exacerbated, due to multiple patterning and other emerging lithography technologies. This talk will present some key challenges and recent results in DFM in ex-treme scaling and beyond.Curriculum Vitae: David Z. Pan is the Engineering Foundation Professor at the ECE Department, UT Austin and an IEEE Fellow. For more info see: www.edacentrum.de/edaworkshop

Thursday Keynote: Georg Sigl: “Design of Secure Systems”Invited Presentation: David Pan: “Design for Manufacturing in Extreme Scaling and Beyond

Abstract:To achieve Europe’s goal of doubling the economic value of semi-conductor production in Europe in the 2020-25 timeframe, outspending competing regions of the world is not pos-sible. We have instead

to define where to focus our R&I money. The European Nanoelec-tronics Infrastructure for Innova-tion (ENI²) supports the European semiconductor sector by helping to define the research agenda of co-operative projects on technologies with high impact on economy and society, and facilitating the prepara-tion and execution of R&D projects which address these priorities. To do so, ENI² brings together

potential application requirements and expected evolutions of the enabling technologies. The talk will present the ENI² structure, the road mapping methodology used to define key research topics, and the 2015 work plan. Recent inputs to H2020 work program will be shared.

Curriculum Vitae: Patrick Cogez chairs ENI² since June 2014. After starting his career as a civil ser-vant, he joined STMicroelectron-ics in 1988, where he is now in charge of innovation and external research at Crolles site. He gradu-ated from Ecole Polytechnique in France, and holds a MSc. in Operations Research and a PhD in Industrial Engineering from UC Berkeley.

Abstract:Effective design methods and technologies are the only way to transform ideas and requirements efficiently into innovative, produc-ible, and testable products, at whatever level in the value chain. They aim at increase of productiv-ity, reducing development costs and time-to-market, according to the level of targeted requirements such as quality, performance, cost and energy efficiency, safety, secu-rity, and reliability. Design methods and technologies must ensure the link between the ever-increasing technology push and the demand for innovative new products and services of ever-increasing complexity that are needed to fulfil societal needs. The new ECSEL JU offers a framework in which

we extend the design technologies from ba-sic technology models via design of SOC to the final application in platforms like cars, aircrafts or commu-nication systems. Examples of the new opportunity will be presented.

Curriculum Vitae: Heinrich Daembkes, Airbus De-fence and Space, is president of ARTEMIS-IA, working on Embed-ded Systems and Cyber Physical systems. He was deeply involved in preparing the content of the Multi-Annual Strategic Research and Innovation Action plans 2015. The chapter on Design Technolo-gies is coordinated by him.

Invited Presenatation: ENI²: “Defining Research Key Topics to Support Europe’s Ambition in Nanoelectronics”

Invited Presenatation: From Material via SOC to Systems/Platforms: “The Design Roadmap in ECSEL MASP”

edaWorkshop15 and CATRENE DTC Topics

System Level and Hardware/Software Design of Embedded Systems

Specification- and Model-based Design Architectural Synthesis and Optmization Advanced Architectures (ASIPs, SoCs, MPSoCs,

NoC, SiPs and Reconfigurable Architectures) Transaction Level Modeling and Simulation Development and Optimization of

Hardware-dependent Software

Design and Verification Formal Verification Statistical Timing Analysis and Variability Low Power Design, Analysis and Optimization Logic- and Technology-dependent Synthesis for Nanometer Circuits Physical Design and Verification Simulation Acceleration and Rapid Prototyping Productivity and Efficiency of Design

Analog- and Mixed-Signal Design

Design Automation for Analog Circuits Synthesis, Simulation and Verification RF Circuits, Smart Power Circuits Model Generation Parasitics and Interconnects Signal Integrity and EMC

Reliability, Robustness and Test

Design for Reliability and Robustness Modeling of Aging Effects Design Centering and Yield Optimization (DfM) Fault-tolerant and Self-healing System Design System Test and Production Test Delay Test and Defect-oriented Test BIST and Design for Testability Test Generation, Diagnosis and Fault Modeling Test of Regular Structures

More than Moore

3D Design, Packaging and SiP Design for Integration of

Multi-Domain components Energy Efficient Design Analysis and Optimization of

Performance and Power Cyber-Physical Systems Design for New Technologies Design for Specific Applications

Tuesd

ay, May 19, 2015

Keyn

ote

Moderator: W

. Rosenstiel (edacentrum

, D)

9:30W

elcom

e W. R


)

9:45S

emico

nd

ucto

r Techn

olo

gies &

Sm

art Cities – Tech

no

logy P

ush

or

Ap

plicatio

n P

ull?

J. Pelka (Fraunhofer, D)

10:15 C

offee B

reak

Techn

ical Sessio

n: C

on

nected

Ob

jectsM

oderator: M. D

iaz-Nava (ST M

icroelectronics, F)

10:45Tech

no

log

ical Co

nvergence – O

pp

ortu

nities an

d C

hallen

ges for In

ternet

of T

hin

gs Tech

no

log

ies and

Ap

plicatio

ns

O. Verm

esan (SIN

TEF, F)

11:20E

nLig

ht – E

xplo

ring

the N

ext Gen

eration

Intelligen

t and

En

ergy E

fficient Lig

htin

g S

ystems

F. van Tuijl (Philips, N

L)

11:45E

arly Exp

erience fro

m S

PO

K, an

En

d-U

ser Develo

pm

ent E

nviron

men

t fo

r the A

pp

sGate S

mart H

om

eJ. C

outaz (Grenoble Inform

atics Laboratory/ UJF, F)

12:10Q

&A

M. D

iaz-Nava (ST M

icroelectronics, F)

12:15 Lu

nch

Techn

ical Sessio

n: E

nergy E

fficient M

PS

oC

Moderator: A

. Castillejo (ST M

icroelectronics, F)

13:45E

fficient Pow

er Man

agemen

t in FD

-SO

I MP

So

CD

. Puschini (CE

A-LETI, F)

14:20D

elay Testing

for Pow

er Efficien

cy Imp

rovemen

tM

. Zandrahimi (TU

Delft, N

L)

14:45A

Sin

gle-P

CB

Min

iature, E

fficient, 900M

Hz R

ectenn

a for R

F Harvestin

gG

. Dolm

ans (IME

C, N

L)

15:10Q

&A

A. C

astillejo (ST Microelectronics, F)

15:15 C

offee B

reak

Techn

ical Sessio

n: E

NI 2

Moderator: P. C

ogez (ST Microelectronics, F)

15:45E

NI²: D

efinin

g R

esearch K

ey Top

ics to S

up

po

rt Eu

rop

e’s Am

bitio

n in

N

ano

electron

ics P. Cogez (ST M

icroelectronics, F)

Panel

Moderator: A

. Fritsch (Thales, F)

16:15 E

NI² R

oad

map

, Make it H

app

en; S

mart Tran

spo

rtation

as a Use C

aseG

. Teepe (GLO

BA

LFOU

ND

RIE

S, D) J. Pelka (Fraunhofer, D

) A

. Bruening (ZM

DI, D

) (tbc) S. Tverdyshev (Sysgo, D)

D. Laousse, (S

NC

F, F) P. Cogez (ST, E

NI2, F)

J. Langheim (ST, F) S. A

llano, (PSA

, F) (tbc)

17:15B

reak

C

on

ference D

inn

er (Location: Restaurant “D

resden 1900”, address below)

18:30M

eeting point at hotel reception

18:45A

rrival at “DR

ES

DE

N 1900” (A

n der Frauenkirche 20, 01067 Dresden)

19:00D

inn

er

22:00E

nd of 1st day

edaWorkshop15:

Ralf Popp (edacentrum

) fon: +

49 511 762-19697 popp@

edacentrum.de

Pro

gram

CATR

EN

E D

TC:

Ahm

ed Jerraya (CE

A-LETI)

fon: +33 438 780 128

ahmed.jerraya@

cea.fr













Wed

nesd

ay, May 20, 2015

Keyn

ote M

oderator: W. R


)

9:00S

ystem o

f System

s – Th

e Key E

nab

ler for Fu

ture A

pp

lication

s A


obile Com

munications, D

)

Techn

ical Sessio

n: M

od

eling

and

Sim

ulatio

nM

oderator: M. D


AS, D

)

9:30

Virtu

al Pro

totyp

ing

with

IP R

euse fo

r a ME

MS

Ap

plicatio

n w

ith

IP-X

AC

T an

d S

ystemC

-AM

S M

DV

PO

. Guillaum

e, F. Cenni, (ST M



AG

IL-LE

M, F), F. R

ahim (ATR

EN

TA, F), G

. Schröpfer, B

. Vernay (CO

VE

NTO

R, F)

10:05Leverag

ing

Verificatio

n o

f System

C w

ith U

VM


/EA

S, D)

10:30Q

&A

M. D


AS, D

)

10:35 C

offee B

reak

Techn

ical Sessio

n: FD

SO

I Eco

systems

Moderator: P. B


11:05FD

SO

I Device Param

eter Op

timizatio

n w

ith T

CA

DE

l Medi B

azizi (GLO

BA

LFOU

ND

RIE

S, D)

11:40FD

SO

I Silico

n E

nab

lemen

t Desig

n C

enter

O. Thom

as (CE

A-LETI, F)

12:05FD

SO

I and

AD

AS

Ap

plicatio

n fo

r Au

tom

otive

J. Benndorf (D

reamchip, D

)

12:30Q

&A

P. Blouet (ST M

icroelectronics, F)

Poster S

ession

Moderator: R


)

12:35In

trod

uctio

n o

f the Po

ster Exh

ibitio

nC


of project posters.

Poster E

xhib

ition


of next page.

13:20Lu

nch

and

Poster E

xhib

ition

Techn

ical Sessio

n: S

ecurity, S

afety and

Privacy – C

hallen

ges and

D

esign

So

lutio

ns fo

r Tom

orrow

´s Ap

plicatio

ns

Moderator: J. H

aase (edacentrum, D

)

14:35S

ecurity, S

afety and

Privacy b

ut w

hat fo

r and

how

…C

. Dietrich (G

emalto, F)

15:10N

ew Tru

sted H

ardw

are and

Firmw

are Co

mp

utin

g M

echan

isms

Ap

plicab

le to E

mb

edd

ed S

ystems

B. C

andaele (Thales, F)

15:35Q

&A


, D)

15:40C

offee B

reak

Techn

ical Sessio

n: V

2X: C

ar to E

nvirom

ent C

om

mu

nicatio

nM

oderator: R. H

oofman (N

XP, N

L)

16:10H

ow V

2X Lead

s to S

afe and

Secu

re Mo

bility

P. Pype (N

XP, B

E)

16:45V

AM

OS

– Th

e Traffic Man

agemen

t System

of D

resden

M. K

rumnov (TU

Dresden, D

)

17:10Q

&A

R. H

oofman (N

XP, N

L)

17:15B

reak

So

cial Even


estaurant “Alte M

eister“, address below)

17:45M



erman only) or


resden‘s old town

19:00M


19:15A

rrival at "Alte M


19:30C

on

fermen

t of "E

DA

-Med

aille 2015" W. R


)

20:00D

inn

er

23:00E

nd of 2nd day

Th

ursd

ay, May 21, 2015

Keyn

ote

Moderator: W

. Nebel (edacentrum

, D)

9:00D

esign

of S

ecure C

hip

sG

. Sigl (TU

München, D

)

9:30D

esign

for M

anu

facturin

g in

Extrem

e Scalin

g an

d B

eyon

dD

. Pan (U Texas at A

ustin, US

)

10:00C

on

fermen

t of “E

DA

Ach

ievemen

t Aw

ard 2015”

W. N

ebel (edacentrum, D

)

10:20C

offee B

reak

Techn

ical Sessio

n: M

EM

S an

d A

nalo

gM

oderator: U. S

chlichtmann (TU

München, D

)

10:50M

EM

S2015 Paves th

e Way to

Sch

ematic D

riven M

EM

S D

esign

T. Maier (B

osch, D), R

. Som

mer (IM

MS, D

)

11:10D

esign

of A

cceleration

Sen

sors U

sing

a System

atic ME

MS

-AS

IC

Desig

n Flow

R


. Som

mer (IM

MS, D

)

11:35B

ehavio

ral Mo

delin

g o

f an A

nalo

g N

eural R

ecord

ing

Fron

t-En

d fo

r S

ystem S

imu

lation

and

Reliab

ility An

alysisN

. Heidm

ann, N. H

ellwege, D


Brem

en, D)

12:00S

ymb

olic S

imu

lation

of M

ixed-S

ign

al System

s with

Exten

ded

Affin

e A

rithm

etic C. R

adojicic, C. G

rimm


Kaiserslautern, D

)

Poster E

xhib

ition


.

12:55Lu

nch

and

Poster E

xhib

ition

Techn

ical Sessio

n: S

trategy, An

alysis and

Diag

no

sis M

oderator: W. N

ebel (edacentrum, D

)

14:10N

ation

al Agen

da P

rocess to

Develo

p S

trategies fo

r Micro

electron

ics C

. Martin (B

MB

F, D)

14:25Fro

m M

aterial via SO

C to

System

s/Platfo

rms: T

he D

esign

Ro

adm

ap in

E

CS

EL M

AS

P

H. D

aembkes (A

irbus, D), J. N



, D)

15:45E

valuatio

n o

f circuit p

erform

ance an

d co

nfig

uratio

n red

uctio

n co

nsid

-erin

g p

ost-silico

n clo

ck skew tu

nin

g

B. Li, U

. Schlichtm

ann (TU M

ünchen, D)

15:10E

ffective Finite E

lemen

t Meth

od

for E

lectrom

igratio

n A

nalysis in

C

om

plex IC

Desig

n


Dresden, IFTE

, D)

15:35K

now

ledge-B

ased O

n-C

hip

Diag

no

sis for M

ulti-C

ore S

ystems-o

n-C

hip

P. W

agner (TU M



), T. W

ild, A. H

erkersdorf (TU M

ünchen, D)

16:00C

losin

g W

. Nebel (edacentrum

, D)

16:10E

nd of 3rd day

A Fram

ewo

rk for au

tom

ated V

erification

of u

ser-defin

ed M

BIS

T-A

lgorith

ms

J. Kinseher, M

. Richter (Intel M

obile Com

munications, D


)

A C

om

plete C

yber-P

hysical System

for M

ovemen

t Related

Poten

tials Detectio

n

by Syn

chro

nized

EE

G an

d E

MG

D



ES

D p

rotectio

n m

etho

do

logy o

n system

level and

con

cept o

n d

evice level G

. Noterm

ans, S. Holland (N

XP, D

), C. S


)

C++ P

rocesso

r Mo

dels fo

r Accelerated

Mu

lti-level Erro

r Effect S

imu

lation

M

. Greim

, D. M


. Schlichtm

ann (TU M

ünchen, D)



tion will show

results of all ED


MB

F within IK

T 2020.

Wo

rksho

p C

on

tribu

tion

s Accep

ted as Po

ster













Wed

nesd

ay, May 20, 2015

Keyn

ote M

oderator: W. R


)

9:00S

ystem o

f System

s – Th

e Key E

nab

ler for Fu

ture A

pp

lication

s A


obile Com

munications, D

)

Techn

ical Sessio

n: M

od

eling

and

Sim

ulatio

nM

oderator: M. D


AS, D

)

9:30

Virtu

al Pro

totyp

ing

with

IP R

euse fo

r a ME

MS

Ap

plicatio

n w

ith

IP-X

AC

T an

d S

ystemC

-AM

S M

DV

PO

. Guillaum

e, F. Cenni, (ST M



AG

IL-LE

M, F), F. R

ahim (ATR

EN

TA, F), G

. Schröpfer, B

. Vernay (CO

VE

NTO

R, F)

10:05Leverag

ing

Verificatio

n o

f System

C w

ith U

VM


/EA

S, D)

10:30Q

&A

M. D


AS, D

)

10:35 C

offee B

reak

Techn

ical Sessio

n: FD

SO

I Eco

systems

Moderator: P. B


11:05FD

SO

I Device Param

eter Op

timizatio

n w

ith T

CA

DE

l Medi B

azizi (GLO

BA

LFOU

ND

RIE

S, D)

11:40FD

SO

I Silico

n E

nab

lemen

t Desig

n C

enter

O. Thom

as (CE

A-LETI, F)

12:05FD

SO

I and

AD

AS

Ap

plicatio

n fo

r Au

tom

otive

J. Benndorf (D

reamchip, D

)

12:30Q

&A

P. Blouet (ST M

icroelectronics, F)

Poster S

ession

Moderator: R


)

12:35In

trod

uctio

n o

f the Po

ster Exh

ibitio

nC


of project posters.

Poster E

xhib

ition


of next page.

13:20Lu

nch

and

Poster E

xhib

ition

Techn

ical Sessio

n: S

ecurity, S

afety and

Privacy – C

hallen

ges and

D

esign

So

lutio

ns fo

r Tom

orrow

´s Ap

plicatio

ns

Moderator: J. H

aase (edacentrum, D

)

14:35S

ecurity, S

afety and

Privacy b

ut w

hat fo

r and

how

…C

. Dietrich (G

emalto, F)

15:10N

ew Tru

sted H

ardw

are and

Firmw

are Co

mp

utin

g M

echan

isms

Ap

plicab

le to E

mb

edd

ed S

ystems

B. C

andaele (Thales, F)

15:35Q

&A


, D)

15:40C

offee B

reak

Techn

ical Sessio

n: V

2X: C

ar to E

nvirom

ent C

om

mu

nicatio

nM

oderator: R. H

oofman (N

XP, N

L)

16:10H

ow V

2X Lead

s to S

afe and

Secu

re Mo

bility

P. Pype (N

XP, B

E)

16:45V

AM

OS

– Th

e Traffic Man

agemen

t System

of D

resden

M. K

rumnov (TU

Dresden, D

)

17:10Q

&A

R. H

oofman (N

XP, N

L)

17:15B

reak

So

cial Even


estaurant “Alte M

eister“, address below)

17:45M



erman only) or


resden‘s old town

19:00M


19:15A

rrival at "Alte M


19:30C

on

fermen

t of "E

DA

-Med

aille 2015" W. R


)

20:00D

inn

er

23:00E

nd of 2nd day

Th

ursd

ay, May 21, 2015

Keyn

ote

Moderator: W

. Nebel (edacentrum

, D)

9:00D

esign

of S

ecure C

hip

sG

. Sigl (TU

München, D

)

9:30D

esign

for M

anu

facturin

g in

Extrem

e Scalin

g an

d B

eyon

dD

. Pan (U Texas at A

ustin, US

)

10:00C

on

fermen

t of “E

DA

Ach

ievemen

t Aw

ard 2015”

W. N

ebel (edacentrum, D

)

10:20C

offee B

reak

Techn

ical Sessio

n: M

EM

S an

d A

nalo

gM

oderator: U. S

chlichtmann (TU

München, D

)

10:50M

EM

S2015 Paves th

e Way to

Sch

ematic D

riven M

EM

S D

esign

T. Maier (B

osch, D), R

. Som

mer (IM

MS, D

)

11:10D

esign

of A

cceleration

Sen

sors U

sing

a System

atic ME

MS

-AS

IC

Desig

n Flow

R


. Som

mer (IM

MS, D

)

11:35B

ehavio

ral Mo

delin

g o

f an A

nalo

g N

eural R

ecord

ing

Fron

t-En

d fo

r S

ystem S

imu

lation

and

Reliab

ility An

alysisN

. Heidm

ann, N. H

ellwege, D


Brem

en, D)

12:00S

ymb

olic S

imu

lation

of M

ixed-S

ign

al System

s with

Exten

ded

Affin

e A

rithm

etic C. R

adojicic, C. G

rimm


Kaiserslautern, D

)

Poster E

xhib

ition


.

12:55Lu

nch

and

Poster E

xhib

ition

Techn

ical Sessio

n: S

trategy, An

alysis and

Diag

no

sis M

oderator: W. N

ebel (edacentrum, D

)

14:10S

trategy Develo

pm

ent in

Micro

electron

ics Fun

din

g - T

he G

erman

A

gend

a Pro

cess C. M

artin (BM

BF, D

)

14:25Fro

m M

aterial via SO

C to

System

s/Platfo

rms: T

he D

esign

Ro

adm

ap in

E

CS

EL M

AS

P

H. D

aembkes (A

irbus, D), J. N



, D)

15:45E

valuatio

n o

f circuit p

erform

ance an

d co

nfig

uratio

n red

uctio

n co

nsid

-erin

g p

ost-silico

n clo

ck skew tu

nin

g

B. Li, U

. Schlichtm

ann (TU M

ünchen, D)

15:10E

ffective Finite E

lemen

t Meth

od

for E

lectrom

igratio

n A

nalysis in

C

om

plex IC

Desig

n


Dresden, IFTE

, D)

15:35K

now

ledge-B

ased O

n-C

hip

Diag

no

sis for M

ulti-C

ore S

ystems-o

n-C

hip

P. W

agner (TU M



), T. W

ild, A. H

erkersdorf (TU M

ünchen, D)

16:00C

losin

g W

. Nebel (edacentrum

, D)

16:10E

nd of 3rd day

A Fram

ewo

rk for au

tom

ated V

erification

of u

ser-defin

ed M

BIS

T-A

lgorith

ms

J. Kinseher, M

. Richter (Intel M

obile Com

munications, D


)

A C

om

plete C

yber-P

hysical System

for M

ovemen

t Related

Poten

tials Detectio

n

by Syn

chro

nized

EE

G an

d E

MG

D



ES

D p

rotectio

n m

etho

do

logy o

n system

level and

con

cept o

n d

evice level G

. Noterm

ans, S. Holland (N

XP, D

), C. S


)

C++ P

rocesso

r Mo

dels fo

r Accelerated

Mu

lti-level Erro

r Effect S

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Program


Location


edaWorkshop 15

jointly organized

Dresden, the capital of Saxony and the former residence of the Wettin dynasty, is a city of art and culture with magnificent buildings, many world-class museums as well as a rich tradition of theatre and music. No book about the history of architecture can forget to men-tion Dresden’s Zwinger Palace (s. picture on the left). The recon-structed Frauenkirche, the Semper Opera House and the Royal Palace as well as many other historical monuments and collections define the image of the city. See also: www.dresden.de















From the airportBy taxi: The taxi fare to the hotel is about EUR 22.By public transportation: Take S2 local train (direction “Heidenau”), get off at “Dresden Hauptbahn-hof” and proceed as written below. See also: www.dresden-airport.de

From the main railway stationTake tram no. 3 or 7 (direction “Dresden Wilder Mann” or “Weix-dorf”), get off at “Pirnaischer Platz”. Take tram 2 or 12 (direction “Dres-den Kleinzschachwitz Freystraße” or “Dresden Ludwig-Hartmann-Straße”), get off at “Deutsches Hygiene-Museum”. See also: www.dvb.de


Restaurant “Dresden 1900” With the era of Empire to Art Nou-veau Dresden provides another heyday apart from the time of Au-gustus the Strong. It was a period of entrepreneurs and inventors, the rising bourgeoisie and of basic development in public transport. The museum restaurant “Dresden 1900” provides a glimpse into the lives of Dresdens’ cirizens and their traffic history(ies) about 1900 showing one of the most beautiful squares of the past - the post office square – in 1900. The restaurant offers a good Saxonian kitchen from around 1900 and also creations of the modern German cuisine. Dresden 1900 is located vis-a-vis to the Frauenkirche, within walking distance to the Dorint hotel (15 min). Adress: An der Frauenkirche 20 www.dresden1900.de

Restaurant “Alte Meister” The Alte Meister café & restaurant was opened in October 2001 on the premises of Albert Braun’s former studio. Braun directed the artistic renovation of the Zwinger after World War II. In the museum café of the world-famous gallery of the same name, freshly made delicacies of creative seasonal kitchen are offered. A café durng the day, the “Alte Meister” turns into a stylish restaurant in the evening where dining between Rubens and Rossini becomes possible. The restaurant “Alte Meister” is located in the lavishly renovated Braun Atelier of the Dresden Zwinger next to the Sem-per Opera House. From the Dorint Hotel it located within walking distance (20 min). Adress: Theaterplatz 2 www.altemeister.net


Program


Location


edaWorkshop 15

jointly organized

Dresden, the capital of Saxony and the former residence of the Wettin dynasty, is a city of art and culture with magnificent buildings, many world-class museums as well as a rich tradition of theatre and music. No book about the his-tory of architecture can forget to mention Dresden’s Zwinger Palace (s. picture above). The recon-structed Frauenkirche, the Semper Opera House and the Royal Palace as well as many other historical monuments and collections define the image of the city. See also: www.dresden.de















From the airportBy taxi: The taxi fare to the hotel is about EUR 22.By public transportation: Take S2 local train (direction “Pirna”), get off at “Dresden Hauptbahnhof” and proceed as written below. See also: www.dresden-airport.de

From the main railway stationTake tram no. 3 (direction “Dresden Wilder Mann”), get off at “Pirnaischer Platz”. Take tram 2 or 12 (direction “Dresden Kleinzschachwitz Freystraße” or “Dresden Ludwig-Hartmann-Straße”), get off at “Deutsches Hygiene-Museum”. See also: www.dvb.de


Restaurant “Dresden 1900” With the era of Empire to Art Nou-veau Dresden provides another heyday apart from the time of Au-gustus the Strong. It was a period of entrepreneurs and inventors, the rising bourgeoisie and of basic development in public transport. The museum restaurant “Dresden 1900” provides a glimpse into the lives of Dresdens’ citizens and their traffic history(ies) about 1900 showing one of the most beautiful squares of the past – the post office square – in 1900. The restaurant offers a good Saxonian kitchen from around 1900 and also creations of the modern German cuisine. “Dresden 1900” is lo-cated vis-a-vis to the Frauenkirche, within walking distance to the Dorint hotel (15 min). Address: An der Frauenkirche 20 www.dresden1900.de

Restaurant “Alte Meister” The Alte Meister café & restaurant was opened in October 2001 on the premises of Albert Braun’s former studio. Braun directed the artistic renovation of the Zwinger after World War II. In the museum café of the world-famous gallery of the same name, freshly made delicacies of creative seasonal kitchen are offered. A café during the day, the “Alte Meister” turns into a stylish restaurant in the evening where dining between Rubens and Rossini becomes possible. The restaurant “Alte Meister” is located in the lavishly renovated Braun Atelier of the Dresden Zwinger next to the Sem-per Opera House. From the Dorint Hotel it is located within walking distance (20 min). Address: Theaterplatz 1a www.altemeister.net


Foto: Popp

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