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RF2THZ SISOC Project 1/35

A 55-nm BiCMOS Platform for Optical and Millimeter-Wave Systems -on-Chip

Pascal CHEVALIER

STMicroelectronics, Crolles (F)[email protected]

Open Bipolar Workshop3 October 2013, Bordeaux (F)

CATRENE – CT209 – RF2THZ SiSOC

RF2THZ SISOC Project / P. Chevalier – 03/10/2013 2/3 5

Acknowledgement

Staff of STMicroelectronics, Crolles from TCAD, Process Development,Process Integration, Physical & Electrical Characterizati on, Modeling,Design, 300mm fab… involved in the development of High-SpeedBiCMOS technologies

G. Avenier, E. Canderle, J.L. Carbonero, D. Céli, N. Derrier , C. Deglise-Favre, C. Durand, D. Gloria, A. Montagné, G. Ribes, B. Sautre uil,T. Quémerais from ST for their direct or indirect contributions to thislecture

French Ministry of the Economy & of the Industry and the Europ eanCommission for their financial support through the RF2THZ S ISOCproject


Project ID

The project CATRENE RF2THZ CT209 aims at the establ ishment of silicon technology platforms for emerging Radio Fre quency (RF), Millimeter-Wave (MMW) and TeraHertz (THz) consumer ap plications. 77GHz/120GHz automotive radars

MMW imaging and sensing

Fast measurement equipment

Two-way satellite communications systems

Duration: 42 months: from 01.07.2011 to 31.12.2014 (+ 3 months for ALUD in Germany)

Consortium: 32 partners

Total Effort: 232.84 MY

60GHz networking and fast downloading

400 Gbit/s fibre optics data communications

4G photonic mobile communication

4 countries

RF

2TH

Z


RF2THZ in Europe

AgilentAlcatel-LucentBoschFraunhofer IHPMicramSynViewSilicon RadarUdSTUBTUDD

Axiom ICBruco

MASERNXP

SallandTU Delft

Tu/e

ASTUSCEA-LETI

ENSICAENESIEEG-INPIEMNIES IMSNXP

STMicroelectronics SASTMicroelectronics SAS

Telecom B XMOD

Newtec

RF

2TH

Z


Main project objectives

3 BiCMOS technology platforms: ST will integrate and optimize SiGe HBT and back-end modules in a new

advanced CMOS technology (55nm)

NXP will focus on improvements of high performance RF passive for current BiCMOS technology generations as well as corresponding RF packaging and testing solutions

IHP will develop silicon photonics devices

5 demonstrators of those platforms: Demo 1: 16QAM 400 Gbit/s system and test solutions

Demo 2: Photonic Transceiver for 4G Wireless based on IHP Photonic SiGeBiCMOS

Demo 3: 120GHz & 240GHz sensor system platform

Demo 4: Two-way satellite communication for consumer application

Demo 5: Radar sensor system components for 79 and 122 GHz

RF

2TH

Z


Outline

RF2THZ project

Motivation

Back to B5T results obtained in Dot Five

B55 platform definition & offer

B55 1st electrical results

Summary

MO

TIV

ATIO

NB

5TB

55 P

LAT

FO

RM

B55

RE

SU

LTS

SU

MM

AR

YR

F2T

HZ


ST high -speed BiCMOS roadmap

BICMOS6G

0.35-µm CMOS

SiGe HBT fT = 45 GHzfMAX = 60 GHz

BICMOS7

0.25-µm CMOS

SiGe HBT fT = 70 GHzfMAX = 90 GHz

HCMOS9SiGe

0.13-µm CMOS

SiGe-C HBTfT = 50 GHzfMAX = 90 GHz

BICMOS9

0.13-µm CMOS

SiGe-C HBT fT = 160 GHz fMAX = 160 GHz

BICMOS6/6M

0.35-µm CMOS

Si BJT fT = 25 GHzfMAX = 40 GHz

BICMOS7RF

0.25-µm CMOS


L/P

D/M D/M

D/M

D/M

8’’

L/P

S/M

Single Poly Double Poly

NSEG SiGe

SEG SiGe-C

P=Polyemitter M=Monoemitter

D=DTIL=LOCOS S=STI

NSEG SiGe:C

Base epitaxy

Collector isolation

E/B architecture

Emitter

Production

R&D

BiCMOS05555-nm CMOS


D/M

Why?

Continuous evolution of SiGeHBT architecture & CMOS node towards best performance vs. complexity trade-off

BICMOS9MW

0.13-µm CMOS


MO

TIV

ATIO

N

12’’


High -speed BiCMOS demand

Driven by Ethernet bandwidth explosion, Optical Com munications companies ask for new BiCMOS technologies featuring: Denser CMOS (skyrocket of digital need)

Faster SiGe HBT

With High-Q passives

To: Reduce power consumption of existing 100 Gb/s solutions

Develop IC for next Ethernet generation (≥ 400 Gb/s)

Other millimeter-wave applications benefit from thi s push: Current applications up to ~100 GHz (60 GHz wireless LAN, 77 GHz automotive

radars, 120 GHz velocity & position sensors) can be improved (gain, noise, power consumption,…)

Move up in frequency spectrum (≥ 160 GHz) with highly integrated solutions becomes possible: Sensors for medical, security,…

Because…M

OT

IVAT

ION


We can make it!

SiGe HBT performance required for next BiCMOS node demonstrated in the frame of the European project DotFive

Because…

0.1 1 10 1000

100

200

300

400 B9MW B5T f

T f

T

fMAX

fMAX

f T &

fM

AX (

GH

z)

Collector current density JC (mA/µm²)

ParameterfT

(GHz)fMAX

(GHz)

B9MW 220 280

B3T 260 330

B4T 270 370

B5T 300 400

P. Chevalier et al, CSISC 2012

Different trade-offs demonstrated in DotFive:430 GHz fMAX / 290 GHz fT380 GHz fMAX / 320 GHz fT

MO

TIV

ATIO

N

RF2THZ SISOC Project / P. Chevalier – 03/10/2013 10/ 35

Double Polysilicon Self-Aligned (DPSA) architecture

This architecture relies on the Selective Epitaxial Growth of the base

B5T


DPSA architecture scaling – 1/2

Lateral scaling allows reducing all capacitances & resistances but R E

Downscaling of emitter, polyemitter and inside spacer widths is beneficial to RB

Downscaling of base/collector width is beneficial to CBC

P. Chevalier et al, BCTM 2009

B5T


DPSA architecture scaling – 2/2

Impact of ττττBC / CBC & ττττB / RB trade-offs, R Bx (extrinsic), and benefit of lateral scaling, on f T & fMAX

250 275 300 325300

325

350

375

high

low

small

large low

high

Collector doping Thermal budget Base doping Emitter width

Max

. osc

illat

ion

freq

. fM

AX (

GH

z)

Current gain transition freq. fT (GHz)

highlow

Collector doping (BV CBO)- Low- HighThermal budget (spike temp.)- High- LowBase doping (Boron dose)- High- LowEmitter width (W E)- Large- Small

CBEBC HBTL = 5 µm, V CB = 0.5 V


B5T


Devices & circuits performance

0 5 10 15 20 25 30 350

2

4

6

8

MA

G @

120

GH

z (d

B)

Collector current density JC (mA/µm²)

B9MW B3T B4T B5T

0.1 1 10 1001.0

1.5

2.0

2.5

3.0

3.5

4.0

NF

min

(dB

)Frequency (GHz)

B9MW B3T B4T B5T

280 300 320 340 3601

2

3

4

5

6

7

0

5

10

15

20

25

30

0.09 µm0.12 µm0.13 µmW

E (µm)

B4TB3T

GT @

1dB

(dB

), O

P1d

B (

dBm

)

Maximum oscillation frequency fMAX

(GHz)

OP1dB (dBm) G

T

B9MW

OP1dB (mW/mm) PAE

OP

1dB

(m

W/µ

m),

PA

E (

%)

0 4 8 12 16 200

1

2

3

4

5

6

7

Gat

e de

lay

ττ ττ D (

ps)

Current Density per Gate (mA/µm²)

B9MW B4T B5T

ττττDmin Med (ps) Min (ps) Max (ps) σ (%)

B9MW 3.22 3.15 3.30 0.87B4T 2.59 2.56 2.64 0.62

B5T 2.33 2.27 2.44 1.71

130 140 150 160 1700

10

20

30

40

-3

0

3

6

9

S21

S21

(dB

)

Frequency (GHz)

Out

put P

ower

(dB

m)

OP B9MW B3T B4T

0 10 20 30 40 50 60 70-50

-40

-30

-20

-10

0

10

20

30

Inpu

t Pow

er (

dBm

)

Frequency (GHz)

B5T B9MW

Maximum Available Gain Minimum Noise Figure Power Performances @ 94GHz

Ring Oscillators Gate Delay 160-GHz Amplifiers 16:1 Static Divider Chains


B5T


From B5T to BiCMOS055

B5T Bipolar-only technology

developed in the frame of the European FP7 project Dotfive

200mm wafer fab

130nm ‘CMOS’ node

mm-W dedicated BEOL (6 ML)

HS NPN HBT:

• fT ~ 300 GHz

• fMAX ~ 400 GHz

R&D technology no longer available for prototyping (will never go into production)

BiCMOS055 = B55 BiCMOS technology supported

in the frame of the European CATRENE project RF2THZ

300mm wafer fab

55nm CMOS node

mm-W dedicated BEOL

HS NPN HBT:

• fT ~ 320 GHz

• fMAX ~ 370 GHz

Industrial technology under development (will go into production)

Bas

edon

B

iCM

OS

9MW

B55

PLA

TF

OR

M


Challenges & opportunities

Challenges Process complexity (number of MOS devices)

Structural integration issues (CMOS/Bipolar patterning compatibility, PMD thickness, …)

BEOL vertical shrink (and low-k dielectrics) for high-Q passives & electromigration capability

Many new operations to develop in 300mm and copy/paste from 200mm not possible

Opportunities Tools (ex: lithography for lateral scaling) &

advanced process bricks available in 300mm

Rotated substrate (hole mobility )

Same HBT architecture and similar thermal budget between B55 and B5T B5T used to build tentative B55 models (w/ TCAD) 0

2

4

6

8

10

130nm (6ML)

65nm (6ML)

65nm (7ML)

28nm (6ML)

28nm (7ML)

28nm (10ML)

Dis

tanc

e (µ

m)

CMOS node (# of Cu layers)

Top of Alucap to Active Bottom of last Cu layer to M2 top

P. Chevalier , BCTM SC 2011

F. Boeuf , VLSI SC 2009

B55

PLA

TF

OR

M


Technology overview

BiCMOS055

55nm SiGe BiCMOS technology

55nm LP/GP CMOS devices(720 KGates/mm²)

Specific MOS varactors

Thick copper BEOL + MIM5

Transmission lines

Inductors, …

SiGe NPN HBTs

High-Speed, Medium-Voltage

& High-Voltage

V-PNP

TFR

+

CMOS055 vs. CMOS065

• 10% linear shrink of CMOS065

• No change of minimum gate lengths

• Uses 65nm design platform

B55

PLA

TF

OR

M


Front-end of line

Same integration of SiGe HBTs as for BiCMOS9MW i.e. : Buried layer / Collector epitaxy and DTI before STI formation

Emitter / Base architecture built between gate deposition and gate patterning

TEM analysis done on 1st B55 full integration LP/GP lot after W CMP

B55

PLA

TF

OR

M

As in-situ doped emitter

B doped polybase

Si/SiGe:C B doped base

Inside spacers


Back-end of line

8M4X2Z1U BEOL based on standard 7ML C055: M8U (h=3.0µm, w/s=0.60µm/0.60µm) & V7U (h=1.5µm, w/s=0.40µm/0.40µm)

MIM5 integrated in V5Z

8.3µm

BiCMOS9MW

polySi

M6T

AP

M5T

M1

CB

ViaT

ViaZ

ViaX

M4Z

M3X

ViaT

3.1µm

CMOS0557M4X2Z0U

polySi

M6Z

M5X

M1

ViaX

ViaZ

M7Z

ViaZ

AP

polySi

M6Z

M5X

M1

ViaX

ViaZ

M7Z

ViaZ

5.5µm

M8U

AP

CB

ViaU

BiCMOS0558M4X2Z1U

MIM5

MIM2

M2 to LM

All the 55-nm CMOS libraries are compatible with B55

B55

PLA

TF

OR

M


Technology offer

Core LP/GP HVT & SVT CMOS w/ 2.5V

IOs (incl. RF SVT for LP & GO2) SRAM LVT + HVT High-Speed Si/SiGe:C HBTs Medium-Voltage Si/SiGe:C HBTs Natural NPN & PNP bipolar

transistors Natural resistors (active, poly &

metal – incl. RF resistors) Natural DC capacitors (poly, plate) Single & Diff. GO1/GO2 varactors RF MOM (M1 to M5) MMW, LAMW & HQ inductors µstrip transmission line Digitally Tuned Capacitor

Options LP & GP CMOS LVT (incl. RF

models for LP) High-Voltage Si/SiGe:C HBTs 6kΩ/sq. HIPO resistor (incl. RF

model) 5fF/µm² MIM capacitor Vertical PNP Thin Film Resistor

Masks

• 53 masks for core process

• +2 for LVT

• +1 for HIPO

• +2 for MIM5

Not available in current design kit

B55

PLA

TF

OR

M


Qualification schedule

B55 is already available for risk prototyping in RF 2THZ and for

preferred customers

2013 2014 2015

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

BiCMOS055

Maturity 30

Maturity 20

Design Platform

DP1.0 with DK_bicmos55lpgp_RF_8m4x0y2z1u_2V5 Rev1.0

B55

PLA

TF

OR

M

Maturity 10


Devices targets – CMOS

LP/GP Mix baseline (SVT/HVT) w/ 2.5V IOs (triple ga te oxide)

LVT is an option for both LP and GP

B55

PLA

TF

OR

M


Devices targets – Varactors

P+/NWell GO1 & GO2 (single ended & differential)

DeviceOxidetype

Capacitancerange

(Cmin / max)

Typical tuning ratio@ 25 GHz

@ C =100 fF

Max Q @ C =100 fF @ 25 GHz@ V =1,2 V

Freq_res @ C =100 fF

@ 1,2 V (GO1)@ 2,5 V (GO2)

Varactor P+/NWell GO1 SEcpo12nw_var

GO11,2 V

5 fF / 1 pF 3(max 5)

20 > 110 GHz

Varactor P+/NWell GO2 SEcpo25nw_var

GO22,5 V

5 fF / 1 pF 3(max 5)

60 > 110 GHz

Varactor P+/NWell GO1 DIFFcpo12nw_diff_var

GO11,2 V

5 fF / 1 pF 3(max 5)

25 > 110 GHz

Varactor P+/NWell GO2 DIFFcpo25nw_diff_var

GO22,5 V

5 fF / 1 pF 3(max 5)

65 > 110 GHz

B55

PLA

TF

OR

M


Devices targets – Inductors & transmission lines

Inductors & TL benefit from the 8ML BEOL with thick Via7/Metal8

Device Stack L QmaxSelf

resonancefrequency

MMW Inductorind_mmw_8m4x0y2z1u

Coil M8UUpath M7ZGnd ring M1

From 10pHto 1.5nH

From 8to 28

From 27GHzto 300GHz

Device Stack Zc IL

µ-strip TLmicrostrip_8m4x0y2z1u

Line in M8UGnd in M1 or M4

From 35to 70Ω

0.65dB/mm@50GHz

4.25-turn inductor 3D view

1-turn inductor 3D view M8 line

M1 gnd

Lateral wall

3D schematic view

B55

PLA

TF

OR

M

Inductors geometry:

• Number of coil turns (n): 1 to 4.25

• Internal coil diameter (d): 10 to 50 µm

• Coil width (w): 0.6 to 4 µm


Devices targets – SiGe HBTs

3 collector flavours sharing the same E/B system

DevicefT

(GHz)fMAX

(GHz)BVCEO

(V)

HS NPN SiGe HBTnpnvhs, npnvhs_t

320VCB=0.5VVBE=0.92V


1.55IB=0µA

MV NPN SiGe HBTnpnvmv, npnvmv_t



1.8IB=0µA

HV NPN SiGe HBTnpnvhv, npnvhv_t

60VCB=2.0VVBE=0.80V


3.5IB=0µA

CBEBC: Wdrawn= 0.2 µm, Ldrawn=5.56µm, T=25°C

B55

PLA

TF

OR

M


CMOS results – LP devices

Si is in specs (on target for HVT) for the 3 flavou rs

Additional tuning to be done on SVT and LVT transis tors

N-Ion (µA/µm)P

-Iof

f(lo

g(A

)/µm

)P-Ion (µA/µm)

N-I

off

(log(

A)/

µm)

W=1m

HVT

SVT

LVT

NMOS LP

LVT

SVT

HVT

PMOS LP

L=60 nm & W=1 µm (drawn dimensions)

B55

RE

SU

LTS


CMOS results – GP devices

Si is on target for the 3 flavours

N-Ion (µA/µm) P-Ion (µA/µm)

N-I

off

(log(

A)/

µm)

P-I

off

(log(

A)/

µm)

LVT

SVT

HVT

LVT

SVT

HVT

NMOS GP PMOS GP

P-I

off

(log(

A)/

µm)

B55

RE

SU

LTS

L=60 nm & W=1 µm (drawn dimensions)


CMOS results – SRAM

All SRAM are in specs, tuning required to reach tar get for 062S 056LH (BitCell SP 0.56 µm² - HVT) 062H (BitCell SP 0.62 µm² - HVT) 062S (BitCell SP 0.62 µm² - SVT)

Sta

nd-b

y le

akag

e(Lo

gA/c

ell)

0.56 LH0.56 LH0.56 LH0.56 LH

0.62H0.62H0.62H0.62H

0.62S0.62S0.62S0.62S

SRAM Cells

Iread(µA/cell)

B55

RE

SU

LTS


Varactor results – GO2 single-ended

C(V) @ f=1GHz

C(V) @ f=1GHz

C(f) @ V=2.5 V Q(f) @ V=2.5 V

C(f) @ V=2.5 V Q(f) @ V=2.5 V

B55

RE

SU

LTS

Measurements in line with targeted values C=48 fF (w=1.5 µm, l=0.25 µm, Nbfp=10, Nbcell=2)

C=550 fF (w=5 µm, l=60 nm, Nbfp=50, Nbcell=4)

---- measmeasmeasmeas. . . . ---- simsimsimsim....


Measurements in line with targeted values

Passives results – MIM

5×5 µm² 150×150 µm²

Cap

acita

nce

(fF

)

Cap

acita

nce

(fF

)

Frequency (Hz) Frequency (Hz)

B55

RE

SU

LTS


Measurements in line with targeted values

Passives results – MOM

M2-M5 (80×80 fingers) M2-M5 (217×217 fingers)

Frequency (Hz) Frequency (Hz)

Cap

acita

nce

(pF

)

Cap

acita

nce

(pF

)

B55

RE

SU

LTS


Passives results – Inductors

Measurements in line with targeted values Inductance range: 10pH to 1.4 nH

Qmax: 8 to 28

Self resonance frequency: 5 to up to 100 GHz

B55

RE

SU

LTS

0

5

10

15

20

25

30

0 200 400 600 800 1000

Qm

ax

Inductance value L (pH)

Ind mmW B55 1-turn Ind mmW B55 n-turns


HS SiGe HBT results – 0.20×5.0 µm²

Si not far from target on first full

integration lots!

Beta @ VBE = 0.7 V ~ 1500

BVCEO = 1.5 V

BVCBO = 5.2 V

VAF = 120 V

VAR = 2.1 V

fT = 290 GHz

fMAX = 350 GHz

IC (A)

f T&

f MA

X(G

Hz)

I C(m

A)

VCE (V)

VCB = 0.5 V

B55

RE

SU

LTS


HS SiGe HBT results – Scalability (DC)

L variations from 0.45 µm to 10 µm (drawn emitter l ength)

LE from 0.32 µm to ~8.9 µm

W variations from 0.20 µm to 0.42 µm (drawn emitter width)

WE from 0.10 µm to ~0.30 µm

I C&

I B(A

)

VBE (V)

I C&

IB

(A)

VBE (V)

L variation – W=0.2µm

VCB = 0 V

W variation – L=5µm

VCB = 0 V

B55

RE

SU

LTS


HS SiGe HBT results – Scalability (HF)

L variation

VCB = 0.5 V

W variation

VCB = 0.5 V

L variation

VCB = 0.5 V

W variation

VCB = 0.5 V

f T(G

Hz)

f T(G

Hz)

f MA

X(G

Hz)

f MA

X(G

Hz)

IC (A)

IC (A) IC (A)

IC (A)

B55

RE

SU

LTS


Summary

BiCMOS055 technology is being developed in the fram e of the European project RF2THZ SISOC

It is a unique technology, offering in 55-nm CMOS ( 300mm fab), state-of-the-art SiGe HBTs and high-Q passives

Electrical results on 1 st full integration lots exhibit Si in specs for all devices, which is a requirement for Maturity 10

Measurements done on high-speed SiGe HBTs featuring different design rules than nominal ones show significant mar gin to increase fMAX above the targeted value

B55 is already available for risk prototyping and w ill go into production end of 2015

SU

MM

AR

Y

catrene – ct209 – rf2thz sisoc - tu dresden · pdf filerf2thz sisoc project 1/35...

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