case study of ibis v4.1 by jeita eda-wg - ibis open forum · pdf filecase study of ibis v4.1...

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Case study of IBIS V4.1Case study of IBIS V4.1　　　　　　　　 by by

JEITA EDAJEITA EDA--WGWG

JEITA ; Japan Electronics and Information Technology Industries Association

June 8 , 2004June 8 , 2004IBIS SUMMIT in San Diego, CaliforniaIBIS SUMMIT in San Diego, California

JEITA EDAJEITA EDA--WGWGA. A. ItohItoh, T. Watanabe, N. Matsui, T. Watanabe, N. Matsui

©© JEITA 2004. All Rights Reserved.JEITA 2004. All Rights Reserved.

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OutlinesOutlines

1. JEITA EDA1. JEITA EDA--WG ActivitiesWG Activities

2. Case study of IBIS V4.12. Case study of IBIS V4.1

3. EMI Model3. EMI Model


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1. 1. JEITA EDAJEITA EDA--WG ActivitiesWG Activities


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EDA Model for

Auto Mobile Electronics ?

(Digital , RF, and Analog circuits)

(Motor Drive, EMC)

Cellular Phone, LCD TV, Digital Camera/Video, DVD Recorder

Digital Consumer Electronics

< Applicability of IBIS V4.1 >


Objectives of JEITA EDAObjectives of JEITA EDA

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DiscreetSemicon

PCB

Passive Component(LCR, Filter)

RF Modules

Displaydevice

Connectors

Cables

FPC

Crystal Oscillator

IC Package

IC ChipLSI Model


EDA Model for SI, PI and EMI SimulationEDA Model for SI, PI and EMI Simulation

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ICs

IC Package

DiscreteSemiconductors

PassiveComponents

(LCR, Filter)

Crystal Oscillator

ConnectorsCables

PCB

FPC

RF Modules

EDA ModelsFor

Digital Consumer electronics


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NECEL

Toshiba

Shin Dengen

TDKMurata

PanasonicSonySharpCanon

Toshiba

CMK

Mectron

EDA ModelsEDA ModelsFor For

Digital Consumer electronicsDigital Consumer electronics

FujitsuMitsubishi

Apsim

DigitalConsumerElectronicsSupplier

EDA(internal/vendor)

Connectors

FPC

PCB

Semicon Passive Components

Discrete　　　　ICs

JAE©© JEITA 2004. All Rights Reserved.JEITA 2004. All Rights Reserved.

JEITA EDA-WG MemberJEITA EDA-WG Member

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2. 2. Case study of IBIS V4.1Case study of IBIS V4.1


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Passive Components　　　　

DSP, AD/DA, Xtal

ASIC/SOC for EMI/SSO 　　　　

Package, Module,PCB

Connector, Cable,FPC

Summary of investigation of IBIS V4.1Summary of investigation of IBIS V4.1

CommentsIBIS V4.1 SPICE V4.1 *AMS

✓✓✓✓ (✓✓✓✓)Accurate models need the internal gates for EMI/SSO. IBIS V4.1 SPICE disclosesprocess parameters.

V3.2

✓✓✓✓ I/O for SI can be described in V3.2. Inside needs *AMS.

Power SemiconductorOpAMP　　　　 ✓✓✓✓ (✓✓✓✓) IBIS V4.1 SPICE discloses

process parameters.

✓✓✓✓

✓✓✓✓ (✓✓✓✓?)

ICM

Can describe LCRK modelsICM describes S-parameters ✓✓✓✓

✓✓✓✓ (✓✓✓✓?) IBIS 4.1 SPICE can’t describe S-parameters or lossy coupledtransmission line. ICM can’t include discrete components.SiP and PWRGND modeling.

✓✓✓✓

✓✓✓✓

(✓✓✓✓)

(✓✓✓✓)

✓✓✓✓(✓✓✓✓) (✓✓✓✓) ICM can’t include discrete components.


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IBISV4.1IBISV4.1

IMICIMIC(Table_SPICE)(Table_SPICE)

ICMICMV1.0V1.0

IBIS excludes IMIC

SPICE3SPICE3

VHDLVHDL--AMSAMS

Understanding of IBIS V4.1Understanding of IBIS V4.1

[Component]

[Model]

[External Circuit]

[External Model]Model_type

IBIS

[Node Declarations][Circuit Call]


VerilogVerilog--AMSAMS

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How to describe SPICE transistor model in IBIS 4.1 without disclosing proprietary informationHow to describe SPICE transistor model in IBIS 4.1 without disclosing proprietary information

Net List Equivalent Circuit (Macro Model)using Transistor Models

TransistorParameters

IBIS V4.1 allows to use SPICE3 but discloses process parameters

Models described in SPICE transistors have flexibility.

IMIC (Table_SPICE) allows to hide the transistorparameters, but IBIS V4.1 excludes IMIC.


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How to hide transistor model parameters in IBIS V4.1 SPICE description without losing accuracyHow to hide transistor model parameters in IBIS V4.1 SPICE description without losing accuracy

IMIC (Table_SPICE) allows to hide the transistorparameters, but IBIS V4.1 excludes IMIC.

Need to have a bridge from IMIC to IBIS V4.1SPICE 3 without disclosing the original SPICEtransistor parameters.


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3. 3. EMI Model (NEC/APSIM)EMI Model (NEC/APSIM)

©© NEC/APSIM 2004. All Rights Reserved.NEC/APSIM 2004. All Rights Reserved.

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Power Supply

LSI

RF Current of LSI

1. Measurement; IEC61967-6.Magnetic Probe Method2. Simulation Model; EMI Model for LSI

LSI Model for EMI SimulationLSI Model for EMI SimulationLSI Model for EMI Simulation


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powerpower

groundgroundClock MacroClock MacroInput/Input/

OutputOutputNonNon--ClockClock

MacroMacro

RF CurrentRF CurrentRF CurrentRF CurrentPower and Ground ModelPower and Ground Model

ClocClockkPKGPKGinputinput

PCBPCB

IO ModelIO Model

ChipChip

Power/GroundPower/GroundPlanePlane

LSILSI

Power/GroundPower/GroundPlanePlane

PKGPKG

PCBPCB

EMI Simulation for PCBEMI Simulation for PCBEMI Simulation for PCB

outputoutput

EMI simulation needs the internal gates power/ground model with loading effects in time/frequency domain.


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Output

Internal

Total

Current Waveforms of 32-bit LSICurrent Waveforms of 32Current Waveforms of 32--bit LSIbit LSI


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Magnetic probe

Pre-amplifier (option)

Spectrum analyzer

Power supplyIC test board Decoupling

capacitor

Magnetic field

Current

LSI

MeasurementMeasurementIEC61967-6. Magnetic Probe Method


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Simulation VS MeasurementSimulation VS Measurement

8Tr D,FL,RAM

-20

0

20

40

60

80

100

10 100 1000

MHz

dBuA

5s(D) 5s(B+D+F) 実測Simulation Measurement8Tr D,FL,RAM

-20

0

20

40

60

80

100

10 100 1000

MHz

dBuA

5s(D) 5s(B+D+F) 実測Simulation Measurement


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© APSIM

Simulation Measurement

Current/Magnetic Field DistributionCurrent/Magnetic Field DistributionCurrent/Magnetic Field Distribution


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outputoutput

powerpower

groundgroundClock MacroClock Macro

inputinput

InputInput NonNon--Clock MacroClock Macro

PKGPKG

OutputOutput

PKGPKG

RF RF RF RF CurrentCurrentCurrentCurrent

Power and Ground Model of Core Logics (internal gates)Power and Ground Model of Core Logics (internal gates)

EMI Simulation Model for LSI EMI Simulation Model for LSI

IBIS 4.1

IMICIBISV3.2 IBISV3.2


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Developed IMIC to IBIS V4.1 ConverterDeveloped IMIC to IBIS V4.1 ConverterAny SPICEAny SPICE.MODEL.MODEL

Table_SPICETable_SPICE.MODEL.MODEL

Table_SPICE Table_SPICE GeneratorGenerator

Table_SPICE Table_SPICE to to SPICE 3 MODEL3 ConverterSPICE 3 MODEL3 Converter

SPICE 3 LEVEL=3SPICE 3 LEVEL=3.MODEL .MODEL

IMIC

IBIS V4.1

Any SPICEAny SPICE

The parameters of LEVEL=3 can’t disclose those of the original SPICE.


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LEVEL=3LEVEL=3

TableTable

Full chip power/ground current models in time/frequency domain for EMI SimulationFull chip power/ground current models in time/frequency domain for EMI Simulation


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Example of LSI Power/Ground Model (IBIS V 4.1)Example of LSI Power/Ground Model (IBIS V 4.1)


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Example of LSI Power/Ground Model (IBIS V 4.1)Example of LSI Power/Ground Model (IBIS V 4.1)Original SPICE MOS parameters

Table_SPICE MOS V-I-C dataSPICE 3 Level=3 MOS minimum parameters


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case study of ibis v4.1 by jeita eda-wg - ibis open forum · pdf filecase study of ibis v4.1...

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