cache memory midterm 2 revision 2 prof. sin-min lee department of computer science
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Cache MemoryMidterm 2 Revision 2
Prof. Sin-Min Lee
Department of Computer Science
The Processor Picture
The Five Classic Components of a Computer
Control
Datapath
Memory
Processor
Input
Output
von NeumannArchitecture
Princeton
Address Pointer
ArithmeticLogic Unit
(ALU)
Memory
Program Counter
Pc = Pc + 1
Data/Instructions
Featuring Deterministic Execution
Cache Memory
• Physical memory is slow (more than 30 times slower than processor)
• Cache memory uses SRAM chips.– Much faster– Much expensive– Situated closest to the processor
• Can be arranged hierarchically– L1 cache is incorporated into processor– L2 cache is outside
Cache Memory
This photo shows level 2 cache memory on the Processor board, beside the CPU
Cache Memory- Three LevelsArchitecture
Address Pointer
MemoryMulti-
Gigabytes
Large and Slow160 X
16XL3 CacheMemory
Cache ControlLogic
L2 CacheMemory
L1 CacheMemory
2X 8X
16 Megabytes128 Kilobytes32 Kilobytes
2 Gigahertz Clock
Featuring Really Non-Deterministic Execution
Cache (1)
• Is the first level of memory hierarchy encountered once the address leaves the CPU– Since the principle of locality applies, and taking
advantage of locality to improve performance is so popular, the term cache is now applied whenever buffering is employed to reuse commonly occurring items
• We will study caches by trying to answer the four questions for the first level of the memory hierarchy
Subtract by Summation
• Subtraction with complement is done with binary numbers in a similar way.
• Using two binary numbers X=1010100 and Y=1000011
• We perform X-Y and Y-X
X-Y
• X= 1010100
• 2’s com. of Y= 0111101
• Sum= 10010001
• Answer= 0010001
Y-X
• Y= 1000011
• 2’s com. of X= 0101100
• Sum= 1101111
• There’s no end carry: answer is negative --- 0010001 (2’s complement of 1101111)
How To Represent Signed Numbers• Plus and minus signs used for decimal numbers: 25
(or +25), -16, etc.
• For computers, it is desirable to represent everything as bits..
• Three types of signed binary number representations: 1. signed magnitude, 2. 1’s complement, and 3. 2’s complement
1. signed magnitude• In each case: left-most bit indicates sign:
positive (0) or negative (1).
Consider 1. signed magnitude:
000011002 = 1210
Sign bit Magnitude
100011002 = -1210
Sign bit Magnitude
2. One’s Complement Representation
• The one’s complement of a binary number involves inverting all bits.
• To find negative of 1’s complement number take the 1’s To find negative of 1’s complement number take the 1’s complement of whole number including the sign bit.complement of whole number including the sign bit.
000011002 = 1210
Sign bit Magnitude
111100112 = -1210
Sign bit 1’complement
3. Two’s Complement Representation
• The two’s complement of a binary number involves inverting all bits and adding 1.
• To find the negative of a signed number take the 2’s the 2’s complement of the positive number including the sign bit.
000011002 = 1210
Sign bit Magnitude
111101002 = -1210
Sign bit 2’s complement
The rule for addition is add the two numbers, including their sign bits, and discard any carry out of the sign (leftmost) bit position. Numerical examples for addition are shown below.Example:
+ 6 00000110 - 6 11111010+13 00001101 +13 00001101+19 00010011 +7 00000111
+6 00000110 -6 11111010-13 11110011 -13 11110011-7 11111001 -19 11101101
In each of the four cases, the operation performed is always addition, including the sign bits.Only one rule for addition, no separate treatment of subtraction. Negative numbers are always represented in 2’s complement.
Sign addition in 2’s complement
Arithmetic Subtraction
• A subtraction operation can be changed to an addition operation if the sign of the subtrahend is changed.
• (±A) - (+B) = (±A) + (-B)
• (±A) - (-B) = (±A) + (+B)
Arithmetic Subtraction• Consider the subtraction of (-6) - (-13) = +7. In
binary with eight bits this is written as 11111010 - 11110011. The subtraction is changed to addition by taking the 2’s complement of the subtrahend (-13) to give (+13). In binary this is 11111010 + 00001101 = 100000111.
• Removing the end carry, we obtain the correct answer 00000111 (+ 7).
4 to 1 MUX
2 - 4 Decoder
Control
DataFlow
D3:D0
4
Sel(3:0)
4
S1:S0
2
Dout
4-to-1 MUX (Gate level)
Three of these signal inputs will always be 0.
The other will depend on the data value selected
Control Section
• Until now, we have examined single-bit data selected by a MUX. What if we want to select m-bit data/words? Combine MUX blocks in parallel with common select and enable signals
• Example: Construct a logic circuit that selects between 2 sets of 4-bit inputs (see next slide for solution).
Multiplexer (cont.)
Example: Quad 2-to-1 MUX
• Uses four 4-to-1 MUXs with common select (S) and enable (E).
• Select line chooses between Ai’s and Bi’s. The selected four-wire digital signal is sent to the Yi’s
• Enable line turns MUX on and off (E=1 is on).
Implementing Boolean functions with Multiplexers
• Any Boolean function of n variables can be implemented using a 2n-1-to-1 multiplexer. A MUX is basically a decoder with outputs ORed together, hence this isn’t surprising.
• The SELECT signals generate the minterms of the function.
• The data inputs identify which minterms are to be combined with an OR.
Example
•F(X,Y,Z) = X’Y’Z + X’YZ’ + XYZ’ + XYZ = Σm(1,2,6,7)•There are n=3 inputs, thus we need a 2222-to-1 MUX-to-1 MUX•The first n-1 (=2) inputs serve as the selection linesThe first n-1 (=2) inputs serve as the selection lines
Efficient Method for implementing Boolean functions
• For an n-variable function (e.g., f(A,B,C,D)):– Need a 2n-1 line MUX with n-1 select lines.– Enumerate function as a truth table with consistent ordering
of variables (e.g., A,B,C,D)– Attach the most significant n-1 variables to the n-1 select
lines (e.g., A,B,C)– Examine pairs of adjacent rows (only the least significant
variable differs, e.g., D=0 and D=1).– Determine whether the function output for the (A,B,C,0) and
(A,B,C,1) combination is (0,0), (0,1), (1,0), or (1,1).– Attach 0, D, D’, or 1 to the data input corresponding to
(A,B,C) respectively.
Another Example
• Consider F(A,B,C) = m(1,3,5,6). We can implement this function using a 4-to-1 MUX as follows.
• The index is ABC. Apply A and B to the S1 and S0 selection inputs of the MUX (A is most sig, S1 is most sig.)
• Enumerate function in a truth table.
MUX Example (cont.)
A B C F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
When A=B=0, F=CWhen A=B=0, F=C
When A=0, B=1, When A=0, B=1, F=CF=CWhen A=1, B=0, When A=1, B=0, F=CF=CWhen A=B=1, When A=B=1, F=C’F=C’
MUX implementation of F(A,B,C) = m(1,3,5,6)
AA
BB
CC
CC
CC
C’C’
FF
These pictures have errors.
2 Input Multiplexor
Inputs: I0 and I1
Selector: S
Output: O
If S is a 0: O=I0
If S is a 1: O=I1
Mux
I0
I1
O
S
2-Mux Logic Design
I1I0S
O
I0 && !S
I1 && S
4 Input Multiplexor
Inputs: I0 I1 I2 I3
Selectors: S0 S1
Output: O Mux
I0
I2
O
S0
S0 S1 O
0 0 I0
0 1 I1
1 0 I2
1 1 I3
I1
I3
S1
One Possible 4-Mux
2-Decoder
I0
I1
I2
I3
S0
S1O
Adder
• We want to build a box that can add two 32 bit numbers.– Assume 2s complement representation
• We can start by building a 1 bit adder.
Addition
• We need to build a 1 bit adder– compute binary addition of 2 bits.
• We already know that the result is 2 bits.
A B O0 O1
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
A
+ B
O0 O1
This is addition!
One Implementation
AB O0
!AB
A!B
O1
A && B
(!A && B) || (A && !B)
Binary addition and our adder
What we really want is something that can be used to implement the binary addition algorithm. – O0 is the carry– O1 is the sum
01001+ 01101
10110
11 Carry
What about the second column?
• We are adding 3 bits– new bit is the carry from the first column.– The output is still 2 bits, a sum and a carry
01001+ 01101
10110
11 Carry
Truth Table for Addition
A B Carry
In
Carry
Out
Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Synchronous Sequential Circuit with T Flip-Flop --
xz
Q
C lo cky
y
CQ
T
Figure 8.12
Timing Diagram
1 01 0 01
C lo ck
0x
y
z
T
0
1 00 0 110 1
1 00 0 010 0
2 43 6 851 70
Figure 8.13
State Table and State Diagram
(a )
1 /0
y k + 1 /zk
x /z
0 /01 /1
y k
x k
y k
x k
y k + 1 /zk
(b )
P resen tsta te
x k
N ex t sta te/o u tp u t
(c)
0 /0
(d )
A B
0 1
A
B
B /0
B /0
A /0
A /1
0 10
1
1 /0
1 /0
0 /0
0 /1
0 1
1
0
K-Maps for Example
(a )
zk
x k
0 1
0
1
(b ) (c)
0
0
0
1
y k
T k
x k
0 1
0
1
1
0
0
1
y k
y k + 1
x k
0 1
0
1
1 *
1
0
0 *
y k
(d )
y k + 1 /zk
x k
0 1
0
1
1 /0
1 /0
0 /0
0 /1
y k
Example 2.Synchronous Sequential Circuit with JK Flip-flops
C lo ck
x
z
y 1
y 1
y 2
y 2
C
J 1
K 1
Q
Q
Q
Q
C
J 2
K 2
Timing Diagram and State Table for Example 2
C
x 0
y 1
y 2
J 1 = x y 2
K 1 = x
J 2 = x
K 2 = x + y 1
z = x y 1 y 2
0 1 1 1 1 0 0
1 0 0 0 1 1 1 0
0 0 0 1 0 1 1 0
0 0 0 0 0 1 0 0
0 0 /0
0 0 /0
0 0 /0
0 0 /0
0 1 /0
1 0 /0
11 /1
11 /0
y 1 y 2
x0 1
0 0
0 1
11
1 0
(b )
(a )
K-Maps for Example 2
y 1 y 2
x
0
0 1
0 0
0 1
11
1 0
0
0 1
0 1
0 0
J 1
x
1
0 1
0 0
0 1
11
1 0
0
1 0
1 0
1 0
K 1
x
0
0 1
0 0
0 1
11
1 0
1
0 1
0 1
0 1
J 2
x
1
0 1
0 0
0 1
11
1 0
1
1 1
1 0
1 0
K 2
x
0
0 1
0 0
0 1
11
1 0
0
0 0
0 1
0 0
z
y 1 y 2
y 1 y 2 y 1 y 2 y 1 y 2
Generating the State Table From K-maps -- Example 2
x
0 0 11
1 0 11
1 0 1 0
0 0 1 0
Y 1 Y 2 Y 1 Y 2 /z
y 1 y 2
0 1
0 1
0 0
0 1
11
1 0
0 1
0 1 0 1
0 1 0 1
0 1 0 1
(a )
J 1 K 1 J 2 K 2 J 1 K 1 J 2 K 2
(b ) (c )
0 1x
0 0
0 1
11
1 0
0 0
0 0
0 0
0 0
0 1
1 0
11
11
0 1x
0 0
0 1
11
1 0
0 0 /0
0 0 /0
0 0 /0
0 0 /0
0 1 /0
1 0 /0
11 /1
11 /0
y 1 y 2 y 1 y 2
Example 3.Synchronous Sequential Circuit Synthesis
(a ) C om p le te ly sp ec if ied c ircu it
(b ) In com p le te ly sp ec if ied c ircu it
1 /1
1 /0
1 /01 /0
0 /0
0 /0
0 /- 0 /0
0 /0
0 /0
1 /1
0 /-1 /-
1 /1
A B
C
D
AB
C
0 1x
A
B
C
D
D /0
D /0
D /0
D /0
B /0
C /0
B /0
A /1
0 1x
A
B
C
B /-
B /0
A /-
- /1
C /1
A /-
Introductory Synthesis Example -- Example 3
(a ) S ta te ta b le
S ta te y 1
0
1
1
0
x
0
0 1
0 0
0 1
11
1 0
0
0 1
0 0
1 0
0
0
1
1
y 2
A
B
C
D
Y 1 Y 2/z
(d ) O u tp u t K -m a p
x
0
0 1
0 0
0 1
11
1 0
0
0 1
0 1
1 1
x
0
0 1
0 0
0 1
11
1 0
1
0 1
1 0
1 0
(b ) S ta tea ss ig n m en t
D 1 (= Y 1 )
(c )T ra n s it ionta b le
D 2 (= Y 2 )(e ) E x c ita t ion K -m a p s (f) L og ic d ia g ra m
x
z
C lock
y 1
y 1
y2
y2
z
Q
Q C
D 1
Q
Q C
D 2
0 1x
A
B
C
D
A /0
A /0
B /0
C /1
B /0
C /1
D /0
D /0
0 1x
0 0
0 1
11
1 0
0 0 /0
0 0 /0
0 1 /0
11 /1
0 1 /0
11 /1
1 0 /0
1 0 /0
y 1 y 2
y 1 y 2 y 1 y 2y 1 y 2
Flip-flop Input Tables -- Example 3
S ta tetra n s it ion sQ (t) Q (t + e )
(a ) D f lip -f lop
0
0
1
1
0
1
0
1
R eq u iredin p u ts
D (t)
0
1
0
1
S ta tetra n s it ion sQ (t) Q (t + e )
(b ) C locked S R
0
0
1
1
0
1
0
1
R eq u iredin p u ts
S (t) R (t)
0
1
0
d
d
0
1
0
S ta tetra n s it ion sQ (t) Q (t + e )
(c ) C locked T f lip -f lop
0
0
1
1
0
1
0
1
R eq u iredin p u ts
T (t)
0
1
1
0
S ta tetra n s it ion sQ (t) Q (t + e )
(d ) C locked J K f lip -f lop
0
0
1
1
0
1
0
1
R eq u iredin p u ts
J (t) K (t)
0
1
d
d
d
d
1
0
Generating the JK Flip-flop Excitation Maps --Example 3
x
0
0 1
0 0
0 1
11
1 0
0
0
d
d d
(c ) E x c ita t ion m a p s
x
d
0 1
0 0
0 1
11
1 0
d
d d
1 0
0 0
x
0
0 1
0 0
0 1
11
1 0
1
d d
d d
1 0
K 1 J 2
1
d
x
d
0 1
0 0
0 1
11
1 0
d
1
d
0 1
d
K 2
0
J 1
(b ) E x c ita t ion ta b le
J 1 K 1 J 2 K 2Y 1 Y 2/z
0 1x
0 0
0 1
11
1 0
0 d
0 d
d 1
d 0
0 d
1 d
d 0
d 0
(a ) T ra n s it ion ta b le
y 1 y 2 0 1x
0 0
0 1
11
1 0
0 0 /0
0 0 /0
0 1 /0
11 /1
0 1 /0
11 /1
1 0 /0
1 0 /0
0 1x
0 0
0 1
11
1 0
0 d
d 1
d 0
1 d
1 d
d 0
d 1
0 d
y 1 y 2 y 1 y 2
y 1 y 2y 1 y 2 y 1 y 2y 1 y 2
Clocked JK Flip-Flop Implementation --Example 3
x
z
C lock
y 1
y 2
Q
Q
C
J 1
Q
Q
C
J 2
K 1
K 2
y 2
y 1
Application Equation Method for Deriving Excitation Equations -- Example 3
y 1 y 2
x
0
0 1
0 0
0 1
11
1 0
0
0 1
0 1
1 1
Y 1
y 1
x
0
0 1
0 0
0 1
11
1 0
1
0 1
1 0
1 0
Y 2
y 2
y 1 y 2
Registers
• Two independent flip-flops with clear and preset
Using T Flip Flop and JK Flip Flop
log24 = 2, so 2 flip flops are needed to implement this FSA
Step 1 - Translate diagram into StateTable
Step 2 - Create maps for T and JK
Step 3 - Determine T, J, and K equations
Step 4 - Draw resulting diagram