by whitney zack and wade campney
TRANSCRIPT
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By Whitney Zack and Wade Campney
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Key points
Problem with MemoryNon‐Volatile Memory
MRAM
Volatile MemorySRAMDRAM
Hybrid/Hyper Memory Cube (HMC)DesignPerformance
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RAM
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The Problem with Memory
Memory performance is not scaling to Moore’s Law (CPU performance.)This creates a bottleneck in performance.Some call this a “memory wall”Conventional memory architectures Memory I/O performance/bandwidth cannot keep upProblems with heat and power consumption when adding more memory or moving it closer to CPU
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Non‐Volatile
Is computer memory that can retain the stored information even when not powered
MRAMFeRAMPRAM
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MRAM: “Universal Memory”
Magnetoresistive Random Access MemoryMagnetic cells instead of electric chargeSlower than SRAMLow voltage, and low cell leakage.Similar density compared to DRAM
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MRAM Drawbacks
Requires a lot of current to write to memoryRequires big cell size to prevent the ‘half‐select problem’No plans for FAB quite yet due to other memory demands(Flash/DRAM)
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MRAM: Toggle Mode
Cell is modified to contain an artificial antiferromagnet layer.Resulting layers only have two stable states, which can be toggles by skewing the write currents to “rotate” the field.This fixes the half‐select problem and allows for smaller MRAM cells.
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MRAM: Toggle Mode(PIC)
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MRAM: Spin Transfer Torque
This method uses spin‐aligned electrons to directly torque the domains.Lower amount of current required to write to the cells.Allows for even smaller cell sizes(~65nm), which allows for a higher density.
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MRAM Spin Transfer(PIC)
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Volatile Memory
Retaining data only as long as there is a power supply connected
SRAMDRAMHybrid Memory Cube
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SRAM(Static RAM) drawbacks
4‐6 transistors to create a single bit of SRAMSRAM takes up much more space than DRAMSRAM is byte for byte more expensive than DRAMNo leaking like in DRAM so there is no need for refresh circuitFlip Flop design allows for instantaneous written instead of capacitor fill up like DRAM
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DRAM(Dynamic Ram) drawbacks
1 transistor and 1 capacitorLow cost per bitHigher memory density of SRAMHigh Power consumption because of refresh circuitHeat problems
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HMC – In Development
Intel/Micron originally researchedMicron/Samsung/IBM created consortiumUses TSV (Through Silicon Via) to stack memory vertically.Low power consumptionSmall SizeSpecs to be released in 2012
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Some Specs
15X bandwidth of DDR370% reduction in energy per bit than DDR3 Reduced latency with lower queue delays, and increased number of banks.System Architecture makes it extremely efficient on space.
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Design
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Actual Picture
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DRAM 512 MB Memory Stick
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512 MB Memory Cube
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1 TB/s HMC DRAM Prototype
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Bandwidth Performance
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Power Performance
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The Future
Intel speculates super computer by 2018 that can operate at exaflop performance (1018)Will probably be seen first in graphics for memory performance improvementAdaptable to many types of systems because of logic layerPotential for first universal memory (Personal/home computing, Commercial use)
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Questions, Comments, etc…
Thank you