batch no.2
TRANSCRIPT
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A FAST CRYPTOGRAPHY PIPELINED HARDWARE DEVELOPED IN FPGA WITH
VHDL
PRESENTED BY
K.KALPANA (093J1A0407)
B.DURGA PRASAD (093J1A0418)
L.SHIVA KRISHNA (093J1A0440)
B.HARI KRISHNA (093J1A0419)
GUIDE: P.VANNUR(M.tech),
KOTTAM KRUNAKARA REDDY INSTITUTE OF TECHNOLOGY
CHINNA TEKURU, KURNOOL-518 218
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CONTENTS
• ABSTRACT• INTRODUCTION• ADVANCED ENCRYPTION STANDARD• ENCRYPTION BLOCK DIAGRAM• ARCHITECTURE OF AES• ADVANTAGES• DISADVANTAGES• APPLICATIONS• CONCLUSION• FUTURE SCOPE
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Key words
• Cryptography• Pipeline• FPGA• AES
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ABSTRACT
Main objective :
• The main objective of the project is to increase the speed of encryption and decryption by using pipelined hardware.
• Pipelined hardware cryptography was used to improve performance in order to achieve higher throughput and greater parallelism.
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What is FPGA ????
• FPGA stands for field programmable gate array.
Why FPGA ????
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What is pipeline?
Four Pipelined Instructions
IF
IF
IF
IF
ID
ID
ID
ID
EX
EX
EX
EX M
M
M
M
W
W
W
W
5
1
1
1
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What is parallelism?????
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INTRODUCTION
• Cryptography - secret writing
DES-Data Encryption Standard
AES-Advanced Encryption Standard
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Which is better (software or hardware based cryptograph)??????
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AES-Advanced Encryption Standard
What is AES????
and
why AES????
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Encryption phases
1.Subbytes
2.Shift rows
3.Mix columns
4.Addround key
• For decryption algorithm will use respective inverse operations.
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SubBytes – A non-linear substitution step where each byte is
replaced with another according to a lookup table (known as S Box).
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ShiftRows –
A transposition step where each row of the state is
shifted cyclically a certain number of steps.
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MixColumns – A mixing operation which operates on the columns of
the state, combining the four bytes in each column using a linear transformation.
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AddRoundKey – It is an XOR operation between the state and the round key.
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Key Expansion - Three operations.
1.RotWord
2.SubWord
3.XOR operations
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Block diagram of I/O of encryption
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Round key
Add round key
Sub bytes
Shift rows
Add round keys
Sub bytes
Shift rows
Mix columns
Add round keys
BUFFER
selector
Block Diagram Of Encryption
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AES architecture and its blocks 1.Key expansion 2.Encryption 3.Decryption
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Architecture diagram of AES
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• High Performance• Time to market• Reprogrammable• Reconfigurable• Long term maintenance
Disadvantages• More expensive.• Power consumption is more.
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FUTURE SCOPE
• Micro electronics intends to use this work as part of larger projects such as smart metering in power systems and cryptography interface in data communication.
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Conclusion
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ThankQ
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Queries….???