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A LOW POWER ARCHITECTURE OF VITERBI

DECODER FOR PROCESSING OF FORWARD

ERROR CONTROL IN SOFTWARE RADIO

RECEIVER

A PROJECT REPORT (Phase-I)

Submitted by

N.BALA DASTAGIRI

0902009004

in partial fulfillment for the award of the degree

of

MASTER OF TECHNOLOGY

in

VLSI DESIGN

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

HINDUSTAN INSTITUTE OF TECHNOLOGY AND SCIENCE

CHENNAI 603 103

NOVEMBER 2010

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HINDUSTAN INSTITUTE OF TECHNOLOGY AND

SCIENCE

BONAFIDE CERTIFICATE

Certified that this project report A Low Power architecture of Viterbi Decoder for

processing of Forward Error Control in Software Radio Receiver is the bonafide work of

N.BALADASTAGIRI (0902009004) who carried out the project work under my

supervision during the academic year 2010-11.

SIGNATURE SIGNATURE

Prof.ABY K. THOMAS Mr. M. RAJMOHAN, M.Tech.

HEAD OF THE DEPARTMENT SUPERVISOR

Assistant Professor (Senior Grade)Electronics and Communication Electronics and Communication

Engineering Engineering

INTERNAL EXAMINER EXTERNAL EXAMINER

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ACKNOWLEDGEMENT

It is my extreme pleasure to thank ChancellorDr. Elizabeth Verghese, Hindustan College of

Engineering, for providing me a good, pleasing and safe environment in out college which

helped me a lot to carry on with my project.

I wish to express my sincere and grateful gratitude to my principal Dr. Devanathan,

Hindustan College of Engineering for providing me with an excellent study environment.

I am thankful to Prof. Aby K. Thomas, Head of the department of Electronics and

communication engineering for having a great interest in out project and encouraging us.

I am indebted to my project guide Mr. M. Rajmohan and project coordinatorMr. JobbinAbraham, of Electronics and Communication engineering for his valuable guidance and

technical support in accomplishment of my project.

Not to forget, my teaching & non-teaching staff, my friends and my family who had directly

or indirectly helped and supported me in completing our project.

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ABSTRACT

Convolution codes are one of the FEC codes that are used in every digital

communication system.Viterbi algorithm is employed in wireless communications to decode

the convolution codes. Such decoders are complex and dissipate large amount of power.

Software Defined Radio (SDR) is realized using configurable hardware platforms. In this

paper, a generic, configurable and low power viterbi decoder for SDR is described using a

VHDL code. The proposed design of the viterbi decoder is considered to be generic so that it

facilitates the prototyping of the decoder with different specifications. The proposed design is

simulated and synthesized by using Xilinx.

Phase 1:

The modules for convolution encoder, branch metric, and path memory and add-compare

select unit have been designed using VHDL code. The functionality of the design was verified

and synthesized using Xilinx 10.1i.

Phase 2:

The modules for survivor memory, output decision and for total viterbi decoder will be

designed using viterbi algorithm and its corresponding power will be calculated. The design is

verified and synthesized using Xilinx 10.1i.

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CONTENTS

CHAPTER PAGE NUMBER

List of Figures 6

List of Tables 6

List of Abbreviations 6

1. Introduction 7

1.1Digital Communication and coding 7

1.1.1 Coding Theory 8

1.2Decoding Convolutiona codes 10

1.3Motivation for low power 11

1.4Objectives and summary of the work 12

2. Scope of the Project 13

3. Literature Survey 15

4. Proposed Method 16

4.1Overview 16

4.2Convolutional encoder 16

4.3Viterbi decoding algorithm 16

4.3.1 Architecture of Viterbi decoder 17

5. Work done in phase 1 20

6. Simulation and Synthesis Results 21

7. Conclusion 23

8. References 24

Appendix 25

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LIST OF FIGURES

NAME PAGE NUMBER

Figure 4.1 Convolutional encoder 16

Figure 4.2 Architecture of Viterbi decoder 17

Figure 4.3 Branch Metric Computation 18

Figure 4.4 ACS module 19

Figure 5.1 Convolutional encoder for K=5 20

Figure 5.2 Branch Metric Computation 20

Figure 5.3 ACS module 21

Figure 6.1 Simulation results for Convolutional encoder 22

Figure 6.2 Synthesis results for Convolutional encoder 23

LIST OF ABBREVATIONS

FPGA-Field Programmable Gate Array

FSM-Finite State Machine

1. INTRODUCTION

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Attention, the Universel! By kingdoms, right wheel! This prophetic phrase

represents the first telegraph message on record. Samuel F. B. Morse sent it over a 16 km line

in 1838. Thus a new era was born: the era of electrical communication.

Now, over a century and a half later, communication engineering has advanced to the

point that earthbound TV viewers watch astronauts working in space. Telephone, radio, and

TV are integral parts of our life. Long-distance circuits span the globe carrying text, data,

voice, and images. Computers talk to computers via intercontinental networks. Wireless

personal communication devices keep us connected wherever we go. Certainly great strides

have been made since the days of Morse.

This report describes the work that has been done in order to improve the power

efficiency of the Viterbi decoder in digital communication systems. In particular, a novel

adaptive Viterbi decoder is presented plus, a lower power Path Metric Unit (PMU) and

Survivor Memory Unit (SMU) designs that have been developed.

1.1 Digital communication and coding

It is remarkable that the earliest form of electrical communication, namely telegraphy

developed by Samuel Morse in 1837, was a digital communication system. Although Morse

was responsible for the development of the first electrical digital communication system, the

beginnings of what we now regard as modern digital communications system from the work of

Nyquist in 1924. His studies led him to conclude that for binary data transmission

(transmitting one of two numbers, 0 or 1) over a noiseless channel of bandwidth W Hertz, the

maximum pulse rate is 2W pulses per second without any cross symbol interference.

Hartley extended this work in 1928 to non-binary data transmission, while

Kolmogorov and Wiener independently in 1939 and 1942, respectively, solved the problem ofoptimally estimating a signal in the presence of additive noise. In 1948 Claude Shannon

established the mathematical foundation for information transmission and derived fundamental

limits for digital communication systems. His work can arguably be considered as the true

beginning of the information age.

The work of Hamming in 1950 on error control coding to combat detrimental effects of

channel noise completes the classic contributions to modern digital communication systems.

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Of more modern contributions, the Viterbi decoding algorithm for trellis codes,

proposed by Andrew Viterbi in 1967 is now found in almost all wireless communication

systems. Efficient error control decoding makes mobile communication systems what they are

today. The latest significant leap forward for improvements of communications systems was in1993 with the discovery of the turbo principle by Berrou and Glavieux. The special turbo

codes developed based on these principles can be efficiently decoded using a very powerful

iterative signal processing approach. The resulting coding system performs very close to

fundamental limits for a range of different channels. In practical terms, this leads to the most

efficient use of bandwidth and power, which is very important for portable wireless devices.

In practice, the subject of digital communications involves the transmission of

information in digital form from a source that generates the information to one or more

destinations. In particular, it includes the concepts of source coding including entropy and rate-

distortion, the characterization of communication signals and systems, optimal receivers,

carrier and symbol synchronization, channel capacity and coding, block and convolutional

codes, signal design for band-limited channels, adaptive equalization, etc.

Theoretically, communication theory consists of two major domains: information

theory and coding theory.

1.1.1 Coding theory

Coding theory is more practical compared with other theories in the information theory

domain. It is primarily concerned with finding the methods, called codes, for increasing the

efficiency and accuracy of data communication over a noisy channel as close to the theoretical

limit that Shannon proved as possible. These codes can be mainly subdivided into source

coding (Entropy encoding) and channel coding (Error correction coding). A third class of

codes is cryptographic ciphers, which implement concepts from coding theory and information

theory in cryptography and cryptanalysis. This report is only concerned with channel coding,

as it is widely used to improve the reliability of communication on digital channels y detecting

and correcting errors .

Although there are many forms of coding schemes, they all have two basic features in

common . One is the use of redundancy. Coded digital messages always contain extra or

redundant symbols. In fact, these redundant symbols are not really redundant as they contain

the information to accentuate the uniqueness of each message so that the channel disturbance

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is unlikely to destroy the message by corrupting enough of the symbols in it. The second

feature is noise averaging . This is achieved by making the redundant symbols depend on a

span of several information symbols. This means the redundant symbols not only make the

sent message more distinctive but also contain the information of the transmitted messageitself. Therefore, each symbol of the message actually contains less transmitted information

and thus causes less damage when it is corrupted by noise.

Two kinds of codes are mainly used in modern communication: block codes and

convolutional codes. This classification is based on the presence or absence of memory in the

encoders for these two codes. An encoder for a block code is memory less as it maps a k-

symbol input sequence into an n-symbol code words sequence. Therefore, each n-symbol

output only depends upon a specific input k-symbol block and the encoder has no memory

of other previous input symbols. For the block codes, there is no correlation between the

encoded output code words. In contrast, the output of encoding a convolutional code is

determined by the current input and a span of the preceding input symbols. Each input is

memorized by the encoder for a certain amount of the time span so that it affects not only the

current output but also the next v output code words.

Although, codes can also be classified as linear or nonlinear, almost all the coding

schemes used in practical applications are linear codes due to their significantly implified

mathematical representations. For this reason, the codes mentioned in this report are all linear

unless otherwise specified.

Block codes:

A block code is normally specified by values of parameters n, k, R = k/n, and dmin.

These parameters indicate that the encoder encodes each k symbols input block into a n

symbols output block. Therefore, the code has a rate of R equal to k/n. The minimum of

Hammming distance, d, of the code is defined as dmin.

dmin = min(d)

Convolutional Codes:

Convolutional coding technique was first introduced by Elias in 1955. A binary

convolutional encoder is normally represented by the values of three parameters: n, m, and k.

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functions. This enables the design problems, leading to inefficiencies and wasting the power

consumption of the decoder, to be discovered. A variety of low power design techniques are

described and applied to the decoder design in order to improve its power efficiency. The new

designs are tested by simulations on software. The results give a clear view of theimprovement of the modifications and enable a novel general methodology for significantly

reducing complexity of decoding convolutional codes to be proposed.

2. SCOPE OF THE PROJECT

The existing paper describes the viterbi decoder for software radio receiver for Viterbi

algorithm. In this paper it describes the low power architecture of viterbi decoder for viterbi

algorithm. In previous works it describes the viterbi algorithm either in register exchange

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method or in trace back method. There is no paper which describes the low power architecture

of viterbi decoder using trace back method for software radio receiver.

A Low Power architecture of Viterbi Decoder for processing of Forward Error Controlin Software Radio Receiver has been developed using viterbi algorithm. The main target of

this work is to develop a new viterbi decoder design for minimizing computation complexity

and power consumption. It examines decoding process of the viterbi algorithm, architecture of

the decoder and the implementations of basic functions.

Viterbi decoder are essential in wide range of applications, such as

wireless network of different standards like GPRS, and WiMAX to maximize the

channel capacity manipulator kinematics

mobile communications and so on

3. LITERATURE SURVEY

Review of previous work on low-power Viterbi decoder design

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code ensemble average error probabilities are also derived and extended by these techniques.

Finally, practical considerations concerning finite decoding memory, metric representation,

and synchronization are discussed[6]..

4. PROPOSED METHOD

4.1 Overview

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In this chapter, we describe the implementation of the Viterbi algorithm and propose a

low-power design of Viterbi decoders. We also describe top-down design approach employed

to implement Viterbi decoders with and without low-power consideration.

4.2Convolutional Encoder

Convolutional coding is applied to a continuous input data and also to blocks of data.

Infact, a convolutional encoder is a finite state machine. It gives a coded output data stream

from an input data stream. It is usually composed of shift registers and a network of XOR

(Exclusive-OR) gates. A convolutional encoder is characterized by the (n, k, m) format, where

n is number of outputs of the encoder; k is number of inputs of the encoder; m is number of

memory elements of the shift register of the encoder.The rate of a (n,k,m) encoder is k/n. Aconvolutional encoder is a Mealy machine, where the output is a function of the current state

and the current input. It consists of shift registers and multiple XOR gates. The stream of

information bits flows in to the shift register from one end and is shifted out at the other end.

XOR gates are connected to some stages of the shift registers as well as to the current input to

generate the output.

Figure 4.1: Convolutional encoder

4.3Viterbi decoding algorithm

The Viterbi algorithm proposed by A.J. Viterbi is known as a maximum likelihood

decoding algorithm for convolutional codes. So, it finds a branch in the code trellis most likely

corresponds to the transmitted one. The algorithm is based on calculating the Hamming

distance for every branch and the path that is most likely through the trellis will maximize that

metric. The algorithm reduces the complexity by eliminating the least likely path at each

transmission stage. The path with the best metric is known as the survivor, while the other

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entering paths are non-survivors. If the best metric is shared by two or more paths, the survivor

is selected from among the best paths at random.

The selection of survivors lies at the heart of the Viterbi algorithm and ensures that the

algorithm terminates with the maximum likelihood path. The algorithm terminates when all of

the nodes in the trellis have been labeled and their entering survivors are determined. We then

go to the last node in the trellis and trace-back through the trellis. At any given node, we can

only continue backward on a path that survived upon entry into that node. Since each node has

only one entering survivor,our trace-back operation always yields a unique path. This path is

the maximum likelihood estimate that predicts the most likely transmitted sequence. The

maximum likelihood is given by:

P(Z/U(m)) = max P(Z/U(m)) over all U(m)

where Z is the received sequence, and U(m) is one of the possible transmitted sequences

4.3.1 Architecture of Viterbi decoder

The major building blocks of a Viterbi decoder are shown in Figure 2. There are eight

conceptual blocks of a Viterbi decoder, and the role of each block is described in detail below.

Figure 4.2: Architecture of Viterbi decoder

Input and output blocks: Input and output blocks provide the interface with the external

components. In the case of radio communications, input received by the decoding block is

usually serial, while the decoding block actually needs a parallel input. Serial to parallel

conversion and vice versa are carried out by the input and output blocks.

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Output Generator: This block generates the decoded output sequence. In the traceback

approach, the block incorporates combinational logic, which traces back along the survivor

path and latches the path (equivalently the decoded output sequence) to a register.

5. WORK DONE IN PHASE 1


select unit have been designed using VHDL code. The block diagrams of designed blocks areshown below.

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Convolutional Encoder: Convolutional coding is applied to a continuous input data and also

to blocks of data. Infact, a convolutional encoder is a finite state machine. It gives a coded

output data stream from an input data stream. It is usually composed of shift registers and a

network of XOR (Exclusive-OR) gates.

Figure 5.1:Convolutiona encoder K=5

Branch Metric: This block calculates the branch metric of each stage in the trellis. It also

calculates the hamming distances (i.e. branch metric) between the received symbol and

expected symbol.

Figure 5.2: Branch Metric Computation

ACS: The Add-Compare-Select block receives two branch metrics and the state metrics. An

ACS module adds each incoming branch metric of the state to the corresponding state metric

and compares the two results to select a smaller one. The state metric of the state is updated

with the selected value, and the survivor path information is recorded in the survivor path

storage module.

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Figure 5.3: ACS module

This design focuses on the prototyping of a small-sized Viterbi decoder with constraint length

K = 5 and code rate r = 1/3 convolutional encoder as illustrated in figure .

A convolutional encoder is a Mealy machine, where the output is a function of the current

state and the current input. It consists of shift registers and multiple XOR gates. The stream

of information bits flows in to the shift register from one end and is shifted out at the other

end. XOR gates are connected to some stages of the shift registers as well as to the current

input to generate the output. The output of encoder is fed to the viterbi decoder for forward

error correction.The process of decoding will be preceeding as in block diagram of viterbi

decoder depending on viterbi algorithm.

6. SIMULATION AND SYNTHESIS RESULTS

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Simulation results for Convolutional encoder is shown in figure 6.1

Figure 6.1 Simulation results for Convolutional encoder

Synthesis results for Convolutional encoder is shown in figure 6.2

Figure 6.2 Synthesis results for Convolutional encoder

7. CONCLUSION

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This work represents the developing new approaches for implementing Viterbi decoder

designs to minimize computation complexity and power consumption. This work examines the

decoding process of the Viterbi algorithm, the architecture of the Viterbi decoder, and the

implementations of the basic functions. Then a variety of low power design techniques aredescribed and applied to the decoder design to improve its power efficiency. The new designs

are tested by simulation on software. The results give a clear view of the improvement of the

modifications and enable a novel general methodology for significantly reducing complexity

of decoding convolutional codes to be proposed.

Phase 1:


select unit have been designed using VHDL code. The functionality of the design was verified

and synthesized using Xilinx 10.1i.

Phase 2:

The modules for survivor memory, output decision and for total viterbi decoder will be

designed using viterbi algorithm and its corresponding power will be calculated. The design is

verified and synthesized using Xilinx 10.1i.

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8. REFERENCES

[1] Joseph Mitola III, Software Radios, IEEE Communications Magazine, volume: 33 no. 5,

pp.24-25, May 1995.

[2] J. Kumagai, Winner: Radio Revolutionaries, IEEE Spectrum Magazine, January 2007.

[3] Ajay D. Jadhav, Anil. R. Yardi, Folding ADC Design for Software Defined GSM Radio-

Mobile Station Receiver, IJCSNS International Journal of Computer Science and Network

Security, vol. 8 No.9, Septemper 2008.

[4] M. Cummings and S. Huruyama, FPGA in the Software Radio, IEEE Communication

Magazine, volume: 37, no. 2, pp. 108-112, February 1999.

[5] Xilinx Inc., Virtex-6 SXT for DSP and memory-intensive applications with low-power

serial connectivity, http://www.xilinx.com/products/v6s6.htm. Last visited: April. 2009.[6] A.J. Viterbi, Convolutional codes and their performance in communication systems,

IEEE Trans. Commun., vol. COM-19, pp. 751-772, Oct., 1971.

[7] B. Sklar, Digital Communication Fundamentals and Applications, Prentice Hall,

Englenwood Cliffs, New Jersey, 2000, Part 2 chapter 7.

[8] J. Proakis, Digital Communications, McGraw-Hill Science/Engineering/Math; 4th

edition, 2000, chapter 8.

[9] GSM 05:03: Channel coding, Version 8.9.0 Release 1999.

[10] GSM 03.64: Overall description of the GPRS radio interface; Stage 2 Version 8.12.0.

Release 1999.

[11] IEEE Std 802.16e-2005: Part 16: Air interface for Fixed and Mobile

Broadband Wireless Access Systems.

[12] Maunu, J.; Laiho, M.; Paasio, A., Performance analysis of BMC and Decision Units in

the differential analog Viterbi decoder, IEEE 25th Norchip Conference, Aalborg, Denmark,

Volume , Issue , 19-20 Nov. 2007 Page(s):1 4.

[13] Kamuf, M. Owall, V. Anderson, J.B., Survivor Path Processing in Viterbi Decoders

Using Register Exchange and Traceforward, IEEE Trans on Circuits and Systems II: Express

Briefs, vol. 54, Issue 6, pp. 537-541, June 2007.

[14] J. Oh and M. Pedram., Gated clock routing for low-power microprocessor design, IEEE

Transactions on Computer-Aided Design, June 2001. Authorized

APPENDIX

CODE FOR CONVOLUTIONAL ENCODER

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity encoder is

Port ( data_in : in STD_LOGIC;

clk : in STD_LOGIC;

reset : in STD_LOGIC;

i0 : out STD_LOGIC_VECTOR (1 downto 0);

i1 : out STD_LOGIC_VECTOR (1 downto 0));

end encoder;

architecture Behavioral of encoder is

signal stored : std_logic_vector ( 0 to 8 ) ;

signal code : std_logic_vector ( 0 to 1 ) ;

begin

process ( reset , clk , stored , data_in )

begin

if clk = '1' and clk'event then

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if reset = '1' then

stored (0)


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end case ;

end process ;

end Behavioral;

Code for Branch Metric Unit

--metricsubmodule(for vertebi_top1)

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity metricsubmodule is

Port ( m_in0 : in STD_LOGIC_VECTOR (4 downto 0);

m_in1 : in STD_LOGIC_VECTOR (4 downto 0);



m_out0 : out STD_LOGIC_VECTOR (4 downto 0);




clk : in STD_LOGIC;

rst : in STD_LOGIC);

end metricsubmodule;

architecture Behavioral of metricsubmodule is

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clk : in STD_LOGIC;

rst : in STD_LOGIC;

q : out STD_LOGIC_vector(4 downto 0));

end dff2;

architecture Behavioral of dff2 is

begin

process(clk,rst)

begin

if(rst='1') then

q'0');

elsif(clk'event and clk='1') then

q


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--use UNISIM.VComponents.all;

entity computemetric is

Port ( m_out0 : in STD_LOGIC_VECTOR (4 downto 0);

m_out1 : in STD_LOGIC_VECTOR (4 downto 0);



s0 : in STD_LOGIC_VECTOR (2 downto 0);




p0_0 : inout STD_LOGIC_VECTOR (4 downto 0);








error:out std_logic);

end computemetric;

architecture Behavioral of computemetric is

function is_error(x1,x2,x3,x4,x5,x6,x7,x8:std_logic)

return std_logic is

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variable is_error1:std_logic;

begin

if((x1='1') or (x2='1') or (x3='1') or (x4='1') or (x5='1') or (x6='1') or (x7='1') or (x8='1')) then

is_error1:='1';

else

is_error1:='0';

end if;

return is_error1;

end is_error;

begin

p0_0

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