Projection Mask-Less Patterning (PMLP) for the fabrication of leading-edge complex masks and nano-imprint templatesElmar Platzgummer, Hans Loeschner, and Gerhard Gross, IMS Nanofabrication AG, Schreygasse 3, A-1020 Vienna, Austria

ABSTRACTThe reliable and cost-effective fabrication of 2D and 3D structured nano-surfaces is prerequisite for a number of industrial and emerging applications: (i) leading-edge complex masks, (ii) high precision nano-imprint templates, (iii) nanofunctionalized surfaces and 3D structures for applica-tions in nano-photonics, nano-magnetics, and nano-biotechnology.

Projection Mask-Less Patterning (PMLP) is based on many hundred thousands of ion beams working in parallel. A PMLP proof-of-concept tool has been realized as part of the European project CHARPAN (Charged Particle Nanotech; www.charpan.com). The novel ion beam projection optics with 200x reduction shows 16nm half pitch resolution. First results with a programmable aperture plate system have been achieved demonstrating high accuracy and fl exible pattern fabrication.

1. IntroductionThe challenges for the mask industry are to produce leading-edge complex masks for the 32nm and 22nm hp nodes within 24 hours. To meet these challenges becomes increasingly diffi cult with e-beam writing tools requiring the use of chemically amplifi ed resists (CARs) and proximity correction. Projection maskless patterning (PMLP) offers a novel solution with massively paral-lel ion beams which can be used for effective non-CAR resist exposures without proximity and resist-less direct patterning of hardmasks.

Continues on page 3.

PHOTOMASKPHOTOMASKBACUS—The international technical group of SPIE dedicated to the advancement of photomask technology.

INDUSTRY BRIEFSFor new developments in technology—see page 10

MARCH 2008VOLUME 24, ISSUE 3

CALENDARFor a list of meetings—see page 11

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TAKE A LOOK INSIDE:

Figure 1. Principles of Projection Mask-Less Patterning (PMLP) and PMLP Proof-of-Concept Tool, realized as part of the European integrated project CHARPAN (Charged Particle Nanotech).

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The EMLC Has Returned to Dresden GermanyDr. Uwe Behringer, UBC Microelectronics, Germany, EMLC Conference ChairIn 2007 the 23rd European Mask and Lithography EMLC2007 took place in Grenoble, France. It was the fi rst time in its 23 year long history that the EMLC took place outside Germany.

For 2008 the 24th Mask and Lithography Conference, EMLC2008 came back to Dresden. The EMLC2008 was held on January 21st to 24th 2008, at the Hilton Hotel in Dresden, Germany. As in the past, the conference has annually brought together scientists, researchers, engineers and technologists from research institutes and companies from around the world to present papers at the forefront of mask lithography and mask technology.

This years sessions included: “Double Patterning”, “Simulation”, “Mask Business & Mask Data Prep”, “Mask Cleaning & Haze”, Inspection & Repair”, “Resist”, “Metrology”, “RET”, “EUV” and “NIL”. A small Poster Session was also included.

There were a total of 254 conference attendees at the EMLC2008. This number included the 25 exhibitors from the Technical Exhibition. Of the largest share of attendees (136), came from Germany, 33 came from the USA, 23 from France, 19 from Japan and 12 from the Netherlands. These were the fi ve largest groups by nationality in attendance. About 55% of the contributions came from Europe about 45% from outside Europe.

Highlights of the EMLC2008The keynote speaker of the EMLC2008 was Steve McDonald the Central Mask Integration Manager of Photronics NanoFab in Boise Idaho. Steve gave a talk about the challenges in mask making today. Here are some excerpts from his presentation:

“Semiconductor manufacturing is changing more rapidly than ever before, and our industry faces enormous near term challenges as we move forward into high NA 193 immersion, double patterning, and double exposure lithography. For mask makers the challenges at the 32 nm node and beyond are extremely diffi cult. Huge data volumes, long write times, and more challeng-ing OPC, coupled with low single digit specifi cations for CD control, increasingly tight pattern placement and plate to plate overlay requirements, and ever smaller defect specifi cations.”

Greg Hughes from SEMATECH, Austin, TX, USA stated in his presentation “Mask Industry Assessment Trend Analysis” that logic designs are driving the majority of mask volume. Looking at year-to-year responses, this percentage has trended down from 70% in 2002 to 43% in 2007.

Mask technologies for the sub-130 nm node have risen to 17% of the mask volume; 60% of all masks are still built to a 250 nm or larger design node. The sub-65 nm node technology is now 2.8% of the mask volume. Currently 70% of photomasks are made on a 6025 format. Over the last fi ve years, this percentage has slowly increased.

As in the past, the major process-related yield loss mechanisms are basically constant year to year. Hard defects account for nearly half of the yield loss for the fi ve-year period. Human errors (administrative and manufacturing errors) combined account for approximately 20% of yield losses. CD control is surprisingly low at 15%. Who are the potential lithography candidates for the 32 nm node? Out of the presentations I see at least 3 candidates: High-n Immersion; Double Patterning: and the late fellow EUVL.

It was also stated that line edge roughness will become a serious problem because not enough photons will arrive to the resist at a high throughput rate of 100 wafers per hour on the proposed exposure tool(s).

Douglas Resnick from Molecular Imprints explained that by using Imprint technology this problem will not appear since the line quality is defi ned by the “template mask” quality where the writing time of the “template mask” can be enlarged several times compared to the writing time of an optical mask. The reason for this: The area exposed by an electron beam writing system is normally 4 times smaller on a template used for nano-imprint lithography (NIL).

Robert de Kruif from ASML of The Netherlands, showed in his presentation “Wafer Based Mask Characterization for Double Patterning Lithography” that Double Patterning Technology (DPT) is considered the most acceptable solution for 32 nm node lithography. He mentioned that apart from the obvious drawbacks of additional exposure and processing steps and therefore reduced throughput, DPT possesses a number of additional technical challenges. This relates to exposure tool capability, the actual applied process in the wafer fab and also mask to mask performance.

For EUV it was stated that EUV lithography seems to have failed to be inserted for the 32 nm node device production due to delay in overcoming technical challenges. The technical issue ranking in 2007 is unchanged from 2006.

Other experts however stated that EUV lithography still has the advantage in the resolution capability than other optical lithography technologies.

In 2009 the “25th European Mask and Lithography Conference, EMLC2009 will again be held at the Hilton Hotel in Dresden, Germany. The date is not quite set but January 12th to 15th 2009 in Dresden, Germany is the proposed date.

EditorialBACUS News is published monthly by SPIE for BACUS, the international technical group of SPIE dedicated to the advancement of photomask technology. Circulation 2600.

Managing Editor/Graphics Linda DeLano

Advertising Sue Siegfried

BACUS Technical Group Manager Pat Wight

■ 2008 BACUS Steering Committee ■

President Brian J. Grenon, Grenon Consulting

Vice-President John Whittey, Vistec Semiconductor Systems, Inc.

Secretary Warren Montgomery, CNSE

Quarterly Meeting Chair Robert (Bob) Naber, Cadence Design Systems, Inc.

2008 Annual Photomask Chairs Hiroichi Kawahira, Sony Atsugi Technology Ctr. (Japan)

Larry S. Zurbrick, Agilent Technologies, Inc.

International Chair

Wilhelm Maurer, Infi neon Technologies AG (Germany)

Education Chair Wolfgang Staud, B2W Consulting

Newsletter Editors Artur Balasinski, Cypress Semiconductor Corp.

Warren Montgomery, CNSE

SponsorshipsSusan Siegfried, SPIE Sponsorship Consultant

Members at Large Frank E. Abboud, Intel Corp.

Michael D. Archuletta, RAVE LLC Uwe Behringer, UBC Microelectronics (Germany)Ute Buttgereit, Carl Zeiss SMS GmbH (Germany)

Chris Constantine, Oerlikon USA Inc.Thomas Faure, IBM Corp.

Gregory K. Hearn, SCIOPT EnterprisesGregg A. Inderhees, KLA-Tencor Corp.Kurt Kimmel, IBM Microelectronics Div.Paul Leuhrmann, ASML (Netherlands)

Mark Mason, Texas Instrument Inc.John A. Nykaza, Toppan Photomask, Inc.

Bryan S. Kasprowicz, Photronics, Inc.Douglas J. Resnick, Molecular Imprints, Inc.

J. Tracy Weed, Synopsys, Inc.

P.O. Box 10, Bellingham, WA 98227-0010 USATel: +1 360 676 3290 or +1 888 504 8171

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Volume 24, Issue 3 Page 3

N • E • W • SContinued from cover.

2. PMLP principlesThe principles of a PMLP tool are shown in Figure 1a. A broad ion beam is directed to a programmable aperture plate with thousands of apertures of micrometric dimension. Near the apertures are tiny defl ection plates, each of which can be individually powered (to several Volts) using integrated CMOS electronics. The slightly defl ected beams are stopped near the cross-over of the ion projection optics with 200x reduction. The non-defl ected beams are projected to the substrate. When using 3.5μm apertures fi nely focused beams of 17.5nm spot size are generated.

3. PMLP proof-of-concept toolA PMLP proof-of-concept (POC) tool was realized (Figure 1b) as part of the European integrated project CHARPAN (Charged Particle Nanotech). Beam-On was reached in February 2007. First

experiments were done using stencil test masks in HSQ resist and then with resist-less direct patterning in Si, GaAs, glass surfaces and in Cr and MoSi layers. Then multibeam exposures were done with multi-pole steering. Using a wired aperture plate providing 4,000 beams, fi rst results of mask-less HSQ resist exposures and resist-less patterning have also been accomplished

4. PMLP POC tool exposure results in HSQ resist

PMLP POC Tool resolution tests were initially concentrated on HSQ resist exposures using stencil resolution test masks. Fig-ure 2 shows exposure results in 20nm thick HSQ resist: 16 nm hp and single lines are resolved but show adhesion problems, caused by the forward scattering of 10 keV Ar+ ions in the 20nm

Figure 2. PMLP POC Tool exposure results in 20nm HSQ resist achieved with 10 keV Argon ions and an exposure dose of 5.6 µC/cm2.

Figure 3. Linewidth vs. dose for PMLP POC Tool exposure in 20nm HSQ resist and ion beam intensity profi le (• deduced from experiment, —error function with16nm FHWM).

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HSQ resist.For a 65nm single line the dose latitude is shown in Figure 3a.

There is only 1.5nm change of linewidth with 10% dose increase. From linewidth vs. dose measurements the ion beam intensity

profi le (including the forward scattering of 10 keV Argon ions in 20nm HSQ resist) was determined (fi t with 16nm FWHM error function) as shown in Figure 3b.

Figure 4. PMLP POC Tool direct patterning of 70nm Cr on quartz using 10 keV Argon ions with a sputtering dose of 39 mC/cm2.

Figure 5. PMLP POC Tool direct patterning of 25nm MoSi hardmask on 70nm Cr on quartz using 10 keV Ar+ ions with a

sputtering dose of 9.34 mC/cm2, showing a resolution pattern (u-l), a 22nm hp device pattern (u-r), 32nm hp (l-l) and 45nm contacts at 112.5nm pitch (l-r).

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Figure 6. PMLP POC Tool direct patterning in 25nm MoSi hardmask using 10 keV Ar+ ions with a sputtering dose of 9.34 mC/cm2 showing 22nm, 16nm and 11nm hp patterns.

Figure 7. PMLP POC Tool direct patterning in Si surface with 10 keV Ar+ ions with multipole induced positioning to form patterns of various depth.

Figure 8. PMLP POC Tool multi ion-beam direct patterning with multipole induced positioning to form complex patterns: a) on Si surface and b) on GaAs surface (logo patterned with 1600 beams).

Figure 9. PMLP POC Tool direct patterning of a 10 x 10 array of square microlenses with ~ 250k 10 keV Ar+ ion beams in parallel: a) convex shape on Si, b) concave shape on GaAs surface.

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5. PMLP resistless direct patterning of CR and MOSI hardmask layers

Resist-less direct patterning of 70nm Cr on quartz is shown in Figure 4. The ~70° sidewalls are due to angle dependent kineticsputtering yields and the ion beam intensity profi le. The required sputtering dose with 10 keV Argon ions was 39 mC/cm2.

Furthermore, 25nm MoSi hardmask layers on 70nm Cr on quartz mask blanks were directly structured with 10 keV Argon ion beams. The sputtering dose was 9.34 mC/cm2 for resistless direct patterning of 32nm hp lines and 45nm contacts, opened to Cr (Figure 5). Smaller patterns are resolved (Figure 6) but due to kinetic sputtering sidewall formation are V-shaped within the MoSi layer for the 16nm and 11nm hp patterns. The ion beam patterned MoSi hardmask layer was found to be suitable for RIE pattern transfer into the 70nm Cr layer.1

6. 3D patterning results achieved with the PMLP POC tool

Using a fi xed pattern array and electrostatic multipole beamlet positioning 3D patterns have been fabricated on Si and GaAs surfaces with nanometer depth precision as shown in Figure 7 and Figure 8. Using a stencil mask with about 250,000 openings (of various size) 10 x 10 arrays of square microlenses of concave

and convex shape have been realized on Si and GaAs surfaces (Figure 9). With prolonged sputtering sharp cones are formed at the microlens edges through re-deposition (Figure 10), in excellent agreement with IonShaper®2 simulations.3

7. First PMLP exposure results with a programmable aperture plate system

First experiments were performed with the PMLP POC Tool, insert-ing an APS demo unit with 4,000 apertures (Figure 11a, realized by the Fraunhofer Institute for Silicon Technology), providing 4.5μmx4.5μm beamlets (Figure 11b) which are demagnifi ed 200x to 22.5nm spot size at the substrate.

Corresponding PMLP POC Tool exposure results with 10 keV Argon ions in 20nm HSQ resist are shown in Figure 12 - Figure 15. There is edge roughness of the 45nm hp lines and variation in dot dimensions due to the very low exposure dose of about 5 μC/cm2. Though, Figure 12 demonstrates excellent dose latitude for single pass writing on a 22.5nm physical grid. The resist pat-tern shown in Figure 13a was exposed on a 11.25 nm physical grid with single pass writing. There is no signifi cant change when inducing 5-pass writing schemes.

Figure 13b shows the possibility of greytone writing of curved patterns with 33nm MFS. Figure 14 shows 30° and 60° oblique patterns. In Figure 15 the edge of three lines was shifted to realize

Figure 10. PMLP POC Tool direct patterning on GaAs with ~ 250k 10 keV Ar+ ion beams in parallel. Prolonged sputtering leads to the formation of cones at the lens edges by re-deposition processes.

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32nm instead of 45nm line width. There is excellent agreement between pattern design and realized exposure.

Furthermore direct sputtering of 20nm HSQ resist on Si was done with a sputtering dose of 10 mC/cm2. Smooth edges were obtained as demonstrated by AFM metrology (Figure 16).

8. PMLP throughput potentialThe main result of a study on the PMLP throughput potential is shown in Figure 17. There is the potential to realize an ionoptical column transporting a total current of 90nA to the substrate. For 140x140mm2 mask area writing times of < 20h seem to be feasible for 22nm technology requirements. For nanoimprint templates the writing times scale with the much lower area but the 1x features might need a dose > 50 μC/cm2.

There is the plan to implement precursor-gas assisted PMLP processes leading to vertical sidewalls and considerably lower ex-posure doses when compared to kinetic sputtering (Figure 18).

9. AcknowledgmentThis work was supported by the European Commission through funding of the integrated project CHARPAN (Charged Particle Nanotech; www.charpan.com). AFM metrology was provided by Bernhard Basnar, Vienna University of Technology, Austria. The SEM micrographs of the microlenses and cones on GaAs surface were provided by Falco van Delft, Philips MiPlaza, Eindhoven, Netherlands. Greyscale exposure data preparation was done with “Layout Beamer“ software from GenISys

10. References[1] J. Butschke et.al., SPIE Photomask / BACUS 2007, SPIE Proc.

Vol. 6730-148.[2] E. Platzgummer et.al., Microelectronic Engineering 83, pp. 936-

939 (2006).[3] Falco van Delft et.al., MNE 2007, Copenhagen, 23-26 Sept

2007, t.b.p. in Microeletronic Engngineering.

Figure 11. APS Demo Unit with 4000 apertures (a) and electron transmission characterization (b).

Figure 12. PMLP POC Tool exposure with APS demo unit of 20nm HSQ resist with 10 keV Ar+ ions with a) 4.5 µC/cm2 and b) 6.2 uC/cm2

exposure dose. Single pass writing using 25nm physical grid.

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Figure 13. PMLP POC Tool exposure with APS demo unit of 20nm HSQ resist with 10 keV Ar+ ions using a 11.25nm physical grid with a) 4.5 µC/cm2 and b) 5.4 uC/cm2 exposure dose.

Figure 14. PMLP POC Tool exposure with APS demo unit of 20nm HSQ resist with 10 keV Ar+ ions using a 11.25nm physical grid. Exposure dose a) 4.6 µC/cm2 and b) 5.4 uC/cm2.

Figure 15. PMLP POC Tool exposure with APS demo unit of 20nm HSQ resist with 10 keV Ar+ ions using a 11.25nm physical grid. At three line the edge was shifted with very good agreement between design and experiment as indicated. Exposure dose: 5.1 µC/cm2.

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Figure 16. PMLP POC Tool direct patterning with APS demo unit of 20nm HSQ resist on Si with 10 keV Ar+ ions with a sputtering dose of 10 mC/cm2.

Figure 17. Potential PMLP throughput for 22nm node masks.

Figure 18. Precursor-gas assisted PMLP processes, planned to be implemented.

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Industry Briefs

Sponsorship OpportunitiesSign up now for the best Photomask 2008 sponsorship opportunities. Contact:

Sue SiegfriedTel: +1 510 728 2105ssiegfried@spie.org

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Advertise in the BACUS News!

The BACUS Newsletter is the premier publication serving the photomask industry. For information on how to advertise, contact:

Sue SiegfriedTel: +1 510 728 2105ssiegfried@spie.org

BACUS Technical Meetings

BACUS holds technical meetings in the Bay Area approximately every quarter, from 8:30 to 11:30 am. If you are interested in presenting a paper at this meeting, contact Robert (Bob) Naber, Cadence Design Systems, Inc., Tel: 510 814 0972; Email: naber@cadence.com

BACUS Corporate Members

Aprio Technologies, Inc.ASML US, Inc.Brion Technologies, Inc.Coherent, Inc.Corning Inc.Gudeng Precision Industrial Co., Ltd.Hamatech USA Inc.Inko Industrial Corp.JEOL USA Inc.KLA-Tencor Corp.Lasertec USA Inc.Micronic Laser Systems ABRSoft Design Group, Inc.Synopsys, Inc.Toppan Photomasks, Inc.

■ NEC Succeeds in Fabrication of CNT Transistor Using Coating Process; Confi rms Feasibility of Environmentally Friendly Electronic Devices using CNTs

Semiconductor international, JCN NewswireNEC Corporation announced the successful development of a carbon nanotube (CNT) transistor using a coating process. The basic operation of the new transistor with advanced characteristics has been verifi ed, confi rming its application in the printed electronics fi eld. Main features of the new CNT transistors (1) Based on an NEC device model, design guidelines were established to verify the relationship between transistor characteristics and the length and density of the CNT when the CNT channel* is created and to increase CNT transistor performance. (2) A channel coating-process technology, capable of accurately controlling the density of the CNT, was also developed. CNT transistors were produced based on the new design guidelines and technology. Despite performance variation, extremely high mobility - the speed at which electrons move in the material - for a transistor manufactured using this type of coating process was achieved. The demand for electronics has rapidly increased in recent years along with environmental concern. This has brought about the need for more advanced electronic products that simultaneously achieve reduced environmental impact. Organic transistors and other printed electronics are one potential solution to this problem. Printed electronics’ technologies are unique in that they allow transistors to be formed by printing directly onto the substrate. This means that manufacturing processes can be dramatically simplifi ed in comparison to conventional semiconductors; waste materials generated through manufacturing processes can be reduced, and CO2 emissions can be reduced by more than 90%. The channel materials of conventional research organic transistors generally demonstrate little mobility and are therefore considered unsuitable for electronic devices with high-speed operation. The basic operations for a transistor formed using this coating process were confi rmed for the newly developed CNT transistor, which adopts CNTs as its channel material to allow 100 times greater mobility than regular organic transistors. The research results prove the potential of CNTs as a core transistor material, even in the fi eld of printed electronics. Further research is expected to show the potential to dramatically expand the scope of printed electronics applications. NEC views the new CNT transistor technology as key to the development of electronic devices with minimal environmental impact, and will continue to proactively conduct research in this area to realize environmentally-sound products.

■ SEMATECH Achieves Single Digit EUV Mask Blank Defect Goal Sematech North, Resist Test Center

Technologists at SEMATECH have successfully demonstrated world-class results in low defect density for mask blanks used in extreme ultraviolet lithography (EUVL)-pushing the technology another signifi cant step toward readiness for advanced manufacturing. In demonstrating a world’s best defect density of 0.04/cm2 for EUV mask blanks-with a total of only 8 defects combined from the substrate and the multilayer-the SEMATECH team surpassed the consortium’s published commercial EUV mask blank roadmap target for the end of 2007. The roadmap was fi rst developed in 2002 to chart SEMATECH’s multiyearstrategy to achieve the defect-free mask blanks needed for high volume EUVL manufacturing. The technical achievement was reported at SEMATECH’s Mask Blank Development Center (MBDC), one of several major R&D centers within the College of Nanoscale Science and Engineering (CNSE) of the University at Albany. “SEMATECH’s comprehensive program to provide manufacturing-ready infrastructure for EUV lithography includes a major focus on the very diffi cult challenge of mask blanks,” said Michael Lercel, director of Lithography at SEMATECH. “We’ve met and exceeded this critical milestone, and we will continue to push ahead on this and other components that our members and the industry will need for successful EUV lithography manufacturing.” To achieve manufacturing capability, EUV lithography must clear several technology hurdles including mask blanks, reticle handling, sources, and resists. The mask blanks are the starting material used to make the reticle that contains the device pattern, and are particularly challenging because of the need to accurately deposit more than 80 layers to form the multilayer refl ector-while keeping the mask blank defect-free. Low defect mask blanks are essential for cost-effective manufacturing. The SEMATECH milestone was achieved through the combination of efforts in multilayer deposition, substrate cleaning, improved substrates from suppliers, and state-of-the-art mask blank defect inspection capability. SEMATECH’s previously announced partnership with Lasertec Corporation of Japan provided the inspection capability to fi nd defects as small as 53nm on the mask blanks, which was instrumental in providing cycles of learning to reduce defects.

Volume 24, Issue 3 Page 11

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2008

Photomask Japan

16-18 April Hotel Pacifi co YokohamaYokohama, Japanwww.photomask-japan.org

Photomask Technology

6-10 October Monterey, California, USAspie.org/photomask

2009

Advanced Lithography

22-27 FebruarySan Jose, California, USAwww.spie.org/al

SPIE TV presents:

Optical Microlithography Webcast - SPIE Advanced Lithography 2008

Beginning 10 March 2008

C a l e n d a r

About the BACUS GroupFounded in 1980 by a group of chrome blank users wanting a single voice to interact with suppliers, BACUS has grown to become the largest and most widely known forum for the exchange of technical information of interest to photomask and reticle makers. BACUS joined SPIE in January of 1991 to expand the exchange of information with mask makers around the world.The group sponsors an informative monthly meeting and newsletter, BACUS News. The BACUS annual Photomask Tech-nology Symposium covers photomask technology, photomask processes, lithography, materials and resists, phase shift masks, inspection and repair, metrology, and quality and manufacturing management.

Join the premier professional organization for mask makers and mask users!

Corporate Membership Benefi ts include:■ One Voting Member in the SPIE General Membership

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Individual Membership Benefi ts include:■ Subscription to BACUS News (monthly)

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