background statement for semi draft document 4418...

Background Statement for SEMI Draft Document 4418 Revision to SEMI E78-0706 - GUIDE TO ASSESS AND CONTROL ELECTROSTATIC DISCHARGE (ESD) AND ELECTROSTATIC ATTRACTION (ESA) FOR EQUIPMENT Note: This background statement is not part of the balloted item. It is provided solely to assist the recipient in reaching an informed decision based on the rationale of the activity that preceded the creation of this document. Note: Recipients of this document are invited to submit, with their comments, notification of any relevant patented technology or copyrighted items of which they are aware and to provide supporting documentation. In this context, “patented technology” is defined as technology for which a patent has issued or has been applied for. In the latter case, only publicly available information on the contents of the patent application is to be provided. Among users and manufacturers of semiconductors, MEMS devices, and flat panel displays, the effects of electrostatic surface charge are well known. Charged surfaces attract particles (electrostatic attraction or ESA) and increase the defect rate. Charged products are sometimes difficult to handle and cause equipment jamming or breakage. Finally, electrostatic discharge (ESD) damages products and reticles, as well as causing numerous equipment malfunctions. Static control methods have been employed by equipment manufacturers to reduce the effects of static charge while the equipment is handling product or reticles. SEMI has issued E78-0706: Guide to Assess and Control Electrostatic Discharge (ESD) and Electrostatic Attraction (ESA) for Equipment to address electrostatic issues that occur within the manufacturing equipment. SEMI E78-0706 was previously harmonized with the technology nodes and electrostatic control recommendations of the International Technology Roadmap for Semiconductors (ITRS) 2005. However, the rapid shrinking of the ITRS technology nodes caused a similar rapid reduction in the recommended levels for static charge control. In some cases, specifically the recommended levels for allowable static charge on wafers and reticles, the recommendations were becoming difficult to attain and not technically necessary. A technical change has been made to SEMI E78 to differentiate between the allowable static charge levels on wafers and reticles, and those recommended for individual IC devices. This change is found in ¶ 12.7 Table 1. Additionally, several editorial changes have been made to clarify existing parts of the document. §1 Purpose, §2 Scope, §9 Test Specimen, and §12 Procedures contain such clarifications. §12 has been rewritten to clarify that unless there is an existing requirement from an end user, equipment manufacturers may follow the recommendations of ¶ 12.7 Table 1, based on the ITRS technology nodes, in designing and qualifying their equipment. End users may also decide to follow the recommendations of ¶ 12.7 Table 1, as an alternative to actual testing to determine the electrostatic sensitivities of their products and reticles. ¶ 5.3 Acronyms has been added to define acronyms used in the document. When the changes in SEMI E78 are approved, they will be harmonized with SEMI E129-0706 and with ITRS 2007. This will support more effective equipment negotiations and purchase agreements between the equipment suppliers and purchaser/users by eliminating confusion about which industry document should be referenced. The values contained in this document will harmonize with those contained in the 2006 and 2007 editions of the International Technology Roadmap for Semiconductors (ITRS) available from International SEMATECH, www.sematech.org. The information on static control is contained in the Factory Integration Chapter, which may be downloaded from the website.

This ballot will be reviewed by the Electrostatic Discharge (ESD) Task Force in April, 2008 (contact Arnie Steinman at [email protected] for specific meeting location and schedule), and adjudicated by the Metrics Committee on Wednesday, April 8, 2008, in Dallas TX, in conjunction with the North America Spring Standards meetings.

This is a draft document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted standard. Permission is granted to reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document development) activity. All other reproduction and/or distribution without the prior written consent of SEMI is prohibited.

Page 1 Doc. 4418 © SEMI®

Semiconductor Equipment and Materials International 3081 Zanker Road San Jose, CA 95134-2127 Phone:408.943.6900 Fax: 408.943.7943

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DRAFTDocument Number: 4418

Date: 10/22/2007

SEMI Draft Document 4418 Revision to SEMI E78-0706 - GUIDE TO ASSESS AND CONTROL ELECTROSTATIC DISCHARGE (ESD) AND ELECTROSTATIC ATTRACTION (ESA) FOR EQUIPMENT

This standard was technically approved by the global Metrics Committee. This edition was approved for publication by the global Audits and Reviews Subcommittee on XXXXXXX. It was available at www.semi.org in XXXXXX and on CD-ROM in XXXXXX. Originally published September 1998; previously published November 2005, and July 2006.

1 Purpose 1.1 The purpose of this document is to minimize the negative impact on productivity caused by static charge and electric fields in semiconductor manufacturing equipment. It is a guide for establishing electrostatic compatibility of equipment used in semiconductor manufacturing. Electrostatic compatibility in the entire semiconductor factory is addressed in SEMI E129. 1.2 Electrostatic surface charge causes a number of undesirable effects in semiconductor manufacturing environments. 1.2.1 Electrostatic discharge (ESD) damages both products and reticles. ESD events also cause electromagnetic interference (EMI), resulting in equipment malfunctions. 1.2.2 Charged wafer and reticle surfaces attract particles (electrostatic attraction or ESA) and increase the defect rate. Charge on products can also result in equipment malfunction or product breakage. 1.2.3 Operating problems and additional product defects due to static charge can have a negative impact on the cost of ownership (COO) of semiconductor manufacturing equipment (refer to SEMI E35). 1.3 This document can be used as a guide for equipment manufacturers during the design and testing of their equipment. The test methods described can also be used by semiconductor manufacturers to check the performance of equipment and to verify its conformance with procurement specifications. 1.4 Semiconductor process technology will continue to move toward smaller product geometries. Acceptable static charge levels will decrease with product feature size. This document provides recommendations for equipment static charge limits that are appropriate for the product being manufactured, referencing the feature sizes contained in the International Technology Roadmap for Semiconductors (ITRS). .

2 Scope 2.1 The scope of this document is limited to methods of measurement and a guide for the maximum recommended level of static charge on: • Product or reticles, • Carriers, and • Parts of the input/exit ports of equipment and minienvironments.

2.2 This document presents a table of maximum recommended levels of static charge on products, reticles, carriers, and the input and exit ports of production equipment or minienvironments. The purpose is to: • Reduce product, reticle, and equipment damage due to ESD, • Reduce equipment lock-up problems due to ESD events, and • Reduce the attraction of particles to charged surfaces.

2.3 This document references SEMI E129, SEMI E43, and other methods of measuring static charge. 2.4 Appendix 1 describes the methodology for determining the maximum recommended static charge levels that are shown in ¶ 12.7 Table 1. It includes both the original methodology contained in SEMI E78 and the updated information that harmonizes this guide with the recommendations of SEMI E129. NOTE 1: Related Information 1 of this document contains a theoretical investigation of electrostatic particle attraction, as well as case histories from users and equipment manufacturers as to the static charge problems encountered and how they were solved. A bibliography of related technical papers is also included. Related Information 2 describes static control methods commonly used in semiconductor manufacturing. A more detailed discussion of these static control methods will be found in SEMI E129.




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Related Information 3 contains an example for adding electrostatic compatability requirements to purchasing documents for semiconductor manufacturing equipment. Related Information 4 discusses the risk to reticles from electric fields. Revision Record describes the changes in this document from SEMI E78-1105. 2.5 For product and reticle protection or EMI control, the ESD risk of an area is defined by the presence and nature of the ESD events that occur. 2.6 For contamination control by reducing particle attraction, the static risk of an area is defined by the presence and level of static charges. 2.7 For damage to reticles, the risk is defined by the rate of change of static charge on a reticle or the electric field strength around a reticle. 2.8 An increasing amount of semiconductor production is done in minienvironments or within the production equipment. The majority of static-related problems occur while the product is in its carriers, or being transferred from them, by the production equipment. 2.9 Static control methods can be incorporated in the equipment design to reduce static charge to acceptable levels. This guide will be used primarily by equipment manufacturers during the design of their equipment. 2.10 There are test methods available (see § 6 and § 7 of this guide) to demonstrate the effectiveness of the static control methods. The end user will be able to use the same test methods to verify compliance with an equipment purchase specification. Testing should be done by persons qualified in the field of electrostatic measurements. 2.11 Increasingly, semiconductor production equipment is assembled using modules supplied by different manufacturers. While each module manufacturer may use the test methods in this guide to demonstrate the effectiveness of their static control methods, it is recommended that the same testing be applied to the complete system by the end user. 2.12 Static control methods applied to equipment design will not solve all static-related problems in the semiconductor manufacturing facility. Transport of product or reticles throughout the facility will be affected by, and the cause of static problems. Moving personnel in the manufacturing facility are also a source of static charge problems. These facility issues are addressed in SEMI E129. NOTICE: This standard does not purport to address safety issues, if any, associated with its use. It is the responsibility of the users of this standard to establish appropriate safety and health practices and determine the applicability of regulatory or other limitations prior to use.

3 Limitations 3.1 Static Measurements — Measurements of electrostatic quantities such as charge, electric field, and voltage are difficult to make. 3.1.1 The nature of the object (insulator or conductor), its geometry, its surroundings, and the measuring equipment itself, are only a few of the factors affecting the accuracy of an electrostatic measurement. 3.1.2 In general, direct measurement of static charge is possible with small, moveable objects. Larger objects, and those fixed in position, will need to be characterized by the electric field that results from the static charge. 3.1.3 Similarly, it is difficult to relate the measurement of an electrostatic quantity to its effect on products or equipment. 3.1.3.1 For example, an ESD simulator produces a standardized discharge waveform when a capacitor is discharged at a known voltage. This device is used to establish the ESD damage threshold for semiconductor products, or the effect of ESD on equipment. 3.1.3.2 While the amount of charge transferred by the ESD simulator is known (q = CV), the maximum current that results is not. There is no guarantee that the same amount of charge would produce the same results if different values of capacitance and voltage were used. 3.2 Location — The test methods and maximum recommended levels of static charge on product, reticles, and carriers are meant to be applied at the input/exit ports of production equipment, and when possible for characterization within the equipment. This document is not meant to be applied in any way that affects the process within the equipment. 3.3 Test Methods — The test methods referenced in this document do not guarantee precise measurements of static charge levels. The maximum static charge levels recommended in this document have large tolerances (see ¶ 15.1).




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3.4 Static Charge Control — There are a variety of static-related issues in a semiconductor manufacturing environment. The issues are complex due to the wide range of electrostatic problems, and device or equipment sensitivities to these problems. This guide contains general recommendations. Users of this document are cautioned that specific static-related problems may require or allow different levels of static charge than are recommended in this document. 3.5 Measurements 3.5.1 Measurements of Very High Static Potentials (>30,000 V) — Measurements of very high static potentials (>30,000 V) may need to be done at large enough distances to avoid exceeding the measurement range of the meter and/or an ESD event to the meter. 3.5.2 Accuracy of measurements of static voltage on the object may vary depending on the size of the object, the distance from the object, and presence of other grounded or charged objects in the immediate proximity to the measured object. Consult the measuring equipment manufacturer for information regarding measurements made at alternative distances. 3.5.3 Measurements on Moving Objects or Surfaces — Care should be taken, when attempting to read electrostatic charges on moving objects or surfaces, to maintain correct distance and avoid any contact; this is to ensure "good" readings with no mechanical damage or personal injury. 3.5.3.1 Measurements made on moving objects should be done using measuring equipment with a response time fast enough for the speed of the moving object. Consult the measuring equipment manufacturer for relevant information. 3.6 This document does not apply to semiconductor manufacturing equipment that does not handle or contain products or reticles, or their carriers.

4 Referenced Standards and Documents 4.1 SEMI Standards SEMI E10 — Specification for Definition and Measurement of Equipment Reliability, Availability, and Maintainability (RAM) SEMI E33 — Specification for Semiconductor Manufacturing Facility Electromagnetic Compatibility SEMI E35 — Guide to Calculate Cost of Ownership (COO) Metrics for Semiconductor Manufacturing Equipment SEMI E43 — Guide for Measuring Static Charge on Objects and Surfaces SEMI E129 — Guide to Assess and Control Electrostatic Charge in a Semiconductor Manufacturing Facility 4.2 ESD Association Standards and Advisories1 ANSI ESD STM5.1 — Electrostatic Discharge Sensitivity Testing – Human Body Model (HBM) - Component Level ANSI ESD STM5.2 — Electrostatic Discharge Sensitivity Testing - Machine Model (MM) - Component Level ANSI ESD STM5.3.1 — Electrostatic Discharge Sensitivity Testing - Charged Device Model (CDM) - Component Level ESD ADV1.0 — Glossary of Terms ESD TR20.20 — ESD Handbook 4.3 JEDEC Documents2 JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) JESD22-C101 — Field-Induced Charged-Device Model Test Method for Electrostatic Discharge Withstand Thresholds of Microelectronic Components 4.4 Other Documents

1 Electrostatic Discharge Association, 7900 Turin Road, Building 3, Suite 2, Rome, NY 13440-2069, USA. Telephone: 315.339.6937; Fax: 315.339.6793, Website: www.esda.org 2 JEDEC Solid State Technology Association (aka the Joint Electron Device Engineering Council), 2500 Wilson Boulevard, Arlington, VA 22201-3834, USA. Telephone: 703.907.7560; Fax: 703.907.7583, Website: www.jedec.org




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IEC 61000-4-2 — Electromagnetic compatibility (EMC) Part 4.2: Testing and measurement techniques – Electrostatic discharge immunity test, Transient Immunity Standard, International Electrotechnical Commission (IEC)3 89/336/EEC —Directive on Electromagnetic Compatibility – European Commission4 ITRS 2005 — International Technology Roadmap for Semiconductors – ITRS5 MIL-STD 883G — Test Method Standard – Microcircuits (Method 3015.7 – Electrostatic Discharge Sensitivity Classification), Defense Supply Center Columbus6

NOTICE: Unless otherwise indicated, all documents cited shall be the latest published versions.

5 Terminology 5.1 Definitions 5.1.1 deposition rate — particle flux to a surface (number of particles deposited per unit area per unit time) divided by the particle concentration adjacent to the surface boundary layer. Sometimes called the deposition velocity. 5.1.2 electromagnetic interference (EMI) — any electrical signal in the non-ionizing (sub-optical) portion of the electromagnetic spectrum with the potential to cause an undesired response in electronic equipment. 5.1.3 electrostatic attraction (ESA) — the force between two or more oppositely charged objects. NOTE 2: The result is increased deposition rate of particles onto charged surfaces, or movement of charged materials. 5.1.4 electrostatic compatibility — charge control adequate to allow the manufacturing of products and the inter-equipment transfer of products, reticles, and carriers without electrostatic problems (from SEMI E129). 5.1.5 electrostatic discharge (ESD) — the rapid spontaneous transfer of electrostatic charge induced by a high electrostatic field. NOTE 3: Usually the charge flows in a spark between two objects at different electrostatic potentials. 5.1.6 equipment electrostatic levels — acceptable static charge levels related to the major technology nodes of product and reticle feature sizes. 5.1.7 ESD simulator — an instrument providing a specified electrostatic discharge current waveform when discharged directly to a product or equipment part. 5.1.8 input and exit ports — the locations where product and/or product carriers are placed to allow the equipment to process them, or where they are removed from the equipment after processing. 5.1.9 minienvironment — a localized environment created by an enclosure to isolate the product from contamination and people. 5.1.10 product — any unit intended to become a functional semiconductor device. 5.2 Description of Terms Specific to this Standard 5.2.1 carrier — a device for holding wafers, dies, packaged integrated circuits (ICs), or reticles for various processing steps in semiconductor manufacturing. 5.3 Acronyms Specific to this Standard ANSI – American National Standards Institute CDM – Charged Device Model COO – Cost of Ownership EEC – European Economic Community EMI – Electromagnetic Interference ESA – Electrostatic Attraction ESD – Electrostatic Discharge HBM – Human Body Model

3 International Electrotechnical Commission, 3, rue de Varembé, Case Postale 131, CH-1211 Geneva 20, Switzerland. Telephone: 41.22.919.02.11; Fax: 41.22.919.03.00, Website: www.iec.ch) 4 European Commission, Rue de la Loi, Wetstraat 200, B-1049 Brussels, Belgium; Website: www.europa.eu.int 5 ITRS Global Communication Center, SEMATECH, 2706 Montopolis Drive, Austin, TX 78741, USA; Website: http://public.itrs.net 6 Defense Supply Center Columbus, P.O. Box 3990, Columbus, OH 43216-5000, USA; Website: www.dscc.dla.mil




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IC – integrated circuit IEC – International Electrotechnical Commission ISO – International Standards Organization ITRS – International Technology Roadmap for Semiconductors JEDEC – Joint Electron Devices Engineering Council MIL-STD – U. S. Military Standard MM – Machine Model nC - nanocoulomb

6 Establishing Requirements 6.1 The following sections contain test methods that can be used to establish static damage thresholds for product, reticles, or equipment. They also contain test methods to determine the levels of static charge and electrostatic fields that result on product, reticles, and equipment during the manufacturing process. 6.2 As an alternative to determining actual static charge sensitivity levels for product, reticles, and equipment, the end user may establish requirements based on the year and technology node of the manufacturing process. Recommendations for acceptable static charge levels are found in ¶ 12.7 Table 1. 6.3 Measurement Methods and Instrumentation — No single method of testing for static charge can determine a “safe” level. The amount of static charge, the distribution of static charge on an object, and the nature of the static discharge will all interact to determine if the charge level is safe. 6.3.1 It will be difficult to determine levels that guarantee static-related problems are totally eliminated. 6.3.2 Measurement methods described in this guide can assist the user in identifying static charge or electric field levels likely to cause problems in process equipment. They can allow the user to evaluate the effectiveness of the methods used to control the static charge and electric field levels. 6.4 Testing for ESD Damage 6.4.1 When considering direct ESD damage to an object (i.e., product, reticle, or equipment), the important parameter is the current accompanying the charge transfer to or from the object. Under a fixed set of test parameters, the damaging amount of current due to the charge transfer to or from the object can be determined. 6.4.2 When testing packaged devices, ESD simulators of various types are used for this purpose. Refer to ESD Association standards ANSI ESD STM5.1, ANSI ESD STM5.2, and ANSI ESD STM5.3.1, JEDEC JESD22-A114, JESD22-A115, and JESD22-C101, or MIL-STD 883 standards listed in § 4 for further information concerning device testing. 6.4.3 There are no established standards for ESD simulator testing of wafers, reticles, or unpackaged semiconductor devices. ESD damage thresholds for these items may be different than for packaged devices. 6.4.4 Once the damaging current level for a product is determined using an appropriate ESD simulator (depending on the standard being used), the corresponding amount of charge is known from the ESD simulator operating parameters. 6.4.5 The end user should determine what is the damaging current level due to charge transfer to product or reticles, that will be handled in a particular piece of production equipment. 6.5 Measuring Static Charge — In the context of production equipment, it appears important to know the charge on the product, its carriers, and any other objects that might directly contact the product. 6.5.1 Charge is measured in coulombs, or more conveniently in nanocoulombs (nC = 10−9 coulombs) for this purpose. Charge measurements are made with a Faraday Cup, as shown in § 7, Figure 1, or a coulombmeter as described in SEMI E43, for isolated conductors (including personnel), or small and moveable objects. 6.5.2 These measurement methods can be used to establish that the charge levels on these objects will pose a hazard to products or reticles from a direct ESD event. 6.5.3 A charged object, like an integrated circuit, is placed in the Faraday Cup and a reading is taken of the charge on it. It will be necessary to obtain an instrument with a large enough “cup” for wafers, carriers, and other equipment parts. It will also be necessary to get the objects into the cup without altering their charge levels. Further information on making these measurements should be available from the manufacturers of the measuring equipment.




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6.5.4 The user should determine with an ESD simulator what levels of ESD cause product or reticle damage. The equipment manufacturer will need to determine with an ESD simulator what levels of static charge cause equipment malfunction or damage. 6.5.5 It will be the responsibility of the equipment manufacturer to demonstrate that equipment operation does not generate more than the allowable amount of charge on product, carriers, or equipment parts. This is shown in § 7, Figure 2. 6.6 Measuring Electric Field — Electric field measurements on large and fixed objects or insulators are less useful in estimating whether or not a damaging direct ESD event will occur. On objects that cannot be conveniently measured with a coulombmeter, electrostatic fieldmeter measurements can be useful in estimating the ESD threat from the object, even though the measurement may be less quantitative than the coulombmeter measurement. In some cases, an electrostatic voltmeter can be used to make measurements of electrostatic surface voltages that can be used to estimate electric fields. 6.7 Testing for ESD Damage Caused by Induced Charge Separation 6.7.1 ESD damage may result from charge separation on an object. Part of a product (e.g., epoxy package) or reticle (e.g., quartz substrate) may become charged and induce charge separation to occur on another part of the product (e.g., lead pins) or reticle (e.g., chrome traces). ESD can occur if the lead pins or chrome traces are brought close enough to or make contact with a grounded surface. 6.7.1.1 Using a coulombmeter or Faraday Cup and the methods of SEMI E43, the end user should test product or reticles to determine the level of static charge at which ESD damage occurs from contact with ground. 6.7.2 Alternatively, either the product or reticles may be handled in proximity to another charged object. The field from this charged object induces charge separation on product or reticles, and ESD can result if the product or reticle is brought close enough to or contacts ground while in the presence of the field. 6.7.2.1 Using an electrostatic fieldmeter or voltmeter and the methods of SEMI E43, the end user should test products and reticles to determine the levels of electric field from static charge which cause ESD damage when there is contact with ground. 6.7.3 It has been shown that both a static and a changing electric field can cause ESD damage to reticles without ground contact occurring. 6.7.3.1 A static electric field occurs when the reticle or its packaging becomes charged during handling. A changing electric field can result at the reticle when an object in proximity to the reticle acquires a charge, the reticle or a charged object are in motion with respect to each other, or grounding conditions change the field between a charged object and the reticle (e.g., due to robot handling). 6.7.4 In equipment that produces or handles reticles, the electric field from any charged object will need to be limited to levels that do not cause reticle ESD damage. Test methods for electric field are contained in SEMI E43. There are currently no industry standards for determining electric-field sensitivity of reticles, but test methods do exist. NOTE 4: See references in Related Information 2 and 4. 6.7.5 There is evidence that reticles may be damaged by electric fields without an ESD event occurring. Further research is needed in this area. NOTE 5: Refer to Related Information 4. 6.7.6 Finally, there is increasing anecdotal evidence that the presence of static charge on wafer surfaces is becoming an ESD hazard as gate oxide thicknesses become thinner. In the future, there may need to be further limits on allowable static charge on wafer surfaces to prevent ESD-related gate oxide damage during front-end semiconductor manufacturing. Further research is needed in this area. 6.8 Testing for Electrostatic Particle Attraction 6.8.1 Electrostatic attraction (ESA) of particles can occur due to the electrostatic field created by the charge on the surface of an object. 6.8.1.1 Both the field strength and, usually to a lesser degree, the divergence of the field influence the electrostatic contribution to particle deposition rate (often referred to as the particle deposition velocity). Electrostatic particle deposition rate also depends on particle size and particle electrical charge.




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6.8.1.2 Unfortunately, even under controlled laboratory conditions, accurate measurements of electric field strength, particle size distribution and especially, particle charge, are difficult. Of these three parameters, electric field measurements are the most likely to be available. 6.8.2 Measurements of electrostatic field can be made with a commonly available electrostatic fieldmeter. The units of electrostatic field are volts/cm (volts/inch). 6.8.2.1 Precise measurements will be difficult as the presence of the measuring instrument changes the field characteristics and may overstate the actual level of electrostatic field. This is shown in § 7, Figure 3. SEMI E43 describes measurement techniques using an electrostatic fieldmeter, as well as alternate measurements using an electrostatic voltmeter. 6.8.3 Electrostatic particle deposition rate depends only on electric field, particle size, and particle charge. However, the number of particles deposited on a surface also depends on the particle concentration in the equipment area and the length of the exposure time during which particle deposition occurs. 6.8.3.1 Mechanisms other than electrostatic particle deposition, such as gravitational settling and diffusion, can also contribute to particle deposition. The number of particles deposited by these non-electrostatic mechanisms will also vary with particle concentration in the equipment ambient and exposure time. 6.8.3.2 Comparisons of the electrostatic particle deposition rate with the particle deposition rate associated with these other deposition mechanisms is the key for determining threshold values of allowed electrostatic field from the viewpoint of particle deposition. Such comparisons are the basis for estimating the allowed values of electrostatic field presented in Appendix A1-2.5. 6.8.3.3 Users and equipment manufacturers should determine and agree on ambient particle sizes and concentrations, and product exposure times. NOTE 6: Additional information on the allowed values of electrostatic field affecting particle deposition are found in Related Information R1-2. 6.8.4 The measurement methods of § 7 and SEMI E43 can be used to establish that the electric field from any product, reticle, or equipment surface meets the requirements of this document. 6.9 Equipment ESD 6.9.1 Equipment ESD immunity has been established at levels considerably higher than those that result in damage to product and reticles. If static charge limits shown in Table 1 of ¶ 12.7 are used to protect product and reticles, they will provide sufficient protection for the equipment. 6.9.2 ESD immunity for manufacturing equipment is being addressed in general through a number of international standards including IEC 61000-4-2, 89/336/EEC for European compliance, and the guidelines in SEMI E33. 6.9.3 Measurements are made using an ESD simulator, which is described in these standards. NOTE 7: A further discussion of ESD-related EMI issues can be found in Related Information 3 of SEMI E129.

7 Apparatus 7.1 ESD Damage — The apparatus for determining the ESD damage thresholds for products will depend on the test methods used. See § 4 for additional information. For measuring the charge generated on product, reticles, or carriers, the Faraday Cup test method is shown in Figure 1, and is described in more detail in SEMI E43.

In

Ground

Electrometer

FaradayCup

IsolatedInner Cup

ShieldingOuter Cup

Figure 1

Faraday Cup Charge Measurement




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7.1.1 Insulators are capable of simultaneously being charged to both polarities of static charge. Measurement with a Faraday cup will indicate the net charge rather that a separate amount of each polarity. An electrostatic fieldmeter or voltmeter should be used to determine whether this condition exists. 7.1.2 The relationship between ESD simulator testing for product damage and charge measurements using the Faraday Cup is shown in Figure 2.

1000VOLTS

DEVICE UNDER

TEST ESD

SIMULATORHBM, MM, CDM

100 NANOCOULOMBDISCHARGE IMMUNITY

FARADAYCUP

WAFER OR RETICLE CARRIERSWAFERS, RETICLES, OR ICs

LESS THAN 100 NANOCOULOMBALLOWABLE CHARGE LEVEL

WAFER RETICLE

IC

Figure 2

ESD Damage Testing

7.2 The instrument used for making electrostatic field measurements is known as an electrostatic fieldmeter. Instructions concerning its use should be obtained from the instrument manufacturer and SEMI E43. 7.3 The measurement configuration shown in Figure 3 illustrates the effect of the instrument on the measurement. In most cases the presence of the fieldmeter will increase both the flux from the charged surface and the divergence of the electric field lines. The fieldmeter will generally indicate a higher value of electric field than would be present without the fieldmeter. 7.4 An electrostatic voltmeter can be used as an alternative to the fieldmeter measurement. For small objects or surface areas, an electrostatic voltmeter is appropriate. 7.4.1 Under appropriate conditions, electrostatic voltmeters exhibit a high degree of accuracy and stability that is independent of the distance from the charged object. The electrostatic voltmeter probe can be located very close to a charged surface without arc-over, and it is able to resolve the field from a small charged object.

1999

+ + + + + + + + + + + + + + + +

2.54 cm(1 inch)

ElectrostaticFieldmeter(volts/cm)

+ + + + + + + + + + + + + + + +

ChargedSurface

Electric Field Lines

ChargedSurface

Figure 3 Electrostatic Field Measurement

8 Safety Precautions 8.1 Personnel — Static charges can create safety hazards during some semiconductor production processes. 8.1.1 ESA or ESD events that result in the jamming or breakage of product in high-speed equipment may create a personnel hazard. 8.1.2 ESD events that produce sparks must be prevented in areas that use flammable or explosive chemicals or gases.




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8.1.3 ESD events to personnel are usually not harmful, but they may result in an unwanted reflex, or “startle” reaction. This reflex may create a personnel hazard, particularly in the vicinity of moving equipment or where caustic chemicals are in use. 8.1.4 EMI resulting from ESD events may cause unpredictable behavior of robotics or other moving equipment that put personnel at risk. 8.1.5 It may be necessary to use additional static control methods, beyond those used inside the equipment, to minimize these personnel hazards. 8.2 Measurement Safety — Users should exercise caution while making static charge measurements in the vicinity of moving parts of production equipment, or in areas where static potentials on ungrounded conductors may exceed 30,000 volts. Refer to SEMI E43 for additional measurement safety considerations.

9 Test Specimen 9.1 The following are recommendations concerning the testing that will be performed. The user and equipment manufacturer should agree upon these recommendations and document them. 9.2 Measurements of electrostatic charge (in nC) should be performed using a nanocoulombmeter with a Faraday Cup. 9.3 Measurements of electrostatic field (in volts/cm or volts/inch) or electrostatic voltage (in volts) should be performed using an electrostatic fieldmeter or electrostatic voltmeter, respectively. 9.4 The user and equipment manufacturer should agree on who will do the testing. Prior to such agreement, the equipment manufacturer may consider using a third party to make measurements on the production equipment. 9.5 Test samples should represent the materials that will be handled by the equipment under actual use conditions. For example, testing with insulated and conductive wafers may produce significantly different results. 9.6 Measurements should be done with a minimum of 10 test samples of insulated or conductive wafers, reticles, packaged devices, or carriers, as handled by the equipment. This may also be done in a minimum of 10 consecutive test cycles with a single sample that is handled by the equipment and then measured. 9.6.1 Electrostatic charge measurements should be made on each test sample. Electrostatic field measurements should be made at multiple locations on each test sample, or on the parts of the input/exit ports of the equipment. Refer to E43 for recommendations on making measurements on small objects. 9.6.2 The average of the electrostatic charge, field, or voltage measurements on each test sample, or the electrostatic field or voltage measurements on parts of the equipment ports should meet the recommendations of ¶ 12.7 Table 1. No individual measurement should exceed two times the table value selected. The standard error of the measurements should also be reported. 9.7 The user and/or equipment manufacturer should agree upon and document the operating history of the equipment prior to, or during testing (e.g., warm-up time, type of carrier, number of products processed, and operating speed). 9.8 The user and/or equipment manufacturer should agree upon and document all appropriate environmental conditions (e.g., temperature, humidity, dew point, and airflow). NOTE 8: § 12 provides guidance on test conditions prior to negotiation between the end user and equipment manufacturer.

10 Preparation of Apparatus 10.1 Depending on the type of testing to be done, consult the appropriate testing document for apparatus preparation. See § 4 for additional information.

11 Calibration and Standardization 11.1 Depending on the type of testing to be done, consult the appropriate testing document for apparatus calibration and verification. See § 4 for additional information.

12 Procedures 12.1 End users may decide to follow the recommendations for acceptable electrostatic charge levels or electrostatic fields contained in ¶ 12.7 Table 1, which are based on product and reticle geometry. See Appendix 1 for more information.




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12.2 Equipment manufacturers design their equipment to avoid producing damaging amounts of electrostatic charge or electrostatic field on products, reticles, or the surfaces of their equipment. Equipment manufacturers can use the test methods of §9, and ¶ 12.4 – 12.5 below to qualify their equipment as following the recommendations for acceptable electrostatic charge or electrostatic field levels contained in ¶ 12.7 Table 1, which are based on product and reticle geometry. 12.3 Alternatively, end users can determine the levels of electrostatic discharge and electrostatic field their products and reticles can withstand without damage. 12.3.1 Measurement methods for integrated circuits are decribed in the documents contained in §4. 12.3.2 Appropriate measurement methods for ESD damage to wafers, reticles, and other items may be adapted from the instrumentation used in the test methods contained in the documents of § 4. Appendix A1-2.1–A1-2.4 contains additional information to select an allowable electrostatic charge level to reduce ESD damage. NOTE 9:Related Information R1-1 contains additional information to select an allowable electrostatic charge level to reduce ESD damage. 12.3.3 End users should work with equipment manufacturers and reticle suppliers to determine ambient particle levels, product exposure times during processing, and reticle damage levels due to electrostatic field. Appendix A1-2.5 contains information to select an appropriate electrostatic field level to reduce electrostatic attraction of particles. NOTE 10: Related Information R1-2 contains information to select an appropriate electrostatic field level to reduce electrostatic attraction of particles. 12.4 ESD Damage 12.4.1 Measurement of ESD damage thresholds are made in units of coulombs (C), or more conveniently in nanocoulombs (nC = 10-9 C). 12.4.2 The Faraday Cup method is used to determine the static charge levels on products, product carriers, and equipment parts. Each item should be transported to the Faraday Cup in a way that does not alter its charge level. Consult the measurement equipment manufacturer’s instructions for recommendations on how to achieve this. 12.4.3 Measurements should be made of products, carriers, and materials in the equipment input/exit ports after significant amounts of product have been handled under normal manufacturing conditions. 12.4.4 Measurements should be made of products and their carriers after they have undergone normal processing in the equipment under test. Typically five measurements of products and/or carriers should be sufficient to demonstrate compliance with the selected electrostatic charge level. See § 13. 12.4.5 Measurements should be made on each of two successive days after equipment has stabilized in its normal operating mode (e.g., after two hours). Equipment configuration (hardware and software) should not be changed for the duration the test period. 12.5 Electrostatic Field 12.5.1 Measurements of electrostatic field are expressed in volts/cm or volts/inch. 12.5.2 Electrostatic field measurements should be made at a minimum on all surfaces within the equipment that will come within 30.5 cm (12 inches) of ESD sensitive items. Typical surfaces to measure would include products, reticles, carriers, robotics, and equipment surfaces. 12.5.3 Measurements should be made at five different locations on any item. Locations should be separated by approximately three times the distance between the measuring instrument and the measurement location. For most electrostatic fieldmeters measuring at 25.4 mm (1 inch), the measurement locations will be 76.2 mm (3 inches) apart. Refer to SEMI E43 for additional measurement considerations, as well as alternate measurement techniques using an electrostatic voltmeter. 12.5.4 Measurements should be made on products, reticles, carriers, and materials in the equipment input/exit ports after significant amounts of product or reticles have been handled under normal manufacturing conditions. 12.5.5 Measurements should be made of products, reticles, and their carriers after they have undergone normal processing in the equipment under test. Typically five measurements at each location should be sufficient to demonstrate compliance with the selected electrostatic level. 12.5.6 Measurements should be made on each of two successive days after equipment has stabilized in its normal operating mode (e.g., after two hours). Equipment configuration should not be changed during the test period. 12.6 SEMI E129 Recommendations




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12.6.1 SEMI E129 ¶ 12.5 Table 1 contains recommendations for maximum electrostatic levels to prevent problems caused by static charge. 12.6.2 These levels apply to all elements of the semiconductor factory, including but not limited to construction materials, furniture, personnel, product, reticles, carriers, and transport and packaging materials. These levels should also apply to the equipment in the factory. 12.6.3 It is desirable in this document to harmonize with SEMI E129 recommended electrostatic levels, as well as to synchronize with the major changes in technology mapped in the International Technology Roadmap for Semiconductors (ITRS). 12.7 Recommendations for acceptable equipment electrostatic levels are listed in Table 1 and given for the major technology nodes of ITRS 2006, which relate to the size of the features on the wafer. Equipment used in semiconductor manufacturing should meet the levels shown in Table 1 for protection from problems caused by static charge. 12.7.1 Since many decisions to use static control methods will result in the permanent installation of these methods in equipment, users may want to consider the expected lifetime of the equipment in their manufacturing process in selecting the acceptable electrostatic level. NOTE 11: For example, at startup the equipment may be processing at 180-nm geometry, but will be capable of use down to 90-nm geometry. The equipment should be designed for the limits recommended for the 90-nm use.

Table 1 Recommended Equipment Electrostatic Levels

Year Node

Wafers and Reticles

Electrostatic Discharge,

nC

10 pF Device

Electrostatic Discharge,

nC

Electrostatic Field, V/cm V/inch

2000 180 nm

10.0 2.5–10 200 500

2002 130 nm

10.0 2.0 150 375

2004 90 nm

10.0 1.0 100 250

2006 70 nm

6.0 0.6 80 200

2007 65 nm

5.0 0.5 70 175

2009 50 nm

3.0 0.3 55 140

2010 45 nm

2.5 0.25 50 125

2013 32 nm

1.25 0.125 35 88

2015 25 nm

0.8 0.08 28 70

2018 18 nm

0.4 0.04 20 50

12.7.2 The levels in Table 1 assume that the equipment is processing silicon semiconductors. Equipment used for specialized components may need to use different levels. NOTE 12: Examples are equipment used to process gallium arsenide semiconductors or magneto-resistive (MR) disk-drive read heads, or equipment experiencing significant losses due to contamination. 12.8 The levels listed in Table 1 have been determined as the result of analysis of working conditions, or experiments done in operating semiconductor facilities. Justifications for these levels are found in Appendix 1.




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12.9 Other levels may be appropriate under specific equipment conditions and for specific devices.

13 Calculations 13.1 The average of the five consecutive measurements should not exceed the recommended level. 13.2 No measurement should exceed two times the recommended level.

14 Reporting Results 14.1 Data records should contain the following information: • Description of equipment under test including model and serial numbers, • Description of the equipment operating conditions and environment, • Measurement equipment and last calibration date, • Description of objects measured and measurement locations, • Humidity and temperature at measurement location when measurements were made, • Results of measurements, • Personnel making the measurements, and • Any other relevant comments.

15 Test Method Precision and Accuracy 15.1 The test methods referenced in this document do not guarantee precise measurements of static charge levels. Similarly, maximum static charge levels recommended in this document are not stated as precise requirements. 15.2 Accuracy of approximately ±20% is acceptable in all measuring instrumentation. At low static charge levels or for more accurate measurements, alternative instrumentation and test methods may be needed. 15.3 To evaluate low levels of electric field strength or the voltage on an object, use an electrostatic fieldmeter or electrostatic voltmeter with the resolution and accuracy required.




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APPENDIX 1 DEVELOPING THE RECOMMENDATIONS FOR ELECTROSTATIC LEVELS NOTICE: The material in this appendix is an official part of SEMI E78 and was approved by full letter ballot procedures on XXXXXX.

A1-1 Recommended Levels A1-1.1 The recommended charge and electrostatic field levels in this guide are not based on specific protection thresholds for individual devices or process equipment. Rather, their aim is to classify the types of ESD events or static levels that are likely to be of concern. Equipment manufacturers and users should determine the type of events that are of most concern to their products and process, so as to apply this guide to their needs. Information on specific device damage thresholds and equipment sensitivities is best determined on an individual basis.

A1-2 Justification of Guide Recommendations in ¶ 12.7 of Table 1 A1-2.1 Recommendations for ESD Damage A1-2.1.1 Devices are qualified according to the highest ESD stresses they can withstand without measurable change in their operating parameters. This section attempts to develop guide recommendations for minimizing ESD damage based on that discussion. NOTE 1: Related Information R1-1 discusses test methods for determining ESD damage thresholds for semiconductor devices. A1-2.1.2 Device damage thresholds continue to decrease as geometries get smaller. Although the classification systems discussed below do not change, more devices are falling into the more sensitive classifications. A1-2.1.3 It is desirable to harmonize this document with SEMI E129 and the ITRS to avoid confusion with SEMI E129 recommended facility electrostatic levels, as well as to synchronize with the technology nodes in the ITRS. Recommendations for acceptable static charge levels are listed in ¶ 12.7 Table 1 and given for the major technology nodes of ITRS 2006, which relate to the size of the features on the wafer. A1-2.2 Industry Device Damage Levels — Each of the device test methods (i.e., HBM, MM, and CDM) have a set of qualification levels defined. These are contained in Tables A1-1, A1-2, and A1-3 below.

Table A1-1 HBM Classification Levels

Class Voltage, V

0 <250 1A 250–499 1B 500–999 1C 1000–1999 2 2000–3999

3A 4000–7999 3B ≥8000

Table A1-2 MM Classification Levels

Class Voltage, V

M1 <100 M2 100–199 M3 200–399 M4 ≥400




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Table A1-3 CDM Classification Levels

Class Voltage, V

C1 <125 C2 125–249 C3 250–499 C4 500–999 C5 1000–1499 C6 1500–1999 C7 ≥2000

A1-2.3 Charge Levels for ESD Damage A1-2.3.1 ESD Simulator testing uses different capacitances for each model. For HBM it is 100 pF, for MM it is 200 pF, and for CDM it depends on the capacitance of the actual device under test. In any case, it is charge (charge = voltage × capacitance) that damages the device. It would seem appropriate, therefore, to state the guide recommendations in Table 1 of ¶ 12.7 in units of charge (e.g., nC). NOTE 2: This issue is discussed in more detail in Related Information R1-1.4. A1-2.3.2 Based on industry testing reflected in device data sheets, there appears to be a wide range for ESD immunity in semiconductor devices. This document deals primarily with ESD occurring within equipment. HBM type ESD discharges are the least likely to occur within equipment. Charged equipment parts contacting devices (MM) and charged devices contacting machine parts (CDM) are the most likely causes of ESD damage to devices in equipment. The following sensitivity levels are defined with respect to the existing industry MM and CDM classifications. A1-2.4 Guide Recommendations A1-2.4.1 At the 180 nm technology node for the year 2000, it is assumed that devices (although some may withstand higher levels of ESD) pass testing at HBM Class 0 (250 V × 100 pF = 25 nC), MM Class M1 (100 V × 200 pF = 20 nC), and CDM Class C3 (500 V × 10 pF device capacitance = 5.0 nC). A1-2.4.1.1 This guide recommends (Table 1 in ¶ 12.7) 2.5–10 nC at the 180 nm node in the year 2000. For this and all further recommendations, the device capacitance is assumed to be 10 pF. A1-2.4.1.2 For major technology nodes, the allowable ESD levels have decreased approximately with the square of the ratio of the critical dimension. The assumption is that energy dissipation capability is proportional to the area of the feature. A1-2.4.1.3 For example, in Table A1-4 at the 90-nm node this guide recommends approximately 25% of the 180-nm node or 1 nC, at the 45-nm node this guide recommends 0.25 nC, and at the 25-nm node this guide recommends 0.08 nC. Intermediate technology years have been changed accordingly. A1-2.4.1.4 The above recommendations are based on a 10 pF device. An entire reticle has a capacity of approximately 100 pF while 300 mm wafers have a capacity of approximately 225 pF. Both the reticle and the oxide-coated wafer are insulators. Charge on both sides of the reticle or wafer is likely the result of a processing step that uniformly creates charge across the entire surface. Charge in the back side alone can result from robotic handling. In either case, it is not possible to discharge the entire reticle or wafer through contact with ground. A1-2.4.1.5 The allowable charge level on the entire surface of the reticle or wafer should be proportional to the capacitance. Following the recommendations of ¶ A1-2.4.1.1 – A1-2.4.1.3 for 10 pF devices should safely allow a 10 times larger charge level on 100-225 pf reticles and wafers. Previous experience of practitioners of this standard have indicated that reducing charge levels on wafers to the 1-2 nC range is practical with existing static control methods. Accordingly, the value for 90 nm and larger technology nodes has been set to 10.0 nC (10 times the value for 90 nm devices). Values in subsequent years have been reduced according to ¶A1-2.4.1.3. A1-2.4.1.6 Table A1-4 contains the recommendations for preventing contact ESD damage to reticles and wafers. While there has been some anecdotal evidence that the electric field from static charge on a wafer surface can cause ESD damage, there are as yet no conclusive studies. The recommendations of Table A1-4 and Table 1 in ¶12.7 may need to be changed when such studies exist.




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Table A1-4 Guide Recommendations to Prevent ESD Damage

Year Node

10 pF Device Electrostatic Discharge, nC

Reticle and Wafer Electrostatic Discharge nC

2000 180 nm

2.5–10 10.0

2002 130 nm

2.0 10.0

2004 90 nm

1.0 10.0

2006 70 nm

0.6 6.0

2007 65 nm

0.5 5.0

2009 50 nm

0.3 3.0

2010 45 nm

0.25 2.5

2013 32 nm

0.125 1.25

2015 25 nm

0.08 0.8

2018 18 nm

0.04 0.4

A1-2.5 Recommendations for Particle Deposition A1-2.5.1 Electrostatic fields from charges on the wafer surface enhance particle deposition. This section attempts to develop the guideline recommendations for minimizing particle deposition from electrostatic fields. NOTE 3: This issue is discussed in detail in Related Information § R1-2. The following equations are found in that discussion. A1-2.5.1.1 Equations of interest are:

N/A = velectct (1) or,

velect = (N/A) / ct (2) where N/A equals the particle burden added to a wafer during exposure time t, to a particle concentration c, in an environment characterized by an electrostatic particle deposition velocity, velect.

velect = [(0.002 E0)] / (d / 0.01) (3) where E0 is the electric field measured in V/cm at one wafer radius and d is the size of the particle of interest in microns (the “killer particle”, typically assumed to be 1/2 of the feature size). Rewriting this equation,

E0 = (velect / 0.002) × (d / 0.01) (4)

A1-2.5.1.2 The only variable in Equation A1-1 that depends on electrical forces is velect. Both the particle charge and the electric field in the vicinity of the wafer affect the magnitude of velect. Particle charge is generally unknown unless it is deliberately controlled by a neutralizing action, such as flooding the environment with both positive and negative charges. Under these conditions a Fuchs type charge distribution is a reasonable assumption for the particle charge. This assumption is used to calculate the values of E0 (the electric field at which velect is equal to the particle deposition rate from diffusion). NOTE 4: These values of E0 are found in Table R1-1 of Related Information ¶ R1-2.3.2.




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A1-2.5.1.3 When the environmental electric field is less than E0, deposition of electrically “neutralized” particles is dominated by diffusion. When the environmental electric field is greater than E0, electrostatic forces dominate particle deposition even when particle charge has been “neutralized.” NOTE 5: Values of E0 for a Fuchs charge distribution can be calculated from Related Information ¶ R1-2.3.2 Equation R1-10. For particle charge greater than the Fuchs charge, velect increases by a factor of q/qFuchs. Unfortunately, the actual particle charge q is generally unknown and calculations are made only for the q = qFuchs condition. A1-2.5.2 Calculations are made based on the following assumptions: 1. Calculations are made for ISO Class 3 (corresponding to obsolete Federal Standard 209E Class 1) where

(c ≤ 0.00124 particles/cm3). 2. As contained in both ITRS 1999 and ITRS 2002, particle deposition velocity (rate) is assumed to be 0.01 cm/s

(ITRS 2002 Yield Enhancement Chapter, Notes Table 95a). Calculations of the allowable electric field are made assuming the electrostatic deposition velocity, velect, is equal to this value. Using Equation A1-4 in ¶ A1-2.5.1.1, with d = 0.09 µm for 180-nm technology, E0 = 45 V/cm).

3. The value of the electrostatic field is initially calculated at a distance of one wafer radius from the wafer (15 cm for a 300 mm wafer) using the equations of ¶ A1-2.5.1.1. While electrostatic field measurements can certainly be made at this distance, they are typically made at 2.5 cm (1 inch) with common instrumentation. This measurement is described in SEMI E43. Measurements made at this smaller distance will be proportionally higher, but under varying measurement conditions, it is difficult to determine a precise relationship between electric field and measurement distance. To provide a suitable safety factor, assume a linear relationship, rather than one proportional to the square of the distance.

NOTE 6: For example, with a 300 mm wafer, the electric field will be multiplied by a factor of 6 (15 cm / 2.5 cm). The allowable value of E measured at 2.5 cm is therefore, 270 V/cm) (6E0). A1-2.5.3 Guide Recommendations A1-2.5.3.1 Table A1-5 contains guide recommendations for allowable electrostatic field levels to minimize particle attraction. It is based on the calculations of ¶ A1-2.5.3 with the following additional assumptions: • Calculations assume that the value of velect decreases by the same percentage that the value of d decreases. See

Equation A1-3 of ¶ A1-2.5.1.1. • As velect decreases, the allowable value of E decreases by the same percentage, as shown by Equation A1-4 of

¶ A1-2.5.1.1. A1-2.5.3.2 The relationship of technology node, particles added at constant airborne particle concentration, and electrostatic field are shown in Table A1-5. The years and technology nodes shown in Table A1-5 correspond to those used in ITRS 2005. A1-2.6 Guide Recommendations for Induced ESD Damage A1-2.6.1 The presence of electrostatic fields in semiconductor manufacturing areas also creates the risk for induced ESD damage. A charge separation occurs in an isolated conductor when it is placed in an electric field. If the conductor momentarily touches ground, a flow of charge will occur to the conductor. This flow of charge may be a damaging ESD event. If the conductor, now possessing excess charge, is removed from the electric field, a second ESD event can occur when the conductor contacts ground again. A1-2.6.2 The most obvious example of these phenomena occurs once the semiconductor device is packaged. The package material is epoxy, an easily charged insulator. The electric field from the charged package induces a charge separation on the device leads. ESD events occur when the leads contact ground during processing. A1-2.6.3 A second problem for semiconductor manufacturing occurs when ESD sensitive objects experience a changing electric field. This occurs when an object moves within an electric field, or when the field around a stationary object changes in magnitude or configuration. Charge separation can be induced within the object causing potential differences between parts of the object. For example, position within the field can cause different potentials on a long and a short conductor. ESD events can occur between conductors at different potentials, establishing an equilibrium potential. Each time the field changes in any way the equilibrium is upset and multiple ESD events can occur.




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Table A1-5 Electrostatic Field Levels – Limit Particle Attraction

Year Node

d, Killer Particle Size

nm

Electrostatic Field

V/cm

2000 180 nm

90 270

2002 130 nm

65 195

2004 90 nm

45 135

2006 70 nm

35 105

2007 65 nm

32.5 97.5

2009 50 nm

25 75

2010 45 nm

22.5 67.5

2013 32 nm

16 48

2015 25 nm

12.5 37.5

2018 18 nm

9.0 27

A1-2.6.4 Charge separation induced by both static and changing electric fields is a concern in the handling of reticles with micron and sub-micron feature sizes. While ESD damage occurred with 5X reticles with 3–5 μm features, it was infrequent. At the 180-nm technology node, even 5X reticles have sub-micron features and the trend is to 4X reticles, making the feature sizes even smaller. As reticle feature dimensions have moved below 1 µm there is evidence that the sensitivity of reticles to ESD damage is increasing. With ever shrinking lithography process windows and critical dimension (CD) budgets, even minor field induced damage to a reticle may become a yield limiter. A1-2.6.5 The problem occurs because a reticle is basically a large collection of closely spaced, isolated conductors on an insulating quartz substrate. The substrate is easily charged, creating an electric field. The field changes whenever the spacing between the reticle and ground changes (e.g., during handling by robotics). Transporting the reticle, whether in static dissipative reticle carriers or not, exposes it to changing electric fields from other charged objects (e.g., equipment panels, windows, work surfaces, equipment parts). The result is an increased risk of field induced damage as reticle feature dimensions are reduced. A1-2.6.6 While there have been several studies documenting the existence of the field induced damage problem on reticles, there is currently a need for further research to demonstrate the level at which it occurs for production facilities. A recent study (Montoya, et al.) was able to produce the following information: 1. Testing was done on a reticle test device with 1.5 µm gaps between features. Approximately 800 V/cm

(2 kV/inch) of electric field was needed to cause ESD damage. 2. Current production 180-nm reticles are 4X with a nominal gap width of 0.72 µm (or less depending on the

technology). ESD should occur at 400 V/cm (1 kV/inch) or less. 3. To avoid ESD on 180-nm reticles, electric fields should be kept below 50% of the damage threshold, or 200

V/cm (500 V/inch). A1-2.6.7 The values in Table A1-6 column 2 below are based on these measurements. It is acknowledged that discharge phenomena may change at very small conductor spacing, and that the relationship to electric field may not be a linear function of the geometry. The values in Table A1-6 column 2 may need to be changed as more




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information becomes available. Table A1-6 column 3 reproduces the values to limit particle deposition from Table A1-5. NOTE 7: Refer to Related Information 4. A further study of the field sensitivity of reticles is included in Related Information 4, suggesting that damage other than ESD can occur more than an order of magnitude below these field strengths. A1-2.7 Guide Recommendations A1-2.7.1 This document recommends the values shown in parentheses in the second column of Table A1-6 of this Appendix and includes them in ¶ 12.7 Table 1.

Table A1-6 Electrostatic Field Levels – Limit Induced ESD Damage on Reticles

Year Node

Electrostatic Field Limits

Induced ESD Damage on Reticles,

V/cm

Electrostatic Field Limits

Particle Attraction,

V/cm

2000 180 nm

200 (200) 270

2002 130 nm

144 (150) 195

2004 90 nm

100 (100) 135

2006 70 nm

80 (80) 105

2007 65 nm

72 (70) 97.5

2009 50 nm

55 (55) 75

2010 45 nm

50 (50) 67.5

2013 32 nm

35 (35) 48

2015 25 nm

27 (28) 37.5

2018 18 nm

20 (20) 27

A1-2.8 Guide Recommendations for Equipment Malfunctions A1-2.8.1 Most semiconductor manufacturing equipment should comply with the ESD immunity requirements of the European Community (EC). The testing mandated by the EC uses the test methods and ESD immunity levels specified in IEC 61000-4-2. To test for compliance, make measurements with an ESD simulator described by IEC 61000-4-2. Equipment is required to pass a test involving the discharge produced by a 150 pF capacitor charged to 4000 V, or 600 nC. A1-2.8.2 Users should note that the above test discharge level and properties (i.e., discharge voltage, discharge model pulse rise time) may not be sufficient to predict actual discharges that occur in semiconductor production environments. In addition, the ESD immunity of equipment in an isolated test environment may change when it is installed in a production environment. A1-2.8.3 The discharge test specified in IEC 61000-4-2 is done at significantly higher charge levels than are recommended to prevent ESD damage to products in Table A1-4 of this Appendix. If the recommendations of Table A1-4 are followed, static charge levels should be low enough to prevent ESD induced equipment malfunctions. A1-2.8.4 If the recommended electrostatic levels regarding ESD contained in ¶ 12.7 Table 1 are not used, equipment should at least meet the requirements of IEC 61000-4-2.




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A1-2.8.5 Refer to SEMI E33 for additional information regarding the electromagnetic compatibility of production equipment.

A1-3 References Montoya, J. A., Levit, L., and Englisch, A., “A Study of the Mechanisms of ESD Damage for Reticles”, Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 394–405 (2000) Cooper, D. W., Miller, R. J., Wu, J. J., and Peters, M. H., "Deposition of Submicron Aerosol Particles During Integrated Circuit Manufacturing: Theory", Particulate Sci. Technol. 8 (3 and 4): 209–224 (1990) Liu, B. Y. H., and Ahn, K. H., "Particle Deposition on Semiconductor Wafers", Aerosol Sci. Technol. 6: 215–224 (1987) International Technology Roadmap for Semiconductors (1999, 2002, 2005, 2006)7 ISO 14644 — Cleanrooms and Associated Controlled Environments – Part 1 – Classification of Air Cleanliness8 SEMI E33 — Specification for Semiconductor Manufacturing Facility Electromagnetic Compatibility

7 ITRS Global Communication Center, SEMATECH, 2706 Montopolis Drive, Austin, TX 78741, USA; Website: http://public.itrs.net 8 Institute of Environmental Sciences and Technology (IEST), 5005 Newport Drive, Rolling Meadows, IL, 60008-38411, USA; Website: www.iest.org.




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RELATED INFORMATION 1 STATIC CHARGE PROBLEMS NOTICE: The material contained in this related information is not an official part of SEMI E78 and is not intended to modify or supersede the guide in any way. These notes are provided as a source of information to aid in the application of the guide, and are to be considered reference material. Determination of the suitability of the material is solely the responsibility of the user.

R1-1 ESD Damage Contributed by Leo G. Henry, Ph.D., [email protected]. R1-1.1 Introduction — ESD damage to devices occurs when devices contact personnel or equipment. Either may store a residual charge large enough to destroy the device if a discharge occurs. In the semiconductor industry, it has been established that a significant proportion of customer field returns are attributed to damage resulting from ESD. R1-1.2 Description of ESD Damage Mechanisms — ESD failures are the result of either a current-induced phenomenon or a charge-induced phenomenon, and the damage can be either junction, contact, dielectric or oxide related. The apparent similarity in current-induced damage resulting from ESD due to human body model discharges (HBM) or machine model discharges (MM) results from the thermal nature of both of these processes. The HBM and MM damages result when the temperature (joule heating) of the region dissipating the ESD pulse energy reaches a critical value and melting occurs. R1-1.2.1 Charge-induced phenomena are predicted by the charged device model (CDM). For CDM type discharges, oxide punch through occurs when the ESD voltage applied across the oxide creates a high enough field to break down the oxide. Excessive current flow results, causing an oxide short, but there is no heat transfer (adiabatic process). R1-1.2.2 It should be noted here that the time duration for typical ESD events from charged objects and personnel ranges from 10–100 ns, while CDM type events occur in less than 1 ns. R1-1.3 Device Testing Models R1-1.3.1 Human Body Model (HBM) — The Human Body Model is the oldest and the most widely used of the three ESD models. The model attempts to replicate the discharge from a real human when the latter touches a device that is at a lower potential. The human capacitance and resistance are chosen to be 100 pF and 1500 Ω respectively. The values were chosen after measurements were made on humans in varying positions with respect to their surroundings. The resulting discharge waveform has a double exponential shape with risetime range of 2–10 ns and a decay constant (1/e position) of 150 ± 20 ns. The typical peak currents range from 0.67 A at 1000 V to 2.67 A at 4000 V. R1-1.3.2 Machine Model (MM) — The Machine Model is described by Electronic Industries Association of Japan (EIAJ) as a worst case HBM. The model attempts to replicate the discharge from a metallic arm of an automatic handler that contacts the metallic leads of a semiconductor device that are at a lower potential. A capacitance of 200 pF and ideally zero resistance produces a sinusoidal decaying waveform with an effective pulse duration of 200 ns. The typical peak currents range from 1.75 A at 100 V to 14.0 A at 800 V. Note that MM failures occur at 5–10 times lower voltage than HBM. R1-1.3.3 Charged Device Model (CDM) — The Charged Device Model in its purest form is actually a field induced model because the device is actually part of model. This model attempts to describe a device which itself becomes charged due to an external field, or due to triboelectric charging of the device surfaces. During discharge, the parasitics (i.e., capacitance, inductance, impedance) in the device play a significant role in the resulting failure. The discharge pulse is a sinusoidal waveform with an extremely fast risetime of less than 500 ps. The waveform decays rapidly with a total pulse duration of less than 5 ns. The peak currents range from 2.0 A at 250 V charging voltage, to 18.0 A at 2000 V charging voltage. R1-1.3.4 Correlation Between Models — There is much debate on whether or not there is any type of correlation between HBM and MM. While some companies report a correlation of roughly 10:1 between the two models, other companies have seen anywhere from 5:1–20:1 differences in passing voltages between the two models. There is also no established voltage correlation between CDM damage and HBM or MM ESD events. In equipment, ESD damage events are related to the MM or CDM types of ESD. Users will need to determine the type of ESD hazard to their devices and choose the test method accordingly.




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R1-1.4 ESD Laboratory Simulation Testing R1-1.4.1 Description of Test Methods — Test procedures discussed here for ESD simulation conform to those established by the ESD Association Standards ANSI ESD STM5.1 (for HBM), ANSI ESD STM5.2 (for MM), ANSI ESD STM5.3.1 (for CDM) and MIL-STD-883 Method 3015.7. Details are found in these standards. R1-1.4.1.1 Devices are qualified at a level corresponding to the highest ESD stress they are able to withstand. These levels are discussed in more detail in Appendix A1-2.1. R1-1.4.2 Simulation Test Results — In general, all units must be data-logged both pre- and post-stress test. Any leakage current equal to or greater than a specific amount (company dependent — typically 10 µA or less) is “flagged” as a failure, and any current shift greater than about 200 nA is marked on the record. R1-1.4.3 HBM Stress Testing — An R-C network is used to simulate the ESD event. In an HBM ESD Simulator, high voltage charges the capacitor (100 pF) which discharges through the resistor (1500 Ω) into the device under test. The present standard requires a minimum of two discharges (1 positive and 1 negative) per voltage level. R1-1.4.4 MM Stress Testing — An R-C network is also used in the MM ESD Simulator for ESD testing. High voltage charges the capacitor (200 pF) which discharges through the short wire (0 Ω) into the device under test. The present standard requires a minimum of six discharges (3 positive and 3 negative). R1-1.4.5 CDM Stress Testing — The package and leadframe of the device are charged by direct charging or field induction. For the Direct Charging Method, direct contact is made to one of the device leads connected to the substrate or bulk material of the device. The device is then discharged via a 1-Ω resistor to ground. R1-1.4.5.1 For the Field Induced Method, the device is placed on a metallic charging plate with the device packaging material touching the plate. The potential of the device is raised by applying a voltage to the charging plate. The induced voltage on the device is discharged to ground through a 1-Ω resistor that contacts each device lead. The present standard requires a minimum of 6 discharges (3 positive and 3 negative) from each device lead. R1-1.5 Examples of Damage from Device Testing R1-1.5.1 HBM ESD Damage

Figure R1-1

Example of HBM Damage

R1-1.5.1.1 In this example of HBM damage (refer to Figure R1-1), de-processing (i.e., removal of the processed layers) down to the polycrystalline silicon (poly) level and very high magnification (SEM) examination were required in order to see the failure site morphology of arcing from source to drain within the ESD protective structures. The electrical characteristics found were: resistive shorts, leakages, low breakdown voltages and Icc failures.




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R1-1.5.2 MM ESD Damage

Figure R1-2

Example of MM Damage

R1-1.5.2.1 In the above MM example (refer to Figure R1-2), the damage was more severe than for HBM. De-processing down to the poly level and the SEM examination showed the failure site morphology of large deep pits occurring at the contact(s) suggesting high current parasitic bipolar action deep in the substrate and also within the ESD protective structures. The electrical characteristics found also resistive shorts, leakages, low breakdown voltages and Icc failures. R1-1.5.3 CDM ESD Damage

Figure R1-3

Example of CDM Damage

R1-1.5.3.1 In the above CDM example (refer to Figure R1-3), the gate oxide damage is seen as a unique failure signature beyond the input protection structures at an internal location of the die. Most often the oxide failure is located beneath the poly at the field oxide edge, or is located at the poly edge adjacent to the source/drain junction. To date, all CDM ESD damage has been found in the gate oxide at the input buffer circuitry. R1-1.6 References Cook, C., Daniel, S., Proceedings EOS/ESD Symposium, Dallas, TX (1992), p. 149–157 Euzent, B.L., Maloney, T.J., Donner II, J.C., Proceedings EOS/ESD Symposium, Las Vegas, NV (1991), p. 59–64 Morgan, I.H., A Handbook of EOS and ESD Models, AMD Internal Publication (1992)




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Pierce D.G., Shiley, W., Mulcahy, B., Wunder, M., Proceedings EOS/ESD Symposium, Anaheim, CA (1988), p. 137–146 May, J.T., Guravage, J.F., Proceedings ISTFA, Los Angeles, CA (1990), p. 143–147 Avery, L.R., EOS/ESD Symposium, Orlando, Florida (1987), p. 186–191 Avery, L.R., EOS/ESD Symposium, Orlando, Florida (1987), p. 88–92 Renninger, R.G., Jon, M.C., Lin, D.L., Diep, T., Welsher, T.L., Proceedings EOS/ESD Symposium, New Orleans, LA (1989), p. 59–71 Bossard, P.R., Chemelli, R.G., Unger, B.A., Proceedings EOS/ESD Symposium, San Diego, CA (1980), p. 17–22 AMD Internal Publications, PLD/CQD EOS/ESD, EOS/ESD Task Force Reports, July 1993 and January 1994 Raymond, T., Chang, K.L., Henry, Leo G., AMD 3rd Engineering Conference, February 1994 ANSI ESD STM5.1 — Sensitivity Testing – Human Body Model (HBM) - Component Level ANSI ESD STM5.2 — Sensitivity Testing -- Machine Model (MM) - Component Level ANSI ESD STM5.3.1 — Charged Device Model (CDM) – Component Level MIL-STD-883G Method 3015.7 – Microcircuits – Electrostatic Discharge Sensitivity Classification Gieser, H.A., Egger, P., Herrmann, M.R., Reiner, J.C., Birolini, A., ESREF Proceedings, Bordeaux, France (1993) Henry, Leo G., Raymond, T., Mahanpour, M., Morgan, I., 20th International Symposium for Testing and Failure Analysis (ISTFA), 1994

R1-2 Enhanced Particle Deposition Attributable to Electrical Charge on a Wafer Contributed by Douglas W. Cooper, Ph.D., The Texwipe Company, Upper Saddle River, NJ 07458. R1-2.1 Introduction — The presence of excess electrical charge on a wafer can create an electrostatic field that will lead to accelerated deposition of particles onto the wafer. This undesirable consequence is but one of several threats to product yield posed by the presence of excess electrical charge on a wafer. §§ R1-1 and R1-3 of this related information discuss two other important and potentially damaging consequences of surface charge. R1-2.1.1 The purpose of the discussion in this section is to estimate the magnitude of electrostatic field that can be tolerated before electrostatically enhanced particle deposition becomes the dominant particle deposition mechanism. Over the particle size range 0.01–0.3 µm, diffusion is the dominant, non-electrostatic mechanism of particle deposition. Thus, values of electrostatic fields that do not produce particle deposition velocities greater than those attributable to particle diffusion will be deemed tolerable. A set of such values calculated under a specific and very restrictive set of conditions are presented in this section. R1-2.2 Theoretical Background — Although there are numerous electrostatic interactions between particles and surfaces, the dominant one is almost always the “Coulombic” interaction: the attraction (or repulsion) of a charged particle by a charged surface. This is the only electrostatic effect considered here. For particles of one diameter, d, and one charge, q, the particle deposition flux, j, (the number of particles deposited per unit area per unit time) is the product of aerosol particle number concentration, c; particle charge, q; the electric field created by the charged wafer, E; and particle mechanical mobility, B (terminal velocity per unit external force):

j = cqEB (1) The group qEB is the “electrostatic deposition velocity”, velect

νelect = qEB = j / c (2) The variables q and E are those containing the electrical parameters that affect the magnitude of velect; B depends on particle diameter but not electrical properties. It is the velect values that will be calculated for comparison with those of vdiff , the particle deposition velocity attributable to particle diffusion. Values of E for which velect < vdiff will be those deemed tolerable in wafer manufacturing. Note that the total number of particles, N, deposited on a wafer, obtained by integrating Equation R1-1 over the wafer area, A, and the time of exposure, t, depends on c as well as the deposition velocity:

N = cqEBAt or N/A = ctν elect (3)




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Reducing c obviously reduces N, but the relative importance of the differing deposition mechanisms and the values of the deposition velocities associated with these mechanisms are assumed to not depend upon c, at least to a first order approximation (see, for example, Peters and Cooper, 1991). R1-2.2.1 Effect of the Particle Charge, q — There are many charging and discharging mechanisms for particles, so q is hard to predict and likely to be highly variable. In a normal atmosphere, the positive and negative air ions tend to have roughly equal effectiveness in charging particles, so that the number of positively charged particles is roughly equal to the number of negatively charged particles. Thus, about half the particles will be attracted and half repelled by a net charge on the wafer. Special circumstances, such as corona discharge ionizers that are not balanced, could alter this conclusion. Without ionizers, cleanrooms tend to have relatively low levels of ions compared to the outdoor or other indoor atmospheres, because the HEPA/ULPA filters efficiently remove ions from the recirculating air. R1-2.2.1.1 A Boltzmann charge equilibrium, the charge distribution approximated by aerosol particles exiting a radioactive neutralizer, is a plausible lower limit for particle charge and will be assumed in the calculations of velect, using an improved version of this distribution developed by Fuchs (1964). Upper limits on particle charge are determined by ion emission limits or, in the case of water droplets, the Rayleigh limit. However, assuming higher particle charge distributions usually means that velect > vdiff for virtually any value of E > 0 and that the only method for avoiding electrostatically enhanced particle deposition is to reduce wafer charge to zero. Thus, the Fuchs charge distribution will be assumed in calculating velect even though it represents the most favorable particle charge distribution for minimizing electrostatically enhanced particle deposition. Under many practical circumstances the particle charge will be greater and the maximum tolerable electrostatic field will be lower than that calculated for the Fuchs charge levels. R1-2.2.2 The Electrostatic Field, E, Induced by the Wafer Surface Charge — The electrostatic field will depend on the charge on the wafer divided by a quantity with the units of length squared; either a distance squared (far from the wafer) or an area (close to the wafer) or some combination at intermediate distances. While field is not properly measured as a voltage, measuring the voltage, V, at a fixed distance, s, from the wafer allows inferring the field from V/s and the appropriate geometric and dimensional factors. The electrostatic field to be used in Equation R1-2 can be estimated from the ratio of the wafer charge to the wafer surface area, or the average field near the surface at the center, E0.

R1-2.2.2.1 Very far from the wafer, many wafer diameters away, the field created by the net wafer charge, Q, will be similar to that from a point charge:

E1 = k1Q / r2 (4) where k1 depends on the system of units used; and r is the distance from the center of the wafer to the particle. R1-2.2.2.2 Very close to the wafer, a fraction of a wafer diameter away, the field created by the net wafer charge is:

E2 = k2Q′ / r2 (5) where Q' is the net wafer charge, assumed to be uniformly distributed, contained within the intersection of a sphere of radius, r, and centered on the point of the wafer closest to the particle. R1-2.2.2.3 This equation indicates that the charge distribution on the wafer can make a difference close to the wafer. For an insulating wafer with a uniform charge and a radius, R:

E2 = E0 = k2Q / πR2 (6) at a distance r = R from the center of the wafer. R1-2.2.2.4 For a conductive wafer, or for a wafer with localized regions of charge, the electric field will vary over the surface, causing greater and lesser deposition velocities. A conductive wafer will have the charge concentrated near the edges, producing a relatively high field there and much lower fields as the center is approached. R1-2.2.2.5 Note that both E1 and E2 are proportional to Q and therefore, other variables being equal, electrostatic deposition is expected to be proportional to Q. Thus, the criterion to be specified is not the tolerable charge on the wafer but the tolerable electrostatic field near the wafer surface (such as that evaluated at a distance of one radius perpendicular to the wafer surface above its center), E0. A maximum tolerable value of E0 will be estimated by calculating the maximum E0 values for which velect < vdiff, assuming a Fuchs distribution for the particle charge. R1-2.3 Tolerable Electrostatic Field R1-2.3.1 Particle Deposition Velocity Attributable to Convective Diffusion (vdiff) — In a microelectronics cleanroom, airflow is generally laminar (“unidirectional”) downward at about 50 cm/s (100 ft/min). If the flow is




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perpendicular to a surface, such as a wafer of diameter, Dw, a boundary layer forms across which particles diffuse to the surface. Liu and Ahn (1987) adapted the correlation of Sparrow and Geiger (1985) and obtained a correlation for the average diffusive deposition velocity as:

νdiff = 1.08 Sc1/3Re1/2D* / Dw (7) where Sc = μ/ρD* is the Schmidt Number, μ is the gas viscosity, ρ is the gas density, D* = kTB is the particle diffusivity, k is Boltzmann’s constant, T is the absolute temperature, B is the particle mobility, Re = ρUDw/μ is the Reynolds number, U is the gas velocity, and Dw is the wafer diameter . Bae, et al. (1994) reviewed the experimental work of others and presented their own, supporting this correlation; Cooper, et al. (1990) obtained a similar equation by a somewhat different method. Oh, et al. (1996) summarized prior experimental and theoretical work and extended the numerical analysis with a turbulent transport properties model, finding a small increase in deposition for the conditions modeled. These authors’ publications support the approximation that the diffusional deposition velocity is about 0.006 cm/s at particle diameter of 0.25 µm and about 0.03 cm/s at particle diameter of 0.01 µm, or:

νdiff = (0.03 cm/s) / (d / 0.01 μm)1/2 (8) for 0.01 µm ≤ d ≤ 0.3 µm in cleanroom air. R1-2.3.2 Particle Deposition Velocity (rate) Attributable to Electrostatic Forces (velect) — Using a power law to approximate the Fuchs particle charge distribution yields the following approximation for electrical mobility (Cooper, et al. 1990):

Z = qB = (0.002 cm/s) / (d / 0.01 μm) × (1 V/cm) (9) from which the deposition velocity attributable to electrostatic forces becomes:

νelect = (0.002 cm/s) × [E0 / (V/cm)] / (d / 0.01 μm) (10) Setting velect/vdiff = 1 results in the following expression for tolerable E0:

[(E0 / (V/cm)] = 15[d / (0.01 μm)]1/2 (11) Table R1-1 lists the values of tolerable electrostatic field adjacent to a wafer surface as calculated from Equation R1-11. Note that the electrostatic fields are calculated at a distance of one wafer radius from the center of the wafer. E0 is the value of electric field at which electrostatically enhanced particle deposition is estimated to match the particle deposition velocity attributable to diffusion, assuming a Fuchs charge distribution on the particles. This charge distribution represents a minimal particle charge. With most particle charge distributions to be encountered in practice, even lower values of electrostatic fields will produce enhanced deposition. A safe conclusion is that there is no safe value of electrostatic field that will avoid enhanced particle deposition unless neutralization of particle charge has been achieved, in which case the very modest values of electrostatic fields calculated from Equation R1-11 and tabulated in Table Rl-1 should be tolerable.




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Table R1-1 Tolerable Levels of Electrostatic Field at a Distance of One Radius from the Center of a Wafer, Assuming a Fuchs Charge Distribution on the Particles

Minimum Particle Diameter d,

µm

Tolerable Field E0,

V/cm 0.01 15 0.02 21 0.03 26 0.05 34 0.10 47 0.20 67 0.30 82

R1-2.4 Conclusions — As indicated in Table R1-1, the calculated value of tolerable electrostatic field (the value of electrostatic field above which electrostatic particle deposition becomes the dominant mechanism of particle deposition) is just 47 V/cm. This is for particles of 0.1 µm diameter when the particle electrical charge is that described by the Fuchs charge distribution, a minimum value of particle charge that is normally exceeded in most environments. In most realistic environments the particle charge will be greater and the tolerable electrostatic field, even lower. It may be that in all practical processing environments electrical forces will be the dominant mechanism of particle deposition on wafers. R1-2.4.1 In an ISO Class 3 environment, corresponding to the obsolete Federal Standard 209E Class 1 environment, (c ≤ 0.00124 particles/cm3) with velect, ~ 0.01 cm/s (the value predicted by Equation R1-10 for a 0.1 µm particle in an electric field of 47 V/cm) the target areal particle densities (N/A = 0.016 particles/cm2 for the 0.25 µm technology of 1998) specified in the National Technology Roadmap for Semiconductors (NTRS, 1994) will be reached after an exposure time of about 1300 s, assuming c is at its maximum allowed concentration. Using Equation R1-3 above, t = (N/A) / cvelect = (0.016) / (0.00124)(0.01) = 1290. R1-2.4.2 With less favorable electrical conditions, or higher particle concentration, the maximum allowed exposure time becomes shorter. In addition, the target values for N/A continue to decrease with each technology generation. Fortunately, one more of the parameters (i.e., particle concentration in the ambient), the charge level on a surface, or the time a charged surface is exposed to a given particle ambient, can be controlled. R1-2.4.3 Charge Neutralization — Achieving the Fuchs charge distribution by means of radioactive isotopes or balanced corona neutralizers is the first step in controlling particle deposition on wafers. This step, while clearly necessary, is unlikely to be sufficient to guarantee meeting the NTRS requirements of the future. Steps to minimize environmental particle concentration, c, and time of exposure, t, will have to be part of the strategy for creating acceptable processing environments. Minimizing these variables reduces particle deposition attributable to all mechanisms, not just electrostatic deposition. R1-2.4.4 Contemporary standards recognize the need for reduced particle concentrations in wafer environments. For example, the classification ISO Class 1 (of the international standard for classifying cleanrooms according to concentration of airborne particulate cleanliness) describes an environment in which the concentration of particles > 0.1 µm is 10-5 particles/cm3 or less. In an environment of this quality, wafer exposure can be as long as 105 s at the deposition velocity predicted for neutralized 0.1 µm particles (~0.01 cm/s) and still meet the target defect density that the NTRS recommends for the 0.1 µm technology anticipated in 2007. Fractional increases in the electric field above 47 V/cm will decrease the allowed exposure time by that same fraction (see Equations R1-10 and R1-12) — an electric field of 94 V/cm reduces the allowed exposure time to 5 × 104 s, etc. R1-2.5 References Bae, G.N., Lee, C. S., and Park, S. O., “Measurement of Particle Deposition Velocity Toward a Horizontal Semiconductor Wafer by Using a Wafer Surface Scanner”, Aerosol Science Technology 21: p. 72–82 (1994) Cooper, D. W., Miller, R. J., Wu, J. J., and Peters, M. H., “Deposition of Submicron Aerosol Particles During Integrated Circuit Manufacturing: Theory”, Particulate Science Technology 8 (3 and 4): p. 209–224 (1990) Fuchs, N. A., The Mechanics of Aerosols, Pergamon Press, Oxford (1964)




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Liu, B. Y. H., and Ahn, K. H., “Particle Deposition on Semiconductor Wafers”, Aerosol Science Technology 6: p. 215–224 (1987) National Technology Roadmap for Semiconductors, Semiconductor Industry Association, 4300 Stevens Creek Boulevard, Suite 271, San Jose, CA 95129, 1994 Oh, M. D., Yoo, K. H., and Myong, H. K., “Numerical Analysis of Particle Deposition onto Horizontal Freestanding Wafer Surfaces Heated or Cooled”, Aerosol Science Technology 25: p. 141–156 (1996) Peters, M. H., and Cooper, D. W., “Approximate Analytical Solutions for Particle Deposition in Viscous Stagnation-Point Flow in the Inertial-Diffusion Regime with External Forces”, J. Colloid Interface Science 142(1): p. 140–148 (1991) Sparrow, E. M. and Geiger, G. T., “Local and Average Heat Transfer Characteristics for a Disk Situated Perpendicular to a Uniform Plow”, J. Heat Transfer 127: p. 321–326 (1985) Federal Standard 209E (Obsolete) — Airborne Particulate Cleanliness Classes in Cleanrooms and Clean Zones ISO 14644 – Cleanrooms and Associated Controlled Environments – Part 1 – Classification of Air Cleanliness R1-2.6 Experimental References R1-2.6.1 Deposition of 0.1–1 µm Particles, Including Electrostatic Effects, onto Silicon Monitor Wafers (Experimental). William J. Fosnight, Vaughn P. Gross, Kenneth D. Murray, Richard D. Wang, IBM Corporation published in 1993 Microcontamination Conference proceedings R1-2.6.2 Summary: Submicron particle contamination continues to be a concern in the manufacture of integrated circuits. Quantifying particle deposition velocity (the ratio of particle deposition rate to airborne particle concentration) is of fundamental importance in understanding the defect-density impact of airborne contamination. R1-2.6.3 As particle size decreases, the effect of electrostatic charge plays an increasing role in the deposition of particles onto surfaces. This four-trial study examines the deposition of 0.1–1.0 µm particles onto horizontal, grounded and electrostatically charged, silicon monitor wafers in an 80 ft/min vertical unidirectional airflow. The experimental deposition rate results were compared to theoretical predictions found in the literature. R1-2.6.4 Three primary observations were obtained from this study. First, measured values of deposition rate agreed reasonably well with predicted values. However, deposition rate was not observed to increase below 0.2 µm. Secondly, particles less than 0.5 µm were observed to deposit onto charged wafers approximately three to ten times faster than onto grounded (not charged) wafers. Finally, settling monitor wafers may be a time consuming (and expensive) means of certifying the cleanliness of a “clean” (less than 10 particles per cubic foot at scanner threshold particle size) environment. However, settling-monitor studies should not be confused with particles-per-wafer-pass (PWP) measurements; PWP measurements often provide useful information regarding the performance of the automation and/or process of an equipment, even if it is in a very clean environment.

R1-3 ESD Impacts in Semiconductor Equipment Contributed by Julian A. Montoya, Intel Corporation, 5200 NE Elam Young Parkway, Hillsboro OR, 97124-6497. R1-3.1 Introduction — Electrostatic phenomena influence semiconductor manufacturing in many ways. These range from increased particle accumulation on wafer surfaces to electrostatic discharge (ESD) events that affect equipment performance, and in some cases impact factory yields and throughput. R1-3.1.1 All areas within a semiconductor manufacturing environment must be concerned with electrostatic control. This encompasses initial wafer receiving to shipping of final product. In addition, the equipment that will be housed within that environment must also be concerned with electrostatic control and electrostatic immunity. R1-3.1.2 This section highlights issues associated with static charge and ESD in a semiconductor manufacturing environment and its effects on production equipment. R1-3.2 Overview — Static charge issues in semiconductor manufacturing manifest themselves in many ways. Problems occur by direct contact with charged items, by induction from electrostatic fields, and indirectly by radiated and conducted electromagnetic interference (EMI) emitted into the environment from ESD events. R1-3.3 Equipment ESD Examples — The following section presents real world examples of the cause and impacts associated with electrostatic discharge and semiconductor manufacturing equipment. R1-3.3.1 Charged operators came into direct contact with diffusion furnace control panel. Process aborted on many occasions resulting in loss of product and reduced equipment utilization.




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R1-3.3.2 Numerous instances where charged reticles came into direct contact with a grounded object. This caused damage to reticles and affected factory throughput. Costs were associated with replacing damaged reticles and requalifying reticle sets. R1-3.3.3 Charged operators came into direct contact with electronic card cage of chemical vapor deposition equipment. This resulted in process abort, loss of product, and reduced equipment availability. R1-3.3.4 A charged wafer cassette induced charge onto the robot arm on a wafer transfer equipment. The robot arm contacted a grounded screw creating an ESD event. This resulted in data corruption that caused robot arms to open, dropping fully loaded wafer cassettes to the floor. Costs were associated with loss of product. R1-3.3.5 Automated material handling system “car” became charged while coming in close proximity to an ionizer. Car contacted a grounded object during charging; creating data corruption that resulted in system downtime, impact to factory throughput, and cost associated with the replacement of control electronics. R1-3.3.6 Wafer taping/detaping equipment generated charge during normal operation. Chassis ground of the equipment was inadvertently removed, causing high charge to be developed within the equipment. Electrostatic Discharge occurred at random time intervals within the equipment. This had an impact on equipment availability, and it took a long time to find the cause of the problem. R1-3.3.7 Wafers became charged during spin rinse process. During transfer to wafer metrology equipment electrostatic discharge occurred, causing data corruption. This resulted in unexpected equipment lockups, and reduced equipment availability. R1-3.3.8 Ungrounded wall panels became charged and generated ESD events. EMI produced from ESD events coupled into photolithography equipment and created data corruption. This resulted in impacts to equipment utilization. It took a long time to identify the cause of the problem. R1-3.3.9 Insulative ceiling panels became charged and generated ESD events that produced high levels of radiated and conducted EMI in a test area. EMI coupled into tester/handler and produced data scramble. This resulted in reduced equipment availability. R1-3.3.10 Finished product became charged during manual handling. Product came into direct contact with test/handler equipment. This resulted in damaged circuit cards that needed to be replaced and decreased equipment availability. R1-3.3.11 Wafer transfer cart became charged while rolling over temporary “insulative” floor. Cart then contacted a plasma etcher control cabinet. Resulting ESD event caused product loss and reduced equipment availability. R1-3.3.12 Wafer polisher robot arm became charged during normal operation because the chassis ground wire for robot was left off. ESD events occurred and caused data scramble that resulted in process being aborted. R1-3.4 Conclusion — Electrostatic Discharge (ESD) affects semiconductor manufacturing equipment in many ways. The issues are wide ranging from trivial lock-ups and aborts of process equipment to factory throughput and yields impacts. The scope of the ESD problem is very broad and encompasses every aspect of semiconductor manufacturing.




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RELATED INFORMATION 2 STATIC CONTROL METHODS NOTICE: This related information is not an official part of SEMI E78 and is not intended to modify or supercede the official standard. Determination of the suitability of the material is solely the responsibility of the user.

R2-1 Static Charge Control R2-1.1 It is usually impossible to totally eliminate static electricity from work areas, but with proper use of equipment and remedial procedures, most static problems can be controlled. Many approaches to controlling static charge have been tried over the years and it is clear that there exists no single method for controlling all static charge problems.

R2-2 Grounding Conductors and Static Dissipative Materials R2-2.1 An important consideration in selecting a method is whether the charged material is a conductor or an insulator. Static dissipative materials are created by lowering the resistivity of insulating materials through the addition of metal or carbon particles, or other chemical additives. R2-2.2 Static charge on a conductive or static dissipative object can be easily controlled if the object is provided with a path for the charge to flow to earth ground. While charge is mobile in a conductor (or in a static dissipative material), in insulators charge is not mobile, and earth grounding is not an effective means of eliminating the static charge. R2-2.3 Equipment manufacturers can use both conductive and static dissipative materials to reduce the presence of static charge. If there is a path for the charge to flow to earth ground, the static charge on equipment, and materials handled by the equipment, can be rapidly, and harmlessly, neutralized. Obviously, the success of earth grounding depends on maintaining the integrity of the ground path. This is sometimes a problem when high-speed, moving parts of equipment must be connected to earth ground. R2-2.4 Static dissipative materials will need to retain their dissipative properties over the range of temperature and humidity conditions they will encounter, and not change significantly over time. In cleanrooms they must also meet requirements for avoiding micro-particle production and outgassing. As long as the ground connection is maintained, these “passive” procedures offer reasonable protection to the equipment and product from sources of static charge. R2-2.5 Unfortunately, these methods do not provide complete protection from static-related problems. Even when earth grounding is an option, it is subject to human error. In applications where contamination is an issue, additives and carbon particles used in static-dissipative materials may become sources of contamination themselves. When earth grounding or the use of dissipative materials is either inappropriate or not cost effective, ionization can be used.

R2-3 Ionization R2-3.1 More often than not, the product itself uses insulating materials, making earth grounding unavailable as an option. While silicon is a semiconductor, its oxide coating transforms it into an insulator. Teflon is used in many chemical processes, and quartz in high temperature processes. Epoxy and ceramic packages are used for integrated circuits. R2-3.1.1 Insulators are easily charged, retain their charge for long periods of time, and are often close to the product. Dealing with static charge on insulators and isolated conductors will often require the use of some type of ionization. Ionizers are the most effective means of dealing with static charges on insulators and isolated conductors. R2-3.2 For purposes of static charge control, ions are molecules of the gases in air (e.g., nitrogen, oxygen, water vapor, carbon dioxide) that have lost or gained an electron. Ions are present in normal outside air, but are removed when air is subjected to filtration and air conditioning. R2-3.2.1 Ionization systems work by increasing the conductivity of the air with the ionized gas molecules. When ionized air comes in contact with a charged surface, the charged surface attracts ions of the opposite polarity. As a result, the static electricity that has built up on products, equipment and surfaces is neutralized. R2-3.3 The most common methods of producing air ions are radioisotopes and “corona discharge” resulting from the electric field created when high voltage is applied to a sharp point.




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R2-3.3.1 The radioisotope most commonly used to produce ionization is Polonium210, an alpha particle emitter. The alpha particle collides with the surrounding gas molecules, dislodging electrons, which results in pairs of positive and negative ions. R2-3.3.2 The corona discharge method produces a very high electric field that interacts with the electrons in the surrounding gas. The polarity of the ions depends on the polarity of the high voltage on the emitter point. Ions of opposite polarity to the charged surface are required. Either polarity of static charge may be created in the equipment or on the product. R2-3.4 Ionizers in equipment must deliver ionization over a wide range of humidity and temperature conditions. Back-end assembly and test areas often do not have the level of temperature and humidity control found in front-end wafer production. R2-3.5 Ionizers installed in the cramped spaces of production equipment will be close to the product, in areas surrounded by grounded metal parts. Ionizers should isolate the emitter points from both the product and adjacent grounded surfaces. Ionizers should produce sufficient ions to discharge static on surfaces and products moving at high speeds despite losses to ground. R2-3.6 Most ionizers require maintenance and periodic verification of their performance.

R2-4 Problem of Controlling Static Charge in Manufacturing Equipment R2-4.1 The interior of high speed production equipment presents a challenge to most static control methods. The cost of production space is high and requires that equipment occupying the space be compact and operate at as high a speed as practical. Product is moved through small spaces at high speed by a variety of robotic and other mechanisms. Triboelectric charging (charge generation due to friction or contact and separation of dissimilar materials) and contact with ground are almost unavoidable. R2-4.2 Grounding of equipment parts that contact the product presents added difficulties when the equipment parts are moving at high speeds. Dissipating charge from insulating surfaces and integrated circuit (IC) packages may be difficult if the charged surfaces are not accessible. Using ionizers in these confined spaces presents challenges.

R2-5 Measuring Electrostatic Discharge in Manufacturing Equipment R2-5.1 Due to nature of ESD Events, special instrumentation is required for accurate detection and measurement. There are both direct and indirect ways of measuring the current of the ESD Events. R2-5.2 Direct Discharge Current Measurement R2-5.2.1 Discharge current is measured with a current probe of sufficient performance. The output of the current probe would be connected to the input of a high-speed digital storage oscilloscope for observation of the waveform. This method is the most accurate one since it measures directly the very parameter of interest. R2-5.2.2 Since the rise time of the ESD Event may be as short as a fraction of a nanosecond, the bandwidth of the oscilloscope and the probe, as well as all the cables should be at the very least 1 GHz, and preferably higher. Sampling rate of the oscilloscope should be no less than 5 Gigasamples/s. R2-5.2.3 Using this method is often difficult since the impedance of the discharge path is unpredictable or there may be many possible discharge paths. This method may only be practical under laboratory conditions when the ESD Event is deliberately caused in a controlled environment. R2-5.3 Indirect Measurements of ESD Events R2-5.3.1 A less precise but far more practical method of measurement of ESD Events in equipments is measurement of the electromagnetic emission that always accompanies the ESD Event. R2-5.3.2 Measurements with a Broadband Antenna and A High-Speed Digital Storage Oscilloscope — For best signal-to-noise ratio and best accuracy, the antenna should be positioned as close as practical to the place of anticipated discharge. It is imperative for accuracy of measurements to have an antenna with sufficient bandwidth (at least from 30 MHz–2.5 GHz) and a flat frequency response. Without flat frequency response in the antenna, the captured waveform of the discharge would be inaccurate and of little relevance. R2-5.3.3 Quantitative data on ESD events can be acquired only when the parameters of the antenna and environment are properly characterized. Some method will be needed to calibrate the antenna response to an ESD event of a known magnitude.




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R2-5.4 Measurements with ESD Event Monitors R2-5.4.1 ESD Event Monitors include both an antenna and a means of measuring the magnitude of the signal produced by the ESD event. Unlike the oscilloscope, ESD Event Monitors do not provide information on the waveform of the discharge. However, ESD Event Monitors can provide already processed information about the magnitude of ESD events, eliminating the need for a high-speed oscilloscope. R2-5.4.2 ESD Event Monitors can be either stationary or hand-held. Hand-held models are helpful for ESD audits and troubleshooting, while stationary models can provide continuous readings when they are connected to a facility monitoring system or to any other data collection device, including the equipment itself. R2-5.4.3 Several monitors working together can help to localize the discharge. Methodology is available to reject extraneous discharges and identify only those ESD Events relevant to the specific process. Some of ESD Event monitors can be characterized for standard device discharge models such as CDM, MM or HBM. R2-5.5 Measurements with ESD Event Detectors R2-5.5.1 ESD Event Detectors, usually hand-held, identify the presence of ESD events and sometimes count of the number of events. Their main advantages are low cost and simplicity of use. They only need to be placed in the area where it is suspected that ESD events are occurring, and typically give visual and/or audible indications. Their main disadvantage is that there is no quantitative information available on the magnitude of the ESD event.

R2-6 Additional Information A more detailed discussion of static control methods and their verification may be found in SEMI E129 Related Information 2 – Static Control Methods.




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RELATED INFORMATION 3 EXAMPLE FOR ADDING ELECTROSTATIC COMPATIBILITY REQUIREMENTS TO PURCHASING DOCUMENTS FOR MANUFACTURING EQUIPMENT NOTICE: This related information is not an official part of SEMI E78 and is not intended to modify or supercede the official standard. Determination of the suitability of the material is solely the responsibility of the user.

R3-1 Purpose R3-1.1 Purchasing semiconductor manufacturing equipment that meets SEMI E78 Electrostatic Compatibility requirements can reduce the cost of ownership of the equipment by reducing operating problems and product defects, by eliminating costly equipment modifications after delivery, and by making the equipment available for use more quickly after delivery. R3-1.2 The purpose of this Related Information 3 is only to describe an example of specifications for electrostatic compatibility that are meant to form part of a general purchasing document for production equipment or minienvironments.

R3-2 Limitations R3-2.1 Related Information 3 is only one possible example of defining SEMI E78 compliance requirements for equipment. Users may include all or any part of it, modifying it as necessary in their purchase documents. Users are responsible for determining the appropriate level of static control protection depending on their specific circumstances.

R3-3 Terminology (Reference: ESD Association Glossary ADV1.0) R3-3.1 conductive material — electrostatic conductive materials have a surface resistance of <1 × 104 Ω or a surface resistivity of <1 × 105 Ω/square when tested according to ESD Association ANSI ESD STM11.11, or a volume resistance of <1 × 104 Ω or a volume resistivity of <1 × 104 Ω-cm when tested according to ESD Association ANSI ESD STM11.12. Other national or international (e.g., IEC) standards may be substituted. R3-3.2 static dissipative material — electrostatic dissipative materials have a surface resistance between 1 × 104 Ω and <1 × 1011 Ω or a surface resistivity of between 1 × 105 Ω/square and <1 × 1012 Ω/square when tested using ESD Association ANSI ESD STM11.11, or a volume resistance of between 1 × 104 Ω and <1 × 1011 Ω or volume resistivity between 1 × 104 Ω-cm and <1 × 1011 Ω-cm when tested using ESD Association ANSI ESD STM 11.12. Other national or international (e.g., IEC) standards may be substituted.

R3-4 General Static Control System Description R3-4.1 The static control system shall provide electrostatic charge and electric field control to meet the recommendations contained in SEMI E78. These recommendations are defined in ¶ 12.7 of Table 1. R3-4.2 The static control system shall consist of the following items, applied as needed to assure compliance. R3-4.2.1 Grounding of conductive equipment parts when feasible. R3-4.2.2 Static dissipative materials to replace insulators when feasible. R3-4.2.3 Ionization sources to control static charge on process essential insulators or isolated conductors, particularly when they are part of the product (e.g., oxide-coated silicon, epoxy-packaged devices, reticles).

R3-5 General Static Control System Design Requirements R3-5.1 Grounding R3-5.1.1 Conductive equipment parts shall maintain a resistance to chassis ground or to electrical ground of less than 1 ohm. (Reference – ESD Association standards ANSI ESD S6.1 Grounding — Recommended Practice and ANSI ESD SP10.1 Automated Handling Equipment. Other national or international (e.g., IEC) standards may be substituted). R3-5.1.2 In critical applications, as determined by the user, constant monitoring of equipment grounding shall be required. In some cases, local electrical safety regulations may prohibit the use of this method. A suitable test method to capture short interruptions of ground connections may need to be used.




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R3-5.1.3 Resistance measurements for moving equipment parts shall be made with the equipment in operation. NOTE 1: Grounding methods to prevent the generation and accumulation of static charge are not necessarily sufficient for conduction at high frequencies, or to provide electrical safety. R3-5.2 Static Dissipative Materials R3-5.2.1 Insulators shall be replaced with grounded static dissipative materials when feasible. R3-5.3 Ionizers R3-5.3.1 Charge on insulators or isolated conductors in the product handling path, product, or reticles (if used by the equipment to produce product) shall be controlled with ionizers. R3-5.3.2 Ionizer performance shall be measured using ESD Association standard ANSI ESD STM3.1 Ionization. Other national or international [e.g., IEC] standards may be used. R3-5.4 Cleanroom Compatibility R3-5.4.1 If equipment or materials are to be installed in a cleanroom, all static control system components shall demonstrate compatibility with cleanroom class requirements. NOTE 2: The user may need to define cleanroom compatibility requirements for static control materials here (e.g., particle shedding, outgassing, chemical compatibility), if such requirements are not defined elsewhere in the purchasing document. (Reference ESD TR55.0-01-01 − Electrostatic Guidelines and Considerations for Cleanrooms and Clean Manufacturing)

R3-6 Compliance Testing R3-6.1 Compliance testing shall be done by: a) a capable independent third party, or b) the equipment manufacturer, or c) the end user

to demonstrate that the equipment meets the recommendations contained in SEMI E78. R3-6.2 Acceptance testing of the static control system performance shall be performed at the actual equipment use location.

R3-7 Referenced Standards (The following ESD Association Standards and Advisories9 are referenced above. There may be other equivalent national or international standards covering these areas.) ESD ADV1.0 — Glossary of Terms ANSI ESD STM3.1 — Ionization ANSI ESD S6.1 — Grounding – Recommended Practice ANSI ESD SP10.1 — Automated Handling Equipment ANSI ESD STM11.11 — Surface Resistance Measurement of Static Dissipative Planar Materials ANSI ESD STM11.12 — Volume Resistance Measurement of Static Dissipative Planar Materials ESD TR55.0-01-01 — Electrostatic Guidelines and Considerations for Cleanrooms and Clean Manufacturing

9 Electrostatic Discharge Association, 7900 Turin Road, Building 3, Suite 2, Rome, NY 13440-2069, USA. Telephone: 315.339.6937; Fax: 315.339.6793, Website: www.esda.org




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RELATED INFORMATION 4 FIELD INDUCED DAMAGE MECHANISMS IN RETICLES NOTICE: This related information is not an official part of SEMI E78 and is not intended to modify or supercede the official standard. Determination of the suitability of the material is solely the responsibility of the user.

R4-1 Background R4-1.1 It has been thought that ESD damage to reticles occurs mainly through charge transferring onto the reticle through contact with a charged handling equipment, then jumping from the chrome border into the pattern area, causing sparks that damage the reticle features. However, this would not happen without an electric field passing through the reticle to drive the motion of the charge. An isolated reticle in free space would not have a strong enough electric field passing through the reticle structure to force charge to jump from the chrome border into the pattern area – almost all the excess charge would reside at the outer edges of the chrome border. R4-1.2 If excess charge is placed on a reticle, either through contact with a charged handling equipment or by tribocharging, the charge creates a field that terminates at ground. The field strength within the charged reticle and the field configuration field strength around it depend on the proximity to nearby conductive surfaces. Hence, moving a charged reticle near to grounded objects can cause variations in the field configuration and field strength passing through the reticle. R4-1.3 The same is true of moving a neutral reticle through the electric field from another charged object. The field strength within the reticle may become high enough to cause ESD events. This happens not because the charge state of the reticle has altered, but because the field has forced mobile charge in the conductive chrome film to move from one place to another. R4-1.4 In all the above examples of reticle damage, the common controlling factor is the electric field that is passing through the reticle, not the charge state of the reticle or its absolute voltage. Charging a reticle to a high voltage in the absence of a hazardous field configuration would not damage the reticle. However, an electric field can damage a reticle that remains electrically neutral and physically isolated from the source of the field, such as when inside a reticle pod. Hence, to protect reticles from damage it is most important to control the electric field strength and configuration around the reticle. Simply concentrating attention on static charge or voltage is not enough. R4-1.5 Electrostatic Shielding — It may be correct to assume that shielding is not present when defining recommended maximum field levels, but it should be noted that shielding will allow a reticle to be carried in higher strength fields without sustaining damage. Only fully conductive enclosures (e.g., metal multi-reticle cassettes or metal boxes) can effectively provide shielding from electric fields. Static dissipative reticle pods may exhibit lower surface charge than insulating ones, but they should not be relied upon to shield the reticle from externally generated electric fields.

R4-2 Field Simulations R4-2.1 When an electric field passes through a reticle, isolated conductive features in the reticle are raised to different potentials. The potential differences induced across the gaps between the chrome traces determine whether charge will move between the features, either as a spark or as a surface “leakage current”. These induced potential differences will vary, depending upon whether any part of the reticle is constrained to be at ground potential or not. R4-2.2 Electrostatic simulation shows what happens if a reticle is grounded in a SMIF pod with a voltage present on the pod handle. Figure R4-1 shows the potential contours between features when the rightmost feature (equivalent to the chrome border on the reticle) is held at ground potential. Figure R4-2 shows the same features in the same field configuration but the rightmost feature is allowed to “float” electrically.




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Figure R4-1 Voltage Contours With Grounded Electrode at Right at 100-V Potential Difference

Figure R4-2 Voltage Contours with Floating Electrode at Right at 30 V Potential Difference

R4-2.3 It is seen that the potential difference induced between the reticle features is lower if the chrome border is not grounded. Thus, a reticle will be less likely to suffer field-induced damage from an external electric field if it is not grounded during handling and storage. This has been demonstrated experimentally. 4,5

R4-3 Field-Induced Reticle Damage R4-3.1 When a reticle is exposed to an electric field as illustrated in Figures R4-1 and R4-2 the features on the reticle come to different potentials. The electrons in the metal lines are forced to move by the electric field. If the potential difference induced between adjacent features is large enough, charge can cross the gap between the features and cause damage. When the field is removed, the charge will return to its original location. Thus, one instance of exposing a reticle to a field causes damage to the reticle twice. R4-3.2 Studies of field interactions with special test reticles have revealed that different types of damage are caused with different induced voltages between the chrome lines. ESD damage (sparking) occurs when there is a high induced voltage between the features (about 150 V across a 1 µm gap1). With induced voltages below this level, two other types of damage are observed. R4-3.3 At low induced voltage (estimated to be below 5 V with a 1 µm gap), the edges of the lines spread outwards onto the quartz, altering reticle CD. With higher induced voltages conductive tracks are seen to form across the quartz surface between chrome lines. These two slightly different damage mechanisms have been attributed to electric field-induced migration (EFM) of chrome on the quartz surface. Although this explanation has not been verified by conducting surface chemical analysis of the reticle defects to confirm that they contain chrome, the characteristics of the physical damage seen on reticles can be fully explained by these proposed mechanisms. 2, 3 R4-3.4 Recent experimentation has shown that a reticle surface conducts a small current whenever a voltage exists between adjacent conductive features. The current/voltage plot has a nonlinear component that is proportional to V2, indicating that this is not simply ohmic conduction through a weakly conductive surface film such as adsorbed water molecules or other contaminants. This surface conduction takes place at all applied voltages, starting at least two orders of magnitude below that which would cause electronic field emission. Wallash and Levit showed that the current/voltage characteristic takes on the Fowler-Nordheim characteristics of electronic field emission when >120V is applied across a 1µm reticle gap.1 The surface current flowing below this voltage results in a swelling and outward spreading of the positively biased chrome line on the quartz surface (Fig.R4.3).




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ORIGINAL PROFILE

AFTER STRESS

1µm

120nm

Figure R4-3

AFM surface profile line scans of a 1µm reticle gap stressed at 100V for four minutes. No ESD took place. The positive line has swollen and the gap has been reduced by >10%.

R4-3.5 This experiment reproduces the characteristics of EFM type 2 induced in test reticles at Sematech. Hence, while the onset of EFM type 1 has not been observed directly, the previous estimates for the induced voltages required to produce EFM type 1 and 2 seem to have been reasonable. 2 R4-3.6 ESD is a transient event that will occur if the induced voltage rises high enough within the reticle. If the field is not sufficiently strong or if the field sensitivity of the reticle is not high enough to create high potential differences in the reticle, ESD may not take place. However, that does not mean that the reticle is safe. Any electrical stress applied to a reticle will produce a reaction; it has been demonstrated that the reaction below the ESD threshold will be for a surface current to flow which can result in line edge degradation. Thus, low level electric field exposure below the safety threshold for ESD events should not be considered safe for a reticle. No onset threshold was observed for surface conduction, hence any strength of electric field has the potential to be hazardous to a reticle, even one that may be considered insensitive to ESD.

R4-4 Effect Of Reticle Structure R4-4.1 When an electric field interacts with a reticle, every piece of conductive material within the field influences the reaction. The structure of the pattern in the reticle therefore affects the induced potentials. Different types of reticle, such as gate level, metallization level, or via level, will have different sensitivities to electric fields. As feature size and spacing vary with each device generation, this also affects the sensitivity to electric fields. This is illustrated in Figure R4-4, which shows how the voltage and average field strength across the gap between two metal lines on a reticle in a constant electric field alters as the gap between them is reduced. R4-4.2 Figure R4-4 shows that as the spacing between features on reticles is decreased, the voltage induced between them falls but the electric field strength in the gap increases. Thus, there will be a tendency in future reticle generations for induced voltages to fall below the threshold for ESD, but the field strength across the gaps will become larger, so field-strength dependent damage like EFM will become prevalent. In addition, the introduction of sub-resolution “scattering bars” to a reticle reduces the gap between conductive features still further, making such reticles particularly sensitive to EFM.




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Figure R4-4 Induced Gap Voltage and Field Strength as a Function of Spacing Between Two

Reticle Features in an Electric Field

R4-5 Consequences R4-5.1 Reticles exposed to electric fields will increasingly become prone to continuous degradation through EFM rather than suffering occasional discrete ESD damage events. The damage caused is cumulative and is capable of gradually degrading reticle CD at certain locations, potentially reducing the lifetime of the reticle in production. R4-5.2 EFM requires much lower levels of electric field interaction with a reticle than ESD. Fabs with reasonable ESD countermeaures in place to prevent reticle ESD problems may begin to experience EFM problems with future reticle generations. Regular review of reticle handling practices can ensure that these newly identified risks will not have a major impact on yield in future.

R4-6 References 1. “Electrical breakdown and ESD phenomena for devices with nanometer-to-micron gaps”, A. Wallash and L. Levit, Proc SPIE Vol. 4980, 2003, pp. 87–96 2. “EFM – a pernicious new electric field induced damage mechanism in reticles”, G. Rider, Semiconductor Manufacturing, Nov 2003 3. “Estimation of the field induced damage thresholds in reticles”, G. Rider, Semiconductor Manufacturing, Feb 2004 4. “Induced ESD Damage on Reticles: A Reticle Evaluation”, Rudack, Pendley, Gagnon and Levit, EOS/ESD

Symposium, Las Vegas, September 2003. 5. “Reticle Carrier Material As ESD Protection”, Helmholz D, Lering M; SPIE BACUS Sept 2006

R4-7 Acknowledgement Contributed by Gavin Rider, Microtome Precision, Inc., 3390B Fillmore Ridge Heights, Colorado Springs, CO 80907. [email protected]




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REVISION RECORD CHANGES IN THIS DOCUMENT FROM E78-1102 NOTICE: The Revision Record is an official part of the standard. It is optional and placed at the end of the standard. Negative votes may not be based on the Revision Record.

Cycle Ballot Section Description Committee Approval

2005-3 3825 § 5, Terminology

Terms Used in the Previous Version of this Document Which Have Been Superceded. sensitivity level 1 — Product, reticles, and equipment are extremely vulnerable to damage and/or problems from static charge. sensitivity level 2 — Product, reticles, and equipment are highly vulnerable to damage and/or problems from static charge. sensitivity level 3 — Product, reticles, and equipment have nominal vulnerability to damage and/or problems from static charge. sensitivity level 4 — Product, reticles, and equipment have negligible vulnerability to damage and/or problems from static charge.

2005-3 3825 ¶ 12.5 Recommendations Table 1 from ¶ 12.5 has been changed. Both old and new versions are shown below. New version has been harmonized with recommendations of both E129 and the 2004 ITRS. Obsolete Recommendations Table 1. Note that Sensitivity Level 1 in this table corresponds to the recommendations for 2004 in the new table 1 shown Table 1 Recommended Sensitivity Levels (Obsolete)

Electrostatic Discharge

(Nanocoulombs)

Particle Attraction (Volts/cm)

Equipment Malfunction

(Nanocoulombs)

Level 4 100 4000 1200 Level 3 50 400 600 Level 2 10 200 300 Level 1 1 100 150

Table 1 Recommended Equipment Electrostatic Levels (new)

Year Node

Electrostatic Discharge,nC

Electrostatic Field, V/cm V/inch

2000 180 nm

2.5–10 200 500

2002 130 nm

2.0 150 375

2003 100 nm

1.5 125 300

2004 90 nm

1.0 100 250

2007 65 nm

0.5 70 175

2009 50 nm

0.25 50 125

2013 32 nm

0.125 35 88

2015 25 nm

0.1 25 63




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Cycle Ballot Section Description Committee Approval

2005-3 3825 ¶ 6.7, Appendix A1-2.8, and Related Information R1-3.

As shown in ¶ 12.5 above, and previously noted in ¶ 6.7, separate recommendations for preventing equipment malfunctions are no longer provided. The justification for these recommendations was contained in E78-1102 Appendix A1-2.3. In this document, comments regarding equipment ESD immunity are contained in ¶ 6.7, Appendix A1-2.8, and Related Information R1-3.

2005-3 3825 ¶ RI2 - Static Control Methods.

Added Section R2-5, Measuring Electrostatic Discharge in Manufacturing Equipment, to Related Information 2 – Static Control Methods.

2005-3 3825 Related Information 4

Added Related Information 4 – Field Induced Damage Mechanism in Reticles.

2006-7 4240 § 4.4, ¶ 12.5, Appendix 1

Updated § 4.4 Other Documents. Revised ¶ 12.5 and Table 1. Revised the following in Appendix 1; ¶ A1-2.1.3, ¶ A1-2-4.1.3, Table A1-4, ¶A1-2.5.1.2, NOTE 4, ¶ A1-2.5.2, ¶ A1-2.5.3.1, added ¶ A1-2.5.3.2, Table A1-5, ¶ A1-2.6.5, Table A1-6, and § A1-3 References.

2007-x 4418 § 1, § 2, ¶ 5.3, § 9, § 12, ¶ 12.7, Appendix 1

Revised § 1 Purpose and § 2 Scope. ¶ 5.3 Acronyms added. Revised § 9 Test Specimen. Revised §12, ¶ 12.7 and Table 1. In Appendix 1: Added ¶ A1-2.4.1.4, ¶ A1-2.4.1.5, ¶ A1-2.4.1.6. Revised Table A1-4. Deleted unneeded information in ¶ A1-2.5 Revised Table A1-5 and Table A1-6.

NOTICE: SEMI makes no warranties or representations as to the suitability of the standard(s) set forth herein for any particular application. The determination of the suitability of the standard(s) is solely the responsibility of the user. Users are cautioned to refer to manufacturer’s instructions, product labels, product data sheets, and other relevant literature respecting any materials or equipment mentioned herein. These standards are subject to change without notice. By publication of this standard, Semiconductor Equipment and Materials International (SEMI) takes no position respecting the validity of any patent rights or copyrights asserted in connection with any item mentioned in this standard. Users of this standard are expressly advised that determination of any such patent rights or copyrights, and the risk of infringement of such rights are entirely their own responsibility.