bachelor thesis: analysis and design of a 900mhz doherty power amplifier

”Analysis and design of a 900 MHzDoherty Power Amplifier”

by

Nam Tran Pham

in Partial Fulfillment of the Requirements for the Degree

of

Bachelor of Engineering

at the Konstanz University of Applied Sciences

Faculty of Electrical and Information Technology

August 14, 2011

Thesis Supervisors:

Prof. Dr. Christoph Schick

Abstract

In the late 1930s Radio became the dominant mass media in industrial nationsand with it there was a demand for higher power levels in broadcasting. Atthat time most of the RF power amplifiers had very low efficiency, which in-creased the expense for operating a broadcast station in power consumptionand cooling system. In September 1936 William H. Doherty introduced a newmethod to increase the efficiency of power amplifiers, this technique was ableto increase the efficiency up to nearly 80%, later it was widely used in medium-and high-power RF amplifiers.Nearly 60 years later energy-efficiency becomes more and more important,especially in new wireless transmitters such as cellular telephones, in whichbattery life is one of the key features of the device, the Doherty power ampli-fier architecture has become the ”amplifier of choice”.There have been many improvements since the first publication of the Do-herty amplifier; this thesis, however, only introduces the basic ideal of Dohertyarchitecture. The basic functionality will be discussed and finally a Dohertyamplifier is implemented at 900 MHz, both in simulation and hardware.

i

Acknowledgements

I wish to express my sincere gratitude and appreciation to my advisor, Prof.Dr. Christoph Schick, for introducing me to this challenging and interestingtopic. I have significantly benefited from his broad range of expertise.I would also like to thank to my committee members for all of the time theyspent to review my thesis and their helpful comments. Special thanks to Prof.Edmund Zahringer for his advices on working with transistor at high frequency.My gratefulness is directed to all the technical engineers at faculty of Electricaland Information Technology, HTWG Konstanz and to all my friends, whosupported me during the research for this thesis.Finally, I am grateful and indebted to the continuous love, understanding andsupporting from my family. Love you all.

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Declaration

I declare that this thesis was composed by myself, that the work containedherein is my own except where explicitly stated otherwise in the text, andthat this work has not been submitted for any other degree or professionalqualification except as specified.

Konstanz, August 14, 2011Nam Tran Pham

iii

Contents

Table of contents iv

List of figures vi

List of tables ix

Abbreviation x

1. Introduction 11.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2. Thesis organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2. Doherty Amplifier Architecture 32.1. Power Amplifier Classes . . . . . . . . . . . . . . . . . . . . . . . . . 32.2. Doherty Load Modulation . . . . . . . . . . . . . . . . . . . . . . . . 52.3. Analysis of the Doherty Amplifier Architecture . . . . . . . . . . . . 8

2.3.1. Classical Doherty Amplifier . . . . . . . . . . . . . . . . . . . 82.3.2. Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . 102.3.3. Peak-Power Operation . . . . . . . . . . . . . . . . . . . . . . 112.3.4. Medium-Power Operation . . . . . . . . . . . . . . . . . . . . 122.3.5. Summary of Operation . . . . . . . . . . . . . . . . . . . . . . 13

3. Design with analytic method 153.1. Design Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.2. Input and output design . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.1. Input design . . . . . . . . . . . . . . . . . . . . . . . . . . . 193.2.2. Output design . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.3. Carry Amplifier design . . . . . . . . . . . . . . . . . . . . . . . . . . 253.4. Peak Amplifier design . . . . . . . . . . . . . . . . . . . . . . . . . . 263.5. Design review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4. Design with Load-Pull technique 314.1. Quality factor Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314.2. Power Amplifier design with Load-Pull Technique . . . . . . . . . . . 334.3. Design parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344.4. Amplifier design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.4.1. Carry amplifier V4 . . . . . . . . . . . . . . . . . . . . . . . . 364.4.2. Carry amplifier V5, Peak amplifier V4 and Doherty amplifier 40

4.5. Performance review . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444.5.1. DC current behavior . . . . . . . . . . . . . . . . . . . . . . . 444.5.2. Carry amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . 444.5.3. Peak amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . 46

iv

Contents

4.5.4. Doherty amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 48

5. Conclusions and Recommendations 525.1. Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525.2. Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

A. Load pull simulation results 54

B. Schematics and layouts 59

C. Data sheet 65

Bibliography 69

v

List of Figures

2.1. Ideal class B amplifier circuit . . . . . . . . . . . . . . . . . . . . . . 32.2. Conduction angles for a class A, B or C amplifier . . . . . . . . . . . 42.3. Collector current and voltage with power dissipation . . . . . . . . . 52.4. Transistor amplifier in common emitter circuit . . . . . . . . . . . . 62.5. Active load-pull concept . . . . . . . . . . . . . . . . . . . . . . . . . 72.6. Doherty amplifier architecture . . . . . . . . . . . . . . . . . . . . . . 72.7. Output voltage and current of classical Doherty amplifier[6] . . . . . 82.8. Efficiency of classical Doherty amplifier[6] . . . . . . . . . . . . . . . 92.9. Comparision of real Doherty amplifier with class A and AB amplifier[20] 102.10. Doherty amplifier architecture . . . . . . . . . . . . . . . . . . . . . . 102.11. Ideal efficiency of Doherty amplifier vs. output power[5] . . . . . . . 14

3.1. Simplified transistor circuit . . . . . . . . . . . . . . . . . . . . . . . 153.2. Collector current and voltage of class B transistor . . . . . . . . . . . 163.3. Peak value of collector voltage at 50mW output . . . . . . . . . . . . 173.4. Fundamental and peak value of collector current at 50mW output . 173.5. Collector voltage at 25mW output . . . . . . . . . . . . . . . . . . . 183.6. Current through load and collector at 25mW output . . . . . . . . . 183.7. Doherty amplifier architecture . . . . . . . . . . . . . . . . . . . . . . 193.8. Hybrid divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203.9. Wilkinson coupler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.10. Input circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.11. Return loss and Insertion loss of the input circuit . . . . . . . . . . . 223.12. Phase delay and isolation of the input circuit . . . . . . . . . . . . . 223.13. Output circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233.14. Phase of output signal . . . . . . . . . . . . . . . . . . . . . . . . . . 243.15. Insertion loss and Isolation from P1 and P2 . . . . . . . . . . . . . . 243.16. Collector current of AT42086 with Vcc = 2.7V . . . . . . . . . . . . 253.17. Carry-Amplifier circuit simulation . . . . . . . . . . . . . . . . . . . 263.18. Peak-Amplifier simulation circuit . . . . . . . . . . . . . . . . . . . . 263.19. Doherty Amplifier Simulation . . . . . . . . . . . . . . . . . . . . . . 273.20. Collector efficiency of the simulation circuit . . . . . . . . . . . . . . 273.21. Carry- and Peak-Transistor at transition point Pin = 3dBm . . . . . 283.22. Carry- and Peak-Transistor at max input power Pin = 6dBm . . . . 283.23. Summary of collector current and voltage in simulation (line - carry,

dashed - peak), peak value of the fundamental frequency . . . . . . . 293.24. Waveform of collector current at the Carry- and Peak-Transistor . . 293.25. PAE and Gain of Doherty amplifier . . . . . . . . . . . . . . . . . . . 293.26. Output power, PAE, Gain versus input power [10] . . . . . . . . . . 30

4.1. Capacitor and inductor model at radio-frequency . . . . . . . . . . . 31

vi

List of Figures

4.2. Insertion loss of capacitor [Murata-Data sheet] . . . . . . . . . . . . 324.3. Measurement the 220nF capacitor . . . . . . . . . . . . . . . . . . . 324.4. Block diagram of a load-pull system[19] . . . . . . . . . . . . . . . . 334.5. Results of load-pull technique . . . . . . . . . . . . . . . . . . . . . . 344.6. Measurement results from test device Carry-V4B, measurement 1 . . 354.7. Measurement results from test device Carry-V4B, measurement 2 . . 354.8. Schematic of input matching for carry V4 . . . . . . . . . . . . . . . 374.9. Comparison between software simulation and hardware measurement

of the carry input matching network V4 , Simulation-Line, Hardware-Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.10. Layout and S-Parameter simulation result of the carry input matchingnetwork V4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.11. Schematic of the output matching network for carry amplifier V4D . 384.12. Layout and S-Parameter simulation of the carry output matching net-

work V4D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394.13. Stability factor of the carry amplifier V4 . . . . . . . . . . . . . . . . 394.14. Schematic of the input network for the carry amplifier V5 . . . . . . 404.15. Layout and S-Parameter simulation results of the input network for

the carry amplifier V5 . . . . . . . . . . . . . . . . . . . . . . . . . . 414.16. Schematic of the output network for the carry amplifier V5 . . . . . 414.17. Layout and S-Parameter simulation results of the output network for

the carry amplifier V5 . . . . . . . . . . . . . . . . . . . . . . . . . . 424.18. Schematic of the input network for the peak amplifier V4 . . . . . . 424.19. Layout and S-Parameter simulation results of the input network for

the peak amplifier V4 . . . . . . . . . . . . . . . . . . . . . . . . . . 424.20. Schematic of the output network for the peak amplifier V4 . . . . . 434.21. Layout and S-Parameter simulation results of the output network for

the peak amplifier V4 . . . . . . . . . . . . . . . . . . . . . . . . . . 434.22. Collector current versus base voltage of AT42086, with 2.7V Vcc supply 444.23. Measurement setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444.24. Measurement results from test device Carry-V4B . . . . . . . . . . . 454.25. Measurement results from test device Carry-V5A with 5V supply volt-

age . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454.26. Measurement results from test device Carry-V5A with different sup-

ply voltages, Pin = 3dBm . . . . . . . . . . . . . . . . . . . . . . . . 454.27. Measurement results from test device Carry-V5A with different sup-

ply voltages, Pin = 6dBm . . . . . . . . . . . . . . . . . . . . . . . . 464.28. Measurement results from test device Peak-V4 with different bias volt-

ages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474.29. Measurement results of Doherty amplifier V1B . . . . . . . . . . . . 494.30. Measurement results of Doherty amplifier V1B . . . . . . . . . . . . 494.31. Measurement results of Doherty amplifier V2B . . . . . . . . . . . . 504.32. Measurement results of Doherty amplifier V2B . . . . . . . . . . . . 504.33. Measurement results of Doherty amplifier V2B . . . . . . . . . . . . 51

A.1. Load pull contour with 0.7V bias and 2.7 V supply . . . . . . . . . . 54A.2. Source and Load impedance with 0.7V bias and 2.7V supply . . . . 54A.3. Load pull contour with 0.3V bias and 2.7V supply . . . . . . . . . . 55A.4. Source and Load impedance with 0.3V bias and 2.7V supply . . . . 55

vii

List of Figures

A.5. Load pull contour with 0.7V bias and 5V supply . . . . . . . . . . . 56A.6. Source and Load impedance with 0.7V bias and 5V supply . . . . . 56A.7. Load pull contour with 0.3V bias and 5V supply . . . . . . . . . . . 57A.8. Source and Load impedance with 0.3V bias and 5V supply . . . . . 57A.9. Load pull contour with 0.5V bias and 5V supply . . . . . . . . . . . 58A.10.Source and Load impedance with 0.5V bias and 5V supply . . . . . 58

B.1. Carry amplifier schematic with 0.7V bias and 2.7V supply, V4B . . . 60B.2. Carry amplifier schematic with 0.7V bias and 2.7V supply, V4D . . . 61B.3. Carry amplifier schematic with 0.7V bias and 5V supply, V5A . . . . 62B.4. Peak amplifier schematic with 0.5V bias and 5V supply, V4 . . . . . 63B.5. Layout of the Doherty amplifier V1B . . . . . . . . . . . . . . . . . . 64B.6. Layout of the Doherty amplifier V2B . . . . . . . . . . . . . . . . . . 64

viii

List of Tables

2.1. Summary of class A, AB, B and C amplifier . . . . . . . . . . . . . . 5

4.1. Summary of source and load impedance for design . . . . . . . . . . 36

ix

Abbreviation

ADS . . . . . . . . . . . . . . . . . . . . . . Advanced Design SystemBJT . . . . . . . . . . . . . . . . . . . . . . Bipolar Junction TransistorCAD . . . . . . . . . . . . . . . . . . . . . Computer Aided DesignCAE . . . . . . . . . . . . . . . . . . . . . Computer-Aided EngineeringCDMA . . . . . . . . . . . . . . . . . . . Code Division Multiple AccessDUT . . . . . . . . . . . . . . . . . . . . . Device Under TestESR . . . . . . . . . . . . . . . . . . . . . . Equivalent Series ResistanceFET . . . . . . . . . . . . . . . . . . . . . . Field Effect TransistorHBT . . . . . . . . . . . . . . . . . . . . . Heterojunction Bipolar TransistorHTN . . . . . . . . . . . . . . . . . . . . . Harmonic Termination NetworkLSSP . . . . . . . . . . . . . . . . . . . . . Large-Signal S-ParameterPA . . . . . . . . . . . . . . . . . . . . . . . Power AmplifierPAE . . . . . . . . . . . . . . . . . . . . . . Power Added EfficiencyPCB . . . . . . . . . . . . . . . . . . . . . Printed Circuit BoardPEP . . . . . . . . . . . . . . . . . . . . . . Peak Envelope PowerPSK . . . . . . . . . . . . . . . . . . . . . . Phase Shift KeyQAM . . . . . . . . . . . . . . . . . . . . . Quadrature Amplitude ModulationRF . . . . . . . . . . . . . . . . . . . . . . . Radio FrequencyRFC . . . . . . . . . . . . . . . . . . . . . Radio Frequency Choke

x

1. Introduction

1.1. Introduction

For the last decade the phenomenal growth of wireless communications has maderemarkable impacts on the modern life. It began with the radio in the late 1930s andnowadays billions of people use mobile cellular phones everyday with the massivecoverage around the world, which requires a signal with higher power level as wellas high dynamic range. In order to communicate with the base station and amongeach other, every mobile device needs a RF power amplifier, which is a circuit forconverting DC supply power into a significant amount of RF output power. In caseof cellular telephone, the DC supply comes from the battery and the time it takes todischarge the battery while on call is an important metric to the success of a phone.Hence, there is an increasing demand for highly efficient RF power amplifier to meetthe growing need for power saving, compact and low cost solutions. RF power am-plifier with high efficiency is able to extend the battery life and produce less heat,which means smaller heat sinks, this allows the cellular phone to have smaller size.Likewise for cellular base stations, high efficiency power amplifier is the key to saveoperation supply power, lower the cooling system cost and reduce thermal stress onactive devices.The instantaneous efficiency for the most power amplifiers is at its highest at itspeak envelope power and decreases as output power decreases. In modern digitalcommunication for maximum spectrum efficiency the modulation techniques likePhase Shift Key (PSK) or Quadrature Amplitude Modulation (QAM) are used inmodulated signals such as W-CDMA. This results in a very large peak to averageratios of between 6 dB and 13 dB in the output power of signal [3], it means thepower amplifier are often operated in low efficiency area. There are many methodsto increase the efficiency of power amplifier for large range of output power like theKahn Envelope Elimination and Restoration method [16] or the Chireix-outphasingtransmitter [8], but they require a complicated circuitry. The Doherty amplifier isthe best candidate, as a relatively simple efficiency enhancement technique.The first goal in this thesis is to analyze the functionality and performance of theclassical Doherty amplifier architecture. The second one is to design, manufactureand evaluate a classical Doherty amplifier, which is capable of deliver 20 dBm max-imum output power at 900 MHz.

1

CHAPTER 1. INTRODUCTION

1.2. Thesis organization

The thesis is organized as follows:

• Chapter 1 is a short introduction on the topic of power amplifier and the needfor high efficiency amplifier. The main objects of this thesis are given at theend of the chapter.

• Chapter 2 starts with a brief review of the classes of power amplifiers and theirmaximum available efficiencies. This is followed by the principle of Doherty’ssolution to increase the efficiency of the power amplifier. At the end is thereview of the ideal Doherty power amplifier. This chapter provides the supporttheory for the power amplifier design process.

• Chapter 3 explains in detail the design and implementation of a Doherty poweramplifier using the analytic method or load-line technique. A discussion onthe advantages and disadvantages of this design is given at the end of thechapter.

• Chapter 4 discusses the new approach on design of a Doherty amplifier withload-pull technique. The problem with the implementation from simulationinto hardware using the lumped component is explained at the begin of thechapter. This is followed by the introduction of the load-pull technique, afterthat the detail of using of using load-pull technique in designing Doherty am-plifier is given. At the end a short review of the performance and measurementresults is provided.

• Finally the conclusions of this thesis and recommendations for further workare given in Chapter 5.

2

2. Doherty Amplifier Architecture

2.1. Power Amplifier Classes

Before going to the functionality of Doherty architecture, a short review of class A,B and C power amplifiers and the collector efficiency of a PA1 is in order.The class of a PA is defined by its conduction angle, which is defined as the portionof each RF2 sine wave the transistor is ”on”.The simplified circuit in Figure 2.1 shows an example for PA class B: the input drivecurrent I is assumed to be sinusoidal, the collector current maintains a sinusoidalshape when the transistor is ”on” and conducts no current when it is ”off”, all theharmonic currents are assumed to be shorted to ground by the ideal parallel resonantcircuit at VCC . The resulting current I1 is sinusoidal and creates a sinusoidal voltagewaveform as it terminates in the load resistance RL. The class B amplifier is definedas having a conduction angle of γ = π, which means that the transistor conductsfor half of the RF cycle. The bias voltage VPC is configured for class B operation sothat the base-emitter junction remains forward biased for half of the RF cycle.

Class A amplifier has a conduction angle of γ = 2π, it requires the bias voltage

Figure 2.1.: Ideal class B amplifier circuit

VPC to be sufficiently high to maintain forward base current throughout the RFcycle. Class C operation is defined as having any conduction angle less than π andamplifiers with conduction angle between π and 2π are referred to as class AB.Figure 2.2 shows resulting collector current IC with different amplifier class.

Collector efficiency η is defined as the ratio of the to load delivered RF power tothe consumed DC power from collector voltage supply, as show in (2.1), where If1

1Power Amplifier2Radio Frequency

3

CHAPTER 2. DOHERTY AMPLIFIER ARCHITECTURE

Figure 2.2.: Conduction angles for a class A, B or C amplifier

is the magnitude of the fundamental component of the collector current waveform:

η =Pout

PDC,coll=

(If1/√

2)2RLIDC,collVcc

=I2f1RL

2IDC,collVcc(2.1)

A class B amplifier example is used to demonstrate the calculation of efficiency,because of its ease of analysis and its application in Doherty architecture. Figure 2.3displays the collector waveform current and voltage of a class B transistor (assumingall harmonic currents are terminated that the voltage at the load is a sinusoidalwave), the drawn line shows the transistor in saturation mode3, the dashed lineshows the transistor out of saturation mode. The efficiency is directly related to theDC power dissipated in the transistor. Since the collector current IC is zero for halfthe conduction cycle, the instantaneous power dissipation in the transistor happensonly during the lower half cycle of the voltage swing, where the product of IC andVC is non-zero. This area is shown in Figure 2.3 as a hashed area under the curve,and as the voltage swing is reduced, the ”area under the curve” goes up, thereforethe efficiency of transistor is reduced.

The current waveform of a class B transistor is a half sine wave, its DC andfundamental values If1 from the Fourier Series are:

IDC =IPeakπ

(2.2)

If1 =IPeak

2(2.3)

Substituting these into (2.1) gives

η =If1IPeakRL

4· π

IPeakVcc(2.4)

η =π

4

VLVcc

(2.5)

3Saturation: The condition, in which the minimum value of voltage swing at the collectorequals the minimum voltage of P-N junction or in ideal condition 0V

4


Figure 2.3.: Collector current and voltage with power dissipation

which VL = If1 · RL is a magnitude of voltage swing at the load.At saturation,VL = Vcc and η = π/4 = 78.5%, therefore the maxinum efficiency of class B transistoris 78.5%.Table 2.1 shows the summary of different transistor classes versus conduction anglesand ideal collector efficiencies.

Amplifier class Conduction angle Ideal collector efficiencyClass A γ = 2π 50%

Class AB π < γ < 2π 50% to 78.5%Class B γ = π 78.5%Class C γ < π 78.5% to 100%

Table 2.1.: Summary of class A, AB, B and C amplifier

2.2. Doherty Load Modulation

Figure 2.4 displays a transistor in common emitter circuit, the LC resonator atcollector terminates all DC and harmonic frequency. UL is denoted as magnitude ofvoltage swing at the load and when the transistor is in saturation-mode UL reachesits maximum value. The basic idea of the load modulation is: an amplifier capableof delivering P1 to load R1 at its saturation UL = UL,max (high efficiency), if theload R1 can be reduced to R2 with R2 = α · R1(0 < α < 1), where α is a ratiobetween R1 and R2, and the amplifier still remains in saturation mode, then the

5


Figure 2.4.: Transistor amplifier in common emitter circuit

amplifier can deliver more output power at the same UL,max and consequently thesame efficiency. This can be derived as follow:

P1 =U2L,max

2

1

R1(2.6)

P2 =U2L,max

2

1

R2=P1

α> P1 (2.7)

To achieve this condition Doherty introduced the second current source into thecircuit of amplifier, where current from the second transistor (or tube) is used tomodify the load seen by the first device. This technique is called the ”active load-pull” concept[14], which is shown in Figure 2.5. Assume that I1 and I2 combinein-phase at RL, the relation between the impedances R1, R2 and currents I1, I2 isshown as follows:

R1 = RLI1 + I2I1

(2.8)

R2 = RLI1 + I2I2

(2.9)

By using this effect, the current from one transistor can be used to manipulate theload resistance seen by the other. But the active load-pull concept illustrated inFigure 2.5 moves the load impedance seen by Q1 in the wrong way, as the currentI2 increases so increases the impedance R1. So Doherty used an impedance inverternetwork at the output of the first transistor to reverse the active load-pull effect,this provides a reducing of R1 as I2 increases. If this reducing R1 is coupled with arising RF drive to Q1, the saturation mode at Q1 is still assured, consequently theefficiency remains at maximum.The impedance inverter in Figure 2.6 is realized by using a quarter wavelength line

with characteristic impedance of ZINV , the governing equation for the impedanceinverters is:

R1 ·R1,T = Z2INV (2.10)

6


Figure 2.5.: Active load-pull concept

Figure 2.6.: Doherty amplifier architecture

P1 is denoted as the output power delivered from Transistor T1 into the transmis-sion line and P1,T is the power out of the transmission line. Assuming a losslesstransmission line, the current I1 at transistor’s side can be calculated as:

P1 = P1,T (2.11)

I21,eff ·R1 =V 2L,eff

R1,T(2.12)

I21,eff ·R1 ·R1,T = V 2L,eff (2.13)

Using (2.10)

⇒ I1,eff =VL,effIINV

(2.14)

and the current I1,T at load’s side is:

I21,T,eff ·R1,T =V 21,eff

R1(2.15)

I21,T,eff ·R1,T ·R1 = V 21,eff (2.16)

⇒ I1,T,eff =V1,effZINV

(2.17)

7


Note from (2.14) and (2.17) that the voltage on one side of the inverter is proportionalto the current on the other side, but voltages are not directly related. This propertyallows V1 to remain fixed at saturation while VL is varied.The impedance inverter at the output of transistor T1 introduces a 90o phase lag inthe output current from T1, therefore the RF input of T2 must also be delayed by 90o

for I2 and I1,T to combine in phase. This can be achieved with a second impedanceinverter at the input of transistor T2, in Figure 2.6 a second quarter wavelengthtransmission line is used.

2.3. Analysis of the Doherty AmplifierArchitecture

2.3.1. Classical Doherty Amplifier

Doherty chose both transistors to deliver half the power to the load at full outputpower:

PT1,maxPL,max

=PT2,maxPL,max

=1

2(2.18)

this establishes a relation between R1,T , R2 and RL at full power as follows:

V 2L,max

R1,T,max=V 2L,max

R2,max=

1

2

V 2L,max

RL(2.19)

R1,T,max = R2,max = 2 ·RL (2.20)

The characteristic impedance of the impedance inverter is also chosen to be 2 timesthe load impedance

ZINV = 2 ·RL (2.21)

These decisions result a region of high efficiency from full power to 6dB below fullpower. Doherty summarized the voltage and current relationships for the two de-vices in Figure 2.7 and the efficiency of the amplifier in Figure 2.8.In the following paragraph, the term ”tube” is used, because at the time, when Do-

Figure 2.7.: Output voltage and current of classical Doherty amplifier[6]

herty first introduced this technique, most of the power amplifier were vacuum tube

8


Figure 2.8.: Efficiency of classical Doherty amplifier[6]

amplifier. Figure 2.9 shows the comparison of collector efficiency between classicalDoherty amplifier and class A, B amplifiers [20]. Noted that the comparison is madewith real components and a research [9] has confirmed the second ”peak” in effi-ciency at the transition point, the Doherty’s curve of efficiency in Figure 2.8 doesn’tshow the second ”peak” at −6 dB under full power, therefore not fully satisfyingthe relationship of voltage and current in Figure 2.7. Note that tube 1 maintainsconstant RF plate voltage after transition point, which is defined as the point wheretube 2 begins to conduct current. Both RF current curves are linear functions, butsince the tube 2 turns on much later than tube 1 and ends up at the same value,the collector current’s slopes are different. This is one of the main problem duringthe design of Doherty Amplifier, Doherty solved this problem by using a class Camplifier, which turns later on and has higher slope than the class B amplifier.The ratio α between R1 and R2 in Section 2.2 also designates the operation of the

Doherty amplifier,which can be divided into 3 main areas, the next sub-sections arededicated to review the working progress of Doherty amplifier in these areas:

• Low-Power area: 0 < VL < αVcc

• Medium-Power area: αVcc < VL < Vcc

• Peak-Power area: VL = Vcc.

From this point on all the given AC values are peak values of the fundamentalfrequency and transistor T1 is referred as Carry-Transistor, transistor T2 as Peak-Transistor.

9


Figure 2.9.: Comparision of real Doherty amplifier with class A and ABamplifier[20]

2.3.2. Low-Power Operation


At low input power levels, the Peak-Transistor is ”off” (I2 = 0) and Carry-Transistoroperates as a linear current source, the impedance R1,T according to (2.8) is

R1,T = RL (2.22)

Using (2.10) gives the impedance R1 seen by the Carry-Transistor

R1(I2 = 0) =ZINV 2

R1,T=

(2RL)2

RL= 4RL (2.23)

Assuming that the quarter wavelength transmission line is lossless, the voltage trans-

10


formation produced by the coupler is given by

V 2L

2 ·R1,T=

V 21

2 ·R1(2.24)

V 21

V 2L

=R1

R1,T(2.25)

V1VL

=

√R1

R1,T= 2 =

1

α(2.26)

The Carry-Transistor enters the saturation mode when V1 = Vcc, therefore the satu-ration of Carry-Transistor occours at VL = α ·Vcc. The RF-Output current deliveredby the Carry-Transistor is derived as follows

I1V12

=I1,TVL

2for I1,T = IL (2.27)

I1I1,T

=VLV1

= α (2.28)

I1 = I1,T · α =VL · αR1,T

(2.29)

For an ideal B class transistor and relationships from (2.2) and (2.3) the DC-currentis calculated as

Idc =2

π

α · VLR1,T

(2.30)

hence, the efficiency of the amplifier is:

η =PACPDC

=

V 2L

2·R1,T

2πα·VLR1,T

· Vcc(2.31)

η =π

4α

VLVcc

(2.32)

When the Carry-Transistor reaches saturation and the Peak-Transistor remains cut-off VL = α · Vcc, the resultant efficiency is η = π/4 = 78.53%. This is the firstpeak of collector efficiency at −6 dB under maximum output power or −3 dB undermaximum input power as shown in Figure 2.9.

2.3.3. Peak-Power Operation

In this area sufficient input power is provided to allow the Peak-Transistor to becomesaturated, collector voltages of the Carry-Transistor and the Peak-Transistor bothswing from 0 < VCE < 2Vcc. According to (2.18) the currents from the Carry- andthe Peak-Transistor are equal I1 = I2 = α · IL. Using the relation from (2.8) and(2.9) the impedances R1,T and R2 are given as follows

R1,T = R2 = 2 ·RL (see Figure 2.10) (2.33)

Since the characteristic impedance of the impedance inverter ZINV = 2·RL, no trans-formation will occur, therefore the load impedance seen by the Carry-Transistor is

11


also R1 = R1,T = 2·RL. Normally reducing load impedance tends to reduce the mag-nitude of voltage oscillation, but in this case with the rising input power the Carry-Transistor is able to deliver more output current, allowing the Carry-Transistor toremain saturated during the load modulation process. The Peak-Transistor has thesame supply voltage Vcc like the Carry-Transistor, sees the same load impedanceat collector and delivers the same amount of output current, resulting the Peak-Transistor is also saturated and has the maximum efficiency. This is the secondpeak of efficiency at full output and input power. The DC-Current from both tran-sistor is given

Idc = Idc,1 + Idc,2 =2

π

VLRL

(2.34)

The resultant efficiency

η =

V 2L

2·RL

2πVLRL

=π

4(2.35)

is the same as the first peak efficiency in an ideal class B transistor.The collector voltage of the Carry-Transistor is saturated, the same at the first peakefficiency, while the load impedance seen at the collector node is reduced to a half,as the result the output power of Carry-Transistor at second peak efficiency is twotimes its output power at the first peak efficiency. This accomplishes the goal ofusing load modulation, described at the beginning of section 2.2. The Carry- andthe Peak-Transistor now deliver two times more output power than the maximumoutput power of the Carry-Transistor in low power region, hence, the sum of outputpower at peak power region is four times more than at low power, this explainsthe 6 dB distance between two ”peaks” of the collector efficiency versus the outputpower as mentioned in Section 2.3.1. And because the Peak-Transistor has themaximum efficiency of a B class amplifier, it appears that the biasing point of thePeak-Transistor is shifted from class C to class B, as shown in Figure 3.24(b) thePeak-Transistor at maximum output power has the same conduct angle γ = π likethe Carry-Transistor in Figure 3.24(a).

2.3.4. Medium-Power Operation

At medium power levels, the Carry-Transistor is kept at verge of saturation and thePeak-Transistor operates as a linear current source. As displayed in Figure 2.7 thecurrent I1,T is constant in the medium-power area, in spite of the rising current ofI1, this can be proven by using the relation from (2.17)

I1,T =V1

ZINV=

VccZINV

=α · VccRL

(2.36)

From (2.36), the RF current from Peak-Transistor to produce an output voltage VLis

I2 = IL − I1,T =VL − α · Vcc

RL(2.37)

Using (2.14), (2.17) and (2.36) the output current I1 of the Carry-Transistor is

I1 =VL · I1,TV1

=α · VLRL

for V1 = Vcc(saturated) (2.38)

12


For an ideal class B transistor, the total DC-input current is:

IDC =2

π

(1 + α)VL − α · VccRL

(2.39)

2.3.5. Summary of Operation

In the low-power region, the input power is insufficient to overcome the Peak-Transistor bias, hence the Peak-Transistor remains cut-off. The Carry-Transistorsees a constant load transformed by the quarter wavelength and operates as a nor-mal class-B amplifier. The efficiency of the system in this region is given

ηlow =π

4

VLα · Vcc

for 0 < VL < α · Vcc (2.40)

As the input power increases over the transition point, defined by VL = α · Vcc,the Carry-Transistor saturates and the Peak-Transistor begins to become active.The load R1 seen by Carry-Transistor is reduced by the additional current I2, theCarry-Transistor remains in saturation and acts as a voltage source, since the outputvoltage V1 saturates, it operates at peak efficiency but delivers an increasing amountof power. The efficiency in medium-power region is composited of collector efficiencyfrom Carry- and Peak-Transistor, depending on which side is contributing morepower at each point. Because the Peak-Transistor doesn’t have the benefit of load-modulation like Carry-Transistor, its efficiency is like a normal class-B amplifier

ηmid =π

4

VL/Vccα(1− Vcc/VL) + 1

for αVcc < VL < Vcc (2.41)

At PEP4 output, both transistors see 2RL loads and deliver half of system outputpower. The efficiency is the same as class B amplifier.

ηpeak =π

4for VL = Vcc (2.42)

Figure 2.11 shows the comparison of efficiency between Doherty amplifier withdifferent α values and class-B Amplifier. The value of α = 0.25 is a modern approachwith Doherty amplifier, called extended Doherty amplifier, where the first peakefficiency is −12 dB below full power, therefore the region of high efficiency is larger.But the ”dip” in efficiency with α = 0.25 is also deeper, because the efficiency ofthe Peak-Transistor in area near transition point is quite low. There are severalresearches ( [10],[21],[8],...) to reduce the ”dip” in efficiency with α = 0.25.

4Peak Envelope Power

13


Figure 2.11.: Ideal efficiency of Doherty amplifier vs. output power[5]

14

3. Design with analytic method

3.1. Design Parameters

Figure 3.1.: Simplified transistor circuit

Figure 3.1 shows a simplified common collector circuit for transistor with an RFC1

at the supply voltage. Figure 3.2 shows the resulting collector current and collectorvoltage of a class B transistor, the harmonic frequency is shorted to ground by anLC resonant circuit.The requirement in this thesis is to design a Doherty amplifier with BJTs2 capable ofdelivering a power of 20 dBm or 100 mW at full output power.The design is based onthe classical Doherty (section 2.3.1), therefore at peak output power each transistordelivers half of the output power 17 dBm or 50 mW. From (2.6) the amplitude ofthe voltage swing at the collector node as a function of output power Pf1 and loadimpedance seen by collector RL is:

VL =√

2 · Pf1 ·RL (3.1)

which is shown in Figure 3.3 for an output power P = 50 mW, also the fundamentalfrequency If1 is calculated as

If1 =VLRL

(3.2)

1Radio Frequency Choke2Bipolar Junction Transistor

15

CHAPTER 3. DESIGN WITH ANALYTIC METHOD

Figure 3.2.: Collector current and voltage of class B transistor

using (2.3) the peak value Ipeak of collector current is

Ipeak = 2 · If1 (3.3)

The load impedance is chosen to be 50Ω, because the resulting voltage and collectorcurrent are in the limit range of the AT42086 BJT, and the 50Ω load impedance atfull output power allows the design of Carry- and Peak-Transistor to be directly andindividually tested with a spectrum analyzer without using any impedance converternetwork. Because at saturation the collector voltage is not zero, the saturationvoltage for BJT normaly ranges from 0.3V to 0.5V , therefore the supply voltage is

Vcc = VL + VCE,sat ≈ 2.3 + 0.4 ≈ 2.7V (3.4)

the value of VL is acquired from Figure 3.3 for an 50 Ω impedance, also Figure 3.4displays the peak values of the fundamental and maximal currents at the collectornode for 50 mW output power. As for the low-power region, where Carry-Transistordelivers half of the output power compared to its output at full output power andPeak-Transistor remains cut-off, the output power is Pout,low = 25 mW, the Carry-Transistor sees a load impedance two times larger than in the peak-power regionR1,low = 100Ω (section 2.3.2). The resulting collector current and voltage is shownin Figures 3.5, 3.6.

16


Figure 3.3.: Peak value of collector voltage at 50mW output

Figure 3.4.: Fundamental and peak value of collector current at 50mW output

17


Figure 3.5.: Collector voltage at 25mW output

Figure 3.6.: Current through load and collector at 25mW output

18


The concept circuit of Doherty amplifier in Figure 2.6 is repeated in Figure 3.7 forconvenience.Summary of design parameters:


• Supply voltage: Vcc = 2.7V

• At full output power: R1 = R2 = 50Ω.

• As derived in section 2.3.3, the load impedance RL = 25Ω.

• The characteristic impedance of the impedance inverter ZINV = 50Ω.

• At low-power region: R1,low = 100Ω.

The bipolar-transistor AT-42086 from Avago-Technologies is used in the prototypedesign, because its high output power at high frequency (20dBm at 2GHz - Datasheet) and its available simulator model for CAE3 program. Agilent’s AdvancedDesign System(ADS) is used to simulate and to refine the prototype design. TheFR4 substrate with 1 mm thickness, 35µm copper thickness, double side and ε = 4.3was used.

3.2. Input and output design

3.2.1. Input design

Requirements for designing the input circuit are:

3Computer-aided engineering

19


• The input power is to be equally divided between Carry- and Peak-Transistor.

• The output ports should be isolated from the other to prevent cross-talk.

• The output at port 3 is 90o phase lag compared to port 2.

Figure 3.8.: Hybrid divider

Normally a hybrid-divider (Figure 3.8) can be used to fulfill these requirements,but a hybrid-divider requires a large physical space and is not flexible with respectto layout design. In this thesis the input is designed using the combination of aWilkinson-divider and a microstrip line at the output of the Wilkinson-divider tocreate the phase-offset between the two output-ports of the input circuit, because theoutput signals of Wilkinson-coupler are in-phase. The benefit of using a microstripline for phase-delay is, the length of the microstrip line can be simply adjusted tohave different phase-offset other than 90o without any chance in power divide ratiobetween two transistors, because two transistor with different biasing are expectedto have different phase-delay and regarding the influences of matching circuit at baseand collector node of the transistors on phase-offset. The prototype is designed towork in a 50Ω-enviroment, so the ports P1, P2, P3 of the Wilkinson-coupler will seea Z0 = 50Ω impedance. The characteristic impedance of each ”arm” of the coupleris

Zarm =√

2 · Z0 ≈ 70.71Ω (3.5)

and the coupler resistor between two ”arms” is

Zcoupler = 2 · Z0 = 100Ω (3.6)

The Wilkison-coupler is designed using microstrip line for convenient PCB4 imple-mentation, and at 900MHz the quarter wavelength is short enough for small PCB

4Printed Circuit Board

20


Figure 3.9.: Wilkinson coupler

layout. Using the mircostrip line calculation tool from ADS the parameters of theWilkinson-coupler’s ”arm” are

Width ≈ 1mm

Length ≈ 47.8mm

A 50Ω quarter wavelength transmission line is used to insert the 90o phase lagbetween the output P2 and P3 while maintaining the matching condition for allports. The design of the input circuit is shown in Figure 3.10 There are differences

Figure 3.10.: Input circuit

of the insertion loss between ports P2 and P3 as shown in Figure 3.11(b) due to the

21


(a) Return loss (b) Insertion loss

Figure 3.11.: Return loss and Insertion loss of the input circuit

(a) Phase delay (b) Isolation between outputs

Figure 3.12.: Phase delay and isolation of the input circuit

different length of transmission lines and this also causes degradation in return loss(Figure 3.11(a)), but the difference is negligible. Figure 3.12 displays the resultingphase-offset between the two output ports of the input circuit. The 90o phase-lagbetween port P2 and P3 is temporary, because the phase delay of the Carry- andPeak-Transistor with different biasing is expected to be different, the length of thetransmission line can be later adjusted for the optimal phase delay, which requiredfor the outputs of the Carry- and Peak-Transistor to combine in-phase later. Thereis also a research on uneven power divider [12], in which the Peak-Transistor receivesmore input power than the Carry-Transistor to achieve the same output power. Thiscan be useful, if the both transistor are the same type and it is difficult for the Peak-Transistor to have the same maximal output current like the Carry-Transistor.

22


3.2.2. Output design

As mentioned in the summary of the design paramters (section 3.1) the load impedanceis RL = 25Ω, for the convenience of directly using a spectrum analyzer for measure-ment the output signal later, an impedance converter transformation is used to con-vert the 50Ω terminal impedance of the spectrum analyzer to 25Ω load impedance.The impedance converter is a quarter wavelength mircostrip line, its characteristicimpedance is:

Zoutput =√RL ·Rterminal =

√25 · 50 ≈ 35.35Ω (3.7)

Hence, the physical parameters of the mircostrip line at 900MHz are:

Width = 3.27mm

Length = 45.12mm

The output circuit (Figure 3.13) consists of two parts:

• A 35Ω quarter wavelength microstrip line to transform the 50Ω terminal loadto the 25Ω-load.

• A 50Ω quarter wavelength microstrip line acting as an impedance inverterbetween the output of the Carry-Transistor and the 25Ω load.

Figure 3.13.: Output circuit

The disadvantage of this design is, there is lack of isolation between Port P1 andPort P2 (Figure 3.15(b)), this may cause undesired ”talk over” between P1 and P2.There is also difference in insertion loss from P1 to P3 and from P2 to P3 becauseof the different length of transmission line. Figure 3.14 shows the 90o phase-offsetbetween the signal from P1 to P3 and the signal from P2 to P3.

23


Figure 3.14.: Phase of output signal

(a) Insertion loss (b) Isolation between input P1 and P2

Figure 3.15.: Insertion loss and Isolation from P1 and P2

24


3.3. Carry Amplifier design

Before the design of Carry amplifier begins, a simulation is made to determine thecharacteristic of the transistor AT42086. This information is used to design the biasnetwork for the Carry-transistor. As mention in section 2.3.1 the Carry-transistorneeds to be biased in class B mode, therefore from figure 3.16 the bias voltage toset to UBias,B = 0.7V. To improve the stability behavior of the transistor, a voltage

Figure 3.16.: Collector current of AT42086 with Vcc = 2.7V

feed-back circuit is deployed between the collector and the base node of the Carry-transistor, this will act as a controlled feed-back path between the collector andbase node and the coupling resistance will suppress the unwanted influence fromthe collector node to the base node . The value of impedance in feed-back circuit isselected based on simulation experiment with the stability factor calculation functionfrom ADS, goals are to achieve unconditionally stable and to maintain high-gain at900 MHz.The schematic of the Carry-Amplifier is shown in Figure 3.17,at the base node amatching network is used for matching purpose. This matching network is designedby using the LSSP5 function from ADS. A 50Ω quarter wavelength at the collectoroutput terminates the harmonic frequencies to ground. The components in thesimulation of the carry amplifier shown in Figure 3.17 are ideal components, withinfinite quality factor. From simulation result the carry amplifier has 14 dB gainat 900 MHz, therefore the output reaches the transition point 14 dBm with 0 dBminput power.

5Large Signal S-Parameter simulation

25


Figure 3.17.: Carry-Amplifier circuit simulation

3.4. Peak Amplifier design

The design of Peak-amplifier is highly dependent on the operating point of the Carry-amplifier, in this case the bias voltage of the Peak-amplifier must be low enough sothat at the transition point, 14 dBm output power, the Peak-transistor is in cut-offmode, but still high enough for the peak-transistor to achieve the same output powerlike the carry-transistor at max output power. Because at 900 MHz the AT-42086is almost at its limit in the gain factor, and as discussed in section 2.3.1 the slopeof the collector current from the peak-transistor is higher than the one from thecarry-transistor, therefore a stabilization circuit for the Peak-transistor is removedas a trade-off for power gain. This decision can be accepted at this point, becausethe Peak-Transistor is biased very low, only conducts for short time. The input

Figure 3.18.: Peak-Amplifier simulation circuit

matching for Peak-Amplifier is based on LSSP-Simulation, and used to improve thepower gain. The bias voltage of the Peak-Transistor is set to be 0.3V

26


3.5. Design review

Figure 3.19 shows the final stage of the Doherty amplifier in simulation. The simula-tion circuits of Carry- and Peak-Amplifier are combined with the input and outputcircuit. Figure 3.20 shows the resulting collector efficiency of the simulation circuit.

Figure 3.19.: Doherty Amplifier Simulation

As expected the first maximum efficiency is reached at Pin = 3 dBm or Pout = 14dBm and the second maximum by Pin = 6 dBm or Pout = 20 dBm. The maximumefficiency is only about 50%, lower than the expected efficiency of 78.52% in Section2.3, because of the saturated voltage VCE the collector voltage does not swing from0 to 2Vcc and due to the mis-matched at output of the transistor the output powercan not fully delivery to load.Although the first maximum drifts to near Pout = 15 dBm in Figure 3.20(b), this

can be explained by the performance of Carry- and Peak-Transistor at transitionpoint Pin = 3 dBm in Figure 3.21. At Pin = 3 dBm the Carry-Transistor is almostat its saturation and the voltage at load is relatively high as well as the collectorvoltage of Peak-Transistor, because of Miller-effect[17] between the collector nodeand the base not, the base voltage of Peak-Transistor is shifted higher and the Peak-Transistor begins to conduct sooner than expected.

(a) (b)

Figure 3.20.: Collector efficiency of the simulation circuit

27


(a) Carry-Transistor (b) Peak-Transistor

Figure 3.21.: Carry- and Peak-Transistor at transition point Pin = 3dBm


Figure 3.22.: Carry- and Peak-Transistor at max input power Pin = 6dBm

At Pin = 6 dBm both transistors are in saturation as expected (Figure 3.22) andthe output power is Pout = 20 dBm, the amplifier reaches its maximum efficiency.Figure 3.23 shows the summary performance of voltage and current in Carry- and

Peak-Transistor dependent on Pin. There is a dip in collector voltage of the Carry-Transistor due to the non-linear slope of Peak-Transistor’s collector voltage. At highinput power level the bias of Peak-Transistor is shifted from class C to class B, thisexplains the waveform of collector current in Figure 3.24(b), therefore the maximumefficiency of Doherty amplifier is equal the maximum efficiency of class B amplifieras predicted in Section 2.3.3.Figure3.25(b) illustrates the gain factor of the Doherty amplifier in simulation, the

gain factor has a non-linear progress in comparison with the result from [10], whichdisplays in Figure 3.26, this result is caused because of the small collector current ofthe transistor, the collector current at its maximum value according to Figure 3.16,is still in the non-linear area. In order to improve the linearity the collector currentmust be large enough to overcome the non-linear area, in this case it is not recom-mended from the data sheet, because the maximum limit collector current of theAT42086 transistor is only 80 mA. The research in [22] is dedicated to improving thelinearity of the Doherty Amplifier using Heterojunction Bipolar Transistor(HBT),which is a improvement of BJT for high frequency and high power application.

28


(a) Collector voltage (b) Collector current

Figure 3.23.: Summary of collector current and voltage in simulation (line -carry, dashed - peak), peak value of the fundamental frequency


Figure 3.24.: Waveform of collector current at the Carry- and Peak-Transistor

(a) PAE (b) Gain

Figure 3.25.: PAE and Gain of Doherty amplifier

29


Figure 3.26.: Output power, PAE, Gain versus input power [10]

The design in this section is quite easy to understand and straightforward, but thisalso has some disadvantages:

• Using the S-Paramter simulation is not particularly useful for designing highpower amplifier.

• The performance of the design depends heavily on the accuracy of each discretecomponents.

• Realization with discrete components and microstrip lines can be a majorchallenge, because of the physical form of the components.

• The mircostrip lines between the discrete components are not taken in toaccount in the simulation, and may cause undesired effects on the performance.

• The calculation of load impedance only concerns the resistive impedance, whileat high frequency the imagine part of load impedance also has great influenton performance of the transistor.

• The HF-bypass capacitors have a value of 100 pF and at 900 MHz it is quitedifficult to acquire a capacitor, which has this capacitance. The typical limitvalue for capacitor at this frequency is 10 pF.

• The quarter wavelength microstrip line filter at collector output can only fil-ter the even harmonic frequency and its effect reduces with the increasingfrequency because of the inaccuracy of circuit fabrication.

30

4. Design with Load-Pulltechnique

4.1. Quality factor Q

Quality factor is defined as the ratio of the stored energy and the average dissipatedpower multiplied by the frequency.

Q = ω0 ·EstoredEloss

(4.1)

Noted ω0 is the resonant frequency of a resonant circuit.Regarding a parallel config-uration with a resistor, a capacitor and an inductor in parallel, the equation for theQ is shown

Qp =R√L/C

=R

ω0L= ω0RC (4.2)

and the Q factor for the configuration of RLC in series is

Qs =

√L/C

R(4.3)

The Q Factor is very important at RF, where all the parasitic elements of packageand environment have a significant influence on performance of the circuit. In Fig-ure 4.1 is models of capacitor and inductor at RF. The ESR denotes the resistiveimpedance of parasitic element. Each capacitor and inductor has a self-resonantfrequency, where capacitor becomes inductor and inductor becomes capacitor be-cause of the parasitic capacitor and inductor. Figure 4.2 illustrates the insertionloss of capacitor depend on frequency, this leads to problem with choosing a usable

(a) Capacitor RF model (b) Inductor RF model

Figure 4.1.: Capacitor and inductor model at radio-frequency

31

CHAPTER 4. DESIGN WITH LOAD-PULL TECHNIQUE

Figure 4.2.: Insertion loss of capacitor [Murata-Data sheet]

capacitor for the design in chapter 2, the lowest peak of insertion loss denotes theself-resonant frequency of capacitor. In Figure is a measurement result of a 220 nFcapacitor, the result shows that at 900 MHz the capacitor is already a inductor.

Figure 4.3.: Measurement the 220nF capacitor

32


4.2. Power Amplifier design with Load-PullTechnique

For designing power amplifier, using the conjugated complex impedance with S-Parameter simulation to achieve low noise and maximal power is not so useful, be-cause the S-Parameter simulation only shows the small-signal response of amplifierin a 50Ω environment as a function of frequency and bias point. Due to non-idealeffects, including transistor parasitics, finite RF choke inductance and bias networks,classical design with S-Parameter can not predict well for realistic large-signal op-eration of RF PA device.Design-key to achieve the maximal output power with power amplifier is to presenta optimum source and loadimpedance to the transistor amplifier. Load-pull analy-sis is a method for characterizing nonlinear behavior of high-power transistor underlarge signal, this information is used to determine the optimum source and load-impedance for the desired performance.The load-pull technique is essentially, a process of varying the impedance seen by

Figure 4.4.: Block diagram of a load-pull system[19]

the output of an active device to other than 50Ω in order to measure performanceparameters. The data are plotted on a Smith chart as contours, which directly helpsfinding out the optimal load impedance, normally the decision is based on trade-offbetween the output power and PAE1, where the PAE is calculated as:

PAE =Pout − PinPDC

(4.4)

In Figure 4.4 is a simplified diagram of a load-pull system. The power transistoris placed at DUT2 , the bias voltage and supply voltage are set up as a desiredworking condition. A pair of tuner at input and output are used to vary the input

1Power Added Efficiency2Device Under Test

33


and output impedance. The accuracy of load-pull measurement is highly dependedon the tuner, for high repeatability measurement data a precision tuner is needed.The active transistor’s performance data will be acquired while the tuner varies itsimpedances, the entire process is controlled by a computer. The real hardware load-pull measurement is highly recommended for designing high frequency high poweramplifier, which requires high reliable data, although this method is high cost andrequires large amount of time.There is a alternative for hardware load-pull measurement, in this thesis the ”vir-tual impedance tuner” embedded in the circuit simulator of Agilent’s ADS3 is used,while the Load-Pull Simulation in ADS does not calculate the collector efficiency,the PAE can be used to determine the desired collector efficiency. This load-pullsimulation utilizes the fast computation power of EDA, but it depends on the accu-racy and availability of large-signal transistor model. This is a biggest disadvantageof virtual load-pull measurement, because most of the semiconductor manufactureronly provides the small-signal transistor model, and the large-signal model is not soaccuracy.With the load-pull method, the goal for design is concentrated on maximal outputpower, therefore the input and output matching maybe poor, because it is inten-tionally mismatched in order to achieve maximal RF power generation. The resultsfrom the Load-Pull simulation are the impedance of source ZS and the impedance ofload ZL (Figure 4.5), which are needed to be presented at the base and the collectornodes of the transistor to achieve the desired output power and PAE.

Figure 4.5.: Results of load-pull technique

4.3. Design parameters

The Doherty amplifier design in this section is aimed to have the first peak of collectorefficiency at 0 dBm input power and the second peak at 3 dBm input power like inthe design with analytic method. Therefore, the bias voltage for the carry transistorremains the same 0.7V as in the previous chapter, as well as the supply voltageof 2.7 V. The result from load pull simulation in Figure A.1 shows that the carrytransistor can deliver 17.89 dBm maximal output power and have the PAE of 50.2%

3Advanced Design System

34


(a) Collector efficiency (b) Pout, Gain

Figure 4.6.: Measurement results from test device Carry-V4B, measurement 1


Figure 4.7.: Measurement results from test device Carry-V4B, measurement 2

at 3 dBm input power. At the maximal output power of the Doherty amplifier thecarry transistor only needs to deliver 17 dBm output power at 3 dBm input power(Section 3.1), therefore the load impedance can be moved to further outside of themiddle of the output power contour toward the center of the PAE contour. FigureA.2 shows the pair of source and load impedances, which are needed to present atthe base and collector nodes of the transistor, is:

ZS,B,V 4 = 10.50− j6.6[Ω]

ZL,B,V 4 = 66.398 + j10.26[Ω]

Figure 4.6 shows that with ZS,B,V 4 and ZL,B,V 4 the carry amplifier can not able todeliver 17 dBm output power with 3 dBm input power and the collector efficiencyis only about 35%. The supply voltage was varied to determine the new workingcondition for the amplifier. The new 5 V supply voltage was chosen, because of itshigh efficiency 30% and relatively high output power about 15 dBm. Figure A.5displays the load pull simulation results with the new supply voltage, from FigureA.6 the new pair of source and load impedance for the carry amplifier is:

ZS,B,V 5 = 7.96− j5.63[Ω]

ZL,B,V 5 = 108.46 + j55.464[Ω]

The design for the peak amplifier is made before the measurement on the test deviceCarry-V4B and because of the time limit the design for the peak amplifier is not

35


optimized for the new supply voltage. The result in Figure A.3 shows with 0.3 Vbias and 2.7 V supply voltage the peak transistor only deliver maximum -12.38 dBmoutput power with PAE of −37.97% at 3 dBm input power. The decision of sourceand load impedance is made based on the best possible combination of output powerand PAE, therefore the chosen pair of source and load impedances is:

ZS,C,V 4 = 6.97− j69.01[Ω]

ZL,C,V 4 = 96.3 + j60.186[Ω]

The measurement experiments show that, the peak transistor can work with thisconfiguration but only with higher bias and supply voltages. Table 4.1 shows thesummary of the source and load impedances, which are used to design the amplifier,the values of bias and supply voltages are the ones, which are used in the load pullsimulation.

Device ZS[Ω] ZL[Ω] Bias, sim[V] Supply, sim[V]Carry-V4 10.50 -j6.6 66.398+j10.26 0.7 2.7Carry-V5 7.96-j5.63 108.46+j55.46 0.7 5Peak-V4 6.97-j69.01 96.3+j60.186 0.3 2.7

Table 4.1.: Summary of source and load impedance for design

4.4. Amplifier design

4.4.1. Carry amplifier V4

To start with the design of the input matching network, the source impedanceZS,B,V 4 = (10.50 − j6.6)Ω is conjugated, i.e. ZS,B,V 4 = (10.50 + j6.6)Ω. Usingthe function SmithChart from ADS, the matching network is designed to trans-form a 50Ω to ZS,B,V 4. A DC-Block capacitor is integrated into the input matchingnetwork, with the visual advantage of the SmithChart the value of the DC-Blockcapacitor can be chosen, so that the variance of the capacitor value only has mini-mum affection on the accuracy of the matching network, in this case the value of thecapacitor can range from 6 µF to 9 µF without causing any sufficient degradation onthe matching network. The biasing network can also be a part of the input network,this can be useful in some circumstances. Using the function LineCal from ADSthe input matching network is synthesized into a circuit, which shown in Figure 4.8.Later a physical layout of the input matching network is made (Figure 4.10(a)),there are some differences in the actually physical size of the elements in comparisonwith the ideal strip line model. The results in Figure 4.10(b) is from the simulationwith the physical layout. A small input matching network is made to compare theaccuracy of this design method with the actually hardware, the results in Figure 4.9confirm the precision of the design process.

The design of the output matching network for the carry amplifier follows thesame procedure like the input matching network, the conjugated load impedance

36


Figure 4.8.: Schematic of input matching for carry V4

Figure 4.9.: Comparison between software simulation and hardware measure-ment of the carry input matching network V4 , Simulation-Line,Hardware-Symbol

ZL,B,V 4 = (66.398 − j10.26)Ω is used to design the output matching network, ex-cepted that at the output network a filter for the harmonic frequencies is needed.The filter for the harmonic frequencies can be a part of the matching network or im-plemented separated as a Harmonic Termination Network(HTN), such network wasused in the research [4] to achieve the optimum filter for the harmonic frequencies.Because the lack of time and to simplify the design process only a simple filter withquarter wavelength is used. Figure 4.11 shows the schematic of the output matchingnetwork, in Figure 4.12(a) is the physical layout of the matching network, and inFigure 4.12(b) is the S-Parameter simulation result. Even though the filter networkis quite simple, its result is good enough to filter the second and third harmonicfrequencies.One of the aspect, which was not taken into account with the load pull simulation,

is stability factor of the amplifier. Figure 4.13(a) displays the result of stability fac-tor calculation using the function StabFact from ADS, there is a major problem withthe stability in the low frequency region, the early prototype of the Carry amplifierV4 also confirms this problem during the test measurement. Normally the open loopdesign of amplifier should not cause any problem with the stability factor, but inthis case the Miller capacitor between the collector and the base and the parasiticelements of the transistor package cause the unwanted feed-back from the collectorto the base. In the low frequency region the reactance of the 7 µF DC-Block capac-itor in the input and output network is too high, therefore the low frequency wavecomponent can not be terminated to ground. To solve this problem a 470 nF and a

37


(a) Layout (b) Simulation results

Figure 4.10.: Layout and S-Parameter simulation result of the carry inputmatching network V4

Figure 4.11.: Schematic of the output matching network for carry amplifierV4D

1 nF are implemented into the input and output network, also the bias and supplynetwork are enhanced with large capacitors to create a short-cut to ground for thelow frequency wave. At high frequency region most of the new added capacitorshave already lost the property of capacitor, therefore there is no unwanted effect onthe accuracy of the matching networks. Figure 4.13(b) shows the improvement ofthe stability factor after stabilization procedure, the stability factor is now above 1for all frequencies. The final design for the carry amplifier V4D is shown in FigureB.2.

38



Figure 4.12.: Layout and S-Parameter simulation of the carry output matchingnetwork V4D

(a) Before stabilization (b) After stabilization

Figure 4.13.: Stability factor of the carry amplifier V4

39


4.4.2. Carry amplifier V5, Peak amplifier V4 and Dohertyamplifier

The designs of the carry amplifier V5 and the peak amplifier V4 follow the sameprocedure as one of the carry amplifier V4, but because of the time limit the outputnetwork of the peak amplifier V4 does not have any improvement on filter charac-teristic. Note that the improvements on the stability property of the amplifier forthe carry amplifier V5 and the peak amplifier V4 are taken over from the design ofthe carry amplifier V4.

In Figures 4.14 and 4.16 are the schematics of the input and output networks

Figure 4.14.: Schematic of the input network for the carry amplifier V5

for the carry amplifier V5, their physical layout and S-Parameter simulations resultsare shown in Figure 4.15 and 4.17, respectively. The complete design for the carryamplifier V5 is shown in Figure B.3.Figure 4.18 shows the schematic of the input network for the peak amplifier V4,while the schematic of the output network is shown in Figure 4.20. The physicallayouts and S-Parameter simulation results of the peak amplifier’s input and outputnetworks are illustrated in Figure 4.19 and Figure 4.21, in the order as mentioned.The final design of the peak amplifier V4 is displayed in Figure B.4.The designs of the carry amplifier V4 and the peak amplifier V4 are combined usingthe input and output network of the Doherty amplifier (Section 3.2) to form theDoherty amplifier V1B, while the design of the Doherty amplifier V2B is createdusing the designs of the carry amplifier V5 and the peak amplifier V4. The phys-ical layouts of the Doherty amplifier V1B and V2B are shown in Figure B.5, B.6,respectively. Because the inaccuracy of the AT42086’s CAD model for high powersignal, the performance of the designs can not be evaluated based on the simulationresults, therefore both of these two designs are fabricated for hardware measurementand analysis.

40



Figure 4.15.: Layout and S-Parameter simulation results of the input networkfor the carry amplifier V5

Figure 4.16.: Schematic of the output network for the carry amplifier V5

41



Figure 4.17.: Layout and S-Parameter simulation results of the output networkfor the carry amplifier V5

Figure 4.18.: Schematic of the input network for the peak amplifier V4


Figure 4.19.: Layout and S-Parameter simulation results of the input networkfor the peak amplifier V4

42


Figure 4.20.: Schematic of the output network for the peak amplifier V4


Figure 4.21.: Layout and S-Parameter simulation results of the output networkfor the peak amplifier V4

43


4.5. Performance review

4.5.1. DC current behavior

Figure 4.22.: Collector current versus base voltage of AT42086, with 2.7V Vccsupply

A small test circuit is made to test the accuracy of the available CAD model of theAT42086 transistor. Figure 4.22 shows that the slopes of both collector currents arethe same, but the real AT42086 has the lower ”knee” base voltage than the one fromCAE model, hence, the real AT42086 offers better linearity character than the CADmodel, this property is confirmed through all the measurements with hardware.

4.5.2. Carry amplifier

Figure 4.23.: Measurement setup

The measurement setup is shown in Figure 4.23, the spectrum analyzer has a 50Ω input impedance. For convenient reason the measurement results of the carryamplifier V4 are plotted again in Figure 4.24. Figures 4.25(a) and 4.26(a) show,that the carry amplifier V5A reaches its maximum efficiency at Pin = 3 dBm and 5V supply voltage as expected, but the output power is only 14dBm (Figure 4.25(b)),lower than the output power of 15.5 dBm shown in Figure 4.7(b). The comparisonbetween the linearity of the carry amplifier V4 and the carry amplifier V5 in Figure4.24(b) and Figure 4.25(b) shows that the version V4 has better linear property thanthe version V5. All the results of the collector efficiency measurements indicate, that

44



Figure 4.24.: Measurement results from test device Carry-V4B


Figure 4.25.: Measurement results from test device Carry-V5A with 5V supplyvoltage


Figure 4.26.: Measurement results from test device Carry-V5A with differentsupply voltages, Pin = 3dBm

45



Figure 4.27.: Measurement results from test device Carry-V5A with differentsupply voltages, Pin = 6dBm

the transistor AT42086 in class B configuration only has the maximum collectorefficiency about 32%. According to the results shown in Figure 4.27, to achieve the17 dBm output power the input power must be increased to 6 dBm and the supplyvoltage to 7.5 V.

4.5.3. Peak amplifier

The peak amplifier is designed to have its maximum collector efficiency at Pin = 3dBm, therefore as shown in Figure 4.28 the bias voltage and the supply voltage arechosen to be 0.5 V and 5 V, respectively. Also the measurement results show thatthe maximum collector efficiency of the peak amplifier V4 is about 45%.

46


(a)

(b)

(c)

Figure 4.28.: Measurement results from test device Peak-V4 with different biasvoltages

47


4.5.4. Doherty amplifier

Note that after the input network of the Doherty amplifier each amplifier only re-ceives the half of the input power, therefore if the amplifier is design to reach itsmaximum output power at 3 dBm in Section 4.4 then the actually input power of theDoherty amplifier must be at least 6 dBm. All the collector current values, whichare measured, are DC-current values, but because of the relationship between theDC current and the AC current shown in (2.2) and (2.3) these values are still validfor the analysis.The collector efficiencies in Figure 4.29 and Figure 4.30 have two peaks of efficiency

with different values, the distance between the two peaks is exactly the same aspredicted in Section 2.3.5, 3 dBm versus Pin and 6 dBm versus Pout, and the secondpeak of efficiency is not occurred at Pout = 20 dBm. With the reducing bias forthe peak amplifier, the first peak of efficiency is increased, but the linearity and thesecond peak efficiency of the amplifier is reduced, also the carry amplifier’s collectorcurrent is able to reach a higher value. Figure 4.29(d) and Figure 4.30(d) show,there is a ”dip” in the course of the carry amplifier’s collector current, when thepeak amplifier begins to conduct.Figure 4.31(a) and 4.32(a) show, that the Doherty amplifier at Pin = 3 dBm hasalready reached its first peak efficiency, which is too soon, this explains the lowvalues of the amplifier’s collector efficiency. This may be caused by the high biasof the peak amplifier, from Figure 4.31(d) and Figure 4.32(d) the peak amplifierbegins to conduct before the carry amplifier’s collector current reaches its maximumvalues, unlike the behaviors of the collector current of the Doherty amplifier V1B inFigure 4.29(d) and 4.30(d). With the reduced bias voltage for the peak amplifier,the collector efficiency is able to reach the maximum value of 25% (Figure 4.33), butthe development of the collector currents still does not have the characteristic of aDoherty amplifier. Overall the DC values of V2B amplifier’s collector current aretoo high in comparison with the DC values of the V1B amplifier’s collector currents.The version V2B has a lower gain factor than the gain factor of the version 1B,but the gain factors of both amplifiers V1B and V2B are still lower than expected,therefore the input power level must be higher in oder to reach the maximum outputpower level of 20 dBm. It appears that at high power level the transistor has reachedthe compression, because of the drop in the gain factor.Compared the performance of the version V1B and V2B shows that the version V1Bhas a better controlled performance as calculated and a higher collector efficiency.

48


(a) (b)

(c) (d)

Figure 4.29.: Measurement results of Doherty amplifier V1B

(a) (b)

(c) (d)


49


(a) (b)

(c) (d)


(a) (b)

(c) (d)


50


(a) (b)

(c) (d)


51

5. Conclusions andRecommendations

5.1. Conclusions

The objective of this thesis is to investigate the operation of the classical Dohertyamplifier and the development of a 900 MHz Doherty amplifier, which is capable ofdelivering 20 dBm at its peak efficiency.The functionality and support theory of the Doherty amplifier are first analyzedin Chapter 2. Analysis and design equation based on the classical assumption aregiven.In Chapter 3 a design with the available CAD model is given using the analyticmethod. This design delivers a deeper understanding of the functionality of a tran-sistor with different bias configuration and the usage of the matching network inachieve matched condition between source and input of the amplifier for maximumoutput power. The relation between stability factor and gain shows a typical prob-lem with the design of amplifier, in the case of the carry amplifier a compromisewas made to achieve a stability working behavior of the amplifier while ensure thehigh output power. A S-Parameter simulation is used to determine the effect of thematching network on phase response of the amplifier, this information was used todesign the input network for the Doherty amplifier, to make sure that at the loadimpedance the signal from the carry and peak amplifier combine in-phase for themaximum output power. The problems with the leakage between the carry andpeak amplifier as well as the finite saturated voltage VCE and their influent on theresulting collector efficiency of the amplifier are shown in the simulation result. Thesimulation design has a maximum collector efficiency above 50% and delivers 20dBm output power with 6.5 dBm input power. The difficulty with the realizationof simulation into hardware and the inaccuracy of S-Parameter simulation for highpower signal have led to a new approach on the amplifier design in Chapter4.Amplifier design with load pull technique is one of the widely used methods indesign a high power amplifier. It is used to determine the optimum working con-dition, in which the amplifier has its maximum output power with the optimumefficiency. Using the load pull technique on the amplifier device results in not onlythe real impedance part but also the imagine reactance part of the source and loadimpedance, which is very important in high power and high frequency power am-plifier. With the advance of knowing the exact impedances, which are needed tobe presented to the transistor, the matching network can be designed to eliminatethe unwanted influence of component’s tolerance while including some extra usefulattributes like filter characteristic, but the design process requires more time inten-

52

CHAPTER 5. CONCLUSIONS AND RECOMMENDATIONS

sity. In this thesis a load pull procedure is made based on simulation, therefore thereliability of the results depends on the accuracy of the CAD model. As a result,two designs of Doherty amplifier are built and evaluated. The evaluation resultsshow that the amplifier is capable of delivering 20 dBm at maximum output powerand has a fairly Doherty-like characteristic, but with some problems in linearity andgain factor.

5.2. Recommendations

One of the reasons, which results bad performance and difficulty during the designprocess is caused by the choice of transistor. In the modern RF high power amplifiermost of the transistor use the HBT or FET technology because of their ability towork with high power and high frequency conditions ([21],[11],[12],[10],...), thereforethe further work should focus on using these new technologies.Although working with the load pull technique based on simulation can reduce thetime intensity of the design, it requires an accurate CAD model, which should beable to characterize the behavior of the transistor with high power signal. If it ispossible, a hardware load pull measurement on real hardware is recommended.There are some necessary tests, which are needed to be carried out, in order to fullyunderstand the property of the designed Doherty amplifier like the two-tone test for3dB-interception point or the IMD3 test for the intermodulation distortion from thethird harmonic frequency.If the further work is based on the same transistor, then a research on optimizingthe performance of the amplifier based on the measurement results is advised.

53

A. Load pull simulation results

Figure A.1.: Load pull contour with 0.7V bias and 2.7 V supply

Figure A.2.: Source and Load impedance with 0.7V bias and 2.7V supply

54

APPENDIX A. LOAD PULL SIMULATION RESULTS

Figure A.3.: Load pull contour with 0.3V bias and 2.7V supply

Figure A.4.: Source and Load impedance with 0.3V bias and 2.7V supply

55


Figure A.5.: Load pull contour with 0.7V bias and 5V supply

Figure A.6.: Source and Load impedance with 0.7V bias and 5V supply

56




57




58

B. Schematics and layouts

59

APPENDIX B. SCHEMATICS AND LAYOUTS

Figure B.1.: Carry amplifier schematic with 0.7V bias and 2.7V supply, V4B

60


Figure B.2.: Carry amplifier schematic with 0.7V bias and 2.7V supply, V4D

61


Figure B.3.: Carry amplifier schematic with 0.7V bias and 5V supply, V5A

62


Figure B.4.: Peak amplifier schematic with 0.5V bias and 5V supply, V4

63


Figure B.5.: Layout of the Doherty amplifier V1B

Figure B.6.: Layout of the Doherty amplifier V2B

64

C. Data sheet

65

AT-42086Up to 6 GHz Medium Power Silicon Bipolar Transistor

Data Sheet

Features• High Output Power:

20.5 dBm Typical P1 dB at 2.0 GHz

• High Gain at 1 dB Compression:13.5 dB Typical G1 dB at 2.0 GHz

• Low Noise Figure: 1.9 dB Typical NFO at 2.0 GHz

• High Gain-Bandwidth Product: 8.0 GHz Typical fT

• Surface Mount Plastic Package

• Tape-and-Reel Packaging Option Available

• Lead-free Option Available

DescriptionAvago’s AT-42086 is a general purpose NPN bipolar tran-sistor that off ers excellent high frequency performance. The AT-42086 is housed in a low cost surface mount .085" diameter plastic package. The 4 micron emitter-to-emitter pitch enables this transistor to be used in many diff erent functions. The 20 emitter fi nger interdigitated geometry yields a medium sized transistor with impedances that are easy to match for low noise and medium power applica-tions. Applications include use in wireless systems as an LNA, gain stage, buff er, oscillator, and mixer. An optimum noise match near 50Ω up to 1 GHz, makes this device easy to use as a low noise amplifi er.

The AT-42086 bipolar transistor is fabricated using Avago’s 10 GHz fT Self-Aligned-Transistor (SAT) process. The die is nitride passivated for surface protection. Excellent device uniformity, performance and reliability are produced by the use of ion-implantation, self-alignment techniques, and gold metalization in the fabrication of this device.

86 Plastic Package

Pin Connections

1

4

3

2

EMITTER

BASE

EMITTER

COLLECTOR

420

2

AT-42086 Absolute Maximum Ratings Absolute Symbol Parameter Units Maximum[1]

VEBO Emitter-Base Voltage V 1.5

VCBO Collector-Base Voltage V 20

VCEO Collector-Emitter Voltage V 12

IC Collector Current mA 80

PT Power Dissipation [2,3] mW 500

Tj Junction Temperature °C 150

TSTG Storage Temperature °C -65 to 150

Thermal Resistance [2]: θjc = 140°C/W

Notes:1. Permanent damage may occur if any

of these limits are exceeded.2. TCASE = 25°C.3. Derate at 7.1 mW/°C for TC > 80°C.

Electrical Specifi cations, TA = 25°C

Symbol Parameters and Test Conditions Units Min. Typ. Max.

|S21E|2 Insertion Power Gain; VCE = 8 V, IC = 35 mA f = 1.0 GHz dB 15.0 16.5 f = 2.0 GHz 10.5 f = 4.0 GHz 4.5

P1 dB Power Output @ 1 dB Gain Compression f = 2.0 GHz dBm 20.5 VCE = 8 V, IC = 35 mA f= 4.0 GHz 20.0

G1 dB 1 dB Compressed Gain; VCE = 8 V, IC = 35 mA f = 2.0 GHz dB 13.5 f = 4.0 GHz 9.0

NFO Optimum Noise Figure: VCE = 8 V, IC = 10 mA f = 2.0 GHz dB 1.9 f = 4.0 GHz 3.5

GA Gain @ NFO; VCE = 8 V, IC = 10 mA f = 2.0 GHz dB 13.0 f = 4.0 GHz 9.0

fT Gain Bandwidth Product: VCE = 8 V, IC = 35 mA GHz 8.0

hFE Forward Current Transfer Ratio; VCE = 8 V, IC = 35 mA — 30 150 270

ICBO Collector Cutoff Current; VCB = 8 V µA 0.2

IEBO Emitter Cutoff Current; VEB = 1 V µA 2.0

CCB Collector Base Capacitance[1]: VCB = 8 V, f = 1 MHz pF 0.32

Note:1. For this test, the emitter is grounded.

3

AT-42086 Typical Performance, TA = 25°C

FREQUENCY (GHz)

Figure 3. Insertion Power Gain, Maximum AvailableGain and Maximum Stable Gain vs. Frequency.VCE = 8 V, IC = 35 mA.

GAIN

(dB)

0.1 0.50.3 1.0 3.0 6.0

IC (mA)

Figure 1. Output Power and 1 dB Compressed Gain vs.Collector Current and Frequency. VCE = 8 V.

24

20

16

12

8

4

G 1dB

(dB)

P 1dB

(dBm

)

0 10 20 30 40 50

P1 dB

G1 dB

2.0 GHz

2.0 GHz

4.0 GHz

4.0 GHz

40

35

30

25

20

15

10

5

0

MSG

MAG

|S21E|2

IC (mA)

Figure 2. Insertion Power Gain vs. Collector Currentand Frequency. VCE = 8 V.

20

16

12

8

4

0|S

21E|2

GAIN

(dB)

0 10 20 30 40 50

1.0 GHz

2.0 GHz

4.0 GHz

FREQUENCY (GHz)

Figure 4. Noise Figure and Associated Gain vs.Frequency. VCE = 8 V, IC = 10 mA.

GAIN

(dB)

24

21

18

15

12

9

6

3

0

4

3

2

1

0

NFO

(dB)

0.5 2.01.0 3.0 4.0 5.0

GA

NFO

Bibliography

[1] K. F. Brand. The Experimental Design and Characterization of Doherty PowerAmplifiers. Master’s thesis, Stellenbosch University, 2006.

[2] Bumman Kim, Jangheon Kim, Ildu Kim, and Jeonghyeon Cha. The dohertypower amplifier. IEEE mircowave magazine, October 2006.

[3] Charles J.Meyer, Booton Electronics. Measuring the peak-to-average power ofdigitally modulated signals, April 1993. [Online; accessed August-2011].

[4] X. Cui. Efficient Radio Frequency Power Amplifiers for Wireless Communica-tions. PhD thesis, The Ohio State University, 2007.

[5] Darren W. Ferwalt. A Base Control Doherty Power Amplifier Design for Im-proved Efficiency in GSM Handsets. Master’s thesis, Oregon State University,2004.

[6] W. Doherty. A new high efficiency power amplifier for modulated waves. Pro-ceedings of the Institute of Radio Engineers, 24(9):1163 – 1182, sept. 1936.

[7] N. Dubuc, C. Duvanaud, and P. Bouysse. Analysis of the doherty techniqueand application to a 900mhz power amplifier. In Microwave Conference, 2002.32nd European, pages 1 –3, sept. 2002.

[8] F.H. Raab, P.M. Asbeck, S.C. Cripps, P.B. Kenington, Z.B. Popovic, N. Pothe-cary, J.F. Sevic and N.O. Sokal. Power amplifiers and transmitter for RF andmicrowave. IEEE Trans. Microwave Theory and Tech, 50, March 2002.

[9] Frederick H. Raab. Efficiency of doherty RF power-amplifier systems. IEEE,33(3), September 1987.

[10] M. Iwamoto, A. Williams, P.-F. Chen, A. Metzger, C. Wang, L. Larson, andP. Asbeck. An extended doherty amplifier with high efficiency over a wide powerrange. In Microwave Symposium Digest, 2001 IEEE MTT-S International,volume 2, pages 931 –934 vol.2, 2001.

[11] B. Kim, J. Kim, I. Kim, J. Cha, and S. Hong. Microwave doherty poweramplifier for high efficiency and linearity. In Integrated Nonlinear Microwaveand Millimeter-Wave Circuits, 2006 International Workshop on, pages 22 –25,jan. 2006.

69

Bibliography

[12] A. Z. Markos. Efficiency Enhancement of Linear GaN RF power AmplifierUsing the Doherty Technique. PhD thesis, University Kassel, November 2008.

[13] Robert J. McMorrow, David M. Upton and Peter R. Maloney. The MicrowaveDoherty Amplifier. Microwave Symposium Digest, , IEEE MTT-S Interna-tional, 3, September 1994.

[14] S.C. Cripps. RF Power Amplifier for Wireless Communications. MA: ArtechHouse, 1999.

[15] C. Tongchoi, M. Chongcheawchamnan, and A. Worapishet. Lumped elementbased doherty power amplifier topology in cmos process. In Circuits and Sys-tems, 2003. ISCAS ’03. Proceedings of the 2003 International Symposium on,volume 1, pages I–445 – I–448 vol.1, may 2003.

[16] M. Vasic, O. Garcia, J. Oliver, P. Alou, D. Diaz, J. Cobos, A. Gimeno, J. Pardo,C. Benavente, and F. Ortega. High efficiency power amplifier for high frequencyradio transmitters. In Applied Power Electronics Conference and Exposition(APEC), 2010 Twenty-Fifth Annual IEEE, pages 729 –736, feb. 2010.

[17] Wikipedia. Miller effect — wikipedia, the free encyclopedia, 2011. [Online;accessed 3-August-2011].

[18] www.microwaves101.com. Efficiency of Microwave Devices, October 2009. [On-line; accessed August-2011].

[19] www.microwaves101.com. Load Pull for Power Devices, July 2011. [Online;accessed August-2011].

[20] X. Q. Chen, Y. C. Guo and X. W. Shi. A High Efficiency and Gain DohertyAmplifier for Wireless Mobile Base Stations. Microwave Journal, 51(4):102,April 2008.

[21] Y. Yang, J. Cha, B. Shin, and B. Kim. A fully matched n-way doherty amplifierwith optimized linearity. Microwave Theory and Techniques, IEEE Transac-tions on, 51(3):986 – 993, mar 2003.

[22] Y. Zhao, A. Metzger, P. Zampardi, M. Iwamoto, and P. Asbeck. Linearityimprovement of hbt-based doherty power amplifiers based on a simple analyticalmodel. In Microwave Symposium Digest, 2006. IEEE MTT-S International,pages 877 –880, june 2006.

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bachelor thesis: analysis and design of a 900mhz doherty power amplifier

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