design methodology for dual-band doherty power amplifier ...dual-band doherty power amplifier (dpa)...

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Copyright © 2012 IEEE. Reprinted from IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 12, DECEMBER 2012 This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Cree’s products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permis- [email protected] By choosing to view this document, you agree to all provisions of the copyright laws protecting it. Design Methodology for Dual-Band Doherty Power Amplifier With Performance Enhancement Using Dual-Band Offset Lines Karun Rawat, Student Member, IEEE, and Fadhel M. Ghannouchi, Fellow, IEEE Abstract—This paper proposes a design methodology for dual-band Doherty power amplifier (DPA) with performance en- hancement using dual-band phase offset lines. In the proposed architecture, 50-dual-band offset lines with arbitrary electric lengths at two frequencies are key components, and a novel an- alytical design solution has been proposed for their design and implementation. The methodology is validated with the design and fabrication of a 10-W GaN-based DPA for code division multi- ple access and Worldwide Interoperability for Microwave Access applications at 1960 and 3500 MHz, respectively. The dual-band Doherty amplifier using the proposed design methodology has better performance than the current state of the art. The peak drain efficiency of the amplifier is 59.5% at the first frequency and 49.6% at the second frequency of operation. Compared to bal- anced mode operation, there is an improvement of more than 10% in drain efficiencies, around 6.5-dB back-off, at both frequencies. Index Terms—Dispersive structure, Doherty power amplifier (DPA), dual band, phase offset lines. I. I NTRODUCTION D UAL-BAND/WIDEBAND applications are recently get- ting attention and encouragement in the communications research area due to the modern and upcoming communication standards [1]–[3]. These components can be used in devel- oping multistandard/multimode and reconfigurable transmitter architecture, capable of operating on a number of different air interface standards at different carriers [4], [5]. Such transmitter is intended to be used in a software-defined radio (SDR) termi- nal [4]. Hence, there is a keen motivation toward developing various passive or active radio frequency (RF) circuits [6]–[11] with multiband/wideband operation capability [12]–[16]. The SDR terminals are also proposed as smart devices for energy saving in a high-traffic communication network [17], [18]. Due to their reconfigurability, such radios can optimally choose among appropriate connectivity options with minimized path Manuscript received June 30, 2011; revised September 9, 2011 and October 23, 2011; accepted November 8, 2011. Date of publication November 21, 2011; date of current version July 2, 2012. This work was supported in part by the Alberta Innovates Technology Future, by the Nat- ural Sciences and Engineering Research Council of Canada, by the Canada Research Chair Program, and by TRLabs. The authors are with the Department of Electrical and Computer Engineering, Schulich School of Engineering, University of Calgary, Calgary, AB T2N1N4, Canada (e-mail: [email protected]; fadhel.ghannouchi@ ucalgary.ca). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2011.2176695 loss/shadowing. Thus, in consideration of predicted traffic loads and channel characteristics, the transmitted power can be optimized. This results into energy-efficient communication systems, where the transmitter is the main energy consuming subsystem due to the presence of power amplifier (PA). Apart from being a power-hungry component, PA is also the most nonlinear component [19]–[23] in the entire com- munication link, which contributes to adjacent channel power leakage, reducing the spectral efficiency [20]. Thus, linearity and efficiency are the two main benchmarks for any transmitter topology [19]–[23]; hence, an optimal solution is being sought. In order to achieve high linearity, digital predistortion (DPD) is highly appreciated among several linearization schemes due to its accuracy and its implementation in digital domain, re- sulting into reconfigurable capability [19]–[23]. However, uti- lizing predistortion as a linearization tool results in efficiency reduction as the PA is operated at average power back-off, which depends on the peak-to-average power ratio (PAPR) of the predistorted signal [19]–[23]. To enhance the efficiency in this back-off region, Doherty PA (DPA) is studied extensively, where theoretically the same efficiency as at saturation can be obtained at a certain back-off, which is decided by the load modulation factor [24]–[27]. Thus, for the dual-band transmit- ter architecture, a dual-band DPA design in conjunction with DPD is of great interest. In the literature, some attempts to design a dual-band DPA [28]–[31] have been reported, which discuss architectural overview without any proper design methodology. Since, in a single-band design, phase offset lines are com- monly used to optimize the performance of Doherty [26], [32], such optimization in a dual-band design needs dual-band phase offset lines with arbitrary electric lengths at the two frequencies. Implementing such lines is the main challenge in the design of dual-band DPA as two arbitrary phases are required at the two frequencies which should be controlled using design parameters. This paper presents a novel analytical design methodology for the design of dual-band phase offset lines which have 50-characteristic impedances but two arbitrary electric lengths at the two frequencies. These offset lines are used in the perfor- mance optimization of dual-band DPA, which is validated with simulation, hardware design, and measurements. A 10-W dual-band DPA has been designed using the pro- posed architecture, which operates for code division multiple access (CDMA) and Worldwide Interoperability for Microwave 0278-0046/$26.00 © 2011 IEEE

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Page 1: Design Methodology for Dual-Band Doherty Power Amplifier ...dual-band Doherty power amplifier (DPA) with performance en-hancement using dual-band phase offset lines. In the proposed

Copyright © 2012 IEEE. Reprinted from IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 12, DECEMBER 2012

This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Cree’s products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected] By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 12, DECEMBER 2012 4831

Design Methodology for Dual-Band Doherty PowerAmplifier With Performance Enhancement

Using Dual-Band Offset LinesKarun Rawat, Student Member, IEEE, and Fadhel M. Ghannouchi, Fellow, IEEE

Abstract—This paper proposes a design methodology fordual-band Doherty power amplifier (DPA) with performance en-hancement using dual-band phase offset lines. In the proposedarchitecture, 50-Ω dual-band offset lines with arbitrary electriclengths at two frequencies are key components, and a novel an-alytical design solution has been proposed for their design andimplementation. The methodology is validated with the design andfabrication of a 10-W GaN-based DPA for code division multi-ple access and Worldwide Interoperability for Microwave Accessapplications at 1960 and 3500 MHz, respectively. The dual-bandDoherty amplifier using the proposed design methodology hasbetter performance than the current state of the art. The peakdrain efficiency of the amplifier is 59.5% at the first frequencyand 49.6% at the second frequency of operation. Compared to bal-anced mode operation, there is an improvement of more than 10%in drain efficiencies, around 6.5-dB back-off, at both frequencies.

Index Terms—Dispersive structure, Doherty power amplifier(DPA), dual band, phase offset lines.

I. INTRODUCTION

DUAL-BAND/WIDEBAND applications are recently get-ting attention and encouragement in the communications

research area due to the modern and upcoming communicationstandards [1]–[3]. These components can be used in devel-oping multistandard/multimode and reconfigurable transmitterarchitecture, capable of operating on a number of different airinterface standards at different carriers [4], [5]. Such transmitteris intended to be used in a software-defined radio (SDR) termi-nal [4]. Hence, there is a keen motivation toward developingvarious passive or active radio frequency (RF) circuits [6]–[11]with multiband/wideband operation capability [12]–[16]. TheSDR terminals are also proposed as smart devices for energysaving in a high-traffic communication network [17], [18]. Dueto their reconfigurability, such radios can optimally chooseamong appropriate connectivity options with minimized path

Manuscript received June 30, 2011; revised September 9, 2011 andOctober 23, 2011; accepted November 8, 2011. Date of publicationNovember 21, 2011; date of current version July 2, 2012. This work wassupported in part by the Alberta Innovates Technology Future, by the Nat-ural Sciences and Engineering Research Council of Canada, by the CanadaResearch Chair Program, and by TRLabs.

The authors are with the Department of Electrical and ComputerEngineering, Schulich School of Engineering, University of Calgary, Calgary,AB T2N1N4, Canada (e-mail: [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2011.2176695

loss/shadowing. Thus, in consideration of predicted trafficloads and channel characteristics, the transmitted power canbe optimized. This results into energy-efficient communicationsystems, where the transmitter is the main energy consumingsubsystem due to the presence of power amplifier (PA).

Apart from being a power-hungry component, PA is alsothe most nonlinear component [19]–[23] in the entire com-munication link, which contributes to adjacent channel powerleakage, reducing the spectral efficiency [20]. Thus, linearityand efficiency are the two main benchmarks for any transmittertopology [19]–[23]; hence, an optimal solution is being sought.In order to achieve high linearity, digital predistortion (DPD)is highly appreciated among several linearization schemes dueto its accuracy and its implementation in digital domain, re-sulting into reconfigurable capability [19]–[23]. However, uti-lizing predistortion as a linearization tool results in efficiencyreduction as the PA is operated at average power back-off,which depends on the peak-to-average power ratio (PAPR) ofthe predistorted signal [19]–[23]. To enhance the efficiency inthis back-off region, Doherty PA (DPA) is studied extensively,where theoretically the same efficiency as at saturation can beobtained at a certain back-off, which is decided by the loadmodulation factor [24]–[27]. Thus, for the dual-band transmit-ter architecture, a dual-band DPA design in conjunction withDPD is of great interest.

In the literature, some attempts to design a dual-band DPA[28]–[31] have been reported, which discuss architecturaloverview without any proper design methodology.

Since, in a single-band design, phase offset lines are com-monly used to optimize the performance of Doherty [26], [32],such optimization in a dual-band design needs dual-band phaseoffset lines with arbitrary electric lengths at the two frequencies.Implementing such lines is the main challenge in the designof dual-band DPA as two arbitrary phases are required atthe two frequencies which should be controlled using designparameters.

This paper presents a novel analytical design methodologyfor the design of dual-band phase offset lines which have 50-Ωcharacteristic impedances but two arbitrary electric lengths atthe two frequencies. These offset lines are used in the perfor-mance optimization of dual-band DPA, which is validated withsimulation, hardware design, and measurements.

A 10-W dual-band DPA has been designed using the pro-posed architecture, which operates for code division multipleaccess (CDMA) and Worldwide Interoperability for Microwave

0278-0046/$26.00 © 2011 IEEE

Page 2: Design Methodology for Dual-Band Doherty Power Amplifier ...dual-band Doherty power amplifier (DPA) with performance en-hancement using dual-band phase offset lines. In the proposed

Copyright © 2012 IEEE. Reprinted from IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 12, DECEMBER 2012

This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Cree’s products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected] By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

4832 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 12, DECEMBER 2012

Fig. 1. Proposed architecture for dual-band DPA.

Access (WiMAX) applications at 1960 and 3500 MHz, respec-tively. The results of the prototype are compared with the stateof the art in the dual-band DPA design to report the performanceimprovement.

Section II describes the utilization of dual-band phase offsetlines for optimizing DPA performance. Section III briefs thedesign methodology of these dual-band phase offset lines.Section IV provides the design summary of dual-band DPA,with EM simulated results illustrating the performance en-hancement using dual-band phase offset lines. The performanceis validated experimentally in Section V, with the results anddiscussion provided in Section VI.

II. DUAL-BAND DOHERTY ARCHITECTURE WITH

DUAL-BAND PHASE OFFSET LINE

The proposed architecture is based on replacing each com-ponent of a conventional single-band DPA with correspondingdual-band components. Hence, the specifications and perfor-mance requirements of each circuit component are similarto its respective single-band configuration, which are readilyavailable in the literature [24], [26]. Fig. 1 shows the schematicof the proposed dual-band DPA. The carrier amplifier is a dual-band PA biased at class AB operation. This involves a dual-band matching topology in order to match a 50-Ω load totwo arbitrary complex impedances seen by the device at twodesired frequencies of operation. Such complex impedancesare obtained by load-pull analysis of a stable GaN-based highelectron mobility transistor biased for class AB operation inorder to obtain optimum power added efficiency (PAE) atsaturation.

Once the carrier amplifier is designed, the peaking amplifiercan be developed: the peaking amplifier is similar to thecarrier amplifier circuit but biased at class C operation. Afterthis, a load modulation combiner is designed using Pi-typetransformers which are well known for dual-band quarter-waveapplications [33]. For a load modulation factor of 0.5, animpedance transformer with a characteristic impedance of 50 Ωis required and represented as transformer 1 in Fig. 1. Accord-ingly, transformer 2 in Fig. 1 has a characteristic impedance of35.35 Ω, which transforms a 50-Ω load to 25 Ω at junction A,as per standard DPA architecture. A corresponding input splitter

Fig. 2. Dual-band phase offset line operation. (a) Peaking path. (b) Carrierpath.

will be designed as dual-band branch-line hybrid using Pi-typetransformers, as shown in Fig. 1.

The 50-Ω dual-band phase offset lines in the carrier andpeaking paths, as shown in Fig. 1, are used to optimize theoverall performance of the dual-band DPA. The phase offsetline at the output of the peaking amplifier adjusts the impedanceZP in Fig. 1 to a high value in order to avoid any powerleakage from the carrier to the peaking path. This operation isshown in Fig. 2(a), where the 50-Ω line shifts the correspondingZP to effectively open circuit points. Since, for dual-bandapplications, ZP can be different, the phase shift provided bythis line at the two frequencies of the operation is different[represented as ΦP (f1) and ΦP (f2) in Fig. 2(a)].

Therefore, the design requires a 50-Ω dual-band phase off-set line with arbitrary phases at the two frequencies. If theimpedance ZP is effectively open in the back-off (low-powerregion), then the carrier amplifier will see 100 Ω, which appearsdue to the 50-Ω load transformation by the two quarter-wavetransformers of 50 and 35.35 Ω in the load-modulation circuit.

When this 100-Ω load appears at the output of the carrieramplifier matching network, the offset line in the carrier pathensures that the optimum Zopt corresponding to the optimumPAE will be seen by the device in the carrier amplifier at back-off. The operation of such offset line in the carrier path is shown

Page 3: Design Methodology for Dual-Band Doherty Power Amplifier ...dual-band Doherty power amplifier (DPA) with performance en-hancement using dual-band phase offset lines. In the proposed

Copyright © 2012 IEEE. Reprinted from IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 12, DECEMBER 2012

This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Cree’s products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected] By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

RAWAT AND GHANNOUCHI: DESIGN METHODOLOGY FOR DUAL-BAND DPA 4833

Fig. 3. Proposed schematic of the dual-band phase offset line.

in Fig. 2(b), where a 100-Ω load is shifted to the optimum poweraided efficiency (PAE) points (A and B).

Since the optimum load condition also varies with the outputpower back-off [34], a separate load-pull simulation for a car-rier amplifier along with its matching networks (at the referenceplane of the output matching network) is required for back-offpower region (6-dB back-off in case of conventional Dohertywith load-modulation factor of 0.5), and various PAE contoursare plotted as shown in Fig. 2(b). Each phase offset line addscorresponding phases in their paths; hence, an additional 50-Ωdual-band phase offset line is added at the input to compensatefor the phase difference in the two paths.

It is worth mentioning that these offset lines have a charac-teristic impedance of 50 Ω; hence, at saturation, the load seenby the carrier and peaking amplifiers is 50 Ω. Thus, the offsetwill be effective only at back-off, and these offset lines donot have any effect at saturation, thereby keeping the overallmatching conditions intact at saturation. Moreover, it is alsoevident from Fig. 2(b) that it is not always possible to achieveoptimum load [represented as PAEOPT in Fig. 2(b)] withsuch phase offset lines, which depends on the position of PAEcontours in the Smith chart. However, the closest point can beachieved as shown in Fig. 2(b) for the case of frequency f2.This arrangement also provides an opportunity to use the sameline in the carrier path as used in the peaking path, provided thata reasonable PAE contour can be reached in the carrier path atback-off. Therefore, one can avoid additional phase offset lineat the input if the two similar lines are used in both carrier andpeaking paths, as shown in Fig. 1.

III. THEORY AND DESIGN OF DUAL-BAND OFFSET LINE

It has been demonstrated in [10], [15], and [33] that thedispersive property of stub-loaded structure can be used tomodify its nonlinear phase response to obtain different electriclengths (phase shifts) at different frequencies. Fig. 3 showsthe structure of the stub-loaded line proposed for dual-bandoperation. The proposed structure will imitate a dual-bandline with arbitrary electric lengths θT1 and θT2 at f1 and f2,respectively, while the characteristic impedance is 50 Ω in bothfrequencies. If an arbitrary stub value BS loads a transmission

line of characteristic impedance ZS and electrical length θS ,as shown in Fig. 3(a) can be written as [33], [35][

cos θS−BSZSsin θS jZSsin θS

j 1ZS

sinθS

(1−Z2

SB2S +2ZSBScot θS

)cos θS−BSZSsinθS

].

(1)

The overall effective electrical length and characteristicimpedance of the loaded structure can be derived from (1) as

cos(θT ) =A + D

2= cos θS − BSZS sin θS (2)

ZT =

√B

C= ZS

√1

1 − Z2SB2

S + 2ZSBS cot θS. (3)

If n is the frequency ratio between f1 and f2, (3) can berearranged as

Z2S

Z2T

= 1 − K2(f1) + 2K(f1) cot θS @f1 (4a)

Z2S

Z2T

= 1 − K2(f2) + 2K(f2) cot nθS @f2 (4b)

where ZT is the effective characteristic impedance at twofrequencies and K is defined as

K(f1) =ZSBS(f1) @f1 (5a)

K(f2) =ZSBS(f2) @f2. (5b)

Similarly, (2) can be rearranged as

K(f1) sin θS = cos θS − cos θT1 @f1 (6a)

K(f2) sin nθS = cos nθS − cos θT2 @f2. (6b)

By substituting the corresponding values of K at f1 and f2

from (6) in (4), one can obtain

ZS = ZT| sin θT1|| sin θS |

@f1 ZS = ZT| sin θT2|| sin nθS |

@f2. (7)

Thus, from (7), following condition can be obtained:

| sin nθS || sin θS |

=| sin θT2|| sin θT1|

. (8)

For given values of θT1, θT2, and n, (8) can be solvedanalytically to obtain electrical length θS of the loaded line,as given in Appendix A. Once obtaining the value of θS , ZS

can be calculated from (7) for a desired value of ZT , which is50 Ω in the present case. Similarly, the value of K at the twofrequencies can be obtained using (6) once ZS is known. Thedesign parameter BS at the two frequencies is then calculatedusing (5) once ZS and K are known.

Fig. 4 shows the dependence of the ratio in the right-handside of (8) over the values of θS for different values of ncorresponding to various wireless commercial standards. It isshown in Fig. 4 that the maximum value that can be achieved forthe ratio in (8) is decided by the frequency ratio n. The physicallength corresponding to the electrical length θS is calculated atfrequency f1.

The final step in the design is to realize BS(f1) and BS(f2)using dual-band multisection stub [35], [36] of Fig. 3(b). Such

Page 4: Design Methodology for Dual-Band Doherty Power Amplifier ...dual-band Doherty power amplifier (DPA) with performance en-hancement using dual-band phase offset lines. In the proposed

Copyright © 2012 IEEE. Reprinted from IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 12, DECEMBER 2012

This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Cree’s products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected] By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

4834 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 12, DECEMBER 2012

Fig. 4. Range of θT1 and θT2 obtained from the proposed methodology fordifferent frequency ratios.

multisection stub design can be divided in two sections, asshown in Fig. 3(b), where the first step is the realizationof the required susceptance BS(f1) at the input, which isaccomplished as in section 1 of Fig. 3(b). Here, f1 is thelower frequency between f1 and f2. In Fig. 3(b), section 1can be depicted as a transmission line short circuit at node A.This short circuit is realized by a 90 open-circuit stub at f1,as shown in Fig. 3(b), and ensures that adding any furthersection beyond this point will not affect the input admittanceat frequency f1.

Once section 1 is realized, section 2 is designed as anadmittance which terminates section 1 at node A and emulatessusceptance BS(f2) at the input of section 1. This terminatingadmittance is referred to as section 2 in Fig. 3(b) and can berealized by either an open or short stub. In order to realize thedesired input admittance value of jBS(f1) with section 1 inFig. 3(b), the designer can choose a short-circuit transmissionline (short circuit at node A) with certain realizable value ofcharacteristic impedance ZC1 which has electric length θC1

calculated as

θC1(f1) = tan−1

−1

ZC1BS(f1)

(9)

where BS(f1) can be positive or negative, depending on therequired susceptance value calculated from (5a). The valueobtained for θC1 is considered at f1 in order to calculate thephysical length.

Once the design parameters for section 1 are finalized, thevalue of susceptance YB is synthesized for frequency f2. Thisrequires the synthesis of admittances YA(f2), YB(f2), andYC(f2), as shown in Fig. 3(b).

YA(f2) can be obtained by de-embedding section 1 witha known value of BS(f2) using a standard transmission lineimpedance equation as follows:

YA(f2) =j

ZC1

ZC1BS(f2) − tan

θC1(f1) f2

f1

1 + ZC1BS(f2) tanθC1(f1) f2

f1

(10)

where BS(f2) can be positive or negative, depending on therequired value calculated from (5b).

Since YA(f2) can also be expressed as a parallel combinationof YB(f2) and YC(f2) at node A in Fig. 3(b), the followingrelation holds:

YA(f2) = YC(f2) + YB(f2) (11)

where YC(f2) is the admittance at the input of the 90 trans-former in Fig. 3(b) at f2 and is given as

YC(f2) = j1

ZC,OCtan

π

2f2

f1

. (12)

Thus, by using (12) in (11), one can find the required valueof YB(f2) as follows:

YB(f2) = YA(f2) − j1

ZC,OCtan

π

2f2

f1

(13)

where YA(f2) can be obtained from (10).This synthesized value of YB(f2) can be realized by an open

or short stub of characteristic impedance ZC2 and electricallength θC2, which is represented as section 2 in Fig. 3(b). If thedesigner chooses a certain realizable value for the characteristicimpedance of ZC2 for this stub, its electrical length can begiven by

θC2(f2) =

tan−1 (ZC2 · imag (YB(f2))) , for open stub

tan−1

−1ZC2imag(YB(f2))

, for short stub.

(14)

The choice of using an open or short stub and ZC2 in (14)depends on the realizability of YB(f2) with a minimum stublength. The imaginary value of YB(f2) in (14) can be positiveor negative, depending on the calculated results in (13).

IV. DESIGN OF DUAL-BAND DOHERTY AMPLIFIER AND

ITS OPTIMIZATION USING DUAL-BAND OFFSET LINE

The dual-band DPA architecture consists of various dual-band active and passive components replacing their correspond-ing single-band components in a conventional DPA design. Thefollowing sections brief the design of each of these components.

A. Input Splitter and Load Combiner

A dual-band branch-line hybrid can be used as input splitterin dual-band DPA design. Such coupler is designed with stub-loading at the edges of the line, with a design methodologyreported in [33]. Since the input splitter consists of 50- and35.35-Ω dual-band quarter-wave transformers which are alsorequired in dual-band load-combiner, hence a similar method-ology can be used in the design of dual-band load combinercircuit, as shown in Fig. 1.

B. Carrier and Peaking Amplifier Designs

Similar to any conventional single-band PA design, the tran-sistor is first biased and stabilized in the present dual-banddesign using conventional methodology, as in [37]. A simplebiasing circuit for an RF PA includes an inductor that feeds dc tothe transistor but blocks ac leakage from the RF path. However,

Page 5: Design Methodology for Dual-Band Doherty Power Amplifier ...dual-band Doherty power amplifier (DPA) with performance en-hancement using dual-band phase offset lines. In the proposed

Copyright © 2012 IEEE. Reprinted from IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 12, DECEMBER 2012

This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Cree’s products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected] By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

RAWAT AND GHANNOUCHI: DESIGN METHODOLOGY FOR DUAL-BAND DPA 4835

Fig. 5. Dual-band matching topology.

these inductors suffer great losses due to their low-Q factorsthat are further lowered when high power handling capacity isrequired; therefore, the most conventional approach is to usea transmission line based 90 transformer, short circuit at oneof its ends, realizing an effective open circuit at the other end,connected to the RF path [37]. This behaves as a lossless pathfor dc; however, effectively, no ac leaks through it. For a dual-band PA design, such a 90 transformer should be dual bandwith high characteristic impedance. This dual-band transformeris designed by using a T-type structure, which is a transmissionline loaded by a stub at the center [15]. Once the transistor isbiased using this dual-band 90 transformer, a stability circuitis designed at the input.

After stabilization, a dual-band matching network is de-signed to present optimum load and source impedances, whichare different at two frequencies, when terminated by a 50-Ωload. Several useful techniques have been proposed for suchdual-band matching [35], [36], [38]–[40].

Fig. 5 shows the dual-band matching topology. In the presentdesign, a non-50-Ω matching technique which utilizes a dual-band/dual-impedance quarter-wave transformer of two differentcharacteristic impedances at two frequencies has been used, asshown in Fig. 5. According to this topology, these characteristicimpedances of the transformer are synthesized in such a mannerthat, when it is terminated by certain admittances (YJ(f1) andYJ(f2) in Fig. 5) with the real conductive part as 1/50 Ω(represented by G0 in Fig. 5) at both frequencies, it will realizethe desired input admittances (known from load-pull analysis)Y (f1) and Y (f2) at the two frequencies. In this technique,the first step involves the synthesis of the required values ofthe characteristic impedances ZT1 and ZT2 at two frequen-cies f1 and f2, respectively, and the corresponding values ofthe susceptances jBJ(f1) and jBJ(f2) at the reference JJ

(in Fig. 5). Then, the values of these characteristic impedancesand susceptances are realized as given in [35]. The value ofjunction admittance YJ(f) and the required input admittanceY (f) are related with simple impedance inversion relationshipof a quarter-wave transformer given by

YJ(f)=1

(ZT (f))2 Y (f), where ZT (f)=

ZT1, @f1

ZT2, @f2.(15)

By putting Y (f) and YJ(f) in their complex forms in (15)and by individually comparing the real and imaginary parts,the susceptance values BJ(f) of the junction admittances

Fig. 6. Pi-type structure as dual-band/dual-impedance quarter-wave trans-former with shunt stub realized using the following: (a) open- and (b) short-circuit transmission lines.

(at reference JJ in Fig. 5) and the required characteristicimpedances ZT (f) of the 90 transformer (impedance inverter)can be synthesized as follows:

BJ(f) =−B(f)50G(f)

(16a)

ZT (f) =

√√√√ 1

50G(f)√

(GJ(f))2 + (BJ(f))2. (16b)

Once the required values of BJ(f) are known from(16a), these susceptance values are realized using a similardual-band/dual-susceptance stub as described in Section IIIwith design equations (9)–(14). However, the dual-band/dual-impedance quarter-wave transformer is designed using the Pi-type stub-loaded structure, as described in Appendix B and asshown in Fig. 6.

Fig. 7 shows the circuit topology of the carrier and peakingamplifiers with dual-band dc-feeds. Fig. 8 shows the perfor-mance of the carrier and peaking amplifiers at the two fre-quencies. Since the carrier and peaking amplifiers both havethe same architecture except the bias conditions, thus thetransconductance of the device is lower in the class C bias,resulting into less gain and less output power as compared tothe carrier amplifier biased in a class AB mode. The carrieramplifier is biased at drain voltage and current of 28 V and200 mA, respectively. The gate bias of the peaking amplifier is−5.1 V in order to operate in class C operation. The peak drainefficiencies of the carrier and peaking amplifiers are 66.1%and 67.0%, respectively, at 1960 MHz, as shown in Fig. 8(a).Similarly, in Fig. 8(b), the peak drain efficiencies of the peakingand carrier amplifiers can be obtained as 61.1% and 62.2%,respectively, at 3500 MHz. From these figures, the PAEs ofthe carrier amplifier can be calculated as 54% and 49.7% at1960 and 3500 MHz, respectively. Similarly, the PAEs of thepeaking amplifier are reported as 49.7% and 48.2% at 1960 and3500 MHz, respectively.

C. Dual-Band Phase Offset Line Design

In order to find the design specifications for the dual-bandoffset lines, the graphs similar to Figs. 2 and 3 are obtainedfrom the simulation of the carrier and peaking amplifiers. Fig. 9shows the output return loss of the designed peaking amplifier(without any offset line), which is represented as Γ(f1) andΓ(f2) at the two frequencies.

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4836 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 12, DECEMBER 2012

Fig. 7. Overall architecture of dual-band carrier and peaking amplifiers.

Fig. 8. Performance of the carrier and peaking amplifiers. (a) At 1960 MHz.(b) At 3500 MHz.

It can be seen from this figure that the approximate valueof phase offsets required to bring these impedances to highervalues are 55.84 and 159.68 at frequencies f1 and f2, respec-tively. Fig. 10 shows the measured phase response of the dual-band phase offset line.

Phase shifts of 58.87 and 163.2 at 1960 and 3500 MHz,respectively, are reported with this phase offset line.

In the presence of this offset line, the required high im-pedance is achieved at the output of the peaking amplifier at

Fig. 9. Design specifications and performance of phase offset line in thepeaking path in terms of output return losses of the peaking amplifier.

Fig. 10. Measured phase response of the dual-band phase offset line.

back-off. This fact can also be observed in Fig. 9, where theoutput impedance of the peaking amplifier is also measured inthe presence of this offset line.

Fig. 11 shows the S-parameter response of this dual-bandphase offset line. The insertion loss is less that 0.12 dB, and thereturn loss is better than 38 dB at both frequencies, confirmingthe characteristic impedance of 50 Ω for these lines.

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RAWAT AND GHANNOUCHI: DESIGN METHODOLOGY FOR DUAL-BAND DPA 4837

Fig. 11. Performance of dual-band phase offset line in terms of S-parameters.

Fig. 12. Performance of the carrier amplifier in terms of PAE at 6-dB back-offin the presence of phase offset lines in the carrier path.

Similarly, in order to obtain the required value of phaseoffset in the carrier path, a load-pull simulation of the carrieramplifier including the matching network is done at 6-dB outputpower back-off. These load-pull contours for PAE are shown inFig. 12. Thus, in order to bring 100 Ω to these optimum PAEpoints, dual-band offset lines with arbitrary phases are needed.

In our particular case, when a phase offset line that is thesame as the peaking path is inserted at the output of the carrier,it shifts 100-Ω load at back-off to the impedances correspond-ing to reasonable PAEs, i.e., 47.3% and 39.3% for frequenciesof 1960 and 3500 MHz, as shown in Fig. 12. However, in theabsence of this offset line, the 100-Ω load lies on the 32%and 36% PAE contours at frequencies of 1960 and 3500 MHz,respectively.

Fig. 13 shows the effect of these offset lines in the elec-tromagnetic simulation (EM) based performance of integrateddual-band DPA at 1960 and 3500 MHz. From these figures, itcan be inferred that the absence of the offset lines at 1960 MHzreduces the efficiency by approximately 9% at 6-dB back-off. Moreover, at 3500 MHz, the absence of offset line inthe peaking path reduces efficiency by approximately 7.8%,whereas the absence of phase offset line in the carrier pathreduces the efficiency by 3.4% at 6-dB back-off. The reductionof efficiency at back-off in the absence of carrier offset line is

Fig. 13. Effect of phase offset lines over the performance of the dual-bandDoherty amplifier. (a) At 1960 MHz. (b) At 3500 MHz.

more prominent at 1960 MHz as compared to the operation at3500 MHz as the PAE contours are much closer to 100 Ω in thelater case, as shown in Fig. 12.

Fig. 13 also shows the performance improvements in termsof gain in the presence of these offset lines at 1960 and3500 MHz, respectively.

V. EXPERIMENT AND DESIGN CONSIDERATIONS

In order to validate the proposed design architecture anddesign methodology, each component of the dual-band DPAis fabricated in Rogers RT 5870 board with dielectric constantof 2.33 and loss tangent of 0.0012. The substrate thickness is20 mil.

The photograph of the integrated DPA is shown in Fig. 14.Table I gives the physical design parameters of the carrier

and peaking amplifiers corresponding to the topology shownin Fig. 7. Table II lists various electrical and physical designparameters of the 50-Ω dual-band offset line calculated from thedesign equations. The physical design parameters are obtainedcorresponding to the electrical design parameters shown inFig. 3 using Agilent ADS Linecalc.

VI. RESULTS AND DISCUSSION

The fabricated dual-band DPA is measured for obtainingvarious specifications at different modes of operations.

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4838 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 12, DECEMBER 2012

Fig. 14. Photograph of the fabricated dual-band Doherty amplifier.

TABLE IDESIGN PARAMETERS FOR THE DUAL-BAND PA ELEMENTS

TABLE IIDESIGN PARAMETERS FOR THE DUAL-BAND PHASE OFFSET LINES

A. CW Single-Tone Operation

The fabricated dual-band DPA is measured in the presenceof continuous wave (CW) single tones at 1960 and 3500 MHzfed at its input individually. Fig. 15 shows the performanceof dual-band DPA in comparison with class AB balancedmode operation at 1960 and 3500 MHz. For the operation at1960 MHz, as shown in Fig. 15(a), there was an approximately

Fig. 15. Measured performance of dual-band Doherty amplifier. (a) At1960 MHz. (b) At 3500 MHz.

15.3% improvement in the drain efficiency compared to theclass AB balanced mode operation at 6.6-dB back-off. Thecorresponding PAE improvement is 10.7%. Fig. 15(b) showsthe measured performance of dual-band DPA in comparisonwith class AB balanced mode operation at 3500 MHz. Atthis frequency, the drain efficiency improvement was around10.2%, compared to class AB balanced mode operation at6.7-dB back-off, as shown in Fig. 15(b). The correspondingPAE improvement is 7.1% at this back-off.

Although the proposed dual-band DPA design is optimizedfor individual frequency operation, there is no theoretical limiton the concurrent operation of such a dual-band DPA.

However, it is worth discussing here that, due to the si-multaneous power fed at two carrier frequencies, the PA wassaturated faster; hence, it appears that PA performs at eachfrequency as it operates nominally at a 3-dB back-off (assumingthat both driving signals have equal power levels and that the PAhas the same gain at both frequencies), in comparison with itsoperation when driven by a single frequency signal. This back-off will be further enhanced if the PA has different gains at thetwo different frequencies.

Fig. 16 shows the concurrent operation of the fabricated dual-band Doherty amplifier. The peak drain efficiencies at satura-tion are 22.5% and 23.4% at 1960 and 3500 MHz, respectively,whereas the PAE is reported as 15.8% and 17.7% at 1960 and3500 MHz, respectively.

Page 9: Design Methodology for Dual-Band Doherty Power Amplifier ...dual-band Doherty power amplifier (DPA) with performance en-hancement using dual-band phase offset lines. In the proposed

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RAWAT AND GHANNOUCHI: DESIGN METHODOLOGY FOR DUAL-BAND DPA 4839

Fig. 16. Measured performance of dual-band Doherty amplifier in concurrentmode.

B. Modulated Signal Measurement

In order to test the designed dual-band DPA in the presenceof complex modulated signals, the output of the designed DPAis measured in the presence of a single-carrier WCDMA at1960 MHz and a 5-MHz WiMax signal at 3500 MHz, bothhaving a PAPR of 7 dB. Fig. 17 shows the average drainefficiency and adjacent channel power ratio (ACPR) measuredat 5- and 10-MHz offset and plotted with respect to the averagepower of complex modulated signals. This figure also showsa slight difference between the ACPR in lower frequenciesand at higher frequencies which corresponds to memory effectin the PA. Since the average efficiency depends on the prob-ability density function of the modulated signal [41], it hasslightly different values from the efficiency achieved at back-off in the CW excitation. The ACPRs are better than −34 and−31 dBc at 1960 and 3500 MHz, respectively. The averageefficiencies are 42.1% and 36.8% at 1960 and 3500 MHz,respectively. Fig. 18 shows the average efficiency and ACPRperformance in concurrent mode. It is clearly evident fromthis figure that, in a concurrent mode, the average efficiencyand ACPR performance is poor as compared to individualoperation at respective frequencies. This is due to the factthat the DPA saturates faster in simultaneous excitation bythe two signals, which also interact and result into lowerACPR performance. The average efficiencies are 16.9% and16.7% at 1960 and 3500 MHz, respectively, whereas the ACPRis better than −24.7 dBc at corresponding frequencies ofoperation.

In order to validate the use of the designed DPA in conjunc-tion to DPD, the designed DPA is linearized using memorypolynomial based DPD model.

Fig. 19 shows the linearized output of DPA in the presenceand absence of DPD.

These figures show that linearized output satisfies thespectral-mask requirements for WCDMA and WiMax signals.With the DPD linearization, there are corresponding 25- and20-dB improvements in terms of ACPR at 1960 and 3500 MHz,respectively.

Table III shows the comparison of the proposed dual-bandDPA design with the current state of the art. From this table,it can be seen that the proposed design architecture shows

Fig. 17. Measured average drain efficiency and ACPR with complex modu-lated signals. (a) One-carrier WCDMA signal at 1960 MHz. (b) 5-MHz WiMaxsignal at 3500 MHz.

Fig. 18. Measured average drain efficiency and ACPR in concurrent operationwith one-carrier WCDMA signal at 1960 MHz and 5-MHz WiMax signal at3500 MHz.

performance improvement in terms of efficiency as well as op-erating frequency range in comparison to some of the previousworks.

VII. CONCLUSION

An architectural solution for a dual-band DPA has been pro-posed using dual-band offset line for efficiency improvement.

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4840 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 12, DECEMBER 2012

Fig. 19. Output power spectral density of dual-band DPA measured in thepresence and absence of DPD. (a) WCDMA signal at 1960 MHz. (b) WiMaxsignal at 3500 MHz.

TABLE IIICOMPARISON WITH STATE OF THE ART OF

DUAL-BAND DOHERTY AMPLIFIER

In addition to this architecture, a novel design methodologyfor the dual-band phase offset line has also been described.Such dual-band DPA along with DPD is highly useful for SDRtransmitters in energy-efficient cognitive networks. The effectof utilizing the dual-band phase offset lines in the dual-bandDPA architecture is validated through the design, simulation,and measurement of a prototype.

APPENDIX

A. Polynomial Expansion of the Ratio of Two Sinusoidals

The ratio of two sinusoidals for a range of θS can beexpressed in a polynomial form as

sin(nθS)sin(θS)

=A0+A1θ2S +A2θ

4S +A3θ

6S +A4θ

8S +. . . . . . Akθ2k

S

(A1)where 0 < θS < 2π

n .Expanding sine series in each numerator and denominator of

(A1) and rearranging

nθS − (nθS)3

3!+

(nθS)5

5!− (nθS)7

7!+ . . .

=(A0 + A1θ

2S + A2θ

4S + . . .

)•

(θS − θ3

S

3!+

θ5S

5!− θ7

S

7!. . .

).

(A2)

Comparing each term of θS with the same order in (A2), thevalue of the coefficients can be obtained as

Ak =(−1)kn2k+1

(2k + 1)!+ (−1)k+1

k−1∑m=0

(−1)m Am

(2k − 2m + 1)!;

where k ≥ 0 m < k. (A3)

Since these coefficients in (A3) tend to be very small fora higher value of k, hence approximation up to five terms in(A1) is taken, which gives sufficient accuracy in calculating θS .Thus, if the ratio in (A1) is given, then θS can be obtainedby solving the polynomial expansion given in (A1) with thecoefficient values retrieved in (A3).

B. Dual-Band/Dual-Impedance Quarter-WaveTransformer Design

For a Pi-type structures with stub-loading at the edges asshown in Fig. 6, the following conditions together guaranteethat the structure will emulate 90 transmission line of charac-teristic impedance ZT [33], [35]:

BStub(f) =1

ZS tan θS(B1)

ZT (f) = ZS sin θS . (B2)

If ZT1 and ZT2 are the two required characteristic im-pedances of a dual-band/dual-impedance quarter-wave trans-former at two frequencies and n is the frequency ratio greaterthan 1, then using (B2), these characteristic impedances can beexpressed as

ZT1 = ZS sin θS @f1 (B3)

ZT2 = ZS sin nθS @f2. (B4)

Equations (B3) and (B4) can be solved simultaneously toobtain design parameters ZS and θS , as shown in Fig. 6 [35].These values are considered at frequency f1 while calculatingthe corresponding physical design parameters ws,m and ls,m,

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RAWAT AND GHANNOUCHI: DESIGN METHODOLOGY FOR DUAL-BAND DPA 4841

respectively, as shown in Fig. 7. Once these values are found,they are used to determine the design parameters for the shuntstub loading, depending on whether the stub is realized by anopen- or short-circuit transmission line. If ZP and θP are thecharacteristic impedances of the open-circuit transmission linerealizing the stub as shown in Fig. 6(a), these design parameterscan be obtained as [35]

Zp =ZT1ZS√Z2

S − Z2T1

tan θP @f1 (B5)

Zp =ZT2ZS√Z2

S − Z2T2

tan(nθP ) @f2. (B6)

The values of ZP and θP are obtained by simultaneouslysolving (B5) and (B6). Similarly, for the designer’s choice ofusing a short-circuit transmission line as stub, the electricaldesign parameters ZP and θP in Fig. 6(b) can be related forthe two frequencies of operation as [35]

Zp =−ZT1ZS√Z2

S − Z2T1

1tan θP

@f1 (B7)

Zp =−ZT2ZS√Z2

S − Z2T2

1tan(nθP )

@f2. (B8)

Equations (B7) and (B8) can be solved simultaneously toobtain the design parameters ZP and θP for the shunt stub tobe realized by a short-circuit transmission line.

The design parameters ZP and θP for the shunt stub areconsidered at frequency f1 while calculating the correspondingphysical design parameters wp,m and lp,m, respectively, inFig. 7. The input matching network in Fig. 7 utilizes the stub-loaded structure of Fig. 6(b), while the output matching networkof Fig. 7 is realized using the stub-loaded structure of Fig. 6(a).

ACKNOWLEDGMENT

The authors would like to thank J. Shelley and T. Bata fortheir technical assistance in manufacturing the prototypes; thereviewers and the associate editor for their suggestions andcomments, making this paper more technically informative andenhancing its readiness; and the members of iRadio Laboratory,University of Calgary, particularly R. Darraji, for the technicaldiscussions.

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Karun Rawat (M’08–S’09) received the B.E. de-gree in electronics and communication engineeringfrom Meerut University, Meerut, India, in 2002. Heis currently working toward the Ph.D. degree in theDepartment of Electrical and Computer Engineer-ing, Schulich School of Engineering, University ofCalgary, Calgary, AB, Canada.

He worked for the Indian Space Research Orga-nization from 2003 to 2007. After that, he joinedthe iRadio Laboratory, Schulich School of Engineer-ing, University of Calgary, where he is a Student

Research Assistant. He is also a Reviewer of several reputed journals in thefield of electrical engineering. His current research interests are in the areasof microwave active and passive circuit design, and advanced transmitter andreceiver architecture for software-defined radio applications.

Fadhel M. Ghannouchi (S’84–M’88–SM’93–F’07)received the B.Eng. degree in engineering physicsand the M.S. and Ph.D. degrees in electrical engi-neering from the Ecole Polytechnique de Montreal,Montreal, QC, Canada, in 1983, 1984, and 1987,respectively.

He is currently a Professor and iCORE/CRC Chairwith the Department of Electrical and ComputerEngineering, Schulich School of Engineering, Uni-versity of Calgary, Calgary, AB, Canada, and theDirector of the Intelligent RF Radio Laboratory. He

has held numerous invited positions at several academic and research insti-tutions in Europe, North America, and Japan. He has provided consultingservices to a number of microwave and wireless communications companies.He has authored or coauthored over 400 publications. He is the holder of tenU.S. patents, with three pending. His research interests are in the areas of mi-crowave instrumentation and measurements, nonlinear modeling of microwavedevices and communications systems, design of power- and spectrum-efficientmicrowave amplification systems, and design of intelligent RF transceivers andSDR radio systems for wireless and satellite communications.