avr400 service manual

5/20/2018 Avr400 Service Manual

1/34

AVR400 Service Manual Issue 1

Downloaded from www.Manualslib.commanuals search engine
http://www.manualslib.com/http://www.manualslib.com/


2/34

2

3

1

ITEM NO. PART No. DESCRIPTION QTY

1 TGP3523 / TGP3524 FASCIA ASSEMBLY BLACK / SILVER 1

2 TGP3526 / TGP3527 COVER BLACK / SILVER 1

3 HA4V06S TORX SCREW M4 x 6 4

80

5

5

TOLERANCES UNLESS 0.00 0.10

OTHERWISE STATED 0.0 0.20

ANGULAR TOL. +2 DEGREES

0 70 90

ALL DIMENSIONS IN

MILLIMETERS UNLESS

OTHERWISE STATED

20

6

DATE:

DRAWN BY:

1 3

F

4

CHECKED BY:

4

MATERIAL:

DRAWING TITLE

10

A

30

ORIGINAL SCA

FINISH:

8

50

2

2 87

6

SHT 1 OF 4

7

A & R CAMBRIDGE LTD

PART NUMBER AND DRAWING NUMBER

D

23425

60

E

100

1 3

B

C

40

DATE CHG. ZONE DESCRIPTION OF CHANGE

--

--

--

--

--

ECO NR.

--

--

--

--

-- --

--

--

--

-- --

--

--

--

--

--

--

--

--

--

AVR400 MAIN ASSEMBLY

COVER + FASCIA



3/34

1

2

3


1 TGP3539 TRANSFORMER - POWER 1

2 FAN 80 x 80 x 25mm 2

3 FAN MOUNTING BRACKET 2

80

5

5




0 70 90

ALL DIMENSIONS IN

MILLIMETERS UNLESS

OTHERWISE STATED

20

6

DATE:

DRAWN BY:

1 3

F

4

CHECKED BY:

4

MATERIAL:

DRAWING TITLE

10

A

30

ORIGINAL SCA

FINISH:

8

50

2

2 87

6

SHT 2 OF 4

7

A & R CAMBRIDGE LTD


D

23425

60

E

100

1 3

B

C

40


--

--

--

--

--

ECO NR.

--

--

--

--

-- --

--

--

--

-- --

--

--

--

--

--

--

--

--

--


FANS + TRANSFORMERS



4/34

1

4

2

3

5SOLDERED TO

POWER AMP PCB


1 TGP3534 CHASSIS ASSY 1

2 TGP3535 FRONT PCB ASSY 1

3 TGP3538 POWER AMP PCB ASSY 1

4 TGP3525 FOOT ASSY 4

5 TGP3540 TRANSFORMER - STANDBY 1

80

5

5




0 70 90

ALL DIMENSIONS IN

MILLIMETERS UNLESS

OTHERWISE STATED

20

6

DATE:

DRAWN BY:

1 3

F

4

CHECKED BY:

4

MATERIAL:

DRAWING TITLE

10

A

30

ORIGINAL SCA

FINISH:

8

50

2

2 87

6

SHT 3 OF 4

7

A & R CAMBRIDGE LTD


D

23425

60

E

100

1 3

B

C

40


--

--

--

--

--

ECO NR.

--

--

--

--

-- --

--

--

--

-- --

--

--

--

--

--

--

--

--

--


POWER PCBs + FEET



5/34

1

2

4

5

6

3

7ITEM NO. PART No. DESCRIPTION

1 TGP3528 REAR PANEL ASSY

2 TGP3536 INPUT PCB ASSY - MAIN

3 TGP3536 (part) INPUT PCB ASSY - ETHERNET

4 TGP3536 (part) INPUT PCB ASSY - CONNECTOR

5 TGP3537 HDMI PCB ASSY - MAIN

6 TGP3537 (part) HDMI PCB ASSY - VIDEO

7 TGP3529 / TGP3530 AM/FM TUNER EU / US

80

5

5




0 70 90

ALL DIMENSIONS IN

MILLIMETERS UNLESS

OTHERWISE STATED

20

6

DATE:

DRAWN BY:

1 3

F

4

CHECKED BY:

4

MATERIAL:

DRAWING TITLE

10

A

30

ORIGINAL SCA

FINISH:

8

50

2

2 87

6

SHT 4 OF 4

7

A & R CAMBRIDGE LTD


D

23425

60

E

100

1 3

B

C

40


--

--

--

--

--

ECO NR.

--

--

--

--

-- --

--

--

--

-- --

--

--

--

--

--

--

--

--

--


REAR PANEL + PCBs



6/34

AVR400 Power Amplifier Circuit Description

Apart from the power transformer, the power amplifier electronics is fully contained on the large

double sided PTH PCB and heatsink located at the bottom of the AVR400. This is called the Main Board

on the schematic diagrams (pages 11 and 12). The Main Board also contains the mains input circuitry, in-

cluding the safety fuses and standby power transformer, so great care should be exercised when probing this

area of the board.

Note that some small surface mount components are soldered to the underside of this PCB.

The 7 power amplifiers are identical in terms of circuitry, although necessary compromises in the physi-

cal layout may give rise to slight differences in measured noise, crosstalk and distortion performance.

The two channels at the extreme ends of the heatsink have less radiating area available to them and will

run hotter under load this is not normally an issue as these are assigned to the SBL and SBR channels.

Looking from the rear of the AVR, facing the flat face of the heatsink, the channel order is SBR, SR, FR,

C, FL, SL and SBL, the same order as the loudspeaker terminals. The SBL and SBR channels can also be

assigned to zone 2 or as duplicates of the FL and FR channels for when passively biamping the main

stereo loudspeakers. In this latter condition we recommend assigning the SBL and SBR outputs to the

tweeters of the FL and FR speakers, in order to minimize the power amplifiers heat dissipation.

Note that the 8 pre-amplifier outputs are also on this PCB apart from SUB their phono sockets are

effectively in parallel with the power amplifier inputs, which are fed from the Input Board via a ribbon

cable and CON103. This connector also carries 5 power supply and power amplifier control signals to

and from the system microprocessor (P) IC151 situated on the Input Board above the Main Board.

The amplifiers power supply is provided from a centre-tapped secondary winding on the toroidal

power transformer, via the connector BN508, to the bridge rectifier D5830. This is mounted on a

small PCB near the top of the heatsink. The rectified AC is then sent to the main PCB via connectors

BN581/582. To avoid induced hum and distortion it is important to keep these cables twisted tightly

together and well away from the actual power amplifier circuitry. The main 15,000F 80V reservoir

capacitors, C835 and C836, are positioned on the main PCB well away from the power amplifier inputtraces and close to the system star ground. The smoothed DC is fed to the power amplifiers Vcc and

Vee lines near the centre of the heatsink via a twisted-pair cable, again to minimize induction into the

power amplifiers. Vcc and Vee are typically +/- 52V at 234VAC with no signal. Q5845 sends a fraction of

Vcc to the muting control on the Input Board.

The FL (front left) channel will now be described in detail.

The input stageis a long tailed pair Q5101 and Q5102, with local degeneration provided by R5105 and

R5107. The tail is fed from the negative rail via an approx 3mA ring-of-two constant current source,

Q5109 and Q5110. R5101 and C5101 at the input provide high frequency rolloff and help keep residual

DAC ultrasonic noise above 100kHz out of the power amplifier. DC blocking is provided by C5102 atthe input and C5107 in the feedback loop so that the whole power amplifier has unity gain at DC. The

midband AC gain is 22000/680 = 32.35 after allowing for the attenuation provided by R5101 and R5102.

Thus 875mV at the input produces 100W into 8 ohms at the output.

The long tailed pairs collectors are loaded by a current mirror, Q5103 and Q5104. The resistors R5103/4

and R5105/6 are 1% tolerance to minimize even order distortion. The collector of Q5101 also feeds the

Darlington class A voltage amplifier stage (VAS)made up of Q5115 and Q5116. Q5113 is loaded by the

output stage and the 8mA constant current source made up by Q5125 and Q5126. The amplifiers main

frequency compensation network (for stability) comprises C5115 plus the combination of C5116 and

R 5115. This adds gain inside the loop (two pole compensation) at high audio frequencies so that the



7/34

additional feedback further reduces high frequency distortion and crossover distortion within the audio

band.

These stages are partially decoupled from the Vcc and Vee power supplies by D5130/R5130/C5130 and

D5129/R5129/C5129 respectively. They are also bootstrapped to the amplifier output via the networks

R5118/C5128/R5128 and R5117/C5127/R5127. This raises the supply lines by approximately 3V at full

output to avoid clipping the driver stage prematurely.

The output stage comprises classic complementary emitter followers Q5150/Q5170 (NPN) and Q5160/

Q5180 (PNP). The On Semiconductor output transistors have a current gain that is sustained to about

10 amps and a very large safe operating area, which allows the amplifiers to drive low impedances well.

They also have built-in thermal compensation diodes which helps stabilize the quiescent current both

statically (when hot) and dynamically (when playing music at high level) this minimizes crossover

distortion and improves sound quality.

The output stage biasing is performed in the network around the amplified diode Q5120, which is

mounted in intimate thermal contact with the driver transistor Q5130, plus the two built-in diodes

associated with the output transistors. The thermistor R5122 is positioned on the PCB close to the

heatsink and provides extra downward compensation at very high temperatures. Bias is set by VR51 and

is largely independent of temperature it should be set to16-20mV when measured across the outer

terminals of the compound emitter resistor R5175, using the 2 pin connector CN51, 5 minutes or more

after the AVR400 is powered up.

The power amplifier output is routed across the PCB to the back panel. It includes a Zobel network

(sometimes called a Boucherot cell) R5183/C5183 and a series inductor L5185 damped by a 4.7R 2W re-

sistor R5184. These components help isolate the amplifier from reactive loads to ensure high frequency

stability. One half of the normally-off relay RL52 is used to switch the load in and out.

Each power amplifier is protected against overload in a number of ways. The complementary transistors

Q5130 and Q5131 protect the NPN half of the output stage and Q5140 and Q5141 the PNP half. They

operate as Sziklai pairs, passing negligible current until a threshold voltage of approx 600mV is reached

across R5132 and R5142. Between 600 and 700mV the pairs then ramp up current smoothly, diverting it

away from the bases of Q5150 and Q5160 to limit the output stage drive to a safe level, within the power

transistors SOA (safe operating area). The 600mV threshold voltage depends upon both the instantane-

ous current and voltage across the output transistors, set by the networks R5132/R5136/R5137/R5138/

R5175 for the top half and R5142/R5146/R5147/R5148/R5175 for the bottom half. R5135/R5145 and the

zener diodes D5135/D5145 change the slope of the protection locus at high Vce voltages. R5134/R5135

plus C5134/C5145 prevent fast transients and brief overloads from prematurely triggering the protec-

tion.

The above dual slope SOA protection is self resetting but if a gross overload persists for more than a

second or two (such as when a channels output is short circuited with music playing at a moderate to

loud level) then the open collector transistor Q5181 sinks current for long enough to initiate the ampli-

fiers full shutdown procedure via the line SOA_PROTECT. This can also be triggered by a total output

stage failure (which passes enough current through R5175 to turn on Q5188) via OVERLOAD or by an

excessive DC offset at the output terminals (via R5185) via V_DET. All these signals, and others, feed into

the protection module, described below.

Theprotection modulecomprises 8 transistors and associated parts positioned at the back of the PCB

near the preamplifier output sockets. It has a single output line named PROTECT which, when pulled

down from Vcc to ground, instructs the system P IC151 to shut down the whole amplifier. This occurs

when any of the following events happen:



8/34

1) Any amplifier channel pulls current through the SOA_PROTECT line for long enough to charge

up capacitors C5871 and then C5872 so that Q5874 turns on.

2) Any amplifier channel pulls current through the OVERLOAD line for long enough to charge up

C5882 and turn on Q5882 and thus Q5884.

3) Any amplifier channel has a large long term (DC) offset (typically greater than +/-3V) sFficient

to charge up C5861 enough to turn on either Q5862 (positive offset) or Q 5864 (negative offset).

These then turn on Q5863. N.B. This circuit is also used to detect imbalances in both the Vcc/Vee

and +/-15V power supplies (the latter is generated on the Power Supply board).

4) When the PTC thermistor TH585 mounted at the top centre of the heatsink gets sFficiently hot

(around 100C) and thus high resistance enough to cause Q5855 to turn on via the +12V supply.

Intermediate temperatures will not activate PROTECT but will provide signals to the level detec-

tors associated with the FAN_1 and FAN_2 lines, to run the cooling fans at high or low speeds

respectively.

Note that the fans 12V supply is gated via Q5909 and Q5911. This means the fans will not run when

no signal is present on the FL, C or SR channels, so that during quiet passages no fan noise should be

audible.

AVR400 Main Power Supplies Circuit Description

The main DC power supplies are located on the Power Supply Board - a double sided PTH PCB adjacent

to the Main Board. Note that the mains input switching, mains fuses, standby power transformer with

its associated unregulated DC supply and the relay for enabling the power amplifier supply rails are

located on the Main Board. The two boards communicate via CON501.

Considering the Main Boardfirst, the mains voltage switching uses a double pole double throw slide

switch accessible from the back panel. One pole addresses the standby transformer and the other the

toroidal power transformer. Ensure the switch setting matches the supply voltage before switching on theAVR400.Nominal settings are 115 and 230V +/- 15%. The 20mm 115V fuse in line with the toroidal trans-

former is rated at 15A T (Time delay) and the 20mm 230V fuse is rated at 8A T.Always replace these fuses

with the same type and value.The standby transformer T5941 is not fused but is designed to go open

circuit in case of overheating (e.g. if left connected to a 230V supply for longer than a few minutes when

the mains voltage selector is set to 115V).

The standby transformer generates approximately +9V DC via the bridge rectifier diodes D5495/6/7/8

and the 1,000F reservoir capacitor C5947.This is sent via pin 7 of CN501 to the Power Supply PCB

(confusingly marked as 5V). The rail voltage is also routed to the system microprocessor (P) via D5965/

R5965 and pin 6 of CN103 as POWER_MUTE.

The 5V relay RY594 is normally open. When the mains switch is closed then the SUB_POWER rail (approx

+4.3V) is activated from the Power Supply PCB via the standby transformer. When the system has

booted correctly, without any shutdown signals, then the POWER_RELAY signal from the system P also

goes high, pulling down Q5947 hard. Only then does the relay close and switch on the main toroidal

power transformer, enabling the rest of the system to boot up.

Now consider the Power Supply Board, found on page 14 of the schematic.Thisgenerates all the main

DC supplies for the AVR400 except +Vcc and -Vee for the power amplifiers and the non-logic part of the

VFD display requirements of the Front Panel Board. Note that additional local regulation also takes place

on the other PCBs, e.g. for large digital ICs.



9/34

Two secondary windings from the toroidal power transformer are fed in via CN63. Pins 1, 2 and 3 con-

nect to a centre-tapped secondary winding used to generate approx +/- 20VDC via the bridge rectifier

diodes D603/3/4/5 and the 2,200F 35V reservoir capacitors C609 and C610. R603 and R604 are 0.47R 1W

fusible resistors for circuit protection if they fail replace only with the same type and value.

The 3 terminal regulators IC63 and IC62 are mounted on two of the larger heatsinks near the back of the

amplifier. These provide +/-15V to the op amps on the amplifiers Input Board via the 11-way connector

BN62. The Input Board also then routes the +/-15V onwards to the Front Panel Board.

Pins 4 and 5 of CN63 receive AC from another transformer secondary to generate approx +15VDC via the

heatsink mounted bridge rectifier D601 and the 18,000F 25V reservoir capacitor C631. F601 and F602

are hard wired 6.3Amp T (time delay) fuses for circuit protection if they fail replace only with the same type

and value.

This +15V unregulated supply has 4 main outputs:-

1) It is regulated down to +12V with the low dropout (LDO) 3 terminal regulator IC64. This is situ-

ated on the heatsink closest to the Main Board, near the back panel. Its output goes to BN62 for

the +12V triggers and also to CN501, to drive the power amplifiers cooling fans.

2) It supplies the HDMI Board via CN61. To minimize ripple currents in the ground return, Q643 iswired as a low dropout voltage follower with low pass filtering via R650 and C569.

3) It feeds the switched mode buck regulator IC61 via L631 and C615. The tank circuit comprises

L632, C640 and C641, discharged via D631. R636 and C643 make up a snubber to reduce over-

shoot. This provides a high current +5V supply to the Input Board via pins 4 and 5 of BN62. This

5V supply also feeds two 3V3 linear regulators, IC67 and IC68. These in turn supply the audio DSP

ICs on the Input Board via pins 10 and 11 of BN62.

4) It feeds the +5V 3 terminal LDO regulator IC66 via the diode D616, which itself is preceded by the

smoothing network comprising R615 (2W 15R) and C615. Note IC66s output is actually approx

+5.7V because of D644 in its ground line; this is brought back to +5V after D643, to feed the relay

IC66 is noteworthy because it continues working when the amplifier is in standby.

It takes a second input from the +9V standby power supply on the Power Amplifier PCB D616 acts as a

gate to prevent this from feeding back to the +15V supply when the system is in standby. It also allows

the +15V supply to override and remove the load from the +9V supply when the amplifier is fully booted

up.

D606 and D607 form half of a second bridge rectifier (with the other two diodes coming from the full

bridge rectifier D601). These diodes charge up the 1F/50V capacitor C604 to +15V, generating a mains

power present signal. The 10K resistor R614 in parallel with C604 continually discharges it so that this

signal effectively disappears within about 50 milliseconds of the mains being switched off. This +15V

goes to the Main Board via pin 8 of BN62, where it is used as a pull up signal to help control the vari-

ous audio muting circuits.

AVR400 Front Panel Board Circuit Description

The Front Panel Board is a double-sided PTH PCB. It contains the VFD (Vacuum Fluorescent Display) and

its associated electronics, plus the keyboard, power status LED, IR remote receiver and headphones

amplifier. A daughter board carries the front panel I/O socketry. See page 1 of the schematic diagram.



10/34

It communicates with the Input Board via CN101 and a 31 way ribbon cable. Other connectors comprise

CN94 which connects to two secondaries of the main power transformer and the hard wired BN93

which connects up the daughter board.

There are two associated break off boards. One houses the front panel mounted single pole mains

switch plus its suppression capacitor C901 and a connector BN502. The second is mounted on the

power amplifiers heatsink and is used to route power to the cooling fans and also to guide the 31 way

ribbon cable.

The VFD draws AC filament power from a centre tapped winding of the power transformer connected

to pins 1, 2, and 3 of CN94. The centre tap connects to ground via the zener diodes D901/2 and C903

to provide the filament with its required DC offset. Pins 4 and 5 connect to a relatively high voltage

transformer secondary which is half wave rectified by D916 and smoothed by C907 and C960. The zener

diodes D903 and D904 in series with R906 generate +40V which is then coupled to the emitter follower

Q901 to provide a nominal regulated 40V HT power rail for the VFD.

The VFDs internal driver IC and external data bFfer IC901 run from the main +5V supply generated in

the Power Supply board and routed onwards through the Input Board. The drive signals (data, clock,

chip select and reset) come directly from the system microprocessor via CN101.

The 12 front panel switches are arranged in 2 blocks of 6 with resistive divider chains connected to two

ADC inputs on the system micro. These have 10K pull-up resistors at the system P end to complete the

potential divider chains. The pnp switching transistors Q906 and Q907 turn on the 3V3 supply from the

system P via another 10K pull-up resistor at the P end to provide interrupt control.

The power status LED D905 is a tri-colour type. The green side indicates power on and the red side

standby. A high signal on the LED net turns on Q902 and Q903. This turns off the npn Q913 to disable

the red LED and turns on the pnp Q912 to enable power to the green LED. The reverse is true when the

LED line is low. Pulling the STB(LED) line low when the LED line is also low powers both LEDs and gives

a yellow light to show when the unit is booting up. Note that the power supply is STBY+5V to allow the

red LED to operate in standby mode.

RC901 is a Kodenshi KSM603TH5B encapsulated infra red receiver for processing commands from an

external IR remote control. It is designed to work with the 36-38kHz carrier frequencies associated with

the Philips RC5 protocol. Note that it operates from the ST+5V rail to enable the AVR400 to be woken up.

It does not demodulate the IR this is done by the system microprocessor.

The headphones amplifier IC902 drives external headphones directly via the 330F series capacitors

C935 and C936. IC902 has a gain of about 4, meaning that the headphones output will be about 4V rms

when the volume control is set to clip the L and R main power amplifiers (equivalent to about 120WPC

into 8 ohms). IC902 is a JRC NJM5556AL capable of driving 7V rms into150 ohm loads and about +/-

100mA peak current into lower impedances. Mute transistors Q904/905 in series with 100R resistors are

fitted in front of its input to minimize switching transients and it is powered from the +/-15V suppliesgenerated on the Power Supply Board.

The L and R headphones outputs go via BN93 to the Headphones Board, after passing through relay

RL902 which is normally off. A positive voltage from the P at the emitter of pnp Q911 turns on Q911

and generates the same positive voltage at the base of the npn transistor Q909. Because its emitter is

connected to the -15V rail this pulls the relay on.

The FRONT AUX and MIC inputs come from the Headphones Board and through the microphone relay

RL901. When the relay is off the AUX line level L and R signals are switched through to the unity gain

bFfer IC904 and then on to the Input Board via pins 3 and 1 of CON101. When the relay is closed (in



11/34

the same manner as described above for RL902) then the L front input is routed to the low noise micro-

phone amplifier IC903. This operates as two cascaded virtual earth amplifiers, each with a voltage gain

of approximately 21 (R961/960 and then R965/962). Note the MIC line is biased at +6V via resistors R956,

R957 and R958. The amplified signal is output to the Input Board on pin 5 of CON101.

AVR400 Input Board Circuit Description

The Input Board comprises a 4 layer PCB; this is attached directly to the back panel via its various sock-

ets and to the heatsink by two steel brackets. It is positioned underneath the HDMI Board and abovethe Main Board. 5 ribbon cable sockets connect it to the other 4 boards. CN71 connects it to a daughter

board containing two 9 Pin D socket connectors (an RS232 serial port and an iPod dock interface), plus

two 12V trigger sockets and 2 IR receiver sockets. Note some passive components are mounted on the

underside of the PCB.

The Input Board circuitry is shown on pages 2 5 of the schematic diagram.

Page 2 covers the analogue inputs, volume control and line level outputs.

Page 3 covers the SPDIF (digital) inputs, clock recovery, audio DSPs and the codec (stereo ADC plus

8-channel DAC).

Page 4 covers the system microprocessor and a slaved support microprocessor

Page 5 covers interfaces to the DAB/Ethernet module, and the boot loader microprocessor used to

update the system SW via USB.

Analogue inputs, volume control and outputs

IC101 is a Renesas R2A15218FP analogue multiplexer and volume control, with a gain range of +42 to

-95dB in 0.5dB steps. It is digitally controlled from the system microprocessor via the I2C bus on pins 49

and 50. A high logic signal on pin 51 enables the system mute. IC101 has +/- 7V supplies generated fromthe +/-15V rails with the regulators IC102 and IC103.

All stereo external line level inputs using phono sockets are routed to IC101 via 100R/220pF low pass

CR filters. IC101 also handles the AUX-L, AUX-R and the (mono) MIC_SIGNAL setup microphone inputs

coming from the front panel, plus the internal stereo outputs from AM/FM tuners (TUN-L and TUN-R)

and the DAB/ethernet receiver (VENICE_L and VENICE_R). IC101 additionally switches two multichannel

signals - the 8 channel direct input and the outputs from the 8 post-DAC filters. Note that the +/- 7V

power supply limits the input signals to approximately 4V rms before overload occurs.

The post-DAC filters comprise 4 low noise NJM2068 dual op amps, running from the +/- 7V supplies.

One op amp is assigned to each channel and performs the dual functions of converting a differentialinput from the DAC to a single ended output, whilst simultaneously functioning as a three pole 50kHz

active filter.

The AM/FM tuner modules outputs pass through the inductors L310 and L302 (providing 19kHz notch

and 38 kHz low pass filtering) and the shunt mute circuits formed by the 330R resistors R354/R369 and

the two halves of Q306 plus Q307.

IC101 has a fixed level stereo output for Zone 2 (SUB_L and SUB_R) and a second one, adjustable from

0dB to -18dB in 6dB steps, for the AVR400s analogue to digital converter (ADC_L and ADC_R).



12/34

IC101 has one 8 channel variable level output bus labelled VOL01 through to VOL08. Capacitors C295-8

and C231-4 float the ground ends of the associated internal potentiometers to minimize clicks This bus

goes via specially selected 100F/25V capacitors to the dual op amps IC121-124, wired as voltage follow-

ers and running from the +/- 15V supplies. The C, SL, SR, SBL and SBR outputs are shunt muted when

required via the 560R resistors R383-388 and the dual transistors Q303-305.

The subwoofer output SW has two shunt mute circuits. One using Q311 works in parallel with the rest of

the channels. The other, using Q308 and half of Q303 allows muting of the SW channel alone.

The FL and FR channels take off the stereo headphones amplifier feed from IC121 (it goes via the con-

nector WF101 to the Front Panel Board), then add an extra dual voltage follower IC125 and a double

pole shunt mute switch using 4 x 270R resistors and Q301-302. All the above ICs are JRC NJM2068s or

equivalent.

All 8 of these outputs go to via the connector WF103 to the preamplifier output sockets and (except for

the subwoofer output) to the 7 power amplifier inputs located on the Main Board.

The ADC input amplifiers use a JRC NJM2068 for each channel, operating as a single-ended input to

differential output converter, with HF filtering above about 400kHz. This is sFficient for anti-aliasing

purposes as the analogue modulator of the ADC samples at 6.144 MHz and only needs to keep out

frequencies above 6MHz.

The array of 12 switching transistors in the bottom right hand corner of the schematic is arranged in

4 blocks of 3 devices (two npn and one pnp per block). The array is used to control the muting of 4

specific groups of audio outputs, taking into account the presence of AC mains via P_U (the pull up line

from the Power Supply board) and the MUTE_POWER line derived from the power amplifiers Vcc rail

this is normally high when Vcc is high. The output lines are SB_MUTE2 (for the surround back chan-

nels SBL and SBR), ZONE2_MUTE2, HP_MUTE2 (for the headphones relay on the Front Panel board) and

FUNC_MUTE2 (for the 6 main audio channels excluding SBL and SBR).

Zone 2 volume is independently adjustable in 1dB steps via IC131 (rohm BD3812F). Its outputs are

bFfered and amplified 15dB by the dual op amp IC132 and can be muted when required by Q402. Theoutput goes directly to two phono sockets forming half of JK11 on the back panel.

SPDIF inputs, ADCs, DACs and Audio DSPs

The AVR400 has 4 coaxial 75 ohm SPDIF (Sony/Philips Digital InterFace) inputs and 2 TOSLINK optical

inputs on its back panel. A further optical input is located on the front panel as part of JK92 (this socket

also includes the AUX and MIC inputs). There are 6 further external SPDIF inputs - one per HDMI input

socket and one on the HDMI output socket (the Audio Return Channel or ARC).

Each of the 4 coaxial inputs is bFfered by two NOR gates, contained in IC159 and IC160, before being

switched by one half of the dual 4 input multiplexer IC147. The output on pin 7 is then sent to the 8

input multiplexer IC140. Its other 6 inputs comprise the 3 optical receivers already mentioned, the HDMI

input (multiplexed down from 5:1 on the HDMI board), the HDMI ARC and the output of the Venice 6

DAB/Ethernet module. The 8thinput is unused. The output MUX_SPDIF is sent to the SPDIF receiver

IC153.

IC153 is a Wolfson WM8804 run in hardware mode. It uses X707 to generate its own 12MHz internal

clock. IC153 automatically identifies and dejitters incoming SPDIF signals with sample rates of 32kHz,

44.1kHz, 48kHz, 88.2kHz, 96kHz and 192kHz. Its output, still in SPDIF format, WM_SPDIF, is sent to pin 43

of the system codec IC143.



13/34

IC143 is the Cirrus Logic CS42548. It includes an SPDIF receiver, 2 channel ADC and 8 channel DAC. Only

one input (pin 43) of the SPDIF receiver is used; the others are grounded.

IC143 has +5V analogue supplies, locally decoupled to analogue ground by C721/722 for VA (pin 24)

and C703/704 for VARX (pin 41). The digital supply is also +5V, decoupled to digital ground by C705/706

(pin 5) and C750/756 (pin 51). The control port power VLC (pin 6) is 3V3, decoupled to digital ground by

C752/773 and the serial port power VLS (pin 53) is also +3V3, decoupled to digital ground by R726 and

C753/754. The 3V3 is generated from the +5V supply by the linear regulator IC148.

The system master audio clock is generated by IC143 on pin 55 whenever an SPDIF signal is present (i.e.

in all cases except when an HDMI multichannel signal in I2S is required to be processed or when using

the ADC). Although IC143 has no jitter rejection below 20kHz its master clock is kept clean from incom-

ing jitter by IC153. The PLL filter is located at pin 39. When SPDIF is not in use IC143 inputs its clock on

pin 59 this can be 24.576 MHz from the crystal oscillator X701 associated with DSP1 when ADC mode is

engaged, or the recovered clock from the HDMI Board. This is switched by the 4 way change over mul-

tiplexer IC145 on pins 9, 10 and 11. IC145 also routes IC143s recovered master clock or the HDMI master

clock to DSP1 on pins 5, 6 and 7.

Pins 1, 62, 63 and 64 receive the 24 bit serial audio data that has been processed by the DSPs.

The DACs 8 analogue outputs are in differential mode, so making 16 output lines in total, from pins

20-23 and 26-37. These feed the post-DAC filters IC111-114, described above.

The main audio DSP is a Cirrus Logic CS 497024, IC141.This is a 300MIPS dual core 32 bit fixed point DSP,

with 72 bit accumulators. The first core is used for decoding standard and high definition audio formats

(Dolby, DTS etc) and the second is reserved for post processing such as bass management, delay and

room correction. The secondary DSP, IC142, is a Cirrus Logic CS49DV8, responsible for the Dolby Volume

processing. IC141 gets the 1.8V for its core from the 3-terminal regulator IC149. IC142 gets its 1.8V from

IC150. The 3V3_1 and 3V3_2 supplies for these regulators are generated on the Power Supply Board.

IC141, 142 and 143 communicate with the system microprocessor via an SPI bus. For IC141 and IC142

the chip select lines are on pin 6, the clock is on pin 126, the MISO line on pin 124 and the MOSI onpin 123. For IC 143 the corresponding pins are pins 10, 7, 8 and 9. Note that the 3 chips receive data on

a common line but transmit to the P on two separate ones (DSPDATA for both DSPs and D_OUT for

IC143).

IC141 communicates with its external memory via a 36 line data bus running at 150MHz. This is needed

when providing lip sync delay for audio accompanied by video. IC144 is a 200MHz 16Mbit SDRAM, or-

ganized as 512Kbits x 16bits x 2. It is powered from the boards 3V3 line via 6 pins, with local decoupling

provided by C758-763.

The DSPs programs are stored in two external 3V3 SPI flash memory chips IC106 (8Mbit) for IC141 and

IC107 (4Mbit) for IC142.

IC141 has two sets of I2S data inputs. DAI (pins 23, 24, 26, 27 for data, pin 29 for the system clock and pin

30 for the LR clock) is for up to 8 channels from the HDMI Board via connector WF104.

DA2 (pins 32 for the LR clock, 33 for system clock and 34 for data) is for audio from the codec IC143. This

includes bitstream SPDIF such as Dolby Digital, uncompressed two channel I2S audio decoded from

SPDIF and ADC generated I2S two channel audio.

The DSP master clock is input on pin 40 of IC141 from pin 9 of IC145 as noted earlier.



14/34

IC141 also has two sets of I2S data outputs. DA1 is an 8 channel I2S signal (pins 47, 48, 49 and 51) shown

as part of the bus DA0(04:07). This feeds the input of the second DSP IC142 (on pins 23, 24, 26 and 27).

The system clock is on pin 52 of IC141 and the LR clock on pin 54. These go to pins 29 and 30 of IC142.

DA2 is a stereo I2S output (pin 43 for data, pin 44 for the system clock and pin 46 for the LR clock). This

feeds the HDMI board via WF104 and the octal bus switch IC146. The DSP master clock output from

pin 9 of IC145 follows the same route. An SPDIF output from pin 35 of IC141 goes directly to pin 12 of

WF104.

There is one set of 8 channel I2S outputs from IC142 DA1 (pins 47, 48, 49 and 51). These form part of

the data bus DA0(00:03) where they are routed back to the DACs in IC143 (pins 62, 64, 63 and1 respec-

tively). The I2S system clock and LR clock (pins 52 and 54) also go directly to IC143 (pins 2 and 3).

System Control Microprocessors

There are 3 microprocessors on the Input Board, the main, the sub and the USB micro. The latter is also

kept separate in order to perform upgrades over USB.

The AVR400s main system microprocessor IC151is a Toshiba T5CN5 microcontroller. This has an ARM

Cortex 3 core with 512KB of ROM and 32KB of flash memory. It is a 3V3 part, with this power supplybeing derived from the main 5V supply via the 3-terminal regulator IC156. It has a 40MHz system clock

derived from crystal X702 and a real time clock from the 32.768 kHz crystal X708.

IC152 is a 32Kbit EEPROM for retaining system settings at power down.

IC155 is a MOSFET switch to enable the HDMI CEC (Consumer Electronic Control) bus when the unit is

powered up, and to isolate the parts of the bus external to the AVR400 when it is powered down.

IC151 has several sets of comms busses - SPI, I2C and UARTs - depending on which system or peripheral

ICs are being addressed. SPI (Serial Peripheral Interface) is a fast 3-wire interface (clock, transmit and

receive) with chip select being addressed by individual I/Os. I2C (Inter Integrated Circuit) is a relatively

slow bidirectional 2-wire interface, with open-collector/source clock and transmit/receive busses, each

with a pull up resistor, and a limited number of embedded chip addresses. UART stands for Universal

Asynchronous Receiver/Transmitter and is a form of bus that takes bytes of information and turns them

into serial data on a bus before reassembling them into bytes at the other end.

SPI is used to talk to the codec IC143 and the two DSPs IC141 and IC142.

I2C is used for both the main and zone 2 volume controls IC101 and IC131. I2C also connects to the sub

micro IC154 and to the NJW1321 video input decoders IC81 and IC81.

IC151s UARTs are used for USB Tx/Rx, the Torino (video processor) Tx/Rx and the external RS232 Tx/Rx.

Further UARTs on the sub micro IC154communicate with the Venice 6.2 DAB/Ethernet receiver and

the iPod external interface. IC154 is a Toshiba M333FWFG ARM Cortex 3 microcontroller with 128K ROM

and 8K of flash, effectively used as a helper for IC151. Its 3V3 power supply regulator IC158 runs from the

boards main 5V supply.

The USB micro (Bolero)IC162 is a Toshiba TMP92FD28FG, a 32-bit CISC microcontroller with a built-in

USB2 host controller capable of supporting 12Mbps. Its primary function is to provide a bullet-proof

system updating process via an external USB stick. When the AVR400 is powered up IC162 first self

boots, then interrogates the rest of the system if it receives the wrong response (e.g. if a previous

update failed part way through) then the unit will appear dead. However IC162 will be constantly inter-



15/34

rogating the USB socket and insertion of a clean USB stick containing only the system firmware will

initiate a complete recovery automatically.

IC164 is a MiniLogic ML61C282PR precision voltage detector, with a threshold of 2.8V, built in hysteresis

and a CMOS output, used to reset IC162 at power on.

IC163 is an Intersil USB switch, type ISL54220, which routes the USB socket on the rear panel either to

the Venice 6.2 module, for normal audio applications, or to IC162 when the system SW is being up-

graded from a USB stick. Note that it is positioned underneath the Venice 6.2 module, close to the USB

socket.

The USB high side power switch IC168 is close to IC163. It is a Richtek RT9702A fed from the main +5V

power supply. It is rated at 1.1 amps output and can flag up a fault condition on the USB bus from pin 3;

this is routed to IC162.

The Frontier Silicon Venice 6.2WB moduleis plugged into the input board via a 64 way connec-

tor CN62. This WB version of the module supports Band 3 DAB/DAB+ digital radio for use in Europe,

Australia, Canada, Korea and other Digital Radio markets. It also supports USB2, and Ethernet up to 100

Mb/s, enabling the AVR400 to be a network audio client. A spare copy of the AVR400s unique MAC

(Media Access Controller) address can be found on the screening can of the Venice 6.2 module. Its FM

radio function is not used.

The Venice 6.2 is operated in slave mode via the UART pins 9 and 10 on CN62. These connect to the sub

micro IC154. The USB I/O signal pins are 11 and 12, routed to the USB switch IC163. The other USB pins

are not used. Pins 26, 27, 28 and 29 make up an SPI bus to work with the Ethernet PHY IC161 (pin 33

receives interrupts from IC161).

Audio is decoded inside the Venice 6 (i.e. from AAC, FLAC, MP3, WMA or WAV) and sent out by two

routes. Pin 32 carries an SPDIF signal (at 48ks/s) for the main system and pins 64 and 63 carry L/R linear

audio for zone 2 to the volume control IC101.

The Venice 6.2 requires +3V3 at up to 300mA average and +1V2 at 200mA average for the core of itsmain processor. 3V3 is provided from the main +5V supply via the three terminal regulator IC165 this

also provides the soft start signal to pin 2 of the 1V2 regulator IC167 (also fed from +5V with some volt-

age drop provided by diodes D803/4). Both regulators are SM types, positioned underneath the Venice

6.2 module.

IC161 is a Micrel KSZ8851 single port Fast Ethernet MAC/PHY controller with an SPI interface. It has a

12KB receive bFfer and a 6KB transmit bFfer. It has its own 25MHz crystal oscillator X777. Its 4 I/Osgo

to the Ethernet socket JK52 on the back panel. Its +3V3 power rail is derived from the boards +5V

supply via the three terminal regulator IC166.

AVR400 RS232 board

This is a daughter board connected to the Input Board via an 18 way plug and socket BN71. The circuitry

is shown on page 14 of the schematic diagram.

It contains two 9 way D-type board mounted plugs JK71 and JK72. JK71 is for RS232 control of the

AVR400. JK72 is used to control an iPod or iPhone via an Arcam rDock or rLead (the latter also supports

iPads).

The RS232 dual transmitter and receiver IC73 is an ST3232 run from the standby +5V supply via D721/

R727 and a series pnp transistor Q722 in common emitter mode referred to the +12V rail. Q721 provides



16/34

the necessary level shifting. IC73 includes internal charge pumps to convert CMOS logic level inputs

to +/-5V RS232 level outputs and +/-25V tolerant RS232 inputs to CMOS logic level outputs. Maximum

rated speed is 300kb/sec.

JK73 is a dual mono 3.5mm jack socket providing two +12V trigger outputs Z_1 and Z_2. The series pass

transistors Q712/715 are pnp T0-92 types with emitters referred to the +12V rail via the paralleled 4.7R

resistors R714/715 and R711/712. In conjunction with the pairs of diodes D711/712 and D714/715 this

provides current limiting at approximately 200mA if the trigger outputs are inadvertently shorted to

ground.

JK72 is a dual 3.5mm mono jack socket providing inputs for two modulated infra-red remote control

signals. These are connected to the opto-isolators IC72 and IC71. Note the use of the standby power

supply ST+5V for the subsequent logic.

AVR400 HDMI Input/Output Board

The HDMI Board is described on pages 6 10 of the schematics diagrams. Note that it has components

fitted to both sides of the PCB. HDMI stands for High Definition Multimedia Interface. The AVR400s

system supports certain parts of the HDMI 1.4a specification (3D video compatibility and Audio Return

Channel)

The HDMI Board has 5 type A HDMI input sockets and one type A HDMI output socket, which are flush

with the back panel. It gets its power via the hard wired connector and ribbon cable CN61 and com-

municates with the Input Board via two flex foil cables attached to connectors CN104 (17 ways) and

CN105 (19 ways). It is fitted with a 30 way socket BN301 which attaches to a daughter board handling all

analogue video I/O signals (the Analogue Video Board).

The HDMI Board contains 10 separately regulated local power supplies, mostly derived from the

unregulated but hum filtered +15V supply on the Power Supply Board. This is input on pins 3 and 4 of

the hard wired connector CN61 for +15V and pins 5, 6 and 7 for the ground returns. Pins 1 and 2 are not

used. See page 10 of the schematic diagram for all but the last of these supplies, as described below.

IC923, IC927 and IC930 are all Sanken SI-8005Q 3.5 Amps step-down switching regulators operating at

500kHz +/-10% and drawing power from the +15V line. They are used to generate +3.3VDD, +1.8VDD

and +1.8VH1 (video processor supply) respectively. The potential dividers in their outputs (R839+R844/

R847, R838+852/R851 and R841+843/840) are used to set the required voltages.

All other local power supplies use linear SM 3-terminal regulators.

IC922 and IC929 provide +2.5VH1 and +2.5VH2 for the two DDR memory chips supporting the video

processor. The source supply is +3.3VDD.

IC925 is a KIA7809 generating +8VA from the systems +15VA line (NOT the unregulated +15V usedelsewhere on the board). This is further dropped to +5VA by IC924, a KIA1117S50. Inductor L860 provides

decoupling for the +5VH1 line. The video processor digital power supply lines +3.3VH1, +3.3VH2 and

+1.8VH2 are sourced from the +3.3VDD and +1.8VDD lines via L-C decoupling.

The video ADCs analogue supplies, +3.3VA and +1.8VA, are generated from the +5VA line via IC926

(NJM2845DL133) and IC928 (NJM2845L118) respectively.

The 10thregulator, IC917, an NJU7754 found on sheet 9 of the schematic, is used to provide +5V to the

HDMI output socket. It is enabled via SW_P+5V and derives its input from the +8VA supply described

abov



17/34

The HDMI input SOC, IC901, is a 144 pin LQFP Analog Devices ADV3014B. This is a 4 into 1 HDMI 1.4a

multiplexer and is connected to inputs 4 and 5 (VCR and PVR) on the rear panel (JK95 and JK96). The

other two inputs on IC901 are not used. The core power supply is +1.8V and the receiver terminator

supply voltage is +3.3V. Note that most power supply decoupling components are on the underside of

the PCB. +5V detect and hot plug assert control is carried out by the complementary pairs of switching

transistors Q904/907 and Q910/909. The video system clock is provided by a 28.63636MHz crystal X901

connected across pins 101 and 102.

Pin 63 is set low by R602 meaning IC 901 is controlled by I2C at 3.3V via pins 78 (HDMI_SDA) and 79(HDMI_SCL) from IC902. The HDMI output from IC901 is sent to input A of IC902.

IC902 is an Analog Devices ADV7844, packaged in a 425 pin BGA. It has a 4-input HDMI 1.3 receiver and

one video input supporting standard analogue video formats, from 525/625i up to 1080p, with 12-bit

ADCs. Its primary function is to prepare these signals for the main video processor IC906. Its second

function is to extract digital audio from the HDMI signals, including the reconstruction of a good quality

master clock, and to output all this in I2S or SPDIF format to the DSPs on the Input Board.

JK92 (AV), JK93 (SAT) and JK 94 (BD) connect to 3 of IC902s HDMI input ports. Hot plug detect on

these 3 inputs is carried out by the complementary pairs of switching transistors Q905/906, Q908/901

and Q902/903. The 4thinput receives the output of the HDMI switch IC 901. The core power supply is

+1.8VH2 and the receiver terminator supply voltage is +3.3VH2, with heavy local L-C decoupling. Note

that most of these power supply decoupling components are on the underside of the PCB. The video

system clock is provided by a 28.63636MHz crystal X902.

IC902 has a 256Mb SDRAM IC904 connected via 9 x 4-way 33 ohm resistor packs. This is used as a line/

frame store for digitizing the analogue video signals (CVBS, S-Video and Y, Cr, Cb) received from the

external video inputs and also separate i-Pod derived analogue video signals. It runs from the +2.5VH2

supply with further local decoupling components mounted on both sides of the PCB.

The 12-bit RGB video outputs are sent via 10 x 33ohm resistor packs to the tri-state bFfers IC911 and

IC912. A 10-bit subset of these is also sent to the video processor IC906. Note that the critical video clock

is expanded to drive two output lines HD_VCLK1 (for IC906) and HD_VCLK2 (for IC911) via IC905 and 3 x

33ohm resistors.

The extracted digital audio outputs are sent as I2S and SPDIF signals to the audio DSPs on the input

board via 2 x 33 ohm resistor packs and the switch IC903. IC903 is enabled via Q913.

The video processor IC906 is an ST (formerly Genesis) Torino type FLI30336AC in a large 416 pin

BGA package. It is used to de-interlace and scale all the AVR400s video inputs to the required output

resolution(s) up to 1080p and also to generate the system OSD (on screen display). Note that IC906s

analogue video inputs are not used in this application and are either grounded via an array of resistors

and coupling capacitors close to one long edge of the heatsink or left open (R879-882 are no fits).

IC906 dissipates considerable power (about 4 watts) and is thus equipped with a heatsink soldered

to the PCB via two pins. Its core voltage is +1.8VH1, with +2.5V_DDR being used for its RAM bus and

+3.3VH1 for I/O and 19.66MHz crystal clock X903, all followed by copious local L-C decoupling. Note that

the decoupling capacitors and series inductors required are mounted on the underside of the PCB.

IC906 supports two 256Mbit DDR-1 500MHz 2.5V SDRAMs (IC908 and IC909) via a mix of 33R and 0R

series resistors in the data busses. On the other side of IC906 is its 32Mbit 3.3V flash memory IC907 (Ma-

cronix MX29LV320). IC931 is an Atmel AT24C64C 64K EEPROM with +3.3VH1 power.



18/34

Q914 and Q915 (on the underside of the PCB) send BYPASS_ON and BYPASS_OFF logic signals from

IC906 to the array of 4 x 20-bit non-inverting line driver/bFfers with tri-statable outputs, IC911/912 and

IC915/916. These are arranged as a 40 way 2-in, 1-out fast switch to bypass IC906 when required (e.g.

if 3D video is present). The video is in 12-bit RGB format and 4 more bFfers are required for the video

clock, H and V syncs and the DE (data enable) line, thus using up all of the available 40 ways. See sheet 9

of the schematic diagram. Power is provided via local L-C decoupling from +3.3VH2.

The HDMI output is handled by IC918, an Analog Devices ADV7511 in a 100 pin LQFP package. It is a

225MHz output part that can handle 12-bit 1080p video (up to 165MHz clock speed) and embedded HDaudio. It is compatible with certain parts of the HDMI 1.4 specification, supporting 3D video and an ARC

(audio return channel).

As with the other Analog Devices parts IC918 uses two power rails, namely +1.8VH2 and +3.3VH2. The

necessary decoupling capacitors are mounted on the underside of the PCB.

In the AVR400s implementation the HDMI audio output is limited to stereo rather then 8 channels via

I2S0 (pin 12), plus MCLK (pin 11), SCLK (pin16) and LRCLK (pin 17). SPDIF from the AVR400 is input to pin

10.

The ARC signal, if received from a downstream sink such as a TV, is output from pin 46 of IC918 and sent

via back to the input board. Note that IC921 is not fitted.

The HDMI output is via JK97, a type A HDMI socket. As the AVR400s output is partly HDMI 1.4 compliant,

pin 14 now becomes the HEAC+ and pin 19 HEAC- as well as HPD (Hot Plug Detect). However, because

the Ethernet part of the HDMI1.4 specification is not supported by the AVR400, the ARC is configured

by the sink to be carried in single (i.e. non-differential) mode using HEAC+ as the signal line. HEAC+ and

HEAC- are then AC coupled to pins 52 and 51 of IC918 via the 1F series capacitors C439 and C428. R771,

R777, R785, R795 and R799 bias the inputs and load the cable correctly.(Note HEAC is short for HDMI

Ethernet and Audio (return) Channel).

Q916 is a twin n-channel MOSFET which only turns on when +5VH1 is present. This isolates the DDC

clock and data lines when the AVR400 is turned off.

IC917 is a low dropout voltage regulator feeding +5V power to pin 18 of JK97 from the +8VA supply,

when enabled by the SW_P+5V line.

Analogue video output of digitized and processed 10-bit video from IC906 is available from the AVR400

via the video encoder IC919 an Analogue Devices ADV7342B. Composite, s-video and component

video are supported, although only component analogue video is output by the AVR400.

IC919 is in a 64 pin LQFP powered from the +18VA and +3.3VA lines. Once again most decoupling com-

ponents are on the underside of the PCB.

The 6 x 11-bit video DACs inside IC919 are each loaded with 300R to ground before being AC coupled to

IC913. This is a JRC NJM2566 6-channel video amplifier for SD and HD signals, powered from the +5VA

line. The FS_SEL signal on pin 17 sets the bandwidth on component video to 13.5MHz or 30MHz, to suit

progressive SD or HD signals respectively. The composite and s-video bandwidths are fixed at 6.75MHz.

The outputs go to the analogue video daughter board via the 30 way socket BN301.

Note that the composite and s-video outputs are not actually used in the AVR400 so are not wired

beyond CN301 on the daughter board. The Y, Cr, Cb component video outputs are terminated with 75

ohm series resistors on the Analogue Video daughter board described next.



19/34

AVR400 Analogue Video Board

This is connected into the rest of the system via the HDMI board using CN301.The circuitry is shown on

sheet 13 of the schematic diagram.

The purposes of this PCB are:

(1) to switch between the various analogue video inputs (comprising 4 each composite and s-video

and 3 component video)

(2) to route the chosen video signal to the HDMI board for processing

(3) to provide one set of zone 1 video component video outputs

(4) to provide one zone 2 video output (composite video, with its own OSD) from any of the 4 com-

posite video signal inputs.

The PCBs power supplies are +9VV and +5VV, generated from the three-terminal regulators IC88 and

IC89 from the systems +15VA supply on pin 1 of CN301. Pin 2 carries the systems -15VA supply this is

unused on this PCB.

Note that all video inputs are terminated with 75ohm resistors to ground close to the actual sockets.

IC81 is a JRC NJW1321 a wide bandwidth video switch with 4 inputs, 2 outputs and a 6dB amplifier.

It is used to select between the 4 composite and 4 s-video inputs routed to the HDMI board and also

to output any one of the 4 composite video inputs to the On-Screen Display Controller IC83. IC81 runs

from the +9VV supply, consuming about 85mA so it gets quite hot. It is controlled by i2C commands on

pins 15 and 16.

IC82 is also an NJW1321. It selects between the 3 component video inputs and its fourth input is

unused. Its Y, Cr, Cb outputs and the Y, C and CVBS outputs of IC81 are then AC coupled to IC84 an

NJM2566 6 way video amplifier/filter with 6dB gain, powered from the +5VV rail. Its outputs are also AC

coupled and terminated with 75 ohm series resistors before being routed to CN301.

IC86 is a hex inverter used to bFfer the 3V3 logic level OSD control signals from the HDMI board and

convert them to 5V level for IC83. This is a Sanyo LC74763 in a 30 pin SM package running from the +5VV

rail. It has two crystal oscillators X801 (17.734MHz) and X802 (14.318MHz) to provide composite video

outputs for both PAL and NTSC standards.

IC86s video input signal is AC coupled to and bFfered by the emitter follower Q802 before pin 18.

Similarly its output signal (which now includes an OSD) is bFfered by the pnp transistor Q801 and AC

coupled to the video amplifier/switch IC85 (NJM2244), used here purely as a composite video amplifier/

filter with 6dB gain. Its AC coupled output to the Z 2 OUT single phono socket JK85 is terminated with a

68 ohms series resistor.



20/34

232

AVR400

(

J.I.H

12345

D

C

B

A

6

APPROVECHECKDESIGN DR

MODEL

SCHEMATIC DIAGR

REVISION

1

2

3

4

5

MP

FROM POWER TRANS

VFD_CS

VFD_CLK

VFD_DATA

FilamentV(AC)

40V

REMOTE_IN

VFD_RST

GND

GND

VDISP

ST+5V

+5VD_SYS

ESD

KEY_1

MENU

INPUT-

INPUT+

OK

KEY_2

DIRECT

DISPLAY

ZONE

MUTE

HP_IN

L-CH R-CH

- + -++15V -15V

IC902 NJM4556AL

MICSIGNALIN

MICSIGNALOUT

+15V

-15V

R-CH

L-CH

-15V

MICSIGNALIN

NJM2068M

MIC_RELAY_ON

MICSIGNAL

-15V

+15V

+15V

-15V

+15V

H/PMUTE

A=-Rout/Rin=-10K/1K=-10

A=1+(Rout/Rin)=1+(3.9K/1K)=4.9

-15V

MIC_RELAY_ON

-15V

+15V

HP_DETECT

HP_L

HP_R

FRONTAUX_L(MIC)

FRONTAUX_R

A_GND

D_GND

D_GND

+5VD

D_GND

F_OPT

D_GND

INFO

MODE

VOL-

VOL+

A_GND

SWITCH

FRONT

TOINPUTBD

HP_GND

VOL_EN1

VOL_EN2

KEY1

KEY2

VFD_CS

VFD_CLK/Z2OSDCLK

VFD_DATA/Z2OSDDATA

VFD_RST

IR_IN

MIC_IN

HP_IN

HP_MUTE2

ST+5V

+5VD

D_GND

F_OPT

D_GND

HPL_OUT

HPR_OUT

+15V

-15V

MIC_SIGNAL

HP_RELAY_ON

KEY1

KEY2

VFD_CS

VFD_CLK

VFD_DATA

VFD_RST

+5VD

F_OPT

HPL_OUT

GND

HPR_OUT

MICSIGNAL

HP_GND

A_GND

HP_GND

HP_RELAY_ON

TOAMPBD

L.J.H S.H.S

10.11.17

AUX_L

AUX_R

FRONTAUX_L(MIC)

FRONTAUX_R

HP_L

HP_R

FRONTAUX_L

FRONTAUX_R

HP_RELAY_ON

MIC_RELAY_ON

STBY

PWRON

RED

GREEN

L.E.D

TOHEADPHONEBD

C903:47uF/50V->47uF/25V

2010.04.12

2010.04.12

C903:100uF/63V->47uF/63V2EA

CUP12326Z-1

CUP12326Z-2

HP_IN

D_GND

F_OPT

D_GND

FRONTAUX_R

FRONTAUX_L

+5VD

HPL_OUT

HPR_OUT

HP_GND

+15V

-15V

MIC_SIGNAL

HP_RELAY_ON

-15V

KEY_INPUT_INT

GND

GND

GND

FAN

FAN

FAN

FAN

LED

CUP12326Z-3

STBY(LED)

LED

HIGH: PWR_ON(LED)

LOW:STBY(LED)

FROMAMPBD

FROMFAN

KEY_

INPUT_

INT

HP_L

HP_R

FilamentV(AC)

10.11.17 10.11.17

CWB1B01312047

R919

1K

R918

1K

R917

1K

C915 0.1uF

R916

47

C916 1000P

C917 1000P

C918 1000P

R912

4.7

R913

47

R914

47

R915

47

R910

8.2K

C957

100/16V

C914

0.1uF

C919

0.1uF

C904

0.022u

C905

0.022u

C913

0.1uF

321

VccGNDVOUT

RC901

R909

10

R911

10

R920

1K

D901

4.3V

C903

47/25V

D904

27V

D903

13V

C909

47/63

Q901

C1027Y

D916

1N4003

R908

47K

C911

0.01uF

C910

47/63

R906

1.2K

C908

0.01uF

R905

100K

R907

100K

R901

3.3

1674849505152 557

F1ICNC

TEST

CP

DA

DO

CS

RESET

OSCO

LGND

5354

IC

25556

F1VDD

DGND

VDISP

5862

F2 F2

61

FIP91 CFLHCA16S202T

C912 3

9P

R904

3.3

1 2 3 4 5 6 7

891011121314

IC901

HVITC74HCT7007F

D909 OPEN

C953 OPEN

D908 OPEN

R977 OPEN JW

901OPEN

C907

47/63V

C906

OPEN

C920

1000P

R921

1K

R923

1.8K

R922

1.5K

S902

S903

S904

S901

C921

1000P

R926

1K

R928

1.8K

R927

1.5K

S908

S909

S910

S907

2

1

BN502

CWB4F032950UZ

C901

470P

54321

CN94

R902

10

D902

3.

9V

C902

0.022u

Q908

C107M

Q910

A107M

D906

R938

100

R937

100

R936

4.7K

Q905

C2874

C930

10/50V

C929

10/50V

C932

47/25V

C931

47/25V

J967

J966

R943

56K

R942

56K

C933

680P

R941

3.9K

8 7 6 5 4 3 2 1

IC902

R935

4.7K

Q904C2874

C936

330uF/10V

R948

56K

R947

56K

R945

1K

R944

1K

R946

3.9K

C934

680P

C935

330uF/10V

2

7

1

8

34

65

RL901

C937

0.047

R959

100K

R956

2.2K

R957

1.5K

R958

10K

C944

10/50V

C942

470P

C938

10/50VR960

470

R962

470

R963

100

R964

100

C940

47/25V

C941

47/25V

C939

47P

R961

10K

R965

10K

C943

150P

V+

BOUTPUT

B-INPUT

B+INPUT

V-

A+INPUT

A-INPUT

AOUTPUT

-

+B

-

+A

8 7 6 5

4321

IC903

R955

56K

S905

S90

6

S911

S912

R924

2.7K

R925

3.3K

R929

2.7K

R930

3.3K

2

7

1

8

34

65

RL902

D907

C924

150P

C922

100/16V

Q909

C107M

Q911

A107M

R931

4.7

C926

10/16V

C925

0.1uF

V+

BOUTPUT

B-INPUT

B+INPUT

V-

A+INPUT

A-INPUT

AOUTPUT

-

+

B

-

+A

8 7 6 5

4321

IC904

R933

OPEN

R934

OPEN

R932

OPEN

R985

100

R984

100

C958

47/

25V

C959

47/25V

13

12

11

10

9

8

7

6

5

4

3

2

1

BN93

C960

47/63V

D917

R986

OPEN

30

31

23

22

21

20

25

29

28

27

26

24

14

16

17

18

19

15

8

10

11

12

13

9

3

7

6

5

4

2

1

CN101

1.25mmAngleFFC

S913

KSH1A001ZV

Q906

HVTKRA107MT

Q907

HVTKRA107MT

R903

0

Q902

C107M

Q903

C107M

C927

0.01uF

C928

0.01uF

R980

OPEN

R981

OPEN

G R

D905R978

220

R979

330

R988

56K

R987

56K

Q913

C107MQ912

HVTKRA107MT

R989

10K

3

2

1

CN91

2

1 CN95

2

1

CN96

A_GND

HP_GND

HP_GND

HP_GND

A_GND

A_GND

A_GND

A_GNDA_GND

A_GND

+5VD

M_GND

M_GND

M_GNDM_GND

M_GND

M_GND

M_GND

M_GND

M_GND

M_GND

M_GND

M_GND

M_GND

M_GND

M_GND

M_GND

M_GND

A_GND

HP_GND

A_GND

M_GND

M_GND

M_GND

D_GND

A_GND

CHGND

M_GND

M_GND

M_GND

A_GND

STBY+5V

M_GNDM_GND



21/34



22/34



23/34



24/34



25/34
http://www.manualslib.com/


26/34


27/34


28/34


29/34

10.11.16

AVR400

S.K POWER

12345

D

C

B

A

6

APPROVECHECKDESIGN D

MODEL

SCHEMATIC DIAG

REVISION

1

2

3

4

5

TO VIDEO

DC/DC REGUALTOR

TO INPUT

TO POWER

DDRMEM_REG_ 2.5V

ADC_REG_ 1.8/3.3V

SCALER&Analog_REG

BS VIN

SW GND

FB

COMP

ENSS

N.D

BS

VIN

SW

GND

FB

COMP

ENS

S

BS

VIN

SW

GND

FB

COMP

ENS

S

CUP12328Z

MP

FRONT_HDMI_Option

Option

Op

O

L.J.H

10.11.16

S.H.S

10.11.16

R854

4.7K

R856

4.7K

GND

INOUT 1

2

3

IC925CVIKIA7809AF

C510

220/25V

C491

0.1uF/16V

C519

10/16V

C536

0.1uF/16V

InOut

GND

3

1

2

IC924KIA1117S50

L8609R005Z

L853CLZ9Z014Z

C515

10/16V

C494

0.1uF/16V

L854CLZ9Z014Z

C526

10/16V

C488

0.1uF/16V

L859

L861

L857

C533

0.01uF

C528

1200/35V

C525

0.1uF

C532

10/16V

C537

22/6.3V

2

3 1

OUT

GND

IN

IC9222.5V

C514

0.1uF

C508

0.1uF

L855

C538

10/16V

C496

22/6.3

V

2

3 1

OUT

GND

IN

IC9263.3V

C503

0.1uF

C501

10/16V

C507

22/6.3

V

2

3 1

OUT

GND

IN

IC9281.8V

C502

0.1uF

C516

0.1uF

C529

0.1uF

C509

220/25V

C489

0.

1uF

C495

220P

8 7 6 5

4321

IC930

CVISI8005QTL

D903

CVDSS34SR

L858

10UH/3A

C521

0.1uF

C535

470/16V

R841

12K

R840

5.1

K

R843

2K

C512

1000P

R845

10K

C490

10/16V

C523

22/6.3

V

2

3 1

OUT

GND

IN

IC9292.5V

C522

0.1uF

C530

0.1uF

L863

L851CLZ9Z014Z

C517

10/16V

C542

0.1uF

L849CLZ9Z014Z

CL

L8521

R846

22K

C531

220/25V

C518

0.1uF

C527

220P

8 7 6 5

4321

IC927

CVISI8005QTL

D904

CVDSS34SR

L856

10UH/3A

C493

0.1uFC506

150uF/10V

R838

12K

R851

5.1

K

R852 2K

C513

1000P

C534

220/25V

C511

0.

1uF

C520

220P

8 7 6 5

4321

IC923

CVISI8005QTL

D902

CVDSS34SR

L862

10UH/3A

C500

0.1uF

C505

470/16V

R839

27K

R847

5.1

K

R844

2.2

K

C539

1000P

C551

0.01uF

R872

62k

C552

0.01uF

R873

62k

C553

0.01uF

R874

62k

R875

100_NC

R876

0_NC

R877

0

CL

C498

0.1uFD

905

HVDUDZS5.1

BSR

R885

0_

NC

COM_Y_THRU

COM_PB_THRU

COM_PR_THRU

COM_Y_CONV

COM_PB_CONV

COM_PR_CONV

1321_SCL

1321_SDA

BUSY

$$$17270

V

V-GND

V-GNDV-GNDV-GNDV-GND

V-GND

+8VA

+5VH1

+5VA

+3.3VH1

+3.3VH2

PW_GND

-15VA

GPROBE_RXD

GPROBE_TXD

/RESET

UART_TX

UART_RX

HDMI_MUTE

PW_GND

+3.3VDD

+15V_DC/DC

+3.3VDD

+5VA+3.3VA

SV_Y_CONV

SV_C_CONV

+15VA

-15VA

+1.8VA

+2.5VH1

+15VA

+15V_DC/DC

+1.8VH1

+3.3VDD+2.5VH2

+3.3VH2

+1.8VH2

+1.8VDD

OSD_SDA

OSD_SCL

OSD_CE

CEC_MCU

BUSY_CHECK

CVBS_THRU

SV_Y_THRU

+15VA

OSD_SDA

OSD_SCL

OSD_CE

IPOD_Y/SC

IPOD_PB/CVBS

IPOD_PR/SY

V-GNDV-GND V-GND V-GND

V-GND V-GND V-GND V-GND

V-GND

V-GND

SV_C_THRU

CVBS_CONV

PW_GND

+15V_DC/DC

+1.8VDD

PW_GND

+15V_DC/DC

+3.3VDD

PW_GND

OSD_H

OSD_H

1321_SDA

1321_SCL

PW_GND

PW_GND

PW_GND

PW_GND

BUSY

+15VA

PW_GNDPW_GND

TXEN



30/34


31/34


32/34

10.11.17

AVR400

233L.J.Y

12345

D

C

B

A

6

APPROVECHECKDESIGN DR

MODEL

SCHEMATIC DIAG

REVISION

1

2

3

4

5

I2CBUSFORMAT

S ( 1B I T) S L AV E A DD RE S S( 8 BI T ) A (1 B IT ) D A TA ( 8B I T) A ( 1B I T) D A TA ( 8B I T) A ( 1B I T) P ( 1B I T)

MSB MSB MSBLSB LSB LSB

*DEFINITIONOFI2CREGISTER( NJW1321)

A :AcknowledgeBit

P:EndingT erm

S:StartingTerm

SLAVEADDRESS

1 0 0 0 0 0 ADR(1BIT) R/NOTW(1BIT)

MSB MSB R/NOTW:Set theWriteModeorReadMode.

ADR:SettheSlaveAddressby" ADR"terminal.

Slave Address(8BIT) Hex

-R/NOTW=0: WRITEMODE,ADR=0/1; ADR=0Hex:94(h),ADR=1Hex:96(h)

R/NOTW=0: READMODE,ADR=0/1; ADR=0Hex:95(h),ADR=1Hex:97(h)CONTROLREGISTERTABLE

D0D1D2D3D4D5D6D7

PS1 PS2 OUT1 OUT2

AUX0 AUX1 AUX2 AUX3

DATA 1

DATA 2

NO. BIT

NO.

DATA

D7

BIT

PORT0 PORT1 PORT2 PORT3

D6 D5 D4 D3 D2 D1 D0

PS:POWERSAVE

OUT:OUTPUT

AUX:AUXILIARY(CONTROLSIGNALOUTPUT)

=>PS=1 ;POWERSAVEON(MUTE),PS=0 ;POWERSAVEOFF(OUTON)

PORT:INPUT

Y2

Pb2

Pr2

Y3

Pb3

Pr3

Y_

OUT

Pb_OUT

Pr_OUT

Y1

Pb1

Pr1

Y2 Pr2

Pb2

Y3

Pb3

Pr3

V+

V+

V+

V+

V+

V+

V+

V+

VREF

DGND

SDA

SCL

GND

ADR

PORT2

PORT3

PORT0

PORT1

Pr_OUT2

Pb_O

UT2

AUX0

AUX1

Y_

OUT2

AUX2

AUX3

Y4

Pb4

Pr4

COMPONENTIN3

COM

PONENTIN2

&

Pr_OUT

Pb_OUT

Y_OUT

Pr_OUT

Pb_OUT

Y_OUTMONITOROUT

COMPONENTIN1

COMPONENTOUT

&

Y_

OUT

Pb_OUT

Pr_OUT

Y1

Pb1

Pr1

Y2 Pr2Pb

2

Y3

Pb3

Pr3

V+

V+

V+

V+

V+

V+

V+

V+

VREF

DGND

SDA

SCL

GND

ADR

PORT2

PORT3

PORT0

PORT1

Pr_OUT2

Pb_O

UT2

AUX0

AUX1

Y_

OUT2

AUX2

AUX3

Y4

Pb4

Pr4

VSS

IC83LC74763M

Xin1

Xout1

HSYNCOUT

Xout2

VSYNCOUT

notCS

SIN

SECAM

not525/625

notNTSC/PAL

SCLK

not3.58/4.43

notRST

VDD2

CVIN

CVCR

SYNCIN

PDOUT

AMPIN

PDOUT

AMPIN

AMPOUT

FC

VCOIN

VCOOUT

SYNCDET

VDD1

CVOUT

Xin2

COMPOOSDIN

COMPOOUT

SN74ACT0DR

IC86

OSD_DA

OSD_CLKOSD_CE1

NTSC

PAL

*LC74763MOPTIONTABLE

17.734

14.318

C871 C872 X801

27P 27P

27P 27P

OSD_CE1

OSD_CLK

OSD_DA

OSD_CE1

CVBS

S-C

S-Y

Vin1

Vin2

Vin3

V+

SW1

SW2

VOUT

GND

N.D

Y

Pb

Pr

YC

YC

YC

YC

VIDEO PART

BD

SAT

AV

VCR

Z2 OUT

SAT

BD

AV

1,4,7:UPPER3,6,9:LOWER

1,4,7:UPPER3,6,9:LOWER

X

14.318

X802

Y1

Pb1

Pr1

S.H.SL.J.H

10.11.17 10.11.17

MP

R813

75

R814 7

5

R815

75

R816

75

R817

75

C751

2P

C752

2P

C753

2P

C754

2P

C755

2P

C756

2P

C839

100/16

C838

0.1uF

R818

75

1

2

3

4

5

6

7

8

9

JK83

CJJ4R046Z(GOLD)

47

46

45

44

43

42

41

40

39

38 37 36 35 34 33 32 31 30 29 28 27 26 2524

23

22

21

20

19

18

17

16

15

141312111098765432148

IC82NJW1321FP1

C837

10/50

C771 1/50V

C759

2P

C758

2P

C757

2P

C763

1000/6.3

C764

1000/6.3

C765

1000/6.3

1

2

3

4

5

6

7

8

9

JK84

CJJ4R046Z(GOLD)

C762

2P

R821

75

C761 2

P

R820 7

5

C760

2P

R819

75

47

46

45

44

43

42

41

40

39

38 37 36 35 34 33 32 31 30 29 28 27 26 2524

23

22

21

20

19

18

17

16

15

141312111098765432148

IC81NJW1321FP1

R822

75

R823

75

R824

75

C835

100/16

C836

0.1uF

C834

10/50

R833

47K

C884

56P C885

22P

R867

OPEN

R866

100K

D801

Q802KTC3875SY

R879

8.2

K

C874

27P(EU)

C873

27P(EU)

X80117.734MHz(EU)

R881

1.2K

R868

2.2

K

C878

0.0

22u

C891

0.0

22u

141312111098

7 6 5 4 3 2 1

IC86

C

889

470/10

C886

22P

R878

10K

R885

270

R877

2.2

K

C883

0.1/50

R886

100K

C875

100/16

C876

0.0

22u

C840

1uF

R873

1K C881

1/50

R874

6.8K

R872

1K

R876

39K

C879

22P->33P

C880

22P

L8025.6UH

R875

1.5K

R871

1K

L801

100UH

C888

180P

R882

1K

R883

1K

R884

1K

C887

0.4

7/50

C871

27P

C872

27P

X80214.318MHz

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

IC83LC74763M

R 88 9 1 K

R 88 7 1 K

R 88 8 1 K

R880

0

C882

6800P

C890

10/50

JK85CJJ4M069Z(GOLD)

R848

75

R849

75

R850

75

C813 0.01uF

C774 1/50V

C816 0.01uF

C772 1/50V

C814 0.01uF

C775 1/50V

C817 0.01uF

C773 1/50V

C815 0.01uF

C776 1/50V

C818 0.01uF

C766 1/50V

C819 0.01uF

C767 1/50V

C820 0.01uF

C768 1/50V

C821 0.01uF

C850 10/50V

C844

0.01uF

C851 10/50V

C845

0.01uF

C852 10/50V

C846

0.01uF

C849 10/50V

C843

0.01uF

C847 10/50V

C841

0.01uF

C848 10/50V

C842

0.01uF

R847

75

R845

75

R846

75

R 83 4 3 3

R 83 5 3 3

R831 33

R832 33

8 7 6 5

4321

IC85

HVINJM2244MTE1

C769

68P

C770

470/10V

C86510/50V

R86

1

1M

C869

100/16

C868

0.1uF

R862

1M

C866

0.0

1uF

R863

1M

C867

0.0

1uF

C857

100/16V

J 1 J 2 J 3

C893

0.1uF

C892

10/50V

C894

10/50V

C895

0.1uF

2

1

3

GND

Out In

IC89CVIKIA1117S50

L804

10uH

C897

10/50V

C896

0.1uF

L803

10uH

R825

68

J7

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

11PS1

2SCIN

3V+1

4NC-0

5MIXSW

6VIN

7GND1

8SYIN

9CBSW

10YIN

11V+2

12NC-1

13GND2

14PBIN

15PS2

16PRIN

17LPFSW

18PROUT

19GND3

20NC-2

21PBOUT

22V+3

23YOUT

24GND4

25SYOUT

26V+4

27VOUT

28NC-3

29SCOUT

30SDCOUT

31S2

32S1

IC84 CVINJM2566V

C861

470/10V

C862

470/10V

C863

470/10V

C860

470/10V

C859

470/10V

C858

470/10V

C8550.1uF

C8560.1uF

C8540.1uF

C8530.1uF

R843

4.7K

R841

4.7K

R844

10K

R842

10K

R810

75

R811

75

R812

75

R807

75

R808

75

R809

75

R804

75

R805

75

R806

75

R801

75

R802

75

R803

75

C824 1/50V

C803 0.01uF

C823 1/50V

C802 0.01uF

C822 1/50V

C801 0.01uF

C827 1/50V

C806 0.01uF

C826 1/50V

C805 0.01uF

C825 1/50V

C804 0.01uF

C830 1/50V

C809 0.01uF

C829 1/50V

C808 0.01uF

C828 1/50V

C807 0.01uF

C833 1/50V

C812 0.01uF

C832 1/50V

C811 0.01uF

C831 1/50V

C810 0.01uF

1

2

3

4

56

7

8

9

10

11

12

13

14

15

16

17JK81

CJJ9P004Z(GOLD)

1

2

3

4

56

7

8

9

10

11

12

13

14

15

16

17JK82

CJJ9P004Z(GOLD)

GND

INOUT 1

2

3

IC88CVIKIA7809AF

J9

Q801KTA1504SY

D802CVD1N4003SRT

+9VV

+9VV

+5VV

+5VV

+9VV

+5VV

+5VV

AUX2

AUX3

AUX4

+5VV +9VV+15VV

AUX1

+15VV

-5VA

OSD_SDA

OSD_SCL

OSD_CE

VGND

VGND

VGND

VGND

VGND

VGND

VGND

VGND

VGND

VGND

VGND

VGND

VGND

VGND

VGNDVGND

VGND

VGND VGND

VGND

VGND

VGND

VGND

VGND

VGND

VGNDVGND

VGNDVGND

VGND VGND

VGND VGNDVGNDVGND

VGND

VGNDVGND

VGND VGND

VGND VGND

VGND

VGND

VGND

VGNDVGND

VGNDVGND VGND

VGND

VGND

VGNDVGND

VGND

VGND

VGND

VGND VGND

VGND

VGND

VGND

VGND

VGND VGND

VGND VGND VGND VGND

VGND

VGND

VGND

VGND VGND VGND

VGND VGND VGND

VGND VGND VGND

VGND VGND VGND

VGND

VGND

VGND



33/34

10.11.17

AVR400

233

5

4

3

2

1

REVISION

SCHEMATIC DIAG

MODEL

DRDESIGN CHECK APPROVE

6

A

B

C

D

5 4 3 2 1

L.J.Y

!

!

!

!

!

!

TX

RX

FROM INPUT

iPod

RS

232

+20V

-20V

-15V

+15V

TOHDMI TO INPUT

TOAMP

TRANSFORMER

POWER PART RS232 PART

REMOTE_OUT

R839=(Vout-Vfb)/Iadj,(5V-0.5V)/0.1mA =45Kohm

R844+R847=-Vfb/Iadj,0.5V)/0.1mA = 5Kohm

C1+

V+

C1-

C2+

C2-

V-

T2out

R2in

Vcc

GND

T1out

R1in

R1out

T1in

T2in

R2out

TXD

RXD

DGND

+15VD

+15VD

+15VD

DGND

N.C

N.C

POWER_ON

ST+9V

STBY_GND

_POWER_DOWN

MGND

V_DET

+12V

ST+9V

_POWER_DOWN

MALE

MALE

+15V

-15V

MGND

+5VD

ST+5V

MGND

PULL_UP

+12V

BS

VIN S

WGND

FBCOMP

ENS

S

MGND

POWER_DOWN

POWER_ON

+5VD

USECROSSCABLE

USECRO

SSCABLE

+3.3VD1

+3.3VD2

8CH SBR

8CH SBL

8CH SRch

8CH Cch

8CH SUB

8CH SLch

8CH Rch

8CH Lch

8CH DIRECT INPUT

R743 R744

0 OPEN

OPEN 0

HP_L

HP_R

HP_DETECT

HP_L

HP_R

HP_GND

A_GND

HP_GND

AUX & PHONEHEADPHONE(YUQIU)

AUX & MICOPTICAL &

ESD

+5VD

FRONTAUX_L(MIC)

FRONTAUX_R

A_GND

+5VD

F_OPT

D_GND

D_GND

FRONTAUX_L(MIC)

FRONTAUX_R

A_GND

F_OPT

HP_GND

RECEIVER

HP_DETECT

FROMFRONTBOARD

HP_GND

VOUT

10.11.17 10.11.17

L.J.H S.H.SMP

C721 C722 C723 C724 C725

0 . 1 0 . 1 0 . 1 0 . 1 0 . 1

0.1 0.47 0.1 0.47 0.47

ST202E

ST3232E

VCC

GND

OUT

IN

GND

T6.3A L 250V

T6.3A L 250V

C741 0.1uF

R742 4.7

C742 0.1uF

D742

D741

R741 4.7

Q717HVTKRA107S

R733

47K

R735

220

R731

10K

5

9

4

8

3

7

2

6

1

JK72

CJJ9V001Z

Q711

HVTKRA102SC711

0.0

1u

F

R720

1K

R714

4.7

R715

4.7

Q712KTA1266

D711

1SS355

D712

1SS355

Q713

HVTKRC102S

R718

10K

R719

10K

C712

0.0

1u

F

R717

20

R716

20

D713CVD1SS355T

L701CLZ9Z014Z

C701

22P

C702

22P

D701

D702

R701

47K

L702

CLZ9Z014Z

C703

22P

C704

22P

4

3 2

1

IC71

KP1010B

R734

47K

R736

avr400 service manual

Documents

search enginehttp

zone description of

tgp3538 power amp pcb

r cambridge ltdpart

angular tol

eco nr

tgp3525 foot assy

ha4v06s torx screw m4