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2CS&RSOC YONSEI UNIVERSITY
IntroductionTest Pattern Generation
Test generationManual generationPseudo random generationAlgorithmic (or deterministic) test generation
Automatic Test Pattern Generation (ATPG)Calculate the set of test patterns from a description of the logic network and a set of assumptions called fault models
ATPG TestsCircuit
ModelFault Set
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IntroductionATPG
Result of ATPGFind a test patternRedundant faultRun out of time/memory (Aborted fault)
Cost of ATPGLow CPU time
Quality of the generated testsHigh fault coverage
Cost of Applying TestSmall number of tests
Fault Coverage# of detected faults / # of faults# of detected faults / (# of faults - # of redundant faults)(# of detected faults + # of redundant faults) / # of faults
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IntroductionDefinition
Single Fault AssumptionThe assumption that one and only one fault is present in a givencircuit at a time
Fault ExcitationThe process of finding a sufficient set of PI values to cause the fault site in the good circuit to have a value opposite to the faulty value
Fault PropagationThe process of moving the effect of a fault closer to a PO
Line JustificationThe process of finding a set of PI values which cause the line to achieve the desired valueEssentially the same as backdrive with conflict resolution
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IntroductionDefinition
ImplicationThe process of determining the unique values implied by already assigned valuesThe process can cause both forward and backward assignment of values
BacktrackingRetracing in the search space to resolve the conflict by trying alternate assignments at previously assigned nodesShould store previously determined values
Reconvergent fanoutA fanout node, two or more of whose branches eventually are used as inputs to the same elementThe element at which the branch reconverge is called the point of reconvergence
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IntroductionATPG Example
F output s-a-01/0A
B
CDE
F
GH
I
J
1/00X
CDE
F
GH
I
J
Fault Excitation
1/00X
11
F
GH
I
J1/0
1/001
0Fault Propagation
7CS&RSOC YONSEI UNIVERSITY
IntroductionATPG Example
H s-a-1
AB
1
1H 0/1
K
L
M
N
O
P
Q
R S
0/1
00/1
1
1
CD
AB11
1
1H 0/1
K
L
M
N
O
P
Q
R S
0/1
00/1
1
11
0 0
contradiction
11
1
10 0/1
K
L
M
N
O
P
Q
R S
0/1
00/1
1
1
1
0
1
X
choo
se L=
1
choose
K=1, M=1
8CS&RSOC YONSEI UNIVERSITY
Introduction2 Phase ATPG
Random + Deterministic
while an exit condition happensget a vectorfault simulate the vectorif the vector detects faults
add the vector to the test setdiscard the faults
for all remaining faultsselect a faultgenerate a vectorif successful
add the vector in the test setfault simulate the vectordiscard the faults
9CS&RSOC YONSEI UNIVERSITY
Boolean DifferenceBoolean Difference
))(f)(f(x)(f)(fx)(f)(fx)(f))(fx)(fx(
)x(f)x(f)x(f)x(f)x(f)x(fT
)x,,x,,,x,x(f)(f)x,,x,,,x,x(f)(f
)x,,x,,,x,x(f)x,,x,x(fx
)x,,x,x(fC
iii
iiiiii
iiiii
nii
nii
nin
i
n
010101010
1100
0
121
121
12121
21
⊕=+=
⊕+=
⊕=+=
==
=
=
+
+
+
expansion sShnnon' Use
Let Let
fault be 0-a-s Let
circuit nalCombinatio
α
αα
α
α
o
LLoLLo
LLLoo
L
10CS&RSOC YONSEI UNIVERSITY
Boolean DifferenceBoolean Difference
1-a-s for
excitation Fault
nObservatio
to respect withdifference Boolean
o
o
o
))(f)(f(xT
x
)(f)(f))(f)(f(xT
iii
i
ii
iii
xi
01
0101
⊕=•
⊕⊕=•
∗
∗
∗
β
α
11CS&RSOC YONSEI UNIVERSITY
Boolean DifferenceBoolean Difference
BCACCDDdDdET
D
CABDCDdDdET
CCdDdE
DCABCDE
+===•
=•
===•
=⊕=•
=•+=+=•
β
α
β
α
1)-a-(s Let
0)-a-(s Let
1A
B
C
D
E
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D AlgorithmD Algorithm
Introduce D and D’Good Faulty
D 1 0
D’ 0 1
AND 0 1 D D’ X0 0 0 0 0 01 0 1 D D’ XD 0 D D 0 XD’ 0 D’ 0 D’ 0X 0 X X 0 X
OR 0 1 D D’ X0 0 1 D D’ X1 1 1 1 1 1D D 1 D 1 1D’ D’ 1 1 D’ XX X 1 1 X X
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D AlgorithmD Algorithm
Algorithm1) Initialize all nodes to X2) Select a fault α3) Select a pdcf of α4) Implication (forward and backward)5) D drive6) If not reached PO, go to 4)7) Line justification
D frontierSet of elements whose output values are unspecified but whose input has some signal D or D’
D driveAttempts to propagate D or D’ to the output of elements
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D AlgorithmExample
Primitive Cubes, Primitive D Cubes, Propagation D Cubes
1 1 1
1 1
X1X2X3
1 2 3 40 X 0 1X 1 X 1X 0 1 01 0 X 0
1β
0β1 1
1 1
X1X2X3
1 2 3 40 1 0 DX 1 0 D1 0 0 D’
01 α∩β
10 α∩β
∩ 0 1 X0 0 ∅ 01 ∅ 1 1X 0 1 X
where
1 2 3 4X 0 0 1X 1 1 1X 0 1 0X 1 0 0
1α
0α
1 2 3 4D 0 0 DD’ 0 0 D’ 10 β∩β
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D AlgorithmD Algorithm Example
G1 s-a-0
2
1
3
4
5
6
7
8
9 10
11
12
13
G1
G2
G4
G3
G5
G6
1 2 3 4 5 6 7 8 9 10 11 12 13
Test cube 1 1 D
PropagationD-cube G3 D 0 D
G3 D drive 1 1 D 0 D
Implication 1 1 1 D 0 D
PropagationD-cube G5 D 1 D
G5 D drive 1 1 1 1 D 0 D 1 D
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D AlgorithmD Algorithm : Example
G1 s-a-0G1
G2
G3
G4
G5
G61
2
3
4
5
6
7
8
9
10
11
121 2 3 4 5 6 7 8 9 10 11 12
All to X X X X X X X X X X X X X
pdcf 1 1 D
Implication1=1 2=1
G3 D drive 1 0 D’
Implication3=1 0 1
Implication4=0 1 1 0 1
G4 D drive 0 1G3 G4D drive 1 1
Implication 0 0 1 D’ D’ 1 D
Test 1 1 1 1
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9V Algorithm9V Algorithm
Problem of D AlgorithmSelection of fanout branch - increasing exponentially
Advantage is mainly due to the higher degree of freedomAt fanout point having a fanout of N, at most N attempts have to be made out
D requires 2N-1Faulty
0 1 X0 0 D’ G01 D 1 G1
Goo
d
X F0 F1 X
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PODEMPODEM
Path Oriented DEcision MakingSearch space on PIs Implicit space enumerationAlgorithm
PODEM()if (Error at PO)return SUCCESS
if (test not possible)return FAILURE
get an objectivebacktrace the objective to PIimply the PI valueif PODEM() == SUCCESSreturn SUCCESS
imply PI with X valuereturn FAILURE
assume target fault is I s-a-v
objective()if ( the value of I is X )return (I, v’)
select a gate(G) from the D frontierselect an input j of G with value Xc = controlling value of Greturn ( j, c’)
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PODEMPODEM Example
a s-a-0 : using PODEM
a
b
c
d
e
f
d'
e'
f'
h
i
j
k
l
m
ng
Success
a
Failure
c
d
e
f
b
1
1
1
1
1
1
0
0
20CS&RSOC YONSEI UNIVERSITY
FANFAN
FANout Oriented ATPGStop the backtrace at a headline and postpone the line justification for the headline to the lastMultiple backtraceFree line
Gate output whose predecessors are fanout freeHead line
Free line that enters a region of reconvergent fanout
Z
headline
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FANFAN
Assume that we want to set J=0Assume that with PI assignments previously made, setting J=0 causes D frontier empty Failure
A
B
C
E
F
G
H
J
M
K
L
Failure
Failure
1
1
1
0
0
A
B
C
PODEM
0
J
1
Failure
FAN
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FANFAN Example
M-L s-a-1 using FANAB
CD
E
F
G
H
J
K
L MN
P
Q
R
TS
Free line : F, GBound : J, K, M, P, Q, R,SHead line : F, G
0
D
11
10
1
F
G
H
J
K
L MN
P
Q
R
TS
1
1
1
1.assign L= 0 E= 1 M= D > > implication N= Q= R= 1 2.only path M- P- S- T > > A= C= 1 > > implication P= S= T= D'3. unjustified value L= 0backtrace B= 1 > implication(no change)backtrace D= 0 > implication(J= L= 0 K= 1)
D'
D'
0
11
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HeuristicsX Path CheckX path check
Let s be a signal on the fault sensitization pathIf s has 0 or 1, the fault cannot be propagatedCheck the value using forward implication
A
stuck- at- 0
B= X
C= X
D= 1
E= X G= X
F= X
blocked path
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HeuristicsDominator
A signal y is said to dominate a signal x if all directed paths from x to the POs pass through yDominator
The set of signal that dominate signal xThe fault effect should pass through dominatorsOff-path inputs of dominators are assigned noncontrolling values to propagate fault effect
ExampleDominators of signal C : G2 and G5
Thus D=0 and J=1
C
D= 0
F
E
G
J= 1
I
H
KG1
G2
G3
G4
G5
stuck- at fault
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HeuristicsStatic learning
To assign a logic value to a certain signal of the circuit, perform This is done for all signals of the circuit for both logic value 0 and 1Example
B=1 => F=1F=0 => B=0
A
B= 1
c
D= 1
E= 1
F= 1
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HeuristicsDynamic Learning
If both assignments a=0 and a=1 do not result in a conflict during the implication procedure, the learning is usedExample
When b=1 and c=1, a=1 ⇒ h=1h=0 ⇒ a=0
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HeuristicsRecursive Learning
ExampleAssume that I1 and J are unjustified Verify that K=1 is necessary assignment
0 level learning 1 level learning 2 level learningI1=0(unjust.)J=1(unjust.)
K=1
unjust. I1=01. justify G1=0>> E1=0(unjust.)>> F1=0(unjust.)
E2=0
F2=0>>G2=0 I2=0 K=12. justify H1=0>>H2=0 I2=0 K=1
<<unjust. J=1
unjust. E1=01. justify A1=0>> A2=0 >> E2=02. justify B1=0>> B2=0 >> E2=0
<<
unjust. F1=01. justify C1=0>> C2-0 >> F2=02. justify D1=0>> D2=0 >> F2=0
<<
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Test CompactionTest Compaction
PI test values are usually partially specifiedCombine tests to reduce test lengthTwo tests are compatible if they do not specify opposite values for any PITwo compatible tests Ti and Tj can be combined into one test Tij = Ti ∩ Tj
ExampleT1=01X, T2=0X1, T3=0X0, T4=X01T12=011, T3=0X0, T4=X01T13=010, T24=001
∩ 0 1 X0 0 ∅ 01 ∅ 1 1X 0 1 X
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Scan Design
Combinational
Q D
C
Q D
C
Q D
C
POPI
Clk
MUX0
MUX
MUX0
0
1
1
1
N/T_
Sin
Sout
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Sequential ATPGSequential Test Generation
Generates a sequence of vectors to detect a single stuck-at fault in sequential circuitControllability and Observability in a sequential circuit are mush worse than those in a combinational circuit
Due to the presence of memory elementsSearch space is too large in generalNo single strategy/heuristic outperforms others for all applications/circuitsCan be combined with low-overhead DFT techniques such as partial scan
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Toplogical AnalysisTopological Analysis Based
Iterative Array ModelCombinational model for sequential circuit
Regenerates the feedback signals from previous-time copies of the circuitA rectangle : A copy of the combinational portion of circuits
PI
PO
t=0
justificationsequence
propagationsequence
activationsequence
faulteffect
observation
activationvector
faultactivation
activationstate
justification
x f x f x f x f x f x f
32CS&RSOC YONSEI UNIVERSITY
Topological AnalysisExtended D Algorithm : Example
FF2
FF1
IN
OUT
Y2
Y1
y2
y1
s-a-1
s-a-1s-a-1s-a-1
D D D
Dy1-1
y2-1
Y11
Y21
IN-1 IN0 IN1
OUT1OUT0OUT-1
0 1 1
•Time-frame 0 : Fault activation•Time-frame 1 : Fault propagation•Time-frame -1 : Fault justification
Time-frame -1 Time-frame 0 Time-frame 1
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Topological AnalysisExtended Backtrace Algorithm(EBT)
Reverse Time Processing(RTP)Works backwards in time from last time-frame to first time-frameFor a given fault, RTP pre-selects a path from the fault site to a primary output through several time-framesSelected path is then sensitized backwardsIf sensitization process fails, another path is selected
Advantages of Reverse Time ProcessingAt any time-frame, only two time-frames need to be maintainIt is easier to identify repetition of state requirement
Major ProblemsOnly single-path is selected for sensitization
Faults that require multiple-path sensitization for detection may not be covered
The number of possible paths from the fault site to the primary outputs is very large
Trying path by path is not practical
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Topological AnalysisBack AlgorithmImprovement of the EBT algorithmInstead of pre-selecting path, BACK algorithm pre-selects a primary output
Assigns a D or D’ to the selected primary output and justifies the value backwardsTestability measure(called drivability) is used to guide the backward D-justification from selected primary output to fault site
Require smaller memory spaceEfficient than EBT
number of POs < number of paths