at91sam9g10-ek evaluation board - microchip technology
TRANSCRIPT
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AT91SAM9G10-EK Evaluation Board ....................................................................................................................
User Guide
6479A–ATARM–26-May-09
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AT91SAM9G10-EK Evaluation Board User Guide
Section 1Overview.....................................................................................................................1-1
1.1 Scope................................................................................................................................. 1-1
1.2 Deliverables ....................................................................................................................... 1-1
1.3 The AT91SAM9G10-EK Evaluation Board ........................................................................ 1-1
Section 2Setting Up the AT91SAM9G10-EK Evaluation Board ........................................................................................................2-1
2.1 Electrostatic Warning ......................................................................................................... 2-1
2.2 Requirements..................................................................................................................... 2-1
2.3 Layout ................................................................................................................................ 2-2
2.4 Powering Up the Board ...................................................................................................... 2-4
2.5 Backup Power Supply ........................................................................................................ 2-4
2.6 Getting Started................................................................................................................... 2-4
2.7 AT91SAM9G10-EK Block Diagram.................................................................................... 2-5
Section 3Board Description .......................................................................................................3-1
3.1 AT91SAM9G10 Microcontroller ......................................................................................... 3-1
3.2 AT91SAM9G10 Block Diagram.......................................................................................... 3-4
3.3 Memory .............................................................................................................................. 3-5
3.4 Clock Circuitry .................................................................................................................... 3-5
3.5 Reset Circuitry.................................................................................................................... 3-5
3.6 Shutdown Controller........................................................................................................... 3-5
3.7 Power Supply Circuitry....................................................................................................... 3-5
3.8 Remote Communication..................................................................................................... 3-5
3.9 Audio Stereo Interface ....................................................................................................... 3-5
3.10 User Interface..................................................................................................................... 3-6
3.11 Debug Interface.................................................................................................................. 3-6
3.12 Expansion Slot ................................................................................................................... 3-6
3.13 PIO Usage ......................................................................................................................... 3-7
Section 4Configuration Straps...................................................................................................4-1
4.1 Configuration Straps .......................................................................................................... 4-1
Section 5Schematics .................................................................................................................5-1
5.1 Schematics......................................................................................................................... 5-1
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Section 6Errata ..........................................................................................................................6-1
6.1 JTAGSEL S5 Footprint Selector ........................................................................................ 6-1
6.2 External Capacitor Values on XIN and XOUT.................................................................... 6-1
Section 7Revision History..........................................................................................................7-1
7.1 Revision History ................................................................................................................. 7-1
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Section 1
Overview
1.1 ScopeThe AT91SAM9G10-EK evaluation kit is an effective platform for evaluating chip performance and developing code for applications based on the AT91SAM9G10.
This guide is a description of the hardware included in the AT91SAM9G10-EK evaluation kit. Software files are available embedded into the board’s memory upon delivery.
1.2 Deliverables The AT91SAM9G10-EK package contains the following items:
an AT91SAM9G10-EK board
one A/B-type USB cable
one serial RS232 cable
one RJ45 crossed Ethernet cable
universal input AC/DC power supply with US and EU plug adapter
1.3 The AT91SAM9G10-EK Evaluation BoardThe board is equipped with an AT91SAM9G10 (217-ball LFBGA package) together with the following:
64 Mbytes of SDRAM memory
256 Mbytes of NAND Flash memory
one Atmel® serial DataFlash®
one USB device port interface
two USB host port interfaces
one DBGU serial communication port
JTAG/ICE debug interface
one Ethernet 100-base TX with three status LEDs
one Atmel AT73C213 Audio DAC
one 3.5" 1/4 VGA TFT LCD Module with TouchScreen and backlight
one Power LED and two general-purpose LEDs
four user input pushbuttons
one wakeup input pushbutton
one reset pushbutton
one DataFlash SD/MMC card slot
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two expansion footprint connectors (solder side)
one Lithium Coin Cell Battery Retainer for 12 mm cell size
dual pitch prototyping area
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Section 2
Setting Up the AT91SAM9G10-EK Evaluation Board
2.1 Electrostatic WarningThe AT91SAM9G10-EK evaluation board is shipped in a protective anti-static package. The board must not be subjected to high electrostatic potentials. In risky ESD environments (e.g. offices with carpet) a grounding strap or similar protective device should be worn when handling the board. Also, generally avoid touching the component pins or any other metallic element of the board.
2.2 RequirementsIn order to set up the AT91SAM9G10-EK evaluation board, the following items are required:
the AT91SAM9G10-EK evaluation board itself
AC/DC power adapter (5V at 2A), 2.1 mm by 5.5 mm
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2.3 Layout
C1
12
R3
0
R2
9
BP
5
C1
24
C1
25R7
2
L5C
84
R8
3
R82R75
J131920
1
C1
15
J23
1
J20
BP
6
J10
TP2
C4J2C
3
1
C1
R6
1
MN
1
C9
C2
R2
CR
1
J1
TP
1
R5
Q2
Q1
J3 DS1
k
1
C9
1
C93
C9
2
R20
C9
5C
94
MN13
1
J21
1
TP4
MN
7
C16J15
J7
BP
2BP
1MN
10
J9
J24
C1
26
1
S7
S9
Y1
Y2
C20
R12
S8
C17J18
J41
C19
MN
3
R11
R9
C11
1
1R55
A4B4
MN
6B
R1
9
C5
911
C5
2
A1
C4
5
C5
6
J8
J5
J12 1
R54A1B1
MN
6A
MN
4
C5
1
C4
6
C5
3
R1
8
C5
5
C4
9
MN
5C
57
C4
8
1
TP
3
R63
MN
2
C1
0
R66
R65
R64
R62
R4
R3
C6
0
R3
2
R2
8
R2
7
C6
8
C4
4
DS
4
C5
0
DS
3
DS
2
C4
7
DS
8
DS
7C
54C
7
MN
14
C8
Q5
J19
R34
C69
1
R23
kkk
C72
kkC
11
0
C102
BP
3
C6
7C
66
MN
8
C70
C1
11
R6
8
MN
15
J6
Y3
R31
C7
4
C7
5
C7
3
R8
1
R8
0
R7
8
R7
7
R7
6
R7
3
C1
07
RR
112
BP
4
TP66
TP65
TP
64
TP
63
1M
N1
6
MN11
1
C123C122C121
C120
R7
9
R8
4
R7
4
Q6
C1
13
R2
6
R2
5
C8
7
GN
D
3.3V
5V ONLYWARNING
GN
D
1PO
WE
RF
OR
CE
3.3V3.3
V
LE
DP
OW
ER
ON
GN
D
5V
3.3
V5V
0G
ND
DA
TA
FLA
SH
PORT B
20 16 12
18 14 108
64
2
2G
ND
28 24
4 0 30 26 22
PORT A
22 18 14 10 6
24 20 16 12 8
8 4 0 30 26
6 2 GN
D28
PORT C
28 24 20 16 12
26 22 18 14 10
3.3
VV
DD
BU
NR
ST
GN
D
GN
DG
ND
GN
DN
C30
5V
PO
RT
DE
BU
GS
ER
IAL
GND
GN
D121 17 13 9
19 15 11 75
3
3 29 25
5 11
31 27 23
GN
D
23 19 15 11 7
25 21 17 13 9
9 5 1 31 27
7 3 29G
ND
29 25 21 17 13
27 23 19 15 11NC 31
WK
UP
SH
DN
3.3
V
GN
DG
ND
GN
DG
ND
5VEX
T. C
LO
CK
1.2
VB
BVD
DB
UET
M T
RA
CE
PO
RT
UP
WA
KE
RE
SE
T
USB HOST INTERFACE
SE
LE
CT
BO
OT
MO
DE
VD
DO
SC
+V
DD
PL
L
1.2
V
NA
ND
FL
AS
HVDDCORE
USB DEVICE INTERFACE
SP
EE
D
DU
PL
EX
FU
LL
AC
T&
LIN
KT
OU
CH
SC
RE
EN
CO
NT
RO
LLE
R
CO
NN
EC
TO
RJT
AG
/IC
E
AT
91
SA
M9
26
1-E
K
10
/10
0E
TH
ER
NE
T
AUDIO OUT
ST
UD
IEL
WW
W.S
TU
DIE
L.F
R
Figure 2-1. AT91SAM9G10-EK Layout - Top View
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R15
R1
R53
R52
C58
J16
S21
S12
R17
R16
CR
2
C38
C43C
40
R13
C22
C37
C36
C25
C23
C27
C39C18
C15
C14
C13
R10 R7
R14
C31C30
C29
C24
C26
C42
C41
C21
C28R8
C12R59
R58R56
C99C96
R60
C100S
13
C33 C32
C35
C34
S10
F2
F1R57
C98
C97R61
C101
C6S22
C104
J17
C5
C106
C105
C103
S16
S14
S15
R24
R22
R21
R70
S19
R50
S20
R51
C71
C79S23
R67
L4
S2
S5
R71
C78
L2
C77
C117
C116
C119
C118
C109
C108
C114
R69
S6
C76
S26
S24
S25L1
S3
S4
J22
C63
C62
C61
C64
119
12
120
179
2
80
INT
ER
FA
CE
DA
TA
FLA
SH
CA
RD
SD
CA
RD
/MM
C C
AR
D
R8
5
Figure 2-2. AT91SAM9G10-EK Layout - Bottom View
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2.4 Powering Up the BoardAT91SAM9G10-EK requires 5V DC (±5%). DC power is supplied to the board via the 2.1 mm by 5.5 mm socket (J1). The coaxial power plug center pin is positive polarity.
2.5 Backup Power SupplyThe user has the possibility to add a battery (3V Lithium Battery CR1225 or equivalent) in order to per-manently power the backup part of the device. In this case, J9 configuration must to be set in position 1, 2.
Refer to Table 4-1, “Configuration Jumpers and Straps”.
2.6 Getting StartedThe AT91SAM9G10-EK evaluation board is delivered with an embedded demo and documentation files allowing the user to begin evaluating the AT91 ARM Thumb 32-bit microcontroller quickly. Simply power the board and connect it to the USB port of your PC to open it. Also, please refer to the AT91 web site, www.atmel.com/products/AT91/, for the most up-to-date information on getting started with the AT91SAM9G10-EK.
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2.7 AT91SAM9G10-EK Block Diagram
1V2
1V2
1V2
3V3
3V3
POWER SUPPLY
SH
UTD
OW
N
VDDCORE
5 VDC
VDDPLL VDDOSC
VD
DB
U
GN
DB
U
WK
UP
SYSTEM CONTROLLER
DD
P
DD
M
SH
DN
NR
ST
PIO
EXT CLK INPUT
18.432 MH
z XIN
XOUT
SP
I0_N
PC
S0
DATAFLASHDEVICE
CS
SPI0
MIS
O -
MO
SI -
SP
CK
AT91SAM9G10
1/4 VGA DISPLAY
LCD CONTROLLER
EB
ISDRAM
16 16
320 x 240
US
B H
OS
T
US
B D
EV
ICE
HD
MA
- H
DP
A
HD
MB
- H
DP
B
3V3
VDD3V3
USER'S GREEN LED
EX
PA
NS
ION
CO
NN
EC
TOR
S
LCD
CO
NTR
OL
YELLOW POWER LED
EB
I
256 MbSDRAM256 Mb
32
JTAG/ICE
ADM3202A
DB
GU
DBGU
DR
XD
- D
TXD
TXD
RX
D
RS232
VDDIO
ETM
TRACE PORT
PA
11..P
A31
PIO
LINEAR REGULATOR
REG1V2
ETHERNET 10/100
EMAC + PHY
RJ45
TFT
WITH TOUCHSCREEN
SD/MMCDATAFLASH
MC
ICARD READER
SP
I0
SP
I0_N
PC
S2
CONTROLLERTOUCHSCREEN
NANDFLASH
8
SC
C1
I2S
OUT
AT73C213
HEADPHONE
SC
C1
PA
29 /
SP
I0_N
PC
S3
STEREOAUDIO DAC
SH
UTD
OW
N
SP
I0_N
PC
S3
/ PA
6
1.2V
+3V
NRST
� �� �85 7643219
5V5V
123
123
Figure 2-3. Block Diagram
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Section 3
Board Description
3.1 AT91SAM9G10 Microcontroller
Incorporates the ARM926EJ-S™ ARM Thumb Processor
– DSP Instruction Extensions
– ARM Jazelle® Technology for Java® Acceleration
– 16-KByte Data Cache, 16-KByte Instruction Cache, Write Buffer
– 266 MHz core frequency
– Memory Management Unit
– EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support
– Mid-level implementation Embedded Trace Macrocell™
Additional Embedded Memories
– 32K Bytes of Internal ROM, Single-cycle Access at Maximum Bus Speed
– 160K Bytes of Internal SRAM, Single-cycle Access at Maximum Processor or Bus Speed
External Bus Interface (EBI)
– Supports SDRAM, Static Memory, NAND Flash and CompactFlash®
LCD Controller
– RGB Addressing
– Supports Passive or Active Displays
– Up to 16-bits per Pixel in STN Color Mode
– Up to 16M Colors in TFT Mode (24-bit per Pixel), Resolution up to 2048 x 2048
USB
– USB 2.0 Full Speed (12 Mbits per second) Host Double Port
Dual On-chip Transceivers
Integrated FIFOs and Dedicated DMA Channels
– USB 2.0 Full Speed (12 Mbits per second) Device Port
On-chip Transceiver, 2-Kbyte Configurable Integrated FIFOs
Bus Matrix
– Handles Five Masters and Five Slaves
– Boot Mode Select Option
– Remap Command
Fully Featured System Controller (SYSC) for Efficient System Management, including
– Reset Controller, Shutdown Controller, Four 32-bit Battery Backup Registers for a Total of 16 Bytes
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– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Real-time Timer
– Three 32-bit PIO Controllers
Reset Controller (RSTC)
– Based on Power-on Reset Cells, Reset Source Identification and Reset Output Control
Shutdown Controller (SHDWC)
– Programmable Shutdown Pin Control and Wake-up Circuitry
Clock Generator (CKGR)
– 32.768 kHz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock
– 3 to 20 MHz On-chip Oscillator and two PLLs
Power Management Controller (PMC)
– Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
– Four Programmable External Clock Signals
Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
Debug Unit (DBGU)
– 2-wire USART and Support for Debug Communication Channel, Programmable ICE Access Prevention
Periodic Interval Timer (PIT)
– 20-bit Interval Timer plus 12-bit Interval Counter
Watchdog Timer (WDT)
– Key Protected, Programmable Only Once, Windowed 12-bit Counter, Running at Slow Clock
Real-Time Timer (RTT)
– 32-bit Free-running Backup Counter Running at Slow Clock
Three 32-bit Parallel Input/Output Controllers (PIO) PIOA, PIOB and PIOC
– 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
Nineteen Peripheral DMA (PDC) Channels
Multimedia Card Interface (MCI)
– Compliant with Multimedia Cards and SDCards
– Automatic Protocol Control and Fast Automatic Data Transfers with PDC, MMC and SDCard Compliant
Three Synchronous Serial Controllers (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
Three Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation
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– Support for ISO7816 T0/T1 Smart Card, Hardware and Software Handshaking, RS485 Support
Two Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
One Three-channel 16-bit Timer/Counters (TC)
– Three External Clock Inputs, Two multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
Two-wire Interface (TWI)
– Master Mode Support, All Two-wire Atmel EEPROMs Supported
IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins
Required Power Supplies:
– 1.08V to 1.32V for VDDCORE and VDDBU
– 3.0V to 3.6V for VDDOSC and for VDDPLL
– 2.7V to 3.6V for VDDIOP (Peripheral I/Os)
– 1.65V to 1.95V and 3.0V to 3.6V for VDDIOM (Memory I/Os)
Available in a 217-ball LFBGA RoHS-compliant Package
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3.2 AT91SAM9G10 Block Diagram
Figure 3-1. Block Diagram
PIO
I DI D
SSC0
SSC1
SSC2
Timer Counter
TC0
TC1
TC2
TWI
LCD Controller
DMA
FIFO
LUT
DMA FIFO
USB Host
FIFO
USB Device
ARM926EJ-S Core
JTAGBoundary Scan ICE
AIC
Fast SRAM160K bytes
PIO
Instruction Cache16K bytes
Fast ROM32K bytes
PeripheralBridge
PeripheralDMA
Controller
PLLA
PLLB
ITCM DTCM
TCMInterface
PMC
RSTC
OSC
PIOA PIOB PIOC
RTT
SHDWC
POR
OSC
WDT
GPBREG
PIT
POR
EBI
StaticMemory
Controller
PIOData Cache
16K bytesMMU
PIO
5-layer Matrix
ETM
CompactFlashNAND Flash
SDRAMController
BIU
PIO
PIO
Tran
scei
ver
Tran
scei
ver
PDC
PDC
PDC
APB
DBGU
MCI
USART0
USART1
USART2
SPI0
SPI1
PDC
PDC
PDC
PDC
PDC
PDC
PDC
System Controller
TF0TK0TD0RD0RK0RF0
TF1TK1TD1RD1RK1RF1
TF2TK2TD2RD2RK2RF2
TCLK0TCLK1TCLK2TIOA0TIOB0TIOA1TIOB1TIOA2TIOB2
TWDTWCK
LCDD0-LCDD23LCDVSYNCLCDHSYNCLCDDOTCKLCDDENLCDCC
MCCKMCCDA
MCDA0-MCDA3
RXD0TXD0SCK0RTS0CTS0
RXD1TXD1SCK1RTS1CTS1
RXD2TXD2SCK2RTS2CTS2
SPI0_NPCS0SPI0_NPCS1SPI0_NPCS2SPI0_NPCS3
SPI0_MISOSPI0_MOSISPI0_SPCK
SPI1_NPCS10SPI1_NPCS1
SPI1_NPCS12SPI1_NPCS3
SPI1_MISOSPI1_MOSISPI1_SPCK
D0-D15A0/NBS0
A2-A15/A18-A21
A16/BA0A17/BA1NCS0NCS1/SDCS
NCS3/NANDCSNRD/CFOENWR0/NWE/CFWENWR1/NBS1/CFIORNWR3/NBS3/CFIOWSDCKSDCKERAS-CASSDWESDA10
A23-A24
NCS5/CFCS1
BMS
NCS2
A25/CFRNWNCS4/CFCS0
NCS6/NANDOENCS7/NANDWE
TSYNC
TCLK
TPS0-TPS2
TPK0-TPK15
D16-D31
A1/NBS2/NWR2
NWAIT
HDMA
HDPB
HDPA
HDMB
DDMDDP
CFCE1CFCE2
JTAGSELTDI
TDO
RTCK
TMSTCK
NTRST
FIQIRQ0-IRQ2
PLLRCB
PLLRCA
DRXDDTXD
XIN32XOUT32
NRST
PCK0-PCK3
SHDNWKUP
GNDBU
XINXOUT
VDDBU
VDDCORE
TST
A22/REG
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3.3 Memory
32 Kbytes of Internal ROM
160 Kbytes of Internal High-speed SRAM
Atmel serial DataFlash
64 Mbytes of SDRAM memory
256 Mbytes of NAND Flash memory
3.4 Clock Circuitry
18.432 MHz standard crystal for the embedded oscillator
32.768 kHz standard crystal for the slow clock oscillator
3.5 Reset Circuitry
Internal reset controller with a bi-directional reset pin
External reset push button
3.6 Shutdown Controller
Programmable shutdown and Wake-Up
Wake-up push button
3.7 Power Supply Circuitry
For dynamic power consumption, the AT91SAM9G10 consumes a maximum of 50 mA on VDDCORE at maximum speed in typical conditions (1.2V, 25°C), processor running full-performance algorithm
On-board 1.2V high efficiency step-down charge pump regulator with shutdown control
On-board 3.3V linear regulator with shutdown control
3.8 Remote Communication
One Serial interface (DBGU COM Port) via RS-232 DB9 male socket
USB V2.0 Full-speed Compliant, 12 Mbits per second (UDP)
Two USB Host port V2.0 Full-speed Compliant, 12 Mbits per second (UHP)
One Ethernet 100-base TX with three status LEDs
3.9 Audio Stereo Interface
One Atmel stereo audio DAC AT73C213
One 32 Ohm/20 mW Stereo Headset output (J20) with Master Volume and Mute Controls
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3.10 User Interface
Four user input pushbuttons
Two user green LEDs
One yellow power LED (can be also software controlled)
One ¼ VGA display LCD with Touchscreen and white LED backlight
3.11 Debug Interface
20-pin JTAG/ICE interface connector
DBGU COM Port
3.12 Expansion Slot
One DataFlash, SD/MMC card slot
All I/Os of the AT91SAM9G10 are routed to peripheral extension footprint connectors (J16 and J17). This allows the developer to check the integrity of the components and to extend the features of the board by adding external hardware components or boards.
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3.13 PIO Usage
Table 3-1. PIO Controller A
I/O Line Peripheral A Peripheral B Comments
PA0 SPI0_MISO MCDA0SD/MMC/DATAFLASH SOCKET (J9) & DATAFLASH DEVICE &
TOUCH SCREEN CONTROLLER & AUDIO DACSPI0_MISO or
MCI0_DA0
PA1 SPI0_MOSI MCCDASD/MMC/DATAFLASH SOCKET (J9) & DATAFLASH DEVICE &
TOUCH SCREEN CONTROLLER & AUDIO DACSPI0_MOSI or
MCI0_CDA
PA2 SPI0_SPCK MCCKSD/MMC/DATAFLASH SOCKET (J9) & DATAFLASH DEVICE &
TOUCH SCREEN CONTROLLER & AUDIO DACSPI0_SPCK or
MCCK
PA3 SPI0_NPCS0 DATAFLASH DEVICE or DATAFLASH SOCKET (J9) SPI0_NPCS0
PA4 SPI0_NPCS1 MCDA1 SD/MMC/DATAFLASH SOCKET (J9) MCDA1
PA5 SPI0_NPCS2 MCDA2 SD/MMC/DATAFLASH SOCKET (J9) MCDA2
PA6 SPI0_NPCS3 MCDA3 SD/MMC/DATAFLASH SOCKET (J9)SPI0_NPCS3 or
MCDA3
PA7 TWD PCK0
PA8 TWCK PCK1
PA9 DRXD PCK2 SERIAL DEBUG PORT (J15) DRXD
PA10 DTXD PCK3 SERIAL DEBUG PORT (J15) DTXD
PA11 TSYNC SCK1 TOUCH SCREEN CONTROLLER (MN16) BUSY PA11
PA12 TCLK RTS1 TFT PANEL CONTROL (J23) POWER CONTROL IN PA12
PA13 TPS0 CTS1 GREEN USER'S LED 1 (DS8) PA13
PA14 TPS1 SCK2 GREEN USER'S LED 2 (DS7) PA14
PA15 TPS2 RTS2
PA16 TPK0 CTS2
PA17 TPK1 TF1 I2S AUDIO DAC AT73C213 (MN15) LRFS TF1
PA18 TPK2 TK1 I2S AUDIO DAC AT73C213 (MN15) BCLK TK1
PA19 TPK3 TD1 I2S AUDIO DAC AT73C213 (MN15) SDIN TD1
PA20 TPK4 RD1
PA21 TPK5 RK1
PA22 TPK6 RF1
PA23 TPK7 RTS0 YELLOW POWER LED CONTROL (DS1) PA23
PA24 TPK8 SPI1_NPCS1 USER'S PUSH BUTTON INPUT (BP6) PA24
PA25 TPK9 SPI1_NPCS2 USER'S PUSH BUTTON INPUT (BP5) PA25
PA26 TPK10 SPI1_NPCS3 USER'S PUSH BUTTON INPUT (BP4) PA26
PA27 TPK11 SPI0_NPCS1 USER'S PUSH BUTTON INPUT (BP3) PA27
PA28 TPK12 SPI0_NPCS2 TOUCH SCREEN CONTROLLER (MN16) SPI0_NPCS2
PA29 TPK13 SPI0_NPCS3 I2S AUDIO DAC AT73C213 (MN15) SPI0_NPCS3
PA30 TPK14 A23
PA31 TPK15 A24
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Table 3-2. PIO Controller B
I/O Line Peripheral A Peripheral B Comments
PB0 LCDVSYNC
PB1 LCDHSYNC TFT PANEL CONTROL (J23) LCDHSYNC
PB2 LCDDOTCK PCK0 TFT PANEL CONTROL (J23) LCDDOTCK
PB3 LCDDEN TFT PANEL CONTROL (J23) LCDDEN
PB4 LCDCC LCDD2 TFT PANEL CONTROL (J23) BACKLIGHT LCDCC
PB5 LCDD0 LCDD3
PB6 LCDD1 LCDD4
PB7 LCDD2 LCDD5 TFT PANEL CONTROL (J23) LCDD2 RED
PB8 LCDD3 LCDD6 TFT PANEL CONTROL (J23) LCDD3 RED
PB9 LCDD4 LCDD7 TFT PANEL CONTROL (J23) LCDD4 RED
PB10 LCDD5 LCDD10 TFT PANEL CONTROL (J23) LCDD5 RED
PB11 LCDD6 LCDD11 TFT PANEL CONTROL (J23) LCDD6 RED
PB12 LCDD7 LCDD12 TFT PANEL CONTROL (J23) LCDD7 RED
PB13 LCDD8 LCDD13
PB14 LCDD9 LCDD14
PB15 LCDD10 LCDD15 TFT PANEL CONTROL (J23) LCDD10 GREEN
PB16 LCDD11 LCDD19 TFT PANEL CONTROL (J23) LCDD11 GREEN
PB17 LCDD12 LCDD20 TFT PANEL CONTROL (J23) LCDD12 GREEN
PB18 LCDD13 LCDD21 TFT PANEL CONTROL (J23) LCDD13 GREEN
PB19 LCDD14 LCDD22 TFT PANEL CONTROL (J23) LCDD14 GREEN
PB20 LCDD15 LCDD23 TFT PANEL CONTROL (J23) LCDD15 GREEN
PB21 TF0 LCDD16
PB22 TK0 LCDD17
PB23 TD0 LCDD18 TFT PANEL CONTROL (J23) LCDD18 BLUE
PB24 RD0 LCDD19 TFT PANEL CONTROL (J23) LCDD19 BLUE
PB25 RK0 LCDD20 TFT PANEL CONTROL (J23) LCDD20 BLUE
PB26 RF0 LCDD21 TFT PANEL CONTROL (J23) LCDD21 BLUE
PB27 SPI1_NPCS1 LCDD22 TFT PANEL CONTROL (J23) LCDD22 BLUE
PB28 SPI1_NPCS0 LCDD23 TFT PANEL CONTROL (J23) LCDD23 BLUE
PB29 SPI1_SPCK IRQ2 USB DEVICE INTERFACE (J19) USB_CNX PB29
PB30 SPI1_MISO IRQ1
PB31 SPI1_MOSI PCK2 I2S AUDIO DAC AT73C213 (MN15) MCLK PCK2
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Table 3-3. PIO Controller C
I/O Line Peripheral A Peripheral B Comments
PC0 NANDOE NCS6 NAND FLASH DEVICE (MN6x) NANDOE
PC1 NANDWE NCS7 NAND FLASH DEVICE (MN6x) NANDWE
PC2 NWAIT IRQ0 TOUCH SCREEN CONTROLLER (MN16) PENIRQ IRQ0
PC3 A25/CFRNW
PC4 NCS4/CFCS0
PC5 NCS5/CFCS1
PC6 CFCE1
PC7 CFCE2
PC8 TXD0 PCK2
PC9 RXD0 PCK3
PC10 RTS0 SCK0 ETHERNET CONTROLLER (MN8) RST PC10
PC11 CTS0 FIQ ETHERNET CONTROLLER (MN8) IRQ PC11
PC12 TXD1 NCS6
PC13 RXD1 NCS7
PC14 TXD2 SPI1_NPCS2 NAND FLASH DEVICE (MN6x) CHIP ENABLE (CE) PC14
PC15 RXD2 SPI1_NPCS3 NAND FLASH DEVICE (MN6x) READY/BUSY (R/B) PC15
PC16 D16 TCLK0 EBI DATA BUS D16 D16
PC17 D17 TCLK1 EBI DATA BUS D17 D17
PC18 D18 TCLK2 EBI DATA BUS D18 D18
PC19 D19 TIOA0 EBI DATA BUS D19 D19
PC20 D20 TIOB0 EBI DATA BUS D20 D20
PC21 D21 TIOA1 EBI DATA BUS D21 D21
PC22 D22 TIOB1 EBI DATA BUS D22 D22
PC23 D23 TIOA2 EBI DATA BUS D23 D23
PC24 D24 TIOB2 EBI DATA BUS D24 D24
PC25 D25 TF2 EBI DATA BUS D25 D25
PC26 D26 TK2 EBI DATA BUS D26 D26
PC27 D27 TD2 EBI DATA BUS D27 D27
PC28 D28 RD2 EBI DATA BUS D28 D28
PC29 D29 RK2 EBI DATA BUS D29 D29
PC30 D30 RF2 EBI DATA BUS D30 D30
PC31 D31 PCK1 EBI DATA BUS D31 D31
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3-10 AT91SAM9G10-EK Evaluation Board User Guide
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Section 4
Configuration Straps
4.1 Configuration StrapsTable 4-1 gives details on configuration straps on the AT91SAM9G10-EK evaluation board and their default settings.
Table 4-1. Configuration Jumpers and Straps
DesignationDefault Setting Feature
J2 Closed
3.3V Jumper (1) This jumper footprint is provided for 3.3V power consumption measurement use. By default, it is closed. To use this feature, the user has to open the strap by cutting it before soldering a jumper.
J3 ClosedForces power on. To use the software shutdown control, J3 must be opened.
J4 Open Enables Boot on the internal ROM
Closed Enables Boot on the NCS0
J8 Closed VDDPLL Jumper (1)
J9 2-3VDDBU Jumper select (1) 1-2: Lithium 3V Battery 2-3: 1.2V from VDDCORE
J12 Closed VDDCORE Jumper (1)
J21 1-2
NPCS0 select 1-2: DataFlash device (MN7) 2-3: DataFlash card interface (J22) Warning: In this case NPCS03 must be configured as input.
J24 ClosedEnables the selection of the on-board Nand-Flash device. Remove this jumper to prevent the system boot from that device and to be able to reprogram it.
S2 Open Disables the ICE NTRST input
S3 Closed Enables the ICE RTCK return. S6 must be opened
S4 Closed Enables the ICE NRST input
S5 Open Selects ICE mode or JTAG mode (See Section 6, Errata)
S6 OpenDisables TCK <-> RTCK local loop. If S6 is closed, S3 must be opened.
S7-S8S9
Closed Enables the use of 18.432 MHz crystal. If external clock used, S7-S8 must be opened and S9 closed.Open
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Note: 1. These jumpers are provided for measuring power consumption. By default, they are closed. To use this feature, the user has to open the strap and insert an ammeter.
S10 Closed Enables the use of SDRAM (NCS1_SDCS)
S12 Open Disables Serial DataFlash write protect.
S13 Closed Disables NAND FLASH write protect.
S14 Closed Enables the use of interrupt ETHERNET MAC (PC11_FIQ).
S15 Closed Enables the use of ETHERNET MAC (NCS2).
S16 OpenDisables the use of NWAIT ETHERNET MAC signal (PC2_NWAIT)
S19 Closed Enables the use of the User LED DS7 (PA14)
S20 Closed Enables the use of the User LED DS8 (PA13)
S21 Closed Enables the use of the DBGU RXD signal (PA9)
S22 Closed Enables the use of the USB CNX detection (PB29)
S23 Closed Enables the use of AUDIO DAC INTERFACE (NPCS03)
S24 ClosedEnables the use of TOUCH SCREEN CONTROLLER (NPCS02)
S25 ClosedEnables the use of TOUCH SCREEN CONTROLLER BUSY signal (PA11)
S26 ClosedEnables the use of TOUCH SCREEN CONTROLLER PENIRQ (PC2_IRQ0)
TP1 N.A 3.3V Test point.
TP2 N.A GND Test point.
TP3 N.A 1.2V Test point.
TP4 N.A GND Test point.
TP63 N.A 0 to 3.3V analog user's input
TP64 N.A 0 to 3.3V analog user's input
TP65 N.A AGND of TP63
TP66 N.A AGND of TP64
Table 4-1. Configuration Jumpers and Straps
DesignationDefault Setting Feature
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Section 5
Schematics
5.1 SchematicsThis section contains the following schematics:
Power Supply and Audio
AT91SAM9G10 Device
SDRAM and NAND Flash
Ethernet
LCD and User Interface
Serial and I/O Expansion
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8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
AU
DIO
DA
C IN
TER
FAC
E5
V
EB
I SD
RA
M
NA
ND
FLA
SH
SD
RA
M
CARDREADER
MM
C/S
DD
ATA
FAS
H C
AR
D
SE
RIA
LD
ATA
FLA
SH
ICE
INTE
RFA
CE
DE
BU
GP
OR
T
US
B IN
TER
FAC
ES
HO
ST
DE
VIC
EE
XP
AN
SIO
N C
ON
NE
CTO
RS
LCD
US
ER
INTE
RFA
CE
TOUCH SCREENCONTROLLER
ATMEL ARM9 Processor SAM9G10 (LFBGA217)
EBI SDRAM INTERFACE
PIO A,B,C
DATA BUS
ADRESSE BUS
DATA BUS
"DNP" means the component is not populated by defaultNOTE
SHEET 2
SHEET 3
SHEET 4
SHEET 5
SHEET 6
PIO A,B,C
PIO A,B,C
PIO A,B,C
POWER
SHEET 7
ETH
ER
NE
T
REV DATEMODIF. DES. DATE VER.
SCALE1/1 REV. SHEET
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INIT EDITA
AT91SAM9G10-EK17
15MAY09
A
XX/XX/XXPP XXX
TOP LEVEL
REV DATEMODIF. DES. DATE VER.
SCALE1/1 REV. SHEET
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INIT EDITA
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15MAY09
A
XX/XX/XXPP XXX
TOP LEVEL
REV DATEMODIF. DES. DATE VER.
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TOP LEVEL
PIOAPA0PA1PA2PA3PA4PA5PA6PA7PA8PA9PA10PA11PA12PA13PA14PA15
PA16PA17PA18PA19PA20PA21PA22PA23PA24PA25PA26PA27PA28PA29PA30PA31
PIOA PIOB PIOB PIOCPB0PB1PB2PB3PB4PB5PB6PB7PB8PB9PB10PB11
PB13PB12
PB14PB15
PB16PB17PB18PB19
PB21PB20
PB22PB23PB24PB25PB26PB27PB28PB29PB30PB31
PIO MUXING
PC0
PC2PC1
PC3PC4PC5PC6PC7PC8PC9PC10PC11PC12PC13PC14PC15
USAGE USAGE USAGE USAGE USAGESPI0_MISO /MCDA0SPI0_MOSI /MCCDASPI0_SPCK
MCDA2
SPI0_NPCS0MCDA1
SPI0_NPCS3 MCDA3
DBGU_TXD
--
BUSY
--
POWER CONTROL IN
DBGU_RXD
USER LEDUSER LED--
--
--
----POWER LEDBP6BP5BP4
--
BP3
TF1
SPI0_NPCS2
TK1
SPI0_NPCS3
TD1
--
--R0
G5
PCK2
R1
R3
--
R2
R4
--
R5
B0
--
B1
--
B2
G0
B3
G1
B4
G2
B5
G3
USB_CNX
--
G4
LCDHSYNCLCDDDOTCKLCDDENLCDCC--
USB_DP_PUP
------RSTFIQ----#CER/#B
NANDOENANDWEIRQ0 /NWAIT--------
PIOAPA0PA1PA2PA3PA4PA5PA6PA7PA8PA9PA10PA11PA12PA13PA14PA15
PA16PA17PA18PA19PA20PA21PA22PA23PA24PA25PA26PA27PA28PA29PA30PA31
PIOA PIOB PIOB PIOCPB0PB1PB2PB3PB4PB5PB6PB7PB8PB9PB10PB11
PB13PB12
PB14PB15
PB16PB17PB18PB19
PB21PB20
PB22PB23PB24PB25PB26PB27PB28PB29PB30PB31
PIO MUXING
PC0
PC2PC1
PC3PC4PC5PC6PC7PC8PC9PC10PC11PC12PC13PC14PC15
USAGE USAGE USAGE USAGE USAGESPI0_MISO /MCDA0SPI0_MOSI /MCCDASPI0_SPCK
MCDA2
SPI0_NPCS0MCDA1
SPI0_NPCS3 MCDA3
DBGU_TXD
--
BUSY
--
POWER CONTROL IN
DBGU_RXD
USER LEDUSER LED--
--
--
----POWER LEDBP6BP5BP4
--
BP3
TF1
SPI0_NPCS2
TK1
SPI0_NPCS3
TD1
--
--R0
G5
PCK2
R1
R3
--
R2
R4
--
R5
B0
--
B1
--
B2
G0
B3
G1
B4
G2
B5
G3
USB_CNX
--
G4
LCDHSYNCLCDDDOTCKLCDDENLCDCC--
USB_DP_PUP
------RSTFIQ----#CER/#B
NANDOENANDWEIRQ0 /NWAIT--------
PIOAPA0PA1PA2PA3PA4PA5PA6PA7PA8PA9PA10PA11PA12PA13PA14PA15
PA16PA17PA18PA19PA20PA21PA22PA23PA24PA25PA26PA27PA28PA29PA30PA31
PIOA PIOB PIOB PIOCPB0PB1PB2PB3PB4PB5PB6PB7PB8PB9PB10PB11
PB13PB12
PB14PB15
PB16PB17PB18PB19
PB21PB20
PB22PB23PB24PB25PB26PB27PB28PB29PB30PB31
PIO MUXING
PC0
PC2PC1
PC3PC4PC5PC6PC7PC8PC9PC10PC11PC12PC13PC14PC15
USAGE USAGE USAGE USAGE USAGESPI0_MISO /MCDA0SPI0_MOSI /MCCDASPI0_SPCK
MCDA2
SPI0_NPCS0MCDA1
SPI0_NPCS3 MCDA3
DBGU_TXD
--
BUSY
--
POWER CONTROL IN
DBGU_RXD
USER LEDUSER LED--
--
--
----POWER LEDBP6BP5BP4
--
BP3
TF1
SPI0_NPCS2
TK1
SPI0_NPCS3
TD1
--
--R0
G5
PCK2
R1
R3
--
R2
R4
--
R5
B0
--
B1
--
B2
G0
B3
G1
B4
G2
B5
G3
USB_CNX
--
G4
LCDHSYNCLCDDDOTCKLCDDENLCDCC--
USB_DP_PUP
------RSTFIQ----#CER/#B
NANDOENANDWEIRQ0 /NWAIT--------
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8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
10 SQUARE CM COPPER AREA FOR HEAT SINKINGWITH NO SOLDER MASK
REGULATED5V ONLY
FORCEPOWERON
GND
3.3V
1.2V
GND
POWER LED
ADHESIVE FEET
AUDIO DAC INTERFACE
SPI0_MISOSPI0_MOSISPI0_SPCKSPI0_NPCS3
TF1TD1
TK1
PCK2
PA0PA1PA2
PA29
PA17PA19
PA18
PB31
PA23
GND_DAC
GND_DAC
GND_DAC
3V3
VCC_DAC
3V3
VCC_DAC
3V3
5V
5V
3V3
1V2
3V3
PA23 {3,7}
M5V {6}
SHDN{3,7}
PB31 {3,7}
PA0 {3,4,6,7}
PA19 {3,7}PA17 {3,7}PA18 {3,7}
PA1 {3,4,6,7}PA2 {3,4,6,7}PA29 {3,7}
NRST {3,4,5,7}
REV DATEMODIF. DES. DATE VER.
SCALE1/1 REV. SHEET
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INIT EDITA
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15MAY09
A
XX/XX/XXPP XXX
POWER SUPPLY & AUDIO
REV DATEMODIF. DES. DATE VER.
SCALE1/1 REV. SHEET
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INIT EDITA
AT91SAM9G10-EK27
15MAY09
A
XX/XX/XXPP XXX
POWER SUPPLY & AUDIO
REV DATEMODIF. DES. DATE VER.
SCALE1/1 REV. SHEET
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INIT EDITA
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XX/XX/XXPP XXX
POWER SUPPLY & AUDIO
R3100KR3100K
MN1
LT1963AEQ-3.3
MN1
LT1963AEQ-3.3
VIN2
GND
3
VOUT4
GND
6
SD
1
FB
5
R1120RR1120R
C114
10V10µFC114
10V10µF
R2100KR2100K
C2
10V10µFC2
10V10µF
C111 10uFC111 10uF
J1J1 12
3
C109100NFC109100NF
LINER
LINEL
MONOP
MONON
PAINN
PAINP
LPHNHPN
HPPCBPVBAT
VCM
AUXP
AUXN
HSR
HSL
SMODERSTB
DOUTDINCLKCS
VREF
MCLKSDINLRFSBCLK
VDIG
AVDDHS
AVDD
INGND GNDDGNDB
MN15 AT73C213
LINER
LINEL
MONOP
MONON
PAINN
PAINP
LPHNHPN
HPPCBPVBAT
VCM
AUXP
AUXN
HSR
HSL
SMODERSTB
DOUTDINCLKCS
VREF
MCLKSDINLRFSBCLK
VDIG
AVDDHS
AVDD
INGND GNDDGNDB
MN15 AT73C213
1
2
3
4
5
6
7
8
9
1011
12
1314
15
16
17
1819
20
2122
23
24
25262728
29
30
31
32
33
C107 10uFC107 10uF
Q2Si1563EDHQ2Si1563EDH
1 32
456
R67100KR67100KTP1TP1
+
C112 6V3100µF
+
C112 6V3100µF
TP3TP3
TP2TP2
R69 0RR69 0R
C51uFC51uF
DS1YELLOWDS1YELLOW
CR15VCR15V
C104.7uFC104.7uFC9
15PFC915PF
J2J2
J20
3.5 PHONEJACK STEREO
J20
3.5 PHONEJACK STEREO
2
13
4
C61uFC61uF
TP4TP4
R510KR510K
Z7
11.1
Z7
11.1
Q1IRLML2402Q1IRLML2402
1
3
2
C110100NFC110100NF
C310µFC310µF
Z8
11.1
Z8
11.1
S23S23
J3J3
12
C722uFC722uF
C410µFC410µF
Z3
11.1
Z3
11.1
R4200KR4200K
MN2
TPS60500
MN2
TPS60500
C1M
8
GND
9
VOUT7
EN1
VIN5
C1P
6
C2M
3
C2P
4
FB10
PG2
L44.7uH
L44.7uH
R610KR610K
+C113
6V3100µF
+C113
6V3100µF
R6847RR6847R
C108100NFC108100NF
+C1330µF
+C1330µF
Z4
11.1
Z4
11.1
C810PFC810PF
![Page 28: AT91SAM9G10-EK Evaluation Board - Microchip Technology](https://reader034.vdocuments.us/reader034/viewer/2022052602/628d0afc2ccf6178d15dc6d9/html5/thumbnails/28.jpg)
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
�����
VDDCORE CURRENT MEASURE
VDDOSC + VDDPLLCURRENT MEASURE
WAKE UP
������������
BMSBOOT MODE SELECT
PIPESTAT[2]TRACESYNC
GND
VSUPPLY
TRACEPKT[0]TRACEPKT[1]TRACEPKT[2]TRACEPKT[3]TRACEPKT[4]TRACEPKT[5]TRACEPKT[6]TRACEPKT[7]
TRACEPKT[8]TRACEPKT[9]TRACEPKT[10]TRACEPKT[11]TRACEPKT[12]TRACEPKT[13]TRACEPKT[14]
EXTTRIG
TRACEPKT[15]
TRACECLK
DBGRQ
PIPESTAT[0]PIPESTAT[1]
TRACE PORTETM
ICE_NRST
PB3
PA31
D13
A16
A1
D14
A12
A8
A5
PA4PA5PA6
PA24
A18
PA15 D10
A21
A14
PA19PA20
A17
TMSTDI
TCK
D4
A13
A2
PA8
PA11
PA13
PA29
D12
A15
PA7
PA10
PA16
A20
A11
A9
PA26PA27
A7
A0
PA25
PA2
PA30
PA12
PA17
PA21
PA23
D9
D3
D1D0
PA1
D5
A19
PA22
D11
D6
PA28
PA0
PA3
PA9
PA14
D15
A22
ICE_NTRST
PA18
D8D7
D2
A10
A6
A4A3
ICE_RTCK
NRST
NRST
PA15PA11PA16PA17PA18PA19PA20PA21PA22PA23
PA24PA25PA26PA27PA28PA29PA30PA31
ICE_NTRST
PA12
TDITMS
ICE_RTCKTDO
ICE_NRST
TCK
PA13PA14
TDO
D28
D20
D29
D19
D30
D26
D23
D22
D31
D24
D25
D21
D27
D17
D18
D16
PC
5P
C6
PC
2
PC
9
PC
3
PC
0
PC
4
PC
8P
C7
PC
1
PC
10
PC
15P
C14
PC
12P
C11
PC
13
PB
2P
B1
PB
5P
B4
PB
3
PB
0
PB
7
PB
13
PB
8
PB
12
PB
9
PB
17P
B16
PB
10
PB
6
PB
15P
B14
PB
11
PB
27
PB
29
PB
26
PB
21
PB
25
PB
28
PB
24
PB
30
PB
23
PB
19
PB
22
PB
20
PB
18
PB
31
3V3
3V3
3V3
3V3
3V3
3V3
3V3
1V2
1V2
RAS {4,7}
NRST {2,4,5,7}
PA[0..31]{2,4,6,7}
A[0..22] {4,5,7}
D[0..31] {4,5,7}
PC[0..15]{4,5,6,7}
PB[0..31]{2,6,7}
CAS {4,7}
SDWE {4,7}SDA10 {4,7}
SDCK {4,7}SDCKE {4,7}
SDCS_NCS1 {4,7}NCS0 {7}
NCS2 {5,7}SMCS_NCS3 {7}CFOE_NOE_NRD {5,7}
CFIOR_NBS1_NWR1 {4,7}CFWE_NWE_NWR0 {5,7}
CFIOW_NBS3_NWR3 {4,7}
VDDBU{7}SHDN{2,7}
DDP{7}DDM{7}
HDPA{7}HDMA{7}
HDPB{7}HDMB{7}
WKUP{7}
REV DATEMODIF. DES. DATE VER.
SCALE1/1 REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
INIT EDITA
AT91SAM9G10-EK37
15/05/09
A
XX/XX/XXPP XXX
AT91SAM9G10
REV DATEMODIF. DES. DATE VER.
SCALE1/1 REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
INIT EDITA
AT91SAM9G10-EK37
15/05/09
A
XX/XX/XXPP XXX
AT91SAM9G10
REV DATEMODIF. DES. DATE VER.
SCALE1/1 REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
INIT EDITA
AT91SAM9G10-EK37
15/05/09
A
XX/XX/XXPP XXX
AT91SAM9G10
C22100NFC22100NF
J12J121 2
C26100NFC26100NF
C1910PFC1910PF
C1415nFC1415nF
J6J6
12345678910111213151719
14161820
R12 2KR12 2K
C23
10V10µFC23
10V10µF
R141KR141K
R131KR131K
C34100NFC34100NF
C28
10V10µFC28
10V10µF
C2010PFC2010PF
C32100NFC32100NF
R15 1KR15 1K
J4J4
12
S8S8
C13 2.2nFC13 2.2nF
C35100NFC35100NF
C37100NFC37100NF
R11 1,5K1%
R11 1,5K1%
Y118.4320MHzY118.4320MHz
12
R8DNP
R8DNP
C41100NFC41100NF
C42100NFC42100NFBP2BP2
R17
100K
R17
100K
R10DNP
R10DNP
J7DNP
SMB MALE
J7DNP
SMB MALE
12 3
54
C27100NFC27100NF
C126100NFC126100NF
J9J9123
S5S5
S6S6
C25100NFC25100NF
J8J812
C15 1.5nFC15 1.5nF
C1710PFC1710PF
C39100NFC39100NF
C36100NFC36100NF
C1222nF C1222nF
S9S9
C33100NFC33100NF
C29100NFC29100NF
BP1BP1
MN10R1100D121CMN10R1100D121C
OU
T1
VD
D2
GN
D3
C11DNPC11DNP
C24100NFC24100NF
R16
DNP
R16
DNP
S3S3
J10J10
C40100NFC40100NF
R9
DNP
R9
DNP
AT91SAM9G10
MN3
AT91SAM9G10
MN3
NBS0/A0D8
NWR2/NBS2/A1B8
A2A8
A3A7
A4B7
A5D7
A6A6
A7B6
A8C6
A9A5
A10D6
A11B5
A12A4
A13B4
A14A3
A15B3
BA0/A16A2
BA1/A17C4
A18B2
A19A1
A20B1
A21C2
A22C1
D0G1
D1G2
D2H1
D3H2
D4J1
D5J2
D6K1
D7K4
D8K2
D9L1
D10K3
D11L2
D12L3
D13M1
D14N1
D15M2
TCKD17
TDOF16
TDIE17
TMSC17
RASF2
CASJ4
SDWEG3
PA24/TPK8/SPI1_NPCS1N17 PA23/TPK7/RTS0N16 PA22/TPK6/RF1N14 PA21/TPK5/RK1N15 PA20/TPK4/RD1P17 PA19/TPK3/TD1P16 PA18/TPK2/TK1R17 PA17/TPK1/TF1R15 PA16/TPK0/CTS2P14 PA15/TPS2/RTS2P13 PA14/TPS1/SCK2T17 PA13/TPS0/CTS1R14 PA12/TCLK/RTS1U15 PA11/TSYNK/SCK1T16 PA10/DTXD/PCK3R13 PA9/DRXD/PCK2U16 PA8/TWCK/PCK1T15 PA7/TWD/PCK0R12 PA6/SPI0_NPCS3/MCDA3T14 PA5/SPI0_NPCS2/MCDA2U14 PA4/SPI0_NPCS1/MCDA1T13 PA3/SPI0_NPCS0P10 PA2/SPI0_SPCK/MCCKU13 PA1/SPI0_MOSI/MCCDAT12 PA0/SPI0_MISO/MCDA0R11
PA28/TPK12/SPI0_NPCS2M16 PA27/TPK11/SPI0_NPCS1L15 PA26/TPK10/SPI1_NPCS3M15 PA25/TPK9/SPI1_NPCS2M14
PA29/TPK13/SPI0_NPCS3M17
PA30/TPK14/A23L14
PA31/TPK15/A24L16
LCD
VS
YN
C/P
B0
L17
LCD
HS
YN
K/P
B1
K16
LCD
DO
TCK
/PC
K0/
PB
2K
17
BM
S/L
CD
DE
N/P
B3
K15
LCD
CC
/LC
DD
2/P
B4
J17
LCD
D0/
LCD
D3/
PB
5H
17
LCD
D1/
LCD
D4/
PB
6J1
6
LCD
D2/
LCD
D5/
PB
7H
16
LCD
D3/
LCD
D6/
PB
8G
17
LCD
D4/
LCD
D7/
PB
9J1
5
LCD
D5/
LCD
D10
/PB
10H
14
LCD
D6/
LCD
D11
/PB
11G
16
LCD
D7/
LCD
D12
/PB
12G
15
LCD
D8/
LCD
D13
/PB
13H
15
LCD
D9/
LCD
D14
/PB
14G
14
LCD
D10
/LC
DD
15/P
B15
E16
NRSTF15
TSTC10
VD
DC
OR
EP
12V
DD
CO
RE
M4
VD
DC
OR
ED
5
VD
DC
OR
EK
14
LCD
D11
/LC
DD
19/P
B16
F14
LCD
D12
/LC
DD
20/P
B17
D16
LCD
D13
/LC
DD
21/P
B18
E15
LCD
D14
/LC
DD
22/P
B19
B17
LCD
D15
/LC
DD
23/P
B20
D15
TF0/
LCD
D16
/PB
21C
16
TK0/
LCD
D17
/PB
22E
14
TD0/
LCD
D18
/PB
23D
14
RD
0/LC
DD
19/P
B24
A17
RK
0/LC
DD
20/P
B25
B16
RF0
/LC
DD
21/P
B26
B15
SP
I1_N
PC
S1/
LCD
D22
/PB
27A
15
SP
I1_N
PC
S0/
LCD
D23
/PB
28D
13
SP
I1_M
ISO
/IRQ
1/P
B30
C13
JTAGSELB10
GN
DA
16
GN
DC
7
GN
DC
11
GN
DD
3
GN
DH
8
GN
DH
9
GN
DH
10
GN
DJ3
GN
DJ8
GN
DJ9
GN
DJ1
0
GN
DK
8
GN
DK
9
GN
DK
10
GN
DR
3
GN
DR
16
GN
DU
4
GN
DU
7
VD
DIO
MC
3
VD
DIO
MC
5
VD
DIO
MC
8
VD
DIO
MD
4
VD
DIO
MH
3
VD
DIO
ML4
VD
DIO
MN
4
VD
DIO
PC
15
VD
DIO
PD
11
VD
DIO
PJ1
4
VD
DIO
PP
11
VD
DIO
PP
15
VD
DIO
PT5
VD
DIO
PU
6
XOUTU12
XINU11
VDDOSCT10
GNDOSCT11
XOUT32A10
XIN32A11
VDDPLLR10
GNDPLLP9
PLLRCAU10
SDA10E4
SDCKEF1
SDCKH4
CFWE/NWE/NWR0E2
CFIOR/NBS1/NWR1E1
CFIOW/NBS3/NWR3F3
NCS0F4
SDCS/NCS1D2
NCS2D1
NANDCS/NCS3G4
CFOE/NRDE3
DDMB12 DDPA12
HDPAC12
HDMAB14
HDPBA13
HDMBA14
PLLRCBU9
SP
I1_S
PC
K/IR
Q2/
PB
29D
12
SP
I1_M
OS
I/PC
K2/
PB
31B
13
NA
ND
OE
/NC
S6/
PC
0U
2
NA
ND
WE
/NC
S7/
PC
1P
6
NW
AIT
/IRQ
0/P
C2
T4
A25
/CFR
NW
/PC
3U
3
NC
S4/
CFC
S0/
PC
4R
6
NC
S5/
CFC
S1/
PC
5T6
CFC
E1/
PC
6U
5
CFC
E2/
PC
7P
7
TXD
0/P
CK
2/P
C8
R7
RX
D0/
PC
K3/
PC
9T7
RTS
0/S
CK
0/P
C10
T8
CTS
0/FI
Q/P
C11
P8
TXD
1/N
CS
6/P
C12
R8
RX
D1/
NC
S7/
PC
13U
8
TXD
2/S
PI1
_NP
CS
2/P
C14
R9
RX
D2/
SP
I1_N
PC
S3/
PC
15T9
D16
/TC
LK0/
PC
16P
1
D17
/TC
LK1/
PC
17N
2
D18
/TC
LK2/
PC
18M
3
D19
/TIO
A0/
PC
19R
1
D20
/TIO
B0/
PC
20T1
D21
/TIO
A1/
PC
21R
2
D22
/TIO
B1/
PC
22P
3
D23
/TIO
A2/
PC
23T2
D24
/TIO
B2/
PC
24P
4
D25
/TF2
/PC
25U
1
D26
/TK
2/P
C26
T3
D27
/TD
2/P
C27
R4
D28
/RD
2/P
C28
P5
D29
/RK
2/P
C29
R5
D30
/RF2
/PC
30P
2
D31
/PC
K1/
PC
31N
3
NC1A9
NC2C14
NC3D10
NTRSTF17
GN
DB
UC
9
VD
DB
UB
9
WK
UP
B11
SH
DN
D9
RTCKU17
S2S2
C30100NFC30100NF
R7 1KR7 1K
C38100NFC38100NF
C1610PFC1610PF
RR1100KRR1100K
1
5
2346 7 8
Y232.768 kHzY232.768 kHz
14
S7S7
J5DNPJ5DNP
135791113151719212325272931333537
2468
101214161820222426283032343638
G1
G2
G3
G4
G5
C18100NFC18100NF
C31100NFC31100NF
C43
10V10µFC43
10V10µFCR2
MMBD1704ACR2
MMBD1704A
1
3
2
C21100NFC21100NF
S4S4
![Page 29: AT91SAM9G10-EK Evaluation Board - Microchip Technology](https://reader034.vdocuments.us/reader034/viewer/2022052602/628d0afc2ccf6178d15dc6d9/html5/thumbnails/29.jpg)
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NBS0 NBS2
EBI SDRAM INTERFACE
BA0BA1
BA0BA1
256 Mbits 256 Mbits
SPI0_NPCS0
SPI0_MISO
SPI0_SPCKSPI0_MOSI
WRITE PROTECTNORMALLY OPEN
DUAL FOOTPRINT
SD CARD / MMC CARDDATAFLASH CARDINTERFACE
SPI0_SPCK MCCK
SPI0_MOSI MCCDA
MCDA1SPI0_MISO MCDA0
MCDA2SPI0_NPCS3 MCDA3
16-bit bus width 8-bit bus width
CAS
SDCKE
SDCK
CFIOW_NBS3_NWR3
RAS
SDWE
SDA10
D13
D18
D12
D22
D8D7
D3
D28D11
D26
D21
D2
D14
D4
D24
D0
D23
RAS
D27
D1
D19
D10
D31
D17
CAS
SDA10D25
D29
D16
SDCK
D9
D20
SDWE
SDCKE
D5
D30D15
D6
D6
D0
D3D4
D2D1
D5
D7
D14
D8
D11D12
D10D9
D13
D15
A5
A16
A2
A11
A7
A4
CFIOR_NBS1_NWR1
A9
A14
A21A22
A8
A1
A5
A2
A17
A13
A6
A3A3
A10
A16
A10
A13
A8
A17
A6
A4
A14
A9
A7
A11
A0
WP
PA1PA2
PA0
PA3
D6
D0
D3D4
D2D1
D5
D7
A21A22
NANDCE
PC15
PC1PC0
PC1PC14
PC15
PC0
WP
PA5
PA2
PA0
PA1
PA4
PA6
NANDCENANDCE
3V33V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V33V3
D[0..31]{3,5,7}
RAS{3,7}CAS{3,7}
SDWE{3,7}SDA10{3,7}SDCKE{3,7}SDCK{3,7}
CFIOR_NBS1_NWR1{3,7}CFIOW_NBS3_NWR3{3,7}
SDCS_NCS1{3,7}
A[0..22]{3,5,7}
D[0..31]{3,5,7}
A21{3,7}A22{3,7}PC0{3,7}PC1{3,7}PC14{3,7}
PC15{3,7}
PA1{2,3,6,7}PA0{2,3,6,7}
PA2{2,3,6,7}
PA3{3,7}
PA4{3,7}
PA6{3,7}PA5{3,7}
NRST{2,3,5,7}
REV DATEMODIF. DES. DATE VER.
SCALE1/1 REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
INIT EDITA
AT91SAM9G10-EK47
15MAY09
A
XX/XX/XXPP XXX
SDRAM & NANDFLASH
REV DATEMODIF. DES. DATE VER.
SCALE1/1 REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
INIT EDITA
AT91SAM9G10-EK47
15MAY09
A
XX/XX/XXPP XXX
SDRAM & NANDFLASH
REV DATEMODIF. DES. DATE VER.
SCALE1/1 REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
INIT EDITA
AT91SAM9G10-EK47
15MAY09
A
XX/XX/XXPP XXX
SDRAM & NANDFLASH
C56100NFC56100NF
C46100NFC46100NF
R19100KR19100K
J22
FPS009
J22
FPS009
8
5
76
43219
MT48LC16M16A2
MN4
MT48LC16M16A2
MN4
A023
A124
A225
A326
A429
A530
A631
A732
A833
A934
A1022
BA020
A1236
DQ02
DQ14
DQ25
DQ37
DQ48
DQ510
DQ611
DQ713
DQ842
DQ944
DQ1045
DQ1147
DQ1248
DQ1350
DQ1451
DQ1553
VDD1
VSS28
VSS41
VDDQ3VDD27
N.C40
CLK38
CKE37
DQML15
DQMH39
CAS17
RAS18
WE16
CS19
VDDQ9
VDDQ43
VDDQ49
VSSQ6
VSSQ12
VSSQ46
VSSQ52
VDD14
VSS54
A1135
BA121
MT48LC16M16A2
MN5
MT48LC16M16A2
MN5
A023
A124
A225
A326
A429
A530
A631
A732
A833
A934
A1022
BA020
A1236
DQ02
DQ14
DQ25
DQ37
DQ48
DQ510
DQ611
DQ713
DQ842
DQ944
DQ1045
DQ1147
DQ1248
DQ1350
DQ1451
DQ1553
VDD1
VSS28
VSS41
VDDQ3VDD27
N.C40
CLK38
CKE37
DQML15
DQMH39
CAS17
RAS18
WE16
CS19
VDDQ9
VDDQ43
VDDQ49
VSSQ6
VSSQ12
VSSQ46
VSSQ52
VDD14
VSS54
A1135
BA121
C49100NFC49100NF
J24J241 2
R20 100KR20 100K
C59100NFC59100NF
R85 100KR85 100K
C44100NFC44100NF
C48100NFC48100NF
C50100NFC50100NF
C55100NFC55100NF
MN6B
K9F2G08U0A-PCB0
MN6B
K9F2G08U0A-PCB0
WE18
N.C66
VCC37
CE9
RE8
N.C1120
WP19
N.C55
N.C11
N.C22
N.C33
N.C44
N.C1221
N.C1322
N.C1423
N.C1524
R/B7
N.C1726
N.C2827N.C2728
I/O029
N.C2534N.C2435
VSS36
PRE38N.C2339
VCC12
VSS13
ALE17
N.C811 N.C710
N.C914
N.C1015
CLE16
N.C1625
N.C2633
I/O130
I/O332I/O231
N.C1947
N.C2046
N.C2145
I/O744I/O643I/O542I/O441
N.C2240
N.C1848
S13S13
J21J21
123
C47100NFC47100NF
C58100NFC58100NF
S10S10
C51100NFC51100NF
R18100KR18100K
C53100NFC53100NF
C54100NFC54100NF
R7210KR7210K
MN6A
DNPMT29F2G16AABWP
MN6A
DNPMT29F2G16AABWP
WE18
N.C66
VCC37
CE9
RE8
N.C1120
WP19
N.C55
N.C11
N.C22
N.C33
N.C44
N.C1221
N.C1322
N.C1423
N.C1524
R/B7
I/O026
I/O827
I/O128
I/O929
N.C1634
N.C1735
N.C1936PRE38N.C1839
VCC12
VSS13
ALE17
N.C811 N.C710
N.C914
N.C1015
CLE16
VSS25
I/O1133
I/O230
I/O332
I/O1031
I/O1547
I/O746
I/O1445
I/O644
I/O1343
I/O542
I/O1241
I/O440
VSS48
C60100NFC60100NF
C57100NFC57100NF
C45100NFC45100NF
C115100NFC115100NF
S12S12
MN7
AT45DB642D-CNU
MN7
AT45DB642D-CNU
RESET3
GND7
VCC6
CS4 SCK2 SI1 SO8
WP5
C52100NFC52100NF
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8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Note1: 8/16 bit DataBusselection; Removed R27when using 16-bit mode;otherwise is 8-bit mode.
LINK&ACT
SPEED 100
FULL DUPLEX
NWAIT
FIQ
RST
NOT USED
D1
PC10
D5
D3
A2
D6
D2
D4
D0
D7
D15D14D13D12D11D10D9D8
PC11
PC2
VCCA
3V3
3V3
3V3
VCCA
VCCA VCCA
3V3
3V3
3V3
3V3 VCCA
3V3
3V33V3
3V3
3V3 3V3 3V33V3
3V3
D[0..15]{3,4,7}
NRST{2,3,4,7}
A2{3,4,7}
PC11{3,7}
CFOE_NOE_NRD{3,7}CFWE_NWE_NWR0{3,7}
NCS2{3,7}
PC10{3,7}
PC2{3,6,7}
REV DATEMODIF. DES. DATE VER.
SCALE1/1 REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
INIT EDITA
AT91SAM9G10-EK57
15MAY09
A
XX/XX/XXPP XXX
ETHERNET
REV DATEMODIF. DES. DATE VER.
SCALE1/1 REV. SHEET
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INIT EDITA
AT91SAM9G10-EK57
15MAY09
A
XX/XX/XXPP XXX
ETHERNET
REV DATEMODIF. DES. DATE VER.
SCALE1/1 REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
INIT EDITA
AT91SAM9G10-EK57
15MAY09
A
XX/XX/XXPP XXX
ETHERNET
C77100NFC77100NF
R3049R91%
R3049R91%
S15S15
S16S16
C62 100NFC62 100NF
R284,7KR284,7K
R316,80K
1%
R316,80K
1%
S14S14
DS3 YELLOWDS3 YELLOW
R24 1KR24 1KDS4 GREENDS4 GREEN
C64100NFC64100NF
R21 1KR21 1K
L1 742792093L1 742792093
R344,7KR344,7K
C78
10V10µFC78
10V10µF
R22 1KR22 1K
DM9000
MN8DM9000E
DM9000
MN8DM9000E
IOR
#1
IOW
#2
AE
N3
IOW
AIT
4
DV
DD
5
SD
06
SD
17
SD
28
SD
39
SD
410
SD
511
SD
612
SD
713
RS
T14
DG
ND
15
TE
ST
116
TE
ST
217
TE
ST
318
TE
ST
419
DV
DD
20
X2_
25M
21
X1_
25M
22
DG
ND
23
SD
24
AG
ND
25
BGRES26AVDD27AVDD28RXI+29RXI-30AGND31AGND32TXO+33TXO-34AVDD35DVDD36LINK_I37RXD038RXD139RXD240RXD341DGND42CRS43COL44RX_DV45RX_ER46RX_CLK47TEST548TX_CLK49TXD050
TX
D1
51T
XD
252
TX
D3
53T
X_E
N54
DV
DD
55M
DIO
56M
DC
57D
GN
D58
CLK
20M
O59
SP
EE
D#
60D
UP
#61
LIN
KA
CT
#62
DG
ND
63E
ED
I64
EE
DO
65E
EC
K66
EE
CS
/LE
D67
GP
IO0
68G
PIO
169
GP
IO2
70G
PIO
371
DV
DD
72D
VD
D73
NC
274
NC
175
DGND76
NC77
LINK_O78
WAKEUP79
PW_RST#80
DGND81
SD1582
SD1483
SD1384
SD1285
SD1186
SD1087
SD988
SD889
DVDD90
IO1691
CMD92
SA493
SA594
SA695
SA796
SA897
SA998
DGND99
INT100
C63100NFC63100NF
C6722PFC6722PF
C76
10V10µFC76
10V10µF
C69100NFC69100NF
R70 0RR70 0R
C6622PFC6622PF
Y3
25MHz
Y3
25MHz1 2
C61100NFC61100NF
R2549R91%
R2549R91%
C73100NFC73100NF
L24.7uH
L24.7uH
C74100NFC74100NF
R2949R91%
R2949R91%
C71100NFC71100NF
C68100NFC68100NF
R2649R91%
R2649R91%
R71 0RR71 0R
1
2
3
6
4
5
7
8
75
75
7575
1nF
TD+
TD-
CT
RD+
RD-
CT
TX+
TX-
RX+
RX-
J13 J0026D211
2
3
6
4
5
7
8
75
75
7575
1nF
TD+
TD-
CT
RD+
RD-
CT
TX+
TX-
RX+
RX-
J13 J0026D211
2
7
8
3
6
5
4
15 16
DS2 GREENDS2 GREEN
C72100NFC72100NF
R32100KR32100K
C79100NFC79100NF
C70100NFC70100NF
R23 4,7KR23 4,7K
C75100NFC75100NF
R27
DNP
R27
DNP
![Page 31: AT91SAM9G10-EK Evaluation Board - Microchip Technology](https://reader034.vdocuments.us/reader034/viewer/2022052602/628d0afc2ccf6178d15dc6d9/html5/thumbnails/31.jpg)
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A������������
LCDD12
B5
B2
G5
LCDD5
R5
LCDD15
LCDD6
LCDD3LCDD4
LCDHSYNC
B1
G1G0
R0R1R2
LCDD2
LCDD20
LCDD23
LCDD21
B0
R3R4
G2
LCDDDOTCK
LCDDEN
LCDD13
LCDD22
LCDD18
LCDD14
B3B4
LCDD11LCDD10
G3G4
LCDD19
LCDD7
SPI0_NPCS2SPI0_MISOSPI0_MOSISPI0_SPCK
DTMG
DCLK
HSYNC
PCIVctrl
IRQ0BUSY
POWER CONTROL IN
LCDCC
TWO USER'S ANALOG INPUTS
AGND
Full-Scale Input Span 0 to VREF
TOUCH SCREEN CONTROLLER
NOT POPULATEDPB25
PB8PB9
PB20
PB11PB10
VCTRL
PB15
PB19
PB3
PB18
PB16
PB12
PB23
PB28
PB2
PB27
PB24
PB26
PB7
PB1
PB17
X_RIGHTY_LOWX_LEFTY_UP
PC2
PA12
VCTRLPB4
X_LEFTY_UPX_RIGHTY_LOW
PA26
PA2
PA25
PA28
PA24
PA0
PA14
PA1
PA11
PA27
PA13
3V3
3V3
3V3
3V3
3V3
PA2 {2,3,4,7}
PA12 {3,7}
PA0 {2,3,4,7}
PB[0..31] {2,3,7}
PA1 {2,3,4,7}
PA28 {3,7}
PA11 {3,7}PC2 {3,5,7}
M5V {2}
PA27 {3,7}
PA26 {3,7}
PA25 {3,7}
PA24 {3,7}
PA14 {3,7}
PA13 {3,7}
REV DATEMODIF. DES. DATE VER.
SCALE1/1 REV. SHEET
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INIT EDITA
AT91SAM9G10-EK67
15MAY09
A
XX/XX/XXPP XXX
LCD_USER'S INTERFACE
REV DATEMODIF. DES. DATE VER.
SCALE1/1 REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
INIT EDITA
AT91SAM9G10-EK67
15MAY09
A
XX/XX/XXPP XXX
LCD_USER'S INTERFACE
REV DATEMODIF. DES. DATE VER.
SCALE1/1 REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
INIT EDITA
AT91SAM9G10-EK67
15MAY09
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XX/XX/XXPP XXX
LCD_USER'S INTERFACE
S24S24
C123100NFC123100NF
BP5BP5
C11710NFC11710NF
MN11
MC34064D
MN11
MC34064D
IN2
N.C3 N.C2
7
N.C36
GND4
RST1
N.C45
N.C18
BP4BP4
TP66TP66
R7510KR7510K
BP3BP3
R79 0RR79 0R
MN16
ADS7843E
MN16
ADS7843E
XP2
IN37
YP3
XM4
YM5
GND6
IN48
VREF9
VCC10VCC1
DCLK16
CS15
DIN14
BUSY13
DOUT12
PENIRQ11
C874.7NFC874.7NF
R73 0RR73 0R
C122100NFC122100NF
R76 0RR76 0R
C121100NFC121100NF
L5
4.7uH
L5
4.7uH
DS7
GREEN
DS7
GREEN
BP6BP6
R77 0RR77 0R
R80 100KR80 100K
R50 220RR50 220R
S20S20
R83 10KR83 10K
S19S19
S26S26C11610NFC11610NF
Q6IRLML2402Q6IRLML2402
1
3
2
C124100NFC124100NF
TP65TP65
R82 0RR82 0R
TP63TP63 TP64TP64
R78 0RR78 0R
C11810NFC11810NF
C12510V10µF
C12510V10µF
C11910NFC11910NF
DS8
GREEN
DS8
GREEN
S25S25
R51 220RR51 220R
R84100KR84100K
R81 100KR81 100K
R74 47RR74 47R
C120
10V10µFC120
10V10µF
Z17 TX09D70VM1CCAZ17 TX09D70VM1CCA
C84100NFC84100NF
J23
54132-4097
J23
54132-4097
123456789
10111213141516171819202122232425262728293031323334353637383940
![Page 32: AT91SAM9G10-EK Evaluation Board - Microchip Technology](https://reader034.vdocuments.us/reader034/viewer/2022052602/628d0afc2ccf6178d15dc6d9/html5/thumbnails/32.jpg)
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
USB DEVICE INTERFACE
SERIAL DEBUG PORT
USB HOST INTERFACE
USB_CNX
USB_DP_PUP
DBGU_TXD
DBGU_RXD
RXD
TXDEXPANSION CONNECTORS
USER'S GRID AERA
1.27 PITCH
2.54 PITCH
NOT POPULATED NOT POPULATED
NOT POPULATED
DDP
PB30
DDM
PA9
HDPBHDMB
PB29
PA10
NRST
PC0PC2PC4PC6PC8PC10PC12PC14D16D18D20D22D24D26D28D30
PC1
PC13
D31
D21
PC9PC7
D27
PC3
D23
D17
PC11
D19
D29
PC5
D25
PC15
A1A4A7A11A13A15A18A0A10A17
A22
A5A8A20
A2A3A6A9
A14A16A19
PA0PA1PA2PA3PA4PA5PA6PA7PA8PA9PA10PA11PA12PA13PA14PA15PA16PA17PA18PA19PA20PA21PA22PA23PA24PA25PA26PA27PA28PA29
PA31PA30
PC0PC1PC2PC3PC4PC5PC6PC7PC8PC9PC10PC11PC12PC13PC14PC15
A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14
D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15D16D17D18D19D20D21D22D23D24D25D26D27D28D29D30D31
A15A16A17A18A19A20A21A22
PA1
PA5PA3
PA7
PA11PA13
PA9
PA19
PA15PA17
PA21
PA27PA25PA23
PA29PA31
PB9
PB0
PB22
PB30
PB15
PB11PB10
PB6
PB17
PB21
PB13
PB7
PB1
PB27
PB12
PB28
PB3
PB18
PB29
PB26
PB23
PB31
PB5
PB20
PB24
PB16
PB8
PB14
PB25
PB19
PB4
PB2PB9PB7
PB15
PB5
PB11
PB25
PB13
PB23
PB17
PB31
PB19
PB27
PB21
PB29
PB1PB3
PA0PA2PA4PA6PA8PA10PA12PA14PA16PA18PA20PA22PA24PA26PA28PA30
PB0PB2PB4PB6PB8PB10PB12PB14PB16PB18PB20PB22PB24PB26PB28PB30
A12
A21
D1D0D5D7D4D15D13
D2D3D10D8D12D11D6
D14D9
HDPAHDMA
3V3
3V33V3
3V33V3
3V33V3
3V3
3V3
5V
5V5V
5V5V
5V
5V
3V3
PA[0..31]{2,3,4,6}
SDCS_NCS1{3,4}
PA9{3}
CFOE_NOE_NRD{3,5}CFIOR_NBS1_NWR1{3,4}
RAS{3,4}CFIOW_NBS3_NWR3{3,4}
SDWE{3,4}CAS{3,4}
SDCKE {3,4}NCS2 {3,5}CFWE_NWE_NWR0 {3,5}SDA10 {3,4}NCS0 {3}
SDCK {3,4}
SMCS_NCS3 {3}
PA10{3}
HDMA{3}HDPA{3}
HDMB{3}HDPB{3}
PB29{3}
PB30{3}
NRST{2,3,4,5}
DDM{3}
DDP{3}
NRST{2,3,4,5}
VDDBU{3}WKUP {3}SHDN {2,3}
PB[0..31]{2,3,6}
PC[0..15]{3,4,5,6}
D[0..31]{3,4,5}
A[0..22]{3,4,5}
REV DATEMODIF. DES. DATE VER.
SCALE1/1 REV. SHEET
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INIT EDITA
AT91SAM9G10-EK77
15MAY09
A
XX/XX/XXPP XXX
SERIAL & I/O EXPANSION
REV DATEMODIF. DES. DATE VER.
SCALE1/1 REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
INIT EDITA
AT91SAM9G10-EK77
15MAY09
A
XX/XX/XXPP XXX
SERIAL & I/O EXPANSION
REV DATEMODIF. DES. DATE VER.
SCALE1/1 REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
INIT EDITA
AT91SAM9G10-EK77
15MAY09
A
XX/XX/XXPP XXX
SERIAL & I/O EXPANSION
R55 39RR55 39R
C1+
V+
VCC
C1-C2+
C2- V-
T
T
R
R
GND
MN13
ADM3202ARN
C1+
V+
VCC
C1-C2+
C2- V-
T
T
R
R
GND
MN13
ADM3202ARN
1 16
34
5
15
11
10
12
9 8
13
7
14
2
6
C10515PFC10515PF
C94100NFC94100NF
C92100NFC92100NF
C10047pFC10047pF
J15MALE RIGHT ANGLED
J15MALE RIGHT ANGLED
5
4
3
2
1
9
8
7
6
10 11
R59 39RR59 39R
J17J17
2468101214161820222426283032343638404244464850525456586062646668707274767880
13579
1113151719212325272931333537394143454749515355575961636567697173757779
C104100NFC104100NF
C98100NFC98100NF
R5615KR5615K
R66 39RR66 39R
J16J16
2468101214161820222426283032343638404244464850525456586062646668707274767880828486889092949698100102104106108110112114116118120
13579
111315171921232527293133353739414345474951535557596163656769717375777981838587899193959799
101103105107109111113115117119
C99100NFC99100NF
R54 39RR54 39R
C9647pFC9647pF
C10333PFC10333PF
R52 0RR52 0R
R62 15KR62 15K
C93100NFC93100NF
VCC
GND
MN14
DNPSN74LVC1G00DBV
VCC
GND
MN14
DNPSN74LVC1G00DBV
5
1
2
3
4
C9747pFC9747pF
F1500 mAF1500 mA
R6322KR6322K
C10615PFC10615PF
R65 39RR65 39R
C91100NFC91100NF
C95100NFC95100NF
R5715KR5715K
S21S21
Q5IRLML6302
DNP
Q5IRLML6302
DNP
1
32
R64
DNP
R64
DNP
R6115KR6115K
R53 0RR53 0R
S22S22
C102DNPC102DNP
J19J191
4
2
3
5 6
R58 39RR58 39R
F2500 mAF2500 mA
R6015KR6015K
C10147pFC10147pF
�
�
J18
CCUSBA-32002-30X
�
�
J18
CCUSBA-32002-30X
A1
A4
A2A3
1 2
B1B2B3B4
3 4
![Page 33: AT91SAM9G10-EK Evaluation Board - Microchip Technology](https://reader034.vdocuments.us/reader034/viewer/2022052602/628d0afc2ccf6178d15dc6d9/html5/thumbnails/33.jpg)
5-2 AT91SAM9G10-EK Evaluation Board User Guide
6479A–ATARM–26-May-09
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Section 6
Errata
6.1 JTAGSEL S5 Footprint SelectorFor JTAG selection, the S5 footprint must never be soldered, otherwise the chip can be damaged.
By default, the JTAGSEL input pin integrates a pull-down resistor (ICE mode).
To select JTAG mode, the designer should connect the JTAGSEL input pin to VDDBU power.
6.2 External Capacitor Values on XIN and XOUTThe external capacitor values on XIN and XOUT are not correct.
The 10 pF capacitors must be replaced by 22 pF capacitors.
Please refer to the electrical parameters section of the datasheet.
AT91SAM9G10-EK Evaluation Board User Guide 6-1
6479A–ATARM–26-May-09
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6-2 AT91SAM9G10-EK Evaluation Board User Guide
6479A–ATARM–26-May-09
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Section 7
Revision History
7.1 Revision History
Table 7-1.
Document CommentsChange Request Ref.
6479A First issue.
AT91SAM9G10-EK Evaluation Board User Guide 7-1
6479A–ATARM–26-May-09
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7-2 AT91SAM9G10-EK Evaluation Board User Guide
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