at91sam9m10-g45-ek - microchip...
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AT91SAM9M10-G45-EK ....................................................................................................................
User Guide
6495B–ATARM–21-Apr-10
Section 1Introduction.................................................................................................................1-1
1.1 Scope................................................................................................................................. 1-1
1.2 Applicable Documents ....................................................................................................... 1-2
Section 2Kit Contents ................................................................................................................2-1
2.1 Deliverables ....................................................................................................................... 2-1
2.2 Evaluation Board Specifications......................................................................................... 2-2
2.3 Electrostatic Warning ......................................................................................................... 2-2
Section 3Power up.....................................................................................................................3-1
3.1 Power Up the Board........................................................................................................... 3-1
3.2 Battery................................................................................................................................ 3-1
3.3 DevStart ............................................................................................................................. 3-1
3.4 Recovery Procedure .......................................................................................................... 3-2
3.5 Sample Code and Technical Support ................................................................................ 3-2
Section 4Board Description .......................................................................................................4-1
4.1 Equipment on the Board .................................................................................................... 4-1
4.1.1 Interfaces ............................................................................................................. 4-1
4.1.2 Board Interface Connection ................................................................................. 4-2
4.1.3 Push Button Switches.......................................................................................... 4-2
4.1.4 Display LCD and LEDs ........................................................................................ 4-3
4.2 Hardware Layout and Configuration .................................................................................. 4-3
4.2.1 Processor............................................................................................................. 4-3
4.2.2 Clock Circuitry...................................................................................................... 4-4
4.2.3 Reset Circuitry ..................................................................................................... 4-4
4.2.4 Memory................................................................................................................ 4-4
4.2.5 Power Supplies.................................................................................................... 4-7
4.2.6 Debug Interface ................................................................................................. 4-10
4.2.7 Audio Stereo Interface ....................................................................................... 4-15
4.2.8 TV-Out Extension .............................................................................................. 4-17
4.2.9 Software Controlled LEDs ................................................................................. 4-18
4.2.10 Serial Peripheral Interface Controller (SPI) ....................................................... 4-19
4.2.11 Two Wire Interface (TWI)................................................................................... 4-19
4.2.12 SD/MMC Interface ............................................................................................. 4-19
4.2.13 TFT LCD with Touch Panel ............................................................................... 4-20
4.2.14 Push Buttons ..................................................................................................... 4-22
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4.2.15 Expansion Slot ................................................................................................... 4-22
Section 5Configuration ..............................................................................................................5-1
5.1 JTAG/ICE Configuration..................................................................................................... 5-1
5.2 ETHERNET Configuration ................................................................................................. 5-1
5.3 Jumpers Configuration ....................................................................................................... 5-2
5.4 Miscellaneous Configuration Items .................................................................................... 5-3
5.5 PIO Configuration............................................................................................................... 5-3
5.5.1 Peripheral Signals Multiplexing on I/O Lines ....................................................... 5-3
5.5.2 Multiplexing on PIO Controller A (PIOA).............................................................. 5-3
5.5.3 Multiplexing on PIO Controller B (PIOB).............................................................. 5-5
5.5.4 Multiplexing on PIO Controller C (PIOC) ............................................................. 5-6
5.5.5 Multiplexing on PIO Controller D (PIOD) ............................................................. 5-7
5.5.6 Multiplexing on PIO Controller E (PIOE).............................................................. 5-8
Section 6Connectors .................................................................................................................6-1
6.1 Power Supply ..................................................................................................................... 6-1
6.2 RS232 Connector with RTS/CTS Handshake Support ...................................................... 6-1
6.3 DBGU................................................................................................................................. 6-2
6.4 Ethernet.............................................................................................................................. 6-3
6.5 USB Host ........................................................................................................................... 6-3
6.6 USB Host/Device ............................................................................................................... 6-4
6.7 JTAG Debugging Connector .............................................................................................. 6-4
6.8 SD/MMC- MCI0.................................................................................................................. 6-6
6.9 SD/MMC- MCI1.................................................................................................................. 6-7
6.10 AC97 .................................................................................................................................. 6-8
6.11 Image Sensor - ISI ............................................................................................................. 6-9
6.12 Video................................................................................................................................ 6-10
6.13 Display Devices................................................................................................................ 6-10
6.13.1 TFT LCD ............................................................................................................ 6-10
6.14 LCD Extension ................................................................................................................. 6-11
Section 7Schematics .................................................................................................................7-1
7.1 Schematics......................................................................................................................... 7-1
Section 8Revision History..........................................................................................................8-1
8.1 Revision History ................................................................................................................. 8-1
1-ii AT91SAM9M10-G45-EK User Guide
6495B–ATARM–21-Apr-10
Section 1
Introduction
1.1 Scope
This User Guide introduces the AT91SAM9M10(G45) Evaluation Kit and describes its development and debugging capabilities.
Figure 1-1. Board Photo
The Atmel® SAM9M10-G45-EK is a fully-featured evaluation platform for the Atmel AT91SAM9M10 or AT91SAM9G45 microcontroller. The kit is equipped with an AT91SAM9M10 chip, which is a superset of the AT91SAM9G45, and therefore allows evaluating that reference as well. The evaluation kit allows users to extensively evaluate, prototype and create application-specific designs.
The SAM9M10-G45-EK includes many hardware peripherals such as:
Two high speed USB hosts and one high speed device port
An Ethernet 10/100 interface
Two high speed multimedia card interfaces
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Introduction
An LCD TFT display (480*272 RGB) with resistive touch panel
A composite video output
A camera interface
Several communication peripherals such as:
– Universal Synchronous/Asynchronous Receiver Transmitter (USART)
– Two-Wire Interface (TWI)
The external memory block is made of 3 memory types:
DDR2-SDRAM
NAND Flash
NOR Flash (not populated by default)
1.2 Applicable Documents
Table 1-1. Applicable Documents
Reference Title Comments
Atmel Literature n° 6438 SAM9G45 Preliminary
This document describes the SAM9G45, which is part of the Atmel's Smart ARM® Microcontrollers.
It is available from http://www.atmel.com/dyn/resources/prod_documents/doc6438.pdf
Atmel Literature n° 6355 SAM9M10 PreliminaryThis document describes the SAM9M10, which is part of the Atmel's Smart ARM® Microcontrollers http://www.atmel.com/dyn/resources/prod_documents/doc6355.pdf
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Section 2
Kit Contents
2.1 Deliverables
The Atmel SAM9M10-G45-EK toolkit includes:
Board
– The SAM9M10-G45-EK board
Power supply
– Universal input AC/DC power supply with US, Europe and UK plug adapters
– One 3V Lithium Battery type CR1225
Cables
– One micro A/B-type USB cable
– One serial RS232 cable
– One RJ45 crossed cable
A Welcome Letter
Figure 2-1. Unpacked SAM9M10-G45-EK
Unpack and inspect this kit carefully. Contact your local Atmel distributor, should you have issues con-cerning the contents of the kit.
AT91SAM9M10-G45-EK User Guide 2-1
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Kit Contents
2.2 Evaluation Board Specifications
2.3 Electrostatic Warning
The SAM9M10-G45-EK evaluation board is shipped in a protective anti-static package. The board must not be subjected to high electrostatic potentials. We strongly recommend using a grounding strap or sim-ilar ESD protective device when handling the board in hostile ESD environments (offices with synthetic carpet, for example...). Avoid touching the component pins or any other metallic element on the board.
Table 2-1. SAM9M10-G45-EK Specifications
Characteristics Specifications
Clock speed 400 MHz PCK, 133 MHz MCK
Ports Ethernet, USB, RS232, DBGU, JTAG
Board supply voltage 5 VDC from connector
Temperature
- operating
- storage
-10° to +50° C
-40° to +85° C
Relative humidity 0 to 90% (non condensing)
Dimensions 180 mm x 140 mm
RoHS status Compliant
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Section 3
Power up
3.1 Power Up the Board
Unpack the board taking care to avoid electrostatic discharge. Unpack the power supply, select the right power plug adapter corresponding to that of your country, and insert it in the power supply.
Connect the power supply DC connector to the board and plug the power supply to an AC power plug.
The board LCD should light up and display a welcome page. Then, click or touch icons displayed on the screen and enjoy the demo.
3.2 Battery
The SAM9M10-G45-EK ships with a 3V coin battery.
This battery is not required for the board to start up.
The coin battery is provided for user convenience in case the user would like to exercise the date and time backup function of the SAM9M10 series devices when the board is switched off.
3.3 DevStart
The on-board NAND Flash contains a “SAM9M10-G45-EK DevStart”.
It is stored in the “SAM9M10-G45-EK DevStart” folder on the USB Flash disk available when the SAM9M10-G45-EK is connected to a host computer.
Click the file “welcome.html” in this folder to launch SAM9M10-G45-EK DevStart.
SAM9M10-G45-EK DevStart guides you through installation processes of IAR™ EWARM, Keil MDK and GNU toolkits. Then, it gives you step-by-step instructions on how to rebuild a single example project and
how to program it into the SAM9M10-G45-EK. Optionally, if you have a SAM-ICE™, instructions are also given about how to debug the code.
We recommend that you backup the “SAM9M10-G45-EK DevStart” folder on your computer before launching it.
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Power up
3.4 Recovery Procedure
The DevStart ends by giving step-by-step instructions on how to recover the SAM9M10-G45-EK to the state as it was when shipped by Atmel.
Follow the instructions if you deleted the contents of the NAND Flash and want to recover from this situation.
3.5 Sample Code and Technical Support
After boot up, you can run some sample code or your own application on the development kit. You can down load sample code and ge t Techn ica l suppor t f rom http://www.atmel.com/dyn/products/tech_support.asp?Faq=y&family_id=689%20.
3-2 AT91SAM9M10-G45-EK User Guide
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Section 4
Board Description
4.1 Equipment on the Board
Figure 4-1. Board Architecture
4.1.1 Interfaces
The board is equipped with an AT91SAM9M10-CU embedded microprocessor (324-ball TFBGA pack-age) together with the following interfaces or peripherals:
DDR2/LPDDR memory interface is connected to 128 MB DDR2-SDRAM memory
External Bus Interface (EBI) is connected to three kinds of memory devices (DDR2-SDRAM, NAND Flash and NOR Flash (not populated))
PARALLEL FLASH
AT91SAM9M10AT91SAM9M10
DEBUGDEBUG
JTAG/ICEDBGU
System ControllerSystem Controller
External MemoryExternal Memory
EBI0EBI0
EBI1 / 1.8vEBI1 / 1.8v
DDR2 SDRAM
DDR2 SDRAM
NAND FLASH
Multimédia Cards InterfaceMultimedia Cards Interface
MCI0MCI0
SPI0SPI0
MCI1MCI1
DataFlash
USARTUSART USB
USB
Host AHost A
Host BHost B
DeviceDevice
ETHERNET 10/100 MAC
ETHERNET 10/100 MAC
LCD InterfaceLCD Interface AC97
AC97
PIOPIO
TWITWI
oooooooooooooooo
Serial Eeprom
oooooooooooooooo
4 bits interfaceSD/MMC
8 bits interfaceSD/MMC
Micro
Line In
Line Out
oooooooooooooooo
LCD TFT 480*272
LCD TFT 480*272
PWMPWM
PHY RMIIRS232
Codec
NPCS0
NCS0
NCS3
NCS1
Led
CD
User I/OAudioVidéoLCD TFTMultimedia cardsMain Memory
Touch Screen
Touch Screen
Composite video
VCC 5V PIOJTAG/ICEDBGUUSB
Hub / Device
USB Hub
High / Full
RS232Ethernet RMII/MIIISI
Image SensorInterface
Image SensorInterface
Power / Shdn
Joystick & P.B
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Board Description
One TWI serial memory
One USB Host/Device multiplexed port interface
One USB Host port interface
One RS232 serial communication port
One DBGU serial communication port
One JTAG/ICE debug interface
One Ethernet 100-base TX with three status LEDs
One AC97 Audio CODEC with headphone line out, line in and mono/stereo microphone inputs
One TV interface (composite video output)
One 4.3" TFT LCD Module with touch screen and back light
One ISI connector (camera interface)
One power red LED and two general-purpose green LEDs
Two user input push buttons
One joystick with 4-direction control and selector
One wakeup input push button
One reset input push button
One SD/SDIO/MMC plus card slot (4/8 bit interface)
One SD/SDIO/MMC card slot (4-bit interface)
One Lithium Coin Cell Battery Retainer for 12 mm cell size (memory backup usage)
4.1.2 Board Interface Connection
Ethernet using RJ45 connector (J15)
USB Host, support USB host using a type A connector (J12)
USB Host/Device, support USB host/device using a type micro AB connector (J14)
UART1 (RX, TX, RTS, CTS) connected to a 9-way male D-type RS232 connector (J11)
DBGU (RX and TX only) connected to a 9-way male D-type RS232 connector (J10)
JTAG, 20 pin IDC connector (J13)
SD/MMCplus connector (J5)
SD/MMC connector (J6)
Headphone (J7), line-in (J8) and microphone headset (J9)
Speaker output (JP15)
Image sensor connector (J17)
TFT LCD display, with TouchScreen and backligth (J24)
Test points; various test points are located throughout the board
Main power supply (J2)
4.1.3 Push Button Switches
Reset, board reset (BP1)
Wake up, push button to bring processor out of low power mode (BP2)
Right and left click, user push button switches (BP4 and BP5)
Joystick (BP3)
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Board Description
4.1.4 Display LCD and LEDs
Display, 480xRGBx272 pixels LCD module display connected to the PIO port E (LCD1)
One surface-mounted power red LED, user interface (D3)
Two surface-mounted green LEDs, user interface (D1 and D2)
Three surface-mounted LEDs indicate Ethernet status (D4, D5, D6)
Figure 4-2. Board Layout Commented
The major components of the SAM9M10-G45-EK board are shown in Figure 4-1.
4.2 Hardware Layout and Configuration
4.2.1 Processor
The board features the Atmel SAM9M10-CU 324-ball TFBGA package. This chip runs at a nominal fre-quency of 400 MHz for the core and 133 MHz for the system bus.
For more information, refer to the latest SAM9M10 datasheet available from http://www.atmel.com/
DBGU RS232 JTAG ETHERNET
WAKE-UPBUTTON
RESETBUTTON
BACKUPBATTERY
«RIGHT»USER BUTTON
«LEFT»USER BUTTON
SD/MMC 1SLOTSD/MMC 0
SLOT
USERJOYSTICK
VIDEOOUTPUT
HEADPHONESHEADER
MICROPHONEINPUT
LINEINPUT
LCD DISPLAY AREALCD EXTENSION
CONNECORSISI/CAMERACONNECTOR
POWERHOSTUSB
HOSTDEVICE
USB
Y6
TP2
J20
J7
R85
L11JP15
J9
J8
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J6
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5
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MN
20
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6 MN
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VIDEO
HEAD PHONE
MIC IN
LINE IN
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SELECT
E2PR
OM
NANDCS NCS0
RS232
VDDIOM1
USB
LCD EXTENSION
VDDIOM0
HOST
USB
HOST/DEV
1
ISIJ1
VDD
UTM
IIVD
DU
TMIC
VDD
CO
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VDD
PLLU
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JP2/
P2/J
D3
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IOPn
ETH
ERN
ET
LEFT
BATVDDBU
3V3
NPCS0
SD/MMC+
CR
1225
3V
WAKEUP
5VCC POWER
RIGHT
NRST
AT91SAM9M10-G45-EK User Guide 4-3
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Board Description
4.2.2 Clock Circuitry
The SAM9M10-G45-EK includes six clock sources:
Two are alternatives for the SAM9M10 main clock,
One crystal and one crystal oscillator are used for the Ethernet MII/RMII chip,
One crystal is used for the AC97 codec chip,
One crystal or one crystal oscillator is used for the TV encoder.
4.2.3 Reset Circuitry
The reset sources are:
Power on reset
Push button reset
JTAG reset from an in-circuit emulator interface.
4.2.4 Memory
4.2.4.1 External Memories
The SAM9M10 features a DDR2/LPDDR memory interface and an External Bus Interface (EBI) to permit interfacing to a wide range of external memories and to almost any kind of parallel peripheral.
The SAM9M10-G45-EK board is equipped with DDR2/LPDDR devices featuring 128 MB of DDR2- SDRAM memory (16Meg*8*4).
The External Bus Interface (EBI) is connected to three kinds of memory devices:
One Parallel Flash (not populated by default)
Two DDR2-SDRAM
One NAND Flash (2Gb, 8 bit bus)
The chip selects NCS0, NCS1 and NCS3 are used for NOR Flash, DDR2-SDRAM and NAND Flash memories, respectively. Furthermore, a dedicated jumper can disconnect each of the two NCS0 and NCS3 signals, making them available for other functions.
Table 4-1. Main Components Associated with the Clock Systems
Quantity Description Component assignment
1 Crystal for Internal Clock, 12 MHz Y1
1 Crystal for RTC Clock, 32.768 kHz Y2
1 Oscillator for Ethernet Clock RMII, 50 MHz Y4
1 Crystal for Ethernet Clock MII, 25 MHz (not populated) Y5
1 Crystal for AC97 Codec Clock, 24.576 MHz Y3
1Crystal for TV Encoder Clock, 13 MHz, orOscillator for TV Encoder, 13 MHz (not populated)
Y7Y6
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Board Description
Figure 4-3. EBI0 - DDR2
RA
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MN
7
DDR2 SDRAM
MN
7
A0
H8
A1
H3
A2
H7
A3
J2
A4
J8
A5
J3
A6
J7
A7
K2
A8
K8
A9
K3
A10
H2
BA
0G
2
OD
TF
9
DQ
0C
8
DQ
1C
2
DQ
2D
7
DQ
3D
3
DQ
4D
1
DQ
5D
9
DQ
6B
1
DQ
7B
9
DQ
SB
7
DQ
SA
8
RD
QS
/DM
B3
RD
QS
/NU
A2
VD
DH
9
VD
DL1
VD
DL
E1
VR
EF
E2
VD
DQ
C9
VS
SA
3
VS
SE
3
VD
DQ
A9
VD
DE
9
RF
U1
G1
RF
U2
L3
CK
EF
2
CK
E8
CK
F8
CA
SG
7
RA
SF
7
WE
F3
CS
G8
VD
DQ
C1
VD
DQ
C3
VD
DQ
C7
VS
SQ
B2
VS
SQ
B8
VS
SQ
D2
VS
SQ
D8
VD
DA
1
VS
SJ1
A11
K7
BA
1G
3
A12
L2
A13
L8
VS
SK
9
VS
SD
LE
7
VS
SQ
A7
RF
U3
L7
R5
11
.5k
R5
11
.5k
C7
31
00
nC
73
10
0n
C9
04
.7u
C9
04
.7u
C7
41
00
nC
74
10
0n
C8
81
00
nC
88
10
0n
C8
91
00
nC
89
10
0n
R5
01
RR
50
1R
C8
61
00
nC
86
10
0n
C7
51
00
nC
75
10
0n
AT91SAM9M10-G45-EK User Guide 4-5
6495B–ATARM–21-Apr-10
Board Description
Figure 4-4. EBI1 - DDR2 + Flash
Opt
iona
l 16b
its D
AT
A B
US
With
AT
29F
2G16
AB
D M
icro
n
(SD
A10
)(S
DA
10)
(NC
S3)
(RD
Y/B
SY
)
(NA
ND
ALE
)(N
AN
DC
LE)
(NC
S1)
IMPORTANT note about system booting:
The bootROM allows booting from the block 0 of a NandFlash connected
on CS3. However, the bootROM does not feature ECC (Error Checking and
Correction) on NandFlash.
Most of the NandFlash vendors do not guarantee anymore that block 0
is error free. Therefore we advise the bootstrap program to be located
into another device supported by the bootrom (DataFlash, Serial Flash,
SDCARD or EEPROM) and implement NandFlash access with ECC.
WP
RE
WE
CE
RB
EB
I1_N
AN
D_F
SH
_D6
EB
I1_N
AN
D_F
SH
_D0
EB
I1_N
AN
D_F
SH
_D3
EB
I1_N
AN
D_F
SH
_D4
EB
I1_N
AN
D_F
SH
_D2
EB
I1_N
AN
D_F
SH
_D1
EB
I1_N
AN
D_F
SH
_D5
EB
I1_N
AN
D_F
SH
_D7
EB
I1_N
AN
D_F
SH
_D14
EB
I1_N
AN
D_F
SH
_D8
EB
I1_N
AN
D_F
SH
_D11
EB
I1_N
AN
D_F
SH
_D12
EB
I1_N
AN
D_F
SH
_D10
EB
I1_N
AN
D_F
SH
_D9
EB
I1_N
AN
D_F
SH
_D13
EB
I1_N
AN
D_F
SH
_D15
EB
I1_D
DR
_D15
EB
I1_D
DR
_D11
EB
I1_D
DR
_D10
EB
I1_D
DR
_D12
EB
I1_D
DR
_D8
EB
I1_D
DR
_D9
EB
I1_D
DR
_D13
EB
I1_D
DR
_D14
EB
I 1_D
DR
_ D7
EB
I 1_D
DR
_D3
EB
I 1_D
DR
_D2
EB
I 1_D
DR
_ D4
EB
I 1_D
DR
_D0
EB
I 1_D
DR
_D1
EB
I 1_D
DR
_ D5
EB
I 1_D
DR
_ D6
EB
I1_F
LAS
H_D
4
EB
I1_F
LAS
H_D
2
EB
I1_F
LAS
H_D
10
EB
I1_F
LAS
H_D
5
EB
I1_F
LAS
H_D
12
EB
I1_F
LAS
H_D
9
EB
I1_F
LAS
H_D
14E
BI1
_FLA
SH
_D15
EB
I1_F
LAS
H_D
3
EB
I1_F
LAS
H_D
0
EB
I1_F
LAS
H_D
6E
BI1
_FLA
SH
_D7
EB
I1_F
LAS
H_D
8
EB
I1_F
LAS
H_D
1
EB
I1_F
LAS
H_D
13
EB
I1_F
LAS
H_D
11
EB
I1_D
DR
_A2
EB
I1_D
DR
_A3
EB
I1_ D
DR
_A4
EB
I1_ D
DR
_A5
EB
I1_ D
DR
_A6
EB
I1_ D
DR
_A7
EB
I1_ D
DR
_A8
EB
I1_ D
DR
_A9
EB
I1_ D
DR
_A1 0
EB
I1_ D
DR
_A1 1
EB
I1_ D
DR
_A1 2
EB
I1_ D
DR
_A1 3
EB
I1_D
DR
_A1 5
EB
I1_ D
DR
_A1 4
EB
I1_D
DR
_A2
EB
I1_D
DR
_ A3
EB
I1_D
DR
_A4
EB
I1_D
DR
_ A5
EB
I1_D
DR
_A6
EB
I1_D
DR
_ A7
EB
I1_D
DR
_ A8
EB
I1_D
DR
_ A9
EB
I1_D
DR
_ A10
EB
I1_D
DR
_ A11
EB
I1_D
DR
_ A12
EB
I1_D
DR
_A13
EB
I1_D
DR
_A15
EB
I1_D
DR
_A14
NC
LK_E
BI1
CS
_EB
I1
BA
0_E
BI1
BA
1_E
BI1
RA
S_E
BI1
CA
S_E
BI1
WE
_ EB
I1
CK
E_E
BI1
CLK
_EB
I1N
CL K
_EB
I1
CS
_EB
I1
BA
0_E
BI1
BA
1_E
BI1
RA
S_E
BI1
CA
S_E
BI1
WE
_EB
I1
CK
E_E
BI1
VR
EF
1
EB
I1_F
LAS
H_A
1E
BI1
_FLA
SH
_A2
EB
I1_F
LAS
H_A
3E
BI1
_FLA
SH
_A4
EB
I1_F
LAS
H_A
5E
BI1
_FLA
SH
_A6
EB
I1_F
LAS
H_A
7E
BI1
_FLA
SH
_A8
EB
I1_F
LAS
H_A
9E
BI1
_FLA
SH
_A10
EB
I1_F
LAS
H_A
11E
BI1
_FLA
SH
_A12
EB
I1_F
LAS
H_A
15E
BI1
_FLA
SH
_A14
EB
I1_F
LAS
H_A
13
EB
I1_F
LAS
H_A
16
EB
I1_F
LAS
H_A
18E
BI1
_FLA
SH
_A17
VR
EF
1
VR
EF
1
EB
I1_F
LAS
H_A
19E
BI1
_FLA
SH
_A20
EB
I1_F
LAS
H_A
21
CLK
_EB
I1
1V8
1V8
1V8
1V8
1V8
1V8
1V8
1V8
1V8
EB
I1_ F
LAS
H_D
[0..1
5]
BA
0_E
BI1
PC
8
EB
I1_ D
DR
_D[ 0
.. 15]
EB
I1_ F
LAS
H_ A
[1..2
1]
EB
I1_ D
DR
_A[2
..15]
BA
1_E
BI1
CK
E_ E
BI1
CL K
_EB
I1N
CLK
_ EB
I1
CS
_ EB
I1
CA
S_ E
BI1
RA
S_E
BI1
WE
_EB
I1
DQ
S0_
EB
I1
DQ
M0 _
EB
I1
DQ
S1_
EB
I1
DQ
M1_
EB
I1
EB
I1_N
CS
0
EB
I1_N
RD
/CF
OE
DD
R_V
RE
F
EB
I1_N
WE
/NW
R0/
CF
WE
PC
5P
C4
EB
I1_N
AN
DO
EE
BI1
_NA
ND
WE
PC
14
EB
I 1_N
AN
D_F
SH
_D[0
..15]
JP9
JP9
R43
0RR
430R
C81
100n
FC
8110
0nF
C80
1 00n
FC
801 0
0nF
MT4 7
H64M
8 CF -
3
DDR2
SD R
AM
MN
8
MT4 7
H64M
8 CF -
3
DDR2
SD R
AM
MN
8
A0
H8
A1
H3
A2
H7
A3
J2
A4
J8
A5
J3
A6
J7
A7
K2
A8
K8
A9
K3
A10
H2
BA
0G
2
OD
TF
9
DQ
0C
8
DQ
1C
2
DQ
2D
7
DQ
3D
3
DQ
4D
1
DQ
5D
9
DQ
6B
1
DQ
7B
9
DQ
SB
7
DQ
SA
8
RD
QS
/DM
B3
RD
QS
/NU
A2
VD
DH
9
VD
DL1
VD
DL
E1
VR
EF
E2
VD
DQ
C9
VS
SA
3
VS
SE
3
VD
DQ
A9
VD
DE
9
RF
U1
G1
RF
U2
L3
CK
EF
2
CK
E8
CK
F8
CA
SG
7
RA
SF
7
WE
F3
CS
G8
VD
DQ
C1
VD
DQ
C3
VD
DQ
C7
VS
SQ
B2
VS
SQ
B8
VS
SQ
D2
VS
SQ
D8
VD
DA
1
VS
SJ1
A1 1
K7
BA
1G
3
A1 2
L 2
A13
L8
VS
SK
9
VS
SD
LE
7
VS
SQ
A7
RF
U3
L 7
R40
470K
R40
470K
C10
110
0nF
C10
110
0nF
C10
410
0nF
C10
410
0nF
C82
100n
FC
8210
0nF
R46
470K
R46
470K
AT49
SV32
2DT
FLAS
H CBGA
MN
10
DN
P
AT49
SV32
2DT
FLAS
H CBGA
MN
10
DN
P
A0
E1
A1
D1
A2
C1
A3
A1
A4
B1
A5
D2
A6
C2
A7
A2
A8
B5
A9
A5
A10
C5
A11
D5
A12
B6
A13
A6
A14
C6
A15
D6
A16
E6
A17
B2
A18
C3
RD
Y/
BU
SY
A3
A20
D3
A19
D4
WE
A4
RE
SE
TB
4
OE
G1
CE
F1
VP
PB
3
I /00
E2
I /O
1H
2
I /O
2E
3
I /O
3H
3
I /O
4H
4
I/O
5E
4
I/O
6H
5
I/O
7E
5
I/O
8F
2
I/O
9G
2
I/O
10F
3
I/O
11G
3
I/O
12F
4
I/O
13G
5
I/O
14F
5
I/O
15G
6
VC
CG
4
GN
DH
6G
ND
H1
NC
1C
4
NC
F6
R42
0RR
420R
R39
100K
R39
100K
MT29
F2G0
8ABD
NAND
FL A
SH VFBG
A-63
MN
11
MT
29F
2G08
AB
DH
C:D
MT29
F2G0
8ABD
NAND
FL A
SH VFBG
A-63
MN
11
MT
29F
2G08
AB
DH
C:D
WE
C7
N.C
6B
9
VC
CH
8
CE
C6
RE
D4
N.C
1 1E
3
WP
C3
N.C
5B
1
N.C
1A
1
N.C
2A
2
N.C
3A
9
N.C
4A
10
N.C
1 2E
4
N.C
13E
5
N.C
14E
6
N.C
15E
7
R/B
C8
N.C
17F
3
N.C
36M
1
I/O
0H
4
N.C
34L9
N.C
2 5L 2
VS
SF
7
N.C
29J5
VC
CJ6
VS
SK
3
ALE
C4
N.C
8D
6N
.C7
B10
N.C
9D
7
N.C
10D
8
CLE
D5
N.C
16E
8
N.C
35L1
0
I/O
1J4
I/O
3K
5I/
O2
K4
N.C
28H
5
N.C
30H
6
N.C
32H
7
I/O
7J8
I/O
6K
7I/
O5
J7I/
O4
K6
N.C
27J3
N.C
26H
3
VS
SC
5
N.C
2 4L 1
VS
SK
8
L OC
KG
5
VC
CD
3
VC
CG
4
N.C
31G
6
N.C
18F
4
N.C
19F
5
N.C
20F
6
N.C
22G
3N
.C21
F8
N.C
33G
7
N.C
23G
8
N.C
37M
2
N.C
38M
9
N.C
39M
10
C87
100n
FC
8710
0nF
JP10
JP10
C94
100n
FC
9410
0nF
R4 5
1 KR
4 51 K
C93
100n
FC
9310
0nF
C83
100n
FC
8310
0nF
R4 1
470K
R4 1
470K
MT47
H64M
8 CF-
3
DDR2
SDR
AM
MN
9
MT47
H64M
8 CF-
3
DDR2
SDR
AM
MN
9
A0
H8
A1
H3
A2
H7
A3
J2
A4
J8
A5
J3
A6
J7
A7
K2
A8
K8
A9
K3
A10
H2
BA
0G
2
OD
TF
9
DQ
0C
8
DQ
1C
2
DQ
2D
7
DQ
3D
3
DQ
4D
1
DQ
5D
9
DQ
6B
1
DQ
7B
9
DQ
SB
7
DQ
SA
8
RD
QS
/DM
B3
RD
QS
/NU
A2
VD
DH
9
VD
DL1
VD
DL
E1
VR
EF
E2
VD
DQ
C9
VS
SA
3
VS
SE
3
VD
DQ
A9
VD
DE
9
RF
U1
G1
RF
U2
L3
CK
EF
2
CK
E8
CK
F8
CA
SG
7
RA
SF
7
WE
F3
CS
G8
VD
DQ
C1
VD
DQ
C3
VD
DQ
C7
VS
SQ
B2
VS
SQ
B8
VS
SQ
D2
VS
SQ
D8
VD
DA
1
VS
SJ1
A11
K7
BA
1G
3
A12
L2
A13
L8
VS
SK
9
VS
SD
LE
7
VS
SQ
A7
RF
U3
L7
C92
100n
FC
9210
0nF
C95
100n
FC
9510
0nF
C10
010
0nF
C10
010
0nF
C90
100n
FC
9010
0nF
C10
310
0nF
C10
310
0nF
C88
100n
FC
8810
0nF
C96
100n
FC
9610
0nF
C10
210
0nF
C10
210
0nF
R47
DN
PR
47D
NP
C89
100n
FC
8910
0nF
C10
610
0nF
C10
610
0nF
C99
100n
FC
9910
0nF
C97
100n
FC
9710
0nF
R44
0 RR
440 R
C91
100n
FC
9110
0nF
C10
510
0nF
C10
510
0nF
C98
100n
FC
9810
0nF
C84
1 00n
FC
841 0
0nF
C86
1 00n
FC
861 0
0nF
C85
100n
FC
8510
0nF
4-6 AT91SAM9M10-G45-EK User Guide
6495B–ATARM–21-Apr-10
Board Description
4.2.5 Power Supplies
The SAM9M10 Board contains four regulated power supplies:
3.3 VDC Supply
1.8 VDC Supply
1.0 VDC Core Supply
1.0 VDC Core UTMI Supply, PLL
The outputs of these regulated power supplies1 are distributed as necessary to each part of the circuit board.
The 3.3 VDC Supply is generated by an adjustable LDO. It accepts VIN 5 VCC power and outputs a regulated +3.3 V to most other circuits on the board.
The 1.8 VDC Supply (VDDIOM0, VDDIOM1) is generated by an adjustable LDO. It is powered by VIN 5 VCC power and outputs a regulated +1.8V.
The 1.0 VDC Core Supply (VDDCORE) is generated by an adjustable LDO. It is powered by the output of the 3.3 VDC Supply.
The 1.0 VDC Core Supply (VDDUTMIC, VDDPLLUTMI and VDDPLLA) is generated by an adjustable LDO RT9186A series. It is powered by the output of the 3.3 VDC Supply.
Note: 1. Corresponding test points (TP1 to TP4, GND) are used with jumpers (JP1.1 to JP7) to permit probing of these voltages.
AT91SAM9M10-G45-EK User Guide 4-7
6495B–ATARM–21-Apr-10
Board Description
Figure 4-5. Power Supply
1V_VDDUTMIC
3V3
3V3
3V3
1V
1V8
1V_VDDUTMIC
VDDUTMII
VDDANA
VDDOSC
VDDIOP0
VDDIOP1
VDDIOP2
VDDISI
VDDUTMIC
VDDPLLUTMI
VDDPLLA
VDDCORE
VDDIOM0
VDDIOM1
VDDBU
J3J3
JP3JP3
1
2
3
C294.7uC294.7u
J1-1J1-11 2
C24.7uC24.7u
JP1JP1
1
2
3
C144.7uC144.7u
R201RR201R
C221uC221u
JP2JP2
1
2
3
C1100nC1100n
J1-3J1-35 6
R13
100k
R13
100k
R10100kR10100k
C152.2uC152.2u
R121RR121R
JP7JP7
1
2
3
C18100nC18100n
JP6JP6
1
2
3
C251uC251u
C204.7uC204.7u
MN3RT9186AMN3RT9186A
VIN1
VIN2
PGOOD3
EN4 GND 5ADJ 6
VOUT 7VOUT 8
EP
9
C30100nC30100n
JP5JP5
1
2
3
C28100nC28100n
L4 10uHL4 10uH
R51RR51R
J1-2J1-23 4
C2110uC2110u
C19
10n
C19
10n
L3 10uHL3 10uH
L1 10uHL1 10uH
R1947kR1947k
R1412kR1412k
C8100nC8100n
J1-4J1-47 8
L2 10uHL2 10uH
R11RR11R
4-8 AT91SAM9M10-G45-EK User Guide
6495B–ATARM–21-Apr-10
Board Description
Figure 4-6. Management Power Block
PWR_EN
5V
1V
1V
5V
1V8
1V8
5V
3V3
3V3
5V
3V3
SHDN
FORCEPOWERON
REGULATED5V ONLY
MN4RT9018AMN4RT9018A
PGOOD1
EN2
VIN3
VDD4 NC 5VOUT 6
ADJ 7GND 8
EP
9
C910uC910u
C1210uC1210u
R9100kR9100k
R1812kR1812k
C111uC111u
C261uC261u
R11100kR11100k
C2310uC2310u
R1610kR1610k
C3 10nC3 10n
MN1RT9186AMN1RT9186A
VIN1
VIN2
PGOOD3
EN4 GND 5ADJ 6
VOUT 7VOUT 8
EP
9
R2100kR2100k
C16 10nC16 10n
C510nC510n
C433u
+C433u
R612kR612k
R4 47kR4 47k
C17
15p
C17
15p
R15 15kR15 15k
C7
1u
C7
1u
R715kR715k
JP4
SIP2
JP4
SIP2
12
CR15VCR15V
MN2RT9018AMN2RT9018A
PGOOD1
EN2
VIN3
VDD4 NC 5VOUT 6
ADJ 7GND 8
EP
9
Q1Si1563EDH
Q1Si1563EDH
1 32
456
C610uC610u
R199
100k
R199
100k
J2
DC POWER JACK
J2
DC POWER JACK
1
23
R847kR847k
C131uC131u
R1710kR1710k
C2710uC2710u
C101uC101u
C241uC241u
R3100kR3100k
AT91SAM9M10-G45-EK User Guide 4-9
6495B–ATARM–21-Apr-10
Board Description
4.2.6 Debug Interface
4.2.6.1 JTAG/ICE
Software debug is accessed by a standard 20-pin JTAG connection. This allows connection to a stan-dard USB-to-JTAG in-circuit emulator.
Figure 4-7. JTAG Interface
4.2.6.2 DBGU Com Port
This UART is connected to the DB-9 male socket through an RS-232 Transceiver (TXD and RXD only).
Figure 4-8. DBGU Com Port
TDI
RTCKTDO
TMSTCK
NTRST
NRST
3V3 3V3
3V3
NTRST
RTCK
TDITMSTCK
TDONRST
ICE INTERFACE
R92 0RR92 0R
J13
HTST-110-01-SM-D
J13
HTST-110-01-SM-D
12345678910111213151719
14161820
R940RDNP
R940RDNP
R93 0RR93 0R
R91 0RDNP
R91 0RDNP
RR43100k
RR43100k
12345 6 7 8
3V3
3V3
PB13
PB12
SERIAL DEBUG PORTC1+
V+
VCC
C1-C2+
C2-V-
T
T
R
R
GND
MN15
ADM3202ARNZ
C1+
V+
VCC
C1-C2+
C2-V-
GND
MN15
ADM3202ARNZ
116
34
5
15
11
10
12
98
13
7
14
2
6
R87100kR87100k
C159100nC159100n
R90 0RR90 0R
C163100nC163100n
C157 100nC157 100n
R88100kR88100k
C158 100nC158 100n
J10J10
5
4
3
2
1
9
8
7
6
1011
C165 100nC165 100n
4-10 AT91SAM9M10-G45-EK User Guide
6495B–ATARM–21-Apr-10
Board Description
4.2.6.3 User Serial Com Port
The USART1 is used as a user serial communication port. This USART1 is buffered with an RS-232 Transceiver (TXD, RXD and handshake CTS/RTS control) and connected to the DB-9 male socket. Soft-ware must assign the appropriate PIO pins (PB5 = RXD1, PB4 = TXD1, PD16 = RTS1, PD17 = CTS1) to enable the UART1 function.
Figure 4-9. User Serial Com Port
Refer to the SAM9M10 datasheet for more information about the SAM9M10 USARTs.
4.2.6.4 USB Port
The SAM9M10-G45-EK features USB communication ports:
Two Host Ports: Full speed OHCI and High speed EHCI
One Device Port: High speed.
USB Host Port0 is directly connected to the first UTMI transceiver. The second Host Port (Port1) is mul-tiplexed with the USB Device High speed and connected to the second UTMI port.
One USB high/full speed type standard A connector
One USB interface Host/Device Micro AB connector
Refer to the SAM9M10 datasheet for detailed programming information.
3V3
3V3
PB5
PD17
PB4
PD16
RS232 COM PORTC161100nC161100n
C1+
V+
VCC
C1-C2+
C2- V-
T
T
R
R
GND
MN16
ADM3202ARNZ
C1+
V+
VCC
C1-C2+
C2- V-
GND
MN16
ADM3202ARNZ
1 16
34
5
15
11
10
12
9 8
13
7
14
2
6 C166 100nC166 100n
C162 100nC162 100n
C160100nC160100n
J11J11
5
4
3
2
1
9
8
7
6
10 11
R86100kR86100k C164
100nC164100n
R89100kR89100k
AT91SAM9M10-G45-EK User Guide 4-11
6495B–ATARM–21-Apr-10
Board Description
Figure 4-10. USB Port
4.2.6.5 Ethernet 10/100 (EMAC) Port
The port is compatible with IEEE® Standard 802.3.
The SAM9M10-G45-EK is equipped with a Davicom DM9161AEP 10/100 Mbps Fast Ethernet Physical Layer TX/FX Single Chip Transceiver. It contains the entire physical layer functions of 100BASE-TX as defined by IEEE 802.3u, including the Physical Coding Sublayer (PCS), Physical Medium attachment (PMA), Twisted Pair Physical Medium Dependent Sublayer (TP-PMD), 10BASE-TX Encoder/Decoder (ENC/DEC), and Twisted Pair Media Access Unit (TPMAU).
The Ethernet interface integrates an RJ45 connector with an embedded transformer, and three status LEDs.
The Ethernet interface provides two selectable modes, MII or RMII (Reduced MII), for 100Base-TX or 10Base-TX. The MII and RMII interfaces are capable of both 10Mb/s and 100Mb/s data rates as described in the IEEE 802.3u standard. The signals used by MII and RMII interfaces are described in the table below.
5V
3V3
PD2
PD4
PD1
HDMA
HDPA
PD3
HDMBHDPBPD28
PB19
USB HOST/DEVICE INTERFACE
USB HOST INTERFACE
(ENA)
(ENB)
(FLGA)
(FLGB)
(VBUS)
(IDUSB)
C17110pC17110p
R9668kR9668k
R95 47kR95 47k
+ C17033u
+ C17033u
C169100nC169100n
J12G3505-4NBT1S1W J12G3505-4NBT1S1W
1
4
5
2
3
6
SHIE
LD
J14
G3515-09010101-00
VBUSDMDPID
GND
USB-A
J14
G3515-09010101-00
12345
7
6
+ C16833u
+ C16833u
R9747kR9747k
L14
220ohm at 100MHz
L14
220ohm at 100MHz
1 2
C167100nC167100n
MN17
AIC1526-0GS
MN17
AIC1526-0GS
ENA 1
FLGA 2
ENB 4
OUTA8
GNG6 FLGB 3
IN7
OUTB5
L13
220ohm at 100MHz
L13
220ohm at 100MHz
1 2
C172100nC172100n
4-12 AT91SAM9M10-G45-EK User Guide
6495B–ATARM–21-Apr-10
Board Description
Table 4-2. Pin Mapping for Normal MII and Reduced MII
Pin Name Normal MII Mode Reduced MII Mode
SAM9M10 DM9161 SAM9M10 DM9161
ETX0-ETX1 ETX[0:1] transmit data TXD [0:1] ETX[0:1] TXD [0:1]
ETX2-ETX3 ETX[2:3] transmit data TXD [2:3] NC NC
ETXEN ETXEN: transmit enable TXEN ETXEN: transmit enable TXEN
ETXER ETXER: transmit error TXER/TXD[4] NC NC
ETXCK/REFCK ETXCK: transmit clock TXCLK REFCK: reference clock REF_CLK
ERX0-ERX1 ERX[0:1]: receive data RXD [0:1] ERX[0:1]: receive data RXD [0:1]
ERX2-ERX3 ERX[2:3]: receive data RXD [2:3] NC NC
ERXER ERXER: receive errorRXER/RXD[4]/ RPTR/NODE
ERXER: receive error RPTR/NODE
ERXDV ERXDV: receive valid data RXDVECRSDV: carrier sense / data valid
CRS DV
ERXCK ERXCK: receive clock RXCLK NC NC
ECOL ECOL: collision detect COL NC NC
ECRSECRS: carrier sense / data valid
CRS (PHYAD[2:4] NC NC
EMDC EMDC: management data clock MDCEMDC: management data clock
MDC
EMDIOEMDIO: management data input / output
MDIOEMDIO: management data input / output
MDIO
NRST NRST: microcontroller resetRESET# XT1 (25 MHz)
NRST: microcontroller resetRESET# XT1 (REF_CLK 50MHz)
AT91SAM9M10-G45-EK User Guide 4-13
6495B–ATARM–21-Apr-10
Board Description
Figure 4-11. Ethernet Port
For more information about the Ethernet controller device, refer to the Davicom DM9161 controller man-ufacturer's datasheet.
GN
D_E
TH
GN
D_E
TH
GN
D_E
TH
GN
D_E
TH
GN
D_E
TH
3V3
3V3
3V3
3V3
3V3
3V3
AV
DD
T
AV
DD
T
AV
DD
T
3V3
PA
10P
A14
PA
27
PA
18
NR
ST
PA
19P
D5
PA
29P
A30
PA
16
PA
15P
A28
PA
12P
A13
PA
8P
A9
PA
17
PA
7P
A6
PA
11
SP
EE
D 1
00
FU
LL D
UP
LEX
LIN
K&
AC
T
(TX
_CLK
)
(TX
D3)
(TX
D2)
(RX
D1)
(RX
D0)
(RX
_CLK
)(R
X_D
V)
RJ4
5 E
TH
ER
NE
T C
ON
NE
CT
OR
(RX
D2)
(TX
D1)
(TX
D0)
(TX
_EN
)
(RX
D3)
(CO
L)(C
RS
)
(MD
C)
(MD
IO)
(MD
INT
R)
(TX
_ER
)(R
X_E
R)
JP16
JP16
12
RR
4710
kR
R47
10k
12345
678
C17
610
0nC
176
100n
C18
610
0nC
186
100n
R10
80R
DN
PR
108
0RD
NP
R10
60R
DN
PR
106
0RD
NP
C17
422
pD
NP
C17
422
pD
NP
R10
749
.9R
R10
749
.9R
C18
510
0nC
185
100n
C18
210
0nC
182
100n
C18
410
0nC
184
100n
R98
10k
R98
10k
C18
110
u10
V
C18
110
u10
V
R12
147
0RR
121
470R
C18
310
0nC
183
100n
L15
2200
R
L15
2200
R
12
MN
18
DM
9161
AE
P
MN
18
DM
9161
AE
P
TX
_ER
/TX
D4
16
CO
L/R
MII
36
MD
C24
RX
-4
RX
+3
TX
-8
TX
+7
XT
143
RE
F_C
LK/X
T2
42
RX
_CLK
/10B
TS
ER
34
RX
_DV
/TE
ST
MO
DE
37
RX
_ER
/RX
D4/
RP
TR
38
TX
_EN
21
BG
RE
S48
AV
DD
R1
AV
DD
R2
DV
DD
41
DG
ND
44
DG
ND
15
AG
ND
5
AG
ND
6
LED
2/O
P2
13LE
D1/
OP
112
LED
0/O
P0
11
TX
D3
17
TX
D2
18
TX
D0
20T
XD
119
TX
_CLK
/ISO
LAT
E22
RX
D0/
PH
YA
D0
29R
XD
1/P
HY
AD
128
RX
D2/
PH
YA
D2
27R
XD
3/P
HY
AD
326
CR
S/P
HY
AD
435
MD
IO25
MD
INT
R32
PW
RD
WN
10
DG
ND
33
RE
SE
T40
AV
DD
T9
DIS
MD
IX39
DV
DD
30
DV
DD
23
AG
ND
46
BG
RE
SG
47
CA
BLE
ST
S/L
INK
ST
S14
N.C
45
LED
MO
DE
31
Y5
25M
Hz
DN
P
Y5
25M
Hz
DN
P
13
2 4
1 2 3 6 4 5 7 8
75 75
7575
1nF
TD+
TD-
CT NCRD-
CT
TX+
TX-
RX+
RX-
RD+
J15
J00-
0061
NL
J15
J00-
0061
NL
1 2 7 83 654
15
16
R10
00R
DN
PR
100
0RD
NP
R10
249
.9R
R10
249
.9R
R11
60R
R11
60R
D6
Gre
enD
6G
reen
12
R11
00R
DN
PR
110
0RD
NP
R11
20R
DN
PR
112
0RD
NP
R11
40R
DN
PR
114
0RD
NP
R11
947
0RR
119
470R
C17
910
0nC
179
100n
C17
310
0nC
173
100n
D4
Yel
low
D4
Yel
low
12
R11
349
.9R
R11
349
.9R
C18
010
u10
V
C18
010
u10
V
R10
30R
DN
PR
103
0RD
NP
R10
40R
DN
PR
104
0RD
NP
R99
0RR99
0R
R10
50R
DN
PR
105
0RD
NP
R12
30R
R12
30R
R10
10R
R10
10R
R10
90R
DN
PR
109
0RD
NP
C17
810
0nC
178
100n
D5
Gre
enD
5G
reen
12
R11
51.
5kR
115
1.5k
R11
76.
8kR
117
6.8k
R11
847
0RR
118
470R
R12
00R
R12
00R
RR
4410
kR
R44
10k
12345
678
C17
710
0nC
177
100n
RR
4510
kR
R45
10k
12345
678
R12
20R
R12
20R
R11
149
.9R
R11
149
.9R
C17
522
pD
NP
C17
522
pD
NP
C18
710
u10
V
C18
710
u10
V
VDD
VSS
OUT
OEY4 50
MH
z
VDD
VSS
OUT
OEY4 50
MH
z
41
32
RR
4610
kR
R46
10k
12345
678
4-14 AT91SAM9M10-G45-EK User Guide
6495B–ATARM–21-Apr-10
Board Description
4.2.7 Audio Stereo Interface
The SAM9M10-G45-EK includes a WM9711L AC97 CODEC for digital sound input and output. This interface includes audio jacks for MIC input (J9), line audio input (J8), headphone line output (J7) and a 2-point speaker output connector (JP15).
It is compliant with AC97 Component Specification V2.2.
AT91SAM9M10-G45-EK User Guide 4-15
6495B–ATARM–21-Apr-10
Board Description
Figure 4-12. Audio Stereo Interface
For more information about the AC97 codec device, refer to the Wolfson WM9711L controller manufac-turer's datasheet.
AGND_AC97
AGND_AC97
AGND_AC97
AGND_AC97
AGND_AC97
AGND_AC97
AGND_AC97
3V3 AVDD_AC97
AVDD_AC97
3V3
AVDD_AC97
AGND_AC97
AGND_AC97
3V3
AGND_AC97
NRST
PD6
PD9
PD8
PD7
PE31
LINE-IN
MONO / STEREOMICROPHONE INPUT
HEADPHONELINE-OUT
8 Ohm SPEAKEROUTPUT
(AC97TX)(AC97CK)
(AC97RX)
(AC97FS)
(EXT_CLK)
JP17/JP18 are usedas testpoints
C1471uC1471u
C15410u10V
C15410u10V
JP14
DNP
JP14
DNP
1 2
R7247kR7247k
L1110uHL1110uH
C141100nC141100n
JP18 DNPJP18 DNP12
C129470pC129470p
C14410u10V
C14410u10V
R76 0RR76 0R
R83680RR83680R
L12220ohm at 100MHzL12220ohm at 100MHz
1 2
R73 10kR73 10k
Y3
24.576MHz
Y3
24.576MHz
13
2 4
C131
100n
C131
100n
C13410u10V
C13410u10V
C14010u10V
C14010u10V
J7
STEREO_3.5mm
J7
STEREO_3.5mm
1
3 4
2 5
C137 22pC137 22p
C136100nC136100n
R69 0RR69 0R
JP15DNP
JP15DNP
12
R818.2KR818.2K
+C127 100u/6.3V+C127 100u/6.3V
C145100nC145100n
J8
STEREO_3.5mm
J8
STEREO_3.5mm
1
3 4
2 5R79 8.2KR79 8.2K
L7220ohm at 100MHzL7220ohm at 100MHz
1 2
JP17 DNPJP17 DNP12
R75 0RDNP
R75 0RDNP
+C126 100u/6.3V+C126 100u/6.3V
L9
220ohm at 100MHz
L9
220ohm at 100MHz
1 2
C138100nC138100n
C148470pC148470p
R84680RR84680R
C155470pC155470p
J9
STEREO_3.5mm
J9
STEREO_3.5mm
1
3 4
2 5C1501uC1501u
C153100nC153100n
MN14
WM9711L
MN14
WM9711LO
UT
337
HP
_O
UT
_L
39
HP
_O
UT
_R
41
LOUT2 35ROUT2 36
SDATAIN8
GP
IO5/S
PD
IF48
XTLOUT3
COMP1 29COMP2 30COMP3 31
CAP2 32
VREF 27MICBIAS 28
GP
IO4
47
CREF12
AG
ND
242
AVDD1 25
SP
KV
DD
38
HP
VD
D43
SPKGND 34
DBVDD1
DCVDD9
NC
114
NC
215
PH
ON
E20
PC
BE
EP
19
AG
ND
118
LIN
E_IN
_L
23
LIN
E_IN
_R
24
MIC
121
MIC
222
AV
DD
213
GP
IO2/IR
Q45
GP
IO3
46
SDATAOUT5
RESET11SYNC10
XTLIN2
BITCLK6
NC
417
NC
316
AGND 26
HP
_G
ND
40
GP
IO1
44
MONOOUT 33DGND14
DGND27
TH
ER
MA
L49
R7147kR7147k
C1461uC1461u
C135
100n
C135
100n
C13210u10V
C13210u10V
C143100nC143100n
L10220ohm at 100MHzL10220ohm at 100MHz
1 2
C14210u10V
C14210u10V
C128470pC128470p
R77 0RR77 0R
C130
100n
C130
100n
R828.2KR828.2K
R70 0RR70 0R
R78 49.9RR78 49.9R
C139100nC139100n
R85 0RR85 0R
L6220ohm at 100MHzL6220ohm at 100MHz
1 2
R74 100kR74 100k
C133 22pC133 22p
L8220ohm at 100MHzL8220ohm at 100MHz
1 2
C1511uC1511u
C15210u10V
C15210u10V C156
470pC156470p
R80 8.2KR80 8.2K
C149470pC149470p
4-16 AT91SAM9M10-G45-EK User Guide
6495B–ATARM–21-Apr-10
Board Description
4.2.8 TV-Out Extension
The Chrontel™ CH7024 chip provides an interface between the SAM9M10 LCD Controller and a TV set by converting LCD signals to TV signals.
The CH7024 is a TV encoder device which encodes the video signals and generates synchronization signals for NTSC and PAL standards. Supported TV output formats are NTSC-M, NTSC-J, NTSC-433, PAL-B/D/G/A/I, PAL-M, PAL-N and PAL-60. The CH7024 provides video output support for CVBS or S-video.
Figure 4-13. TV-Out Extension Port
PE23PE24PE25PE26PE27PE28PE29PE30PE15PE16PE17PE18PE19PE20PE21PE22PE7PE8PE9PE10PE11PE12PE13PE14
PE6
PE6
PE17
PE12
PE28
PE23
PE7
PE1
PE18
PE13
PE29
PE24
PE8
PE2
PE0
PE19
PE3
PE14
PE25
PE9
PE20
PE4
PE15
PE26
PE10
PE21
PE5
PE16
PE11
PE27
PE30
PE22 1V8
3V3
3V3
3V3
3V3
3V3
PE[0..30]
PA21
NRST
PA20
TV_XCLKTV_HSYNCTV_VSYNC
CompositeVideo Output
(LCDMOD)
(G4)
(R6)
(B3)
(LCDPWR)
(G5)
(LCDDEN)
(LCDCC)
(R7)(G0)
(B4)
(G6)
(B5)
(R2)
(G7)(B0)
(G1)
(B6)
(R3)
(G2)
(B7)
(R1)
(R4)
(B1)
(G3)
(LCDDOTCK)
(R5)
(R0)
(B2)
(HSYNC)(VSYNC)
(TWDO)(TWCK0)
L212200RL212200R
1 2
C197100nC197100n
MN20 CH7024BMN20 CH7024B
D71
D82
D93
D104
D115
D126
D137
D148
D159
D1610
D1711
D1812
D1913
D2014
D2115
D2217
D2319
D042
D143
D244
D345
D446
D547
D648
V39
H40
XCLK41
DE20
RESET23
VDDIO 38
AVDD_DAC 25
DVDD 16
AVDD_PLL 32
AVDD 33
DGND 18
AGND_DAC 29
AGND_PLL 31
AGND 36
SPD21
SPC22
NC24
C/CVBS 26
Y 27
CVBS 28
ISET 30
XI/
FIN
34
XO
35
P-OUT 37
D8
BAT54SLT1G
D8
BAT54SLT1G
1 2
3R180 4.7kR180 4.7k
C204 33pC204 33p
C206100pC206100p
C200100nC200100n
R183 75RR183 75R
C205100pC205100p
C20810pC20810p
R178 1.2k
1%
R178 1.2k
1%
L182200RL182200R
1 2
J20J20RCA JACK
3
1
C203100nC203100n
C19910u10V
C19910u10V
C202100nC202100n
R186 0RDNP
R186 0RDNP
VDD
VSS OUT
��
Y6
13MHz
DNP
VDD
VSS OUT
��
Y6
13MHz
DNP
41
32
C207100nDNP
C207100nDNP
R181 75RR181 75R
TP6TP6
R1850RR1850R
L172200RL172200R
1 2
L22
1.8uH
L22
1.8uHR179 4.7kR179 4.7k
R18275RR18275R
C19810u10V
C19810u10V
L192200RL192200R
1 2
L202200RL202200R
1 2
C196100nC196100n
Y7
13MHz
Y7
13MHz
1 3
24
C20910pC20910p
R184 10k DNPR184 10k DNP
C20110u10V
C20110u10V
AT91SAM9M10-G45-EK User Guide 4-17
6495B–ATARM–21-Apr-10
Board Description
4.2.9 Software Controlled LEDs
Three users LED are provided for general use. The LEDs are connected to PIO port lines, allowing their control through either GPIO or PWM control.
LEDs D1 to D3 are software controlled by PIO pins.
LEDs D4 to D6 indicate Ethernet traffic and link status. These are automatically managed by on-chip microcontroller hardware. See Section 7.1 ”Schematics” .
Figure 4-14. Software Controlled LEDs
Table 4-3. Discrete LEDs
LED Description Comment
D1 Green LED User software controlled
D2 Green LED User software controlled
D3 Red LED User software controlled
D4 Yellow LED Indicates transmission or reception via Ethernet
D5 Green LED Indicates speed 100
D6 Green LED Is lit when a good link test has been detected
PB17
PB18PB14
PB15PB16
3V3
3V3 PD0
PD31
PD30
PB[14..18]POWER LED
USER INTERFACE
UPRIGHTDOWNPUSH
LEFT
C3610n
C3610n
D2
Green
D2
Green
1 2
C3410n
C3410n R28
100RR28100R
R22 470RR22 470R
R25
470R
R25
470R
D1Green
D1Green
1 2
Q2IRLML2402
Q2IRLML2402 1
3
2
D3RedD3Red
12
C3310n
C3310n
BP3BP3
JOYSTICK
123
456
C3210n
C3210n
C3510n
C3510n
R26100kR26100k
R21 470RR21 470R
4-18 AT91SAM9M10-G45-EK User Guide
6495B–ATARM–21-Apr-10
Board Description
4.2.10 Serial Peripheral Interface Controller (SPI)
The SAM9M10 provides two high-speed Serial Peripheral Interface (SPI) controllers. One port is used to interface with the on-board serial DataFlash®.
Figure 4-15. SPI
4.2.11 Two Wire Interface (TWI)
The SAM9M10 has a full speed (400 kHz) master/slave I2C Serial Controller. The controller is fully com-patible with the industry standard I2C and SMBus Interfaces. This port is used to interface with the on-board Serial EEPROM, ISI and TV encoder interface.
Figure 4-16. TWI
4.2.12 SD/MMC Interface
The SAM9M10-G45-EK has two high-speed 8-bit multimedia interfaces MMC/MMCPlus v4.1. The first interface is used as an 8-bit interface (MCI1), connected to a CE-ATA connector footprint and an 8-bit SD/MMC card slot. The second interface is used as a 4-bit interface (MCI0), connected to a 4-bit SD/MMC card slot.
The users must provide their own compatible cards for use with these connectors.
Please note that the power is connected to VCC, which is 3.3 volts.
3V3
3V3
PB1PB2PB3
PB0
NRST
SERIAL DATAFLASH
(test points)
(SPI0_MISO)(SPI0_MOSI)(SPI0_SPCK)(SPI0_NPCS0)
JP12SIP2JP12SIP2
1 2
C124100nC124100n
JP11DNPJP11DNP
1
2
3R67470kR67470k
MN13MN13
RESET3
GND 7
VCC 6
CS4SCK2SI1SO8
WP 5
R680RDNP
R680RDNP
3V3
3V3
PA21PA20
SERIAL EEPROM
(TWCK0)(TWDO)
JP13
SIP2
JP13
SIP21
2
R6610kR6610k
C125 100nC125 100n
MN12MN12
A0 1
A1 2
WP 7
SCL6
VCC8A3 3
SDA5
GND4
AT91SAM9M10-G45-EK User Guide 4-19
6495B–ATARM–21-Apr-10
Board Description
Figure 4-17. SD/MMC0
Figure 4-18. SD/MMC1
4.2.13 TFT LCD with Touch Panel
The SAM9M10 features an LCD controller. A 4.3" 480x272 Portrait Mode LCD provides the SAM9M10-G45-EK with a low power LCD display, back light unit and a touch panel, similar to that used on commer-cial PDAs.
The TFT LCD component is a truly model number TFT1N4633.
Graphics and text can be displayed on the dot matrix panel with up to 16 million colors by supplying 24-bit data signals (8bitxRGB by default) or 16-bit data signals (5+6+5bitxRGB in option). This allows the user to develop graphical user interfaces for a wide variety of end applications.
Warning: never connect/disconnect the LCD display from the board while the power supply is on. Doing so may damage both units and is not covered by warranty.
The back light voltage is generated from a CP2122ST boost converter. It is powered directly by the VIN 5 VCC power (the control for the back light voltages is separated from the main board voltages due to the specific voltage requirements of the LCD panel).
PA26PA25
PA27PA28PA29PA30
PA24PA23
PA31
PA22
3V3
3V3
PD29PD11
PA[22..31]
SD/MMCPlus CARD INTERFACE - MCI1
(MCI1_DA1)(MCI1_DA0)
(MCI1_CK)
(MCI1_CDA)(MCI1_DA3)(MCI1_DA2)
(MCI1_DA4)(MCI1_DA5)
(MCI1_DA7)(MCI1_DA6)
(MCI1_CD)(MCI1_WP)
RR3610kRR3610k
1 2 3 45678R192
68k
R192
68k
RR39
27R
RR39
27R
1234 5
678
R193
68k
R193
68k
C123100nC123100n
R194
68k
R194
68k
RR41 27RRR41 27R1234 5
678
R195
68k
R195
68k
RR42 27RRR42 27R1234 5
678
R196
68k
R196
68k
R197
68k
R197
68k
R198
68k
R198
68k
J5J58
5
76
43219
141516
13121110
R191
68k
R191
68k
PA1PA5PA4
PA3PA2
PA0
3V3
3V3
PD10PA[0..5]
SD/MMC CARD INTERFACE - MCI0
(MCI0_DA1)(MCI0_DA0)
(MCI0_CK)
(MCI0_CDA)(MCI0_DA3)(MCI0_DA2)
(MCI0_CD)
R188
68k
R188
68k
R189
68k
R189
68k
R187
68k
R187
68kR6410kR6410k
R190
68k
R190
68k
R6510kR6510k
RR38 27RRR38 27R1234 5
678
J6J68
5
76
43219
101112
RR40 27RRR40 27R
1234 5
678
C122 100nC122 100n
4-20 AT91SAM9M10-G45-EK User Guide
6495B–ATARM–21-Apr-10
Board Description
Figure 4-19. TFT LCD
pin1pin2pin3
pin29
pin4
pin37
4.3" 480x272
TFT LCD DISPLAY
pin38pin39
pin32
pin40
pin33
pin42pin43
20mA MAX
(LCDPWR)
pin35
9 LEDs Back Light
pin36
pin41
pin34
pin5pin6pin7pin8pin9pin10pin11pin12pin13pin14pin15pin16pin17pin18pin19pin20pin21pin22pin23pin24pin25pin26pin27pin28
pin30pin31
pin44pin45
(pinxx = display pin number )
(LCDDEN)
(G4)
(R6)
(B3)
(LCDPWR)
(G5)
(LCDDEN)
(LCDCC)
(R7)(G0)
(B4)
(G6)
(B5)
(R2)
(G7)(B0)
(G1)
(B6)
(R3)
(G2)
(B7)
(R1)
(R4)
(B1)
(G3)
(LCDDOTCK)
(R5)
(R0)
(B2)
(AD1Xm)(AD3Ym)(AD0Xp)
(AD2Yp)(LCDCC)
R48 is placed near processor
YpLCD
VLED-XmLCDYmLCD
VLED+
XpLCDYmLCDXmLCD
YpLCD
VLED-VLED+
XpLCD
BLUE6BLUE7
RED0
BLUE2BLUE3BLUE4BLUE5
BLUE0BLUE1
GREEN5GREEN6GREEN7
GREEN2GREEN3GREEN4
RED6RED7GREEN0GREEN1
RED2RED3RED4RED5
RED1
PE0LCDDOTCK
PE2
RED3PE8PE10
RED4PE9PE11
RED5PE10PE12
RED6PE11PE13
RED7PE12PE14
GREEN2PE13PE17
PE14GREEN3 PE18
PE19GREEN4PE15
PE20GREEN5PE16
PE21GREEN6PE17
PE22GREEN7PE18
PE26PE20
BLUE3
PE27BLUE4PE21
PE28BLUE5PE22
PE29BLUE6PE23
PE30BLUE7PE24
PE7PE8PE9
PE15PE16
PE23PE24PE25
PE6
PE6
PE17
PE12
PE28
PE23
PE7
PE1
PE18
PE13
PE29
PE24
PE8
PE2
PE0
PE19
PE3
PE14
PE25
PE9
PE20
PE4
PE15
PE26
PE10
PE21
PE5
PE16
PE11
PE27
PE30
PE22
3V3
3V3
5V
PE[0..30]
PD22PD21PD23PD20
LCDDOTCK
C188100nFC188100nF
Co
nd
ucto
rs
o
n
TO
P S
IDE
LG
PH
ILIP
S
Z7
LB043WQ1
Co
nd
ucto
rs
o
n
TO
P S
IDE
PIN 1
PIN 45
LG
PH
ILIP
S
Z7
LB043WQ1R172 0RR172 0R
R184 DNPR184 DNP
RR53ARR53A1 8
RR49CRR49C3 6
R155 DNPR155 DNP
RR48ARR48A1 8
RR49DRR49D4 5
RR53CRR53C3 6
RR52ARR52A1 8
C209DNPC209DNP
C210DNPC210DNP
R157 DNPR157 DNP
R178 0RR178 0R
R161 DNPR161 DNP
R154 0RR154 0R
RR49ARR49A1 8
R148 0RR148 0R
RR50DRR50D4 5
R164 0RR164 0R
D12STPS0540Z
D12STPS0540Z
R130 0RR130 0R
R176 0RR176 0R
C2012.2uFC2012.2uF
RR50CRR50C3 6
R175 0RR175 0R
R160 0RR160 0R
R12310RR12310R
RR49BRR49B2 7
RR48DRR48D4 5
R149 DNPR149 DNP
R182 DNPR182 DNP
R158 0RR158 0R
C189
10V10uFC189
10V10uF
RR51DRR51D4 5
R48 33RR48 33R
R151 DNPR151 DNP
R18010KR18010K
RR52CRR52C3 6
RR53BRR53B2 7
R150 0RR150 0R
R152 0RR152 0R
RR48BRR48B2 7
R173 0RR173 0R
R177 0RR177 0R
RR52DRR52D4 5
R174 0RR174 0R
RR50ARR50A1 8
R153 DNPR153 DNP
RR50BRR50B2 7
R50 27RR50 27R
R168 0RR168 0RR169 DNPR169 DNP
R162 0RR162 0R
R1364.7KR1364.7K
R13710KR13710K
RR51BRR51B2 7
R183 0RR183 0R
C211DNPC211DNP
R144 0RR144 0R
C203220nFC203220nF
R145 DNPR145 DNP
R166 0RR166 0R
R133 0RR133 0R
R179 0RR179 0R
R181 0RR181 0R
R167 DNPR167 DNP
RR51CRR51C3 6
R163 DNPR163 DNP
RR52BRR52B2 7
L23
22uH
L23
22uH
J24
XF2M45151A
J24
XF2M45151A
123456789
101112131415161718192021222324252627282930313233343536373839404142434445
R159 DNPR159 DNP
R165 DNPR165 DNP
RR53DRR53D4 5
R132 0RR132 0R
R156 0RR156 0R
RR48CRR48C3 6
R170 0RR170 0R
R147 DNPR147 DNP
MN25 TPS61161DRVTMN25 TPS61161DRVT
SW
4
GN
D3
FB1 CTRL
5
COMP2
VIN6
THP
7
R131 0RR131 0R
RR51ARR51A1 8
R171 DNPR171 DNP
R146 0RR146 0R
C2021uFC2021uF C208
DNPC208DNP
AT91SAM9M10-G45-EK User Guide 4-21
6495B–ATARM–21-Apr-10
Board Description
4.2.14 Push Buttons
The SAM9M10-G45-EK is equipped with two system push buttons, two user push buttons and one joy-stick. The push buttons consist of momentary push button switches mounted directly to the board. When any switch is depressed, a low (zero) appears at the associated input pin.
System push buttons:
– Reset, perform system reset
– Wakeup, perform system wake up
User push button:
– Right click
– Left click
Joystick:
– One touch, 5-way switching,
– Normally open momentary contacts,
– Push down to select in any position.
Figure 4-20. Push Buttons
4.2.15 Expansion Slot
GPIO1 & GPIO2, LCD signals (PIO E) are routed to the connectors extension J23
All I/Os of the SAM9M10 Image Sensor Interface are routed to connectors J17
Touch screen signals and analog I/O are connected to J18
This allows the developer to extend the features of the board by adding external hardware components or boards.
VDDBU3V3
NRST
WAKE UP
PB7
PB6
RIGHT CLICK
WAKE UP
NRST
LEFT CLICK
BP5BP5
C37
10n
C37
10n
R241kR241k
BP2BP2
R29
100R
R29
100R
R23100kR23100k
BP4BP4
R27
100R
R27
100R
BP1BP1
C31
10n
C31
10n
4-22 AT91SAM9M10-G45-EK User Guide
6495B–ATARM–21-Apr-10
Board Description
Figure 4-21. Expansion Slot
PE27PE29
PE25PE23
PE2PE1
PE16
PE20PE18
PE14
PE22
PE10PE12
PE26
PE30PE28
PE24
PE6
PE7
PE0
PE9PE8
PE11PE13PE15PE17
PE21PE19
PB21PB23PB25PB27PB9PB11
PA21PB31PB29PB30PB28PB20PB22PB24PB26PB8PB10
PA20
3V3
3V3
3V3
5V
3V3
VDDISI
PD25PD27PD19
PD24PD26PD18
PD15PD14
PD21PD23
PD20PD22
PD12 PD13
LCDDOTCKLCDHSYNC LCDVSYNC
IMAGE SENSOR CONNECTOR
CONNECTOR EXTENSION FOR LARGE LCD
(AD1Xm)(AD3Ym) (AD2Yp)
(AD0Xp)
(GPIO2)(GPIO1)
)2LRTC()1LRTC(
J17
HDR_2x15_SMT
J17
HDR_2x15_SMT
1 23 45 67 89 10
11 1213151719
14161820
21 2223 2425 2627 2829 30
C212100nC212100n
J23
HDR_2x20_SMT
DNPJ23
HDR_2x20_SMT
DNP1 23 45 67 89 10
11 1213151719
14161820
21 2223 2425 2627 2829 3031 3233 3435 3637 3839 40
C210100nC210100n
C21110u10V
C21110u10V
J18
HDR_2x10_SMTDNP
J18
HDR_2x10_SMTDNP
1 23 45 67 89 10
11 1213151719
14161820
R175 0R
DNP
R175 0R
DNP
R176 0RDNP
R176 0RDNP
AT91SAM9M10-G45-EK User Guide 4-23
6495B–ATARM–21-Apr-10
Section 5
Configuration
5.1 JTAG/ICE Configuration
5.2 ETHERNET Configuration
RMII is the factory default mode.
To evaluate the MII mode, the user has to unsolder R99 and solder R100, R103 to R105, R108 to R110, R112, R114, C174, C175, Y5.
Table 5-1. JTAG/ICE Configuration
Designation Default Setting Feature
R91 Not populated Disables the ICE NTRST input
R92 Soldered Enables the ICE RTCK return. R94 must be opened
R93 Soldered Enables the ICE NRST input
R94 Not populated Disables TCK <-> RTCK local loop
AT91SAM9M10-G45-EK User Guide 5-1
6495B–ATARM–21-Apr-10
Configuration
5.3 Jumpers Configuration
Two types of jumpers are used on the SAM9M10-G45-EK board:
2-pin jumpers with two possible settings:
– Fitted: the circuit is closed
– Not fitted: the circuit is open
3-pin jumpers with two possible positions, for which settings are presented in the following tables.
Table 5-2. Jumpers Configuration
DesignationDefault Setting Feature
J1 (combined
jumper array)
Closed J1-1 1-2 VDDUTMII 3V3
Closed J1-2 3-4 VDDUTIMC 1V
Closed J1-3 5-6 VDDCORE 1V
Closed J1-4 7-8 VDDPLLUTMI 1V
JP1 1-2 JP11-2 VDDIOP0 3V3
2-3 External power to VDDIOP0 3V3 nominal
JP2 1-2 JP21-2 VDDIOP1 3V3
2-3 External power to VDDIOP1 3V3 nominal
JP3 1-2 JP31-2 VDDIOP2 3V3
2-3 External power to VDDIOP2 3V3 nominal
JP4 Opened
Forces power on.
To use the software shutdown control, JP4 must be opened. 3V battery backup must be present and JP7 jumper set in position 1-2
JP5 1-2 JP51-2 VDDIOM0 1V8
2-3 External power to VDDIOM0 1V8 nominal
JP6 1-2 JP61-2 VDDIOM1 1V8
2-3 External power to VDDIOM1 1V8 nominal
JP7 1-2 JP71-2 VDDBU Lithium 3V Battery
2-3 VDDBU 3.3V from regulator
JP8 OpenedBMS Enables Boot on the internal ROM; closed selects the boot from the external device connected to NCS0
JP9 Closed Enables chip select access, Boot on the NCS0 (MN10 Flash)
JP10 Closed Enables chip select access, Boot on the NCS3 (MN11 NAND Flash)
JP11 Test point JP11.1: SO JP11.2: SI JP11.3: SCK
JP12 Closed Enables chip select access, Boot on the SPIO_NPCS0 (Serial DataFlash MN13)
JP13 Opened Set address A0 low (MN12 Serial EEPROM), enable Boot access.
JP14 JP14.1 = Line_Out JP14.3 = AGND
JP15 Used to connect a Loudspeaker
JP16 Closed DISMDIX (MN18)
JP17-JP18 Test points Give access to the four GPIOs of WM9711L
5-2 AT91SAM9M10-G45-EK User Guide
6495B–ATARM–21-Apr-10
Configuration
5.4 Miscellaneous Configuration Items
N.P = not populated
P = populated
5.5 PIO Configuration
5.5.1 Peripheral Signals Multiplexing on I/O Lines
The AT91SAM9M10 product features 5 PIO controllers, PIOA, PIOB, PIOC, PIOD and PIOE, which mul-tiplex the I/O lines of the peripheral set. Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B. The multiplexing tables in the following paragraphs define how the I/O lines of peripherals A and B are multiplexed on the PIO Controllers.
5.5.2 Multiplexing on PIO Controller A (PIOA)
"R.Select" = connection selectable via an on-board resistor (default not populated)
Table 5-3. Miscellaneous Configuration
DesignationDefault Setting Feature
R34 N.P JTAGSEL
R35 P Connect TSADVREF to VDDANA (may be used for specific filtering)
R36 P Connect GNDANA to GND (may be used for specific filtering)
R38 P Force TST pin to GND (chip is set in non-test mode = normal operation mode)
R63 N.PWrite protect NAND Flash (mount a 0-ohm resistor to write-protect the NAND Flash device)
R68 N.PWrite protect serial DataFlash (mount a 0-ohm resistor to write-protect the serial Flash device)
R75 N.P External clock Audio AC97 (mount a 0-ohm resistor to connect it)
R91,R92R93,R94
ICE interface reset and clocking schemes (see Section 5.1 ”JTAG/ICE Configuration” )
R100, R103 to R105, R108 to
R110, R112, R114, C174,
C175, Y5
Ethernet interface, MII mode (see Section 5.2 ”ETHERNET Configuration” )
Y6, R184, R186
N.P External 13 MHz oscillator (option) for the on-board video composite encoder
TP1 GND Test point
TP2 GND Test point
TP3 GND Test point
TP4 GND Test point
AT91SAM9M10-G45-EK User Guide 5-3
6495B–ATARM–21-Apr-10
Configuration
Table 5-4. PIO Multiplexing Port A
I/O Peripheral A Peripheral B Function and Comments Power
PA0 MCI0_CK TCLK3 MMCI0 Clock VDDIOP0
PA1 MCI0_CDA TIOA3 MMCI0 Command VDDIOP0
PA2 MCI0_DA0 TIOB3 MMCI0 Data0 VDDIOP0
PA3 MCI0_DA1 TCKL4 MMCI0 Data1 VDDIOP0
PA4 MCI0_DA2 TIOA4 MMCI0 Data2 VDDIOP0
PA5 MCI0_DA3 TIOB4 MMCI0 Data3 VDDIOP0
PA6 MCI0_DA4 ETX2 Ethernet MII VDDIOP0
PA7 MCI0_DA5 ETX3 Ethernet MII VDDIOP0
PA8 MCI0_DA6 ERX2 Ethernet MII VDDIOP0
PA9 MCI0_DA7 ERX3 Ethernet MII VDDIOP0
PA10 ETX0 Ethernet RMII Transmit data 0 VDDIOP0
PA11 ETX1 Ethernet RMII Transmit data 1 VDDIOP0
PA12 ERX0 Ethernet RMII Receive data 0 VDDIOP0
PA13 ERX1 Ethernet RMII Receive data 1 VDDIOP0
PA14 ETXEN Ethernet RMII Transmit enable VDDIOP0
PA15 ERXDV Ethernet RMII Receive data valid VDDIOP0
PA16 ERXER Ethernet RMII Receive Error VDDIOP0
PA17 ETXCK Ethernet RMII Transmit Clock VDDIOP0
PA18 EMDC Ethernet RMII Manag.Data Clock VDDIOP0
PA19 EMDIO Ethernet RMII Manag.Data In/Out VDDIOP0
PA20 TWD0 Two Wire Interface Data VDDIOP0
PA21 TWCK0 Two Wire Interface Clock VDDIOP0
PA22 MCI1_CDA SCK3 MMCI1 Command VDDIOP0
PA23 MCI1_DA0 RTS3 MMCI1 Data0 VDDIOP0
PA24 MCI1_DA1 CTS3 MMCI1 Data1 VDDIOP0
PA25 MCI1_DA2 PWM3 MMCI1 Data2 VDDIOP0
PA26 MCI1_DA3 TIOB2 MMCI1 Data3 VDDIOP0
PA27 MCI1_DA4 ETXER R.Select MMCI1 Data4 Ethernet MII VDDIOP0
PA28 MCI1_DA5 ERXCK R.Select MMCI1 Data5 Ethernet MII VDDIOP0
PA29 MCI1_DA6 ECRS R.Select MMCI1 Data6 Ethernet MII VDDIOP0
PA30 MCI1_DA7 ECOL R.Select MMCI1 Data7 Ethernet MII VDDIOP0
PA31 MCI1_CK PCK0 MMCI1_clock VDDIOP0
5-4 AT91SAM9M10-G45-EK User Guide
6495B–ATARM–21-Apr-10
Configuration
5.5.3 Multiplexing on PIO Controller B (PIOB)
Table 5-5. PIO Multiplexing Port B
I/O Peripheral A Peripheral B Function and Comments Power
PB0 SPI0_MISO SPI Slave Out Serial DataFlash VDDIOP0
PB1 SPI0_MOSI SPI Slave In Serial DataFlash VDDIOP0
PB2 SPI0_SPCK SPI Serial Clock Serial DataFlash VDDIOP0
PB3 SPI0_NPCS0 SPI Chip Select Serial DataFlash VDDIOP0
PB4 TXD1 USART1 Transmit Data VDDIOP0
PB5 RXD1 USART1 Receive Data VDDIOP0
PB6 TXD2 User Push Button Right click VDDIOP0
PB7 RXD2 User Push Button Left click VDDIOP0
PB8 TXD3 ISI_D8 Image Sensor Data 8 VDDIOP2
PB9 RXD3 ISI_D9 Image Sensor Data 9 VDDIOP2
PB10 TWD1 ISI_D10 Image Sensor Data 10 VDDIOP2
PB11 TWCK1 ISI_D11 Image Sensor Data 11 VDDIOP2
PB12 DRXD DBGU Receive Data VDDIOP0
PB13 DTXD DBGU Transmit Data VDDIOP0
PB14 SPI1_MISO Joystick Left VDDIOP0
PB15 SPI1_MOSI CTS0 Joystick Right VDDIOP0
PB16 SPI1_SPCK SCK0 Joystick Up VDDIOP0
PB17 SPI1_NPCS0 RTS0 Joystick Down VDDIOP0
PB18 RXD0 SPI0_NPCS1 Joystick Push VDDIOP0
PB19 TXD0 SPI0_NPCS2 UsbVbus VDDIOP0
PB20 ISI_D0 Image Sensor Data 0 VDDIOP2
PB21 ISI_D1 Image Sensor Data 1 VDDIOP2
PB22 ISI_D2 Image Sensor Data 2 VDDIOP2
PB23 ISI_D3 Image Sensor Data 3 VDDIOP2
PB24 ISI_D4 Image Sensor Data 4 VDDIOP2
PB25 ISI_D5 Image Sensor Data 5 VDDIOP2
PB26 ISI_D6 Image Sensor Data 6 VDDIOP2
PB27 ISI_D7 Image Sensor Data 7 VDDIOP2
PB28 ISI_PCK Image Sensor Data Clock VDDIOP2
PB29 ISI_VSYNC Image Sensor Vertical Synchro VDDIOP2
PB30 ISI_HSYNC Image Sensor Horizontal Synchro VDDIOP2
PB31 ISI_MCK PCK1 Image Sensor Reference Clock VDDIOP2
AT91SAM9M10-G45-EK User Guide 5-5
6495B–ATARM–21-Apr-10
Configuration
5.5.4 Multiplexing on PIO Controller C (PIOC)
Table 5-6. PIO Multiplexing Port C
I/O Peripheral A Peripheral B Function and Comments Power
PC0 DQM2 VDDIOM1
PC1 DQM3 VDDIOM1
PC2 A19 Add19 NAND Flash VDDIOM1
PC3 A20 Add20 NAND Flash VDDIOM1
PC4 A21/NANDALE ALE NAND Flash VDDIOM1
PC5 A22/NANDCLE CLE NAND Flash VDDIOM1
PC6 A23 VDDIOM1
PC7 A24 VDDIOM1
PC8 CFCE1 Ready/Busy NAND Flash VDDIOM1
PC9 CFCE2 RTS2 VDDIOM1
PC10 NCS4/CFCS0 TCLK2 VDDIOM1
PC11 NCS5/CFCS1 CTS2 VDDIOM1
PC12 A25/CFRNW VDDIOM1
PC13 NCS2 VDDIOM1
PC14 NCS3/NANDCS Chip select NAND Flash VDDIOM1
PC15 NWAIT VDDIOM1
PC16 D16 VDDIOM1
PC17 D17 VDDIOM1
PC18 D18 VDDIOM1
PC19 D19 VDDIOM1
PC20 D20 VDDIOM1
PC21 D21 VDDIOM1
PC22 D22 VDDIOM1
PC23 D23 VDDIOM1
PC24 D24 VDDIOM1
PC25 D25 VDDIOM1
PC26 D26 VDDIOM1
PC27 D27 VDDIOM1
PC28 D28 VDDIOM1
PC29 D29 VDDIOM1
PC30 D30 VDDIOM1
PC31 D31 VDDIOM1
5-6 AT91SAM9M10-G45-EK User Guide
6495B–ATARM–21-Apr-10
Configuration
5.5.5 Multiplexing on PIO Controller D (PIOD)
Table 5-7. PIO Multiplexing Port D
I/O Peripheral A Peripheral B Function and Comments Power
PD0 TK0 PWM3 Command LED2 VDDIOP0
PD1 TF0 Output ENA USB Host VDDIOP0
PD2 TD0 Input FLGA USB Host VDDIOP0
PD3 RD0 Output ENB USB Host VDDIOP0
PD4 RK0 Input FLGB USB Host VDDIOP0
PD5 RF0 Int. Ethernet 10/100 MDINTR VDDIOP0
PD6 AC97RX AC97 Receive Signal VDDIOP0
PD7 AC97TX TIOA5 AC97 Transmit Signal VDDIOP0
PD8 AC97FS TIOB5 AC97 Frame Sync Signal VDDIOP0
PD9 AC97CK TCLK5 AC97 Clock Signal VDDIOP0
PD10 TD1 Card Detect MMCI0 MCI0_CD VDDIOP0
PD11 RD1 Card Detect MMCI1 MCI1_CD VDDIOP0
PD12 TK1 PCK0 CTRL1 Image Sensor Interface VDDIOP0
PD13 RK1 CTRL2 Image Sensor Interface VDDIOP0
PD14 TF1 GPIO1 Large LCD (connector) VDDIOP0
PD15 RF1 GPIO2 Large LCD (connector) VDDIOP0
PD16 RTS1 USART1 Request to Send VDDIOP0
PD17 CTS1 USART1 Clear To Send VDDIOP0
PD18 SPI1_NPCS2 IRQ VDDIOP0
PD19 SPI1_NPCS3 FIQ VDDIOP0
PD20 TIOA0 TSAD0 Touch screen X_Right VDDANA
PD21 TIOA1 TSAD1 Touch screen X_Left VDDANA
PD22 TIOA2 TSAD2 Touch screen Y_Up VDDANA
PD23 TCLK0 TSAD3 Touch screen Y_Down VDDANA
PD24 SPI0_NPCS1 PWM0 GPAD4 General purpose A/D4 VDDANA
PD25 SPI0_NPCS2 PWM1 GPAD5 General purpose A/D5 VDDANA
PD26 PCK0 PWM2 GPAD6 General purpose A/D6 VDDIOP0
PD27 PCK1 SPI0_NPCS3 GPAD7 General purpose A/D7 VDDIOP0
PD28 TSADTRG SPI1_NPCS1 USB Plug-ID IDUSB VDDIOP0
PD29 TCLK1 SCK1 MCI1_WP VDDIOP0
PD30 TIOB0 SCK2 Command Power Led VDDIOP0
PD31 TIOB1 PWM1 Command LED1 VDDIOP0
AT91SAM9M10-G45-EK User Guide 5-7
6495B–ATARM–21-Apr-10
Configuration
5.5.6 Multiplexing on PIO Controller E (PIOE)
Table 5-8. PIO Multiplexing Port E
I/O Peripheral A Peripheral B Function and Comments Power
PE0 LCDPWR PCK0 LCD Panel Pow.Enab.Ctrl VDDIOP1
PE1 LCDMOD LCD Modulation Signal VDDIOP1
PE2 LCDCC LCD Contrast Control VDDIOP1
PE3 LCDVSYNC LCD Vertical Synch. VDDIOP1
PE4 LCDHSYNC LCD Horizontal Synch. VDDIOP1
PE5 LCDDOTCK LCD Dot Clock VDDIOP1
PE6 LCDDEN LCD Data Enable VDDIOP1
PE7 LCDD0 LCDD2 LCD-Red0 VDDIOP1
PE8 LCDD1 LCDD3 LCD-Red1 VDDIOP1
PE9 LCDD2 LCDD4 LCD-Red2 VDDIOP1
PE10 LCDD3 LCDD5 LCD-Red3 VDDIOP1
PE11 LCDD4 LCDD6 LCD-Red4 VDDIOP1
PE12 LCDD5 LCDD7 LCD-Red5 VDDIOP1
PE13 LCDD6 LCDD10 LCD-Red6 VDDIOP1
PE14 LCDD7 LCDD11 LCD-Red7 VDDIOP1
PE15 LCDD8 LCDD12 LCD-Green0 VDDIOP1
PE16 LCDD9 LCDD13 LCD-Green1 VDDIOP1
PE17 LCDD10 LCDD14 LCD-Green2 VDDIOP1
PE18 LCDD11 LCDD15 LCD-Green3 VDDIOP1
PE19 LCDD12 LCDD18 LCD-Green4 VDDIOP1
PE20 LCDD13 LCDD19 LCD-Green5 VDDIOP1
PE21 LCDD14 LCDD20 LCD-Green6 VDDIOP1
PE22 LCDD15 LCDD21 LCD-Green7 VDDIOP1
PE23 LCDD16 LCDD22 LCD-Blue0 VDDIOP1
PE24 LCDD17 LCDD23 LCD-Blue1 VDDIOP1
PE25 LCDD18 LCD-Blue2 VDDIOP1
PE26 LCDD19 LCD-Blue3 VDDIOP1
PE27 LCDD20 LCD-Blue4 VDDIOP1
PE28 LCDD21 LCD-Blue5 VDDIOP1
PE29 LCDD22 LCD-Blue6 VDDIOP1
PE30 LCDD23 LCD-Blue7 VDDIOP1
PE31 PWM2 PCK1 AC97 External Clock VDDIOP1
5-8 AT91SAM9M10-G45-EK User Guide
6495B–ATARM–21-Apr-10
Section 6
Connectors
6.1 Power Supply
The SAM9M10-G45-EK evaluation board can be powered from a DC 5V power supply via the external power supply jack (J2) shown in Figure 6-1. The positive pole must be on J2 center pin.
Figure 6-1. Power Supply Connector J2
6.2 RS232 Connector with RTS/CTS Handshake Support
Connector J11 is the COM1 connector.
Figure 6-2. RS232 COM1 Connector J11
Table 6-1. Power Supply Connector J2 Signal Description
Pin Mnemonic Signal description
1 Center +5 VCC
2 Gnd
AT91SAM9M10-G45-EK User Guide 6-1
6495B–ATARM–21-Apr-10
Connectors
6.3 DBGU
Connector J10 is the DBGU connector.
Figure 6-3. RS232 DBGU Connector J10
Table 6-2. Serial COM1 Connector J11 Signal Descriptions
Pin Mnemonic Signal description
1, 4, 6, 9 NC NO CONNECTION
2 TXD TRANSMITTED DATA RS232 serial data output signal
3 RXD RECEIVED DATA RS232 serial data input signal
5 GND GROUND
7 RTS READY TO SEND Active-positive RS232 input signal
8 CTS CLEAR TO SEND Active-positive RS232 output signal
Table 6-3. RS232 DBGU Connector J10 Signal Descriptions
Pin Mnemonic Signal description
1, 4, 6, 7, 8, 9 NC NO CONNECTION
2 TXD TRANSMITTED DATA RS232 serial data output signal
3 RXD RECEIVED DATA RS232 serial data input signal
5 GND GROUND
6-2 AT91SAM9M10-G45-EK User Guide
6495B–ATARM–21-Apr-10
Connectors
6.4 Ethernet
Connector J15 is the RJ-45 Ethernet Connector.
Figure 6-4. Ethernet RJ45 Connector J15
6.5 USB Host
Connector J12 is the USB Host connector.
Figure 6-5. USB Host type A connector J12
Table 6-4. Ethernet RJ45 Connector J15 Signal Descriptions
Pin Mnemonic Pin Mnemonic
1 TxData+ DIFFERENTIAL OUTPUT PLUS 2 Txdata- DIFFERENTIAL OUTPUT MINUS
3 RxData+ DIFFERENTIAL INPUT PLUS 4 Shield
5 Shield 6 RxData- DIFFERENTIAL INPUT MINUS
7 Shield 8 Shield
Table 6-5. USB Host Type A Connector J12 Signal Descriptions
Pin Mnemonic Signal description
1 Vbus 5v power
2 DM Data minus
3 DP Data plus
4 Gnd Ground
5 Shield Shield
AT91SAM9M10-G45-EK User Guide 6-3
6495B–ATARM–21-Apr-10
Connectors
6.6 USB Host/Device
Connector J14 is the USB Host/Device connector.
Figure 6-6. USB Host/Device Micro AB connector J14
6.7 JTAG Debugging Connector
Connector J13 is the JTAG/ICE connector.
A SAM-ICE connector is a 20-way Insulation Displacement Connector (IDC) keyed box header (2.54 mm male) that mates with IDC sockets mounted on a ribbon cable.
Figure 6-7. JTAG/ICE Connector J13
Table 6-6. USB Host/Device MicroAB Connector J14 Signal Descriptions
Pin Mnemonic Signal description
1 Vbus 5v power
2 DM Data minus
3 DP Data plus
4 ID On the Go Identification
5 Gnd Ground
6-4 AT91SAM9M10-G45-EK User Guide
6495B–ATARM–21-Apr-10
Connectors
Table 6-7. JTAG/ICE Connector J13 Signal Descriptions
Pin Mnemonic Description
1 VTref. 3.3V power
This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input comparators, and to control the output logic levels to the target. It is normally fed from VDD on the target board and must not have a series resistor.
2 Vsupply. 3.3V powerThis pin is not connected in SAM-ICE. It is reserved for compatibility with other equipment. Connect to VDD or leave open in target system.
3nTRST TARGET RESET - Active-low output signal that resets the target
JTAG Reset. Output from SAM-ICE to the Reset signal on the target JTAG port. Typically connected to nTRST on the target CPU. This pin is normally pulled HIGH on the target to avoid unintentional resets when there is no connection.
4 GND Common ground
5TDI TEST DATA INPUT - Serial data output line, sampled on the rising edge of the TCK signal.
JTAG data input of target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TDI on target CPU.
6 GND Common ground
7 TMS TEST MODE SELECT
JTAG mode set input of target CPU. This pin should be pulled up on the target. Typically connected to TMS on target CPU. Output signal that sequences the target's JTAG state machine, sampled on the rising edge of the TCK signal.
8 GND Common ground
9TCK TEST CLOCK - Output timing signal, for synchronizing test logic and control register access.
JTAG clock signal to target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TCK on target CPU.
10 GND Common ground
11RTCK - Input Return test clock signal from the target.
Some targets must synchronize the JTAG inputs to internal clocks. To assist in meeting this requirement, a returned and retimed TCK can be used to dynamically control the TCK rate. SAM-ICE supports adaptive clocking which waits for TCK changes to be echoed correctly before making further changes. Connect to RTCK if available, otherwise to GND
12 GND Common ground
13TDO JTAG TEST DATA OUTPUT - Serial data input from the target.
JTAG data output from target CPU. Typically connected to TDO on target CPU.
14 GND Common ground
15 nSRST RESET Active-low reset signal. Target CPU reset signal
16 GND Common ground
17 RFU This pin is not connected in SAM-ICE.
18 GND Common ground
19 RFU This pin is not connected in SAM-ICE
20 GND Common ground
AT91SAM9M10-G45-EK User Guide 6-5
6495B–ATARM–21-Apr-10
Connectors
6.8 SD/MMC- MCI0
Connector J6 is the SD/MMC connector.
Figure 6-8. SD/MMC0 Connector J6
Table 6-8. SD/MMC0 Connector J6 Signal Descriptions
Pin Mnemonic Pin Mnemonic
1 RSV/DAT3 2 CDA
3 GND 4 VCC
5 CLK 6 GND
7 DAT0 8 DAT1
9 DAT2 10 Card Detect
11 GND 12
6-6 AT91SAM9M10-G45-EK User Guide
6495B–ATARM–21-Apr-10
Connectors
6.9 SD/MMC- MCI1
Connector J5 is the SD/MMC connector.
Figure 6-9. SD/MMC1 Connector J5
Table 6-9. SD/MMC1 Connector J5 Signal Descriptions
Pin Mnemonic Pin Mnemonic
1 RSV/DAT3 2 CMD
3 GND 4 VCC
5 CLK 6
7 DAT0 8 DAT1
9 DAT2 10 DAT3
11 DAT4 12 DAT5
13 DAT6 14 DAT7
AT91SAM9M10-G45-EK User Guide 6-7
6495B–ATARM–21-Apr-10
Connectors
6.10 AC97
Connector J7 is the Headphone connector.
Connector J8 is the Line In connector.
Connector J9 is the Microphone Input.
Connector JP15 is the Speaker Output connector
Figure 6-10. Audio Connector J7, J8, J9
Table 6-10. J7, J8, J9 Signal Description
Pin Mnemonic
1 Signal
2 Signal
3 Gnd
Table 6-11. Speaker JP15 Signal Descriptions
Pin Mnemonic
1 Speaker bridge output A
2 Speaker bridge output B
6-8 AT91SAM9M10-G45-EK User Guide
6495B–ATARM–21-Apr-10
Connectors
6.11 Image Sensor - ISI
Connector J17 is the ISI connector.
Figure 6-11. ISI Connector J17
Table 6-12. ISI Connector J17 Signal Descriptions
Pin Mnemonic Pin Mnemonic
1 VCC 3v3 2 Gnd
3 VCC 3v3 4 Gnd
5 Ctrl1 6 Ctrl2
7 SCL 8 SDA
9 Gnd 10 ISI_MCK
11 Gnd 12 ISI_VSYNC
13 Gnd 14 ISI_HSYNC
15 Gnd 16 ISI_PCK
17 Gnd 18 ISI_Data0
19 ISI_Data1 20 ISI_Data2
21 ISI_Data3 22 ISI_Data4
23 ISI_Data5 24 ISI_Data6
25 ISI_Data7 26 ISI_Data8
27 ISI_Data9 28 ISI_Data10
29 ISI_Data11 30 Gnd
AT91SAM9M10-G45-EK User Guide 6-9
6495B–ATARM–21-Apr-10
Connectors
6.12 Video
Connector J20 is the Video connector
Figure 6-12. Video Connector J20
6.13 Display Devices
6.13.1 TFT LCD
Connector J24 is the TFT-LCD connector.
Figure 6-13. TFT LCD Connector J24
Table 6-13. Video Connector J20 Signal Description
Pin Mnemonic Signal description
1 Center Composite video signal output
Table 6-14. TFT LCD Connector J24 Signal Descriptions
Pin Mnemonic Pin Mnemonic
1 VLED- 2 VLED+
3 GND 4 VDD 3V3
5 R0 6 R1
7 R2 8 R3
9 R4 10 R5
6-10 AT91SAM9M10-G45-EK User Guide
6495B–ATARM–21-Apr-10
Connectors
6.14 LCD Extension
Connectors J23 and J18 are for an optional LCD extension (not populated).
11 R6 12 R7
13 G0 14 G1
15 G2 16 G3
17 G4 18 G5
19 G6 20 G7
21 B0 14 B1
23 B2 16 B3
25 B4 18 B5
27 B6 20 B7
29 GND 30 DCLK
31 DISPON 32 HSYNC
33 VSYNC 34 LCDEN
35 NO CONNECT 36 GND
37 X2 38 Y1
39 X1 40 Y2
Table 6-14. TFT LCD Connector J24 Signal Descriptions
Pin Mnemonic Pin Mnemonic
Table 6-15. Connector J23 Signal Description for an LCD Extension
Pin Mnemonic Pin Mnemonic
1 PE8 RED Data Signal 2 PE7 RED Data Signal (LSB)
3 PE10 RED Data Signal 4 PE9 RED Data Signal
5 PE12 RED Data Signal 6 PE11 RED Data Signal
7 PE14 RED Data Signal (MSB) 8 PE13 RED Data Signal
9 PE16 GREEN Data Signal 10 PE15 GREEN Data Signal (LSB
11 PE18 GREEN Data Signal 12 PE17 GREEN Data Signal
13 PE20 GREEN Data Signal 14 PE19 GREEN Data Signal
15 PE22 GREEN Data Signal (MSB) 16 PE21 GREEN Data Signal
17 PE24 BLUE Data Signal 18 PE23 BLUE Data Signal (LSB)
19 PE26 BLUE Data Signal 20 PE25 BLUE Data Signal
21 PE28 BLUE Data Signal 22 PE27 BLUE Data Signal
23 PE30 BLUE Data Signal (MSB) 24 PE29 BLUE Data Signal
25 PE4 LCDHSYNC 26 PE3 LCDVSYNC
27 PE5 LCDDOTCK 28 GND (0V)
29 GND (0V) 30 NC
AT91SAM9M10-G45-EK User Guide 6-11
6495B–ATARM–21-Apr-10
Connectors
31 PE6 LCDDEN 32 PE2 LCDCC
33 PE0 DISPON 34 PE1 LCDMOD
35 PD14 GPIO1 36 PD15 GPIO2
37 GND (0V) 38 GND (0V)
39 VCC +3V3 power source 40 NC
Table 6-16. Connector J18 Signal Description for an LCD Extension
Pin Mnemonic Pin Mnemonic
1 XM AD1XM 2 XP AD0XP
3 YM AD3YM 4 YP AD2YP
5 GND (0V) 6 GND (0V)
7 PD25 PD25 8 PD24 PD24
9 PD27 PD27 10 PD26 PD26
11 PD19 PD19 12 PD18 PD18
13 GND (0V) 14 GND (0V)
15 GND (0V) 16 +5V
17 GND (0V) 18 GND (0V)
19 VCC +3V3 power source 20 VCC +3V3 power source
Table 6-15. Connector J23 Signal Description for an LCD Extension
Pin Mnemonic Pin Mnemonic
6-12 AT91SAM9M10-G45-EK User Guide
6495B–ATARM–21-Apr-10
Section 7
Schematics
7.1 Schematics
This section contains the following schematics:
Top Level view, block architecture of the design
Power Supply
SAM Processor
Bus impedance adaptor
Main memory
EBI memory
MCI & TWI
Audio AC97
Serial interfaces
Ethernet
LCD
Video interfaces and LCD extension
AT91SAM9M10-G45-EK User Guide 7-1
6495B–ATARM–21-Apr-10
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FLA
SHN
AN
DFL
ASH
5 V
DBGU
USB
COM1RS2
32
SERIALDATAFLASH
10/100 FAST ETHERNET
HOSTDEVICE
HOST
EBI0
MM
C S
DS
DIO
CARDREADER
US
ER
INTE
RFA
CE
EBI1
ISI
LCD INTERFACE4.3" 480x272TFT
CAMERA INTERFACE
TOUCH SCREEN
TV INTERFACE
DD
R2
128M
B
SERIALEEPROM
DD
R2
128M
B
PIOCONNECTOR
ICEINTERFACE
MIC
OU
TIN
AUDIO
POWER SUPPLY
"DNP" means the component is not populated by defaultNOTE
RJ
45H
E 10
HE
14
CARDREADER
MM
C S
DS
DIO
HE
14
EBI0 DDR2 INTERFACE
ATMEL ARM9 Processor SAM9M10 (LFBGA324)
Sheet 4
EBI0 DDR2 INTERFACE
EBI1 DATA INTERFACE
EBI1 DDR2 INTERFACE
EBI1 FLASH INTERFACE
EBI1 NANDFLASH INTERFACE
EBI1 ADDRESS INTERFACE
RES.ARRAYSEBI0_EBI1 ADAPTER
PIO
PIO
PIO
PIO A,...E
Sheet 2
Sheet 3
Sheet 5
Sheet 6
Sheet 7
Sheet 8
Sheet 9
Sheet 10
Sheet 11 12
EBI1 BUS INTERFACE
POWER
3V3
1V8
1V
PIO
PIO A,...E
RC
A
NOT USEDNOT USED
NOT USEDNOT USED
NOT USEDNOT USEDNOT USEDNOT USEDNOT USED
NOT USED
NOT USEDNOT USEDNOT USEDNOT USEDNOT USEDNOT USEDNOT USEDNOT USEDNOT USEDNOT USEDNOT USEDNOT USEDNOT USEDNOT USEDNOT USEDNOT USED
J18 12J18 11
J18_8J18_7J18_10J18_9
PIOB USAGEPB0PB1PB2PB3PB4PB5PB6PB7PB8PB9PB10PB11PB12PB13PB14PB15
PIOB USAGEPB16PB17PB18PB19PB20PB21PB22PB23PB24PB25PB26PB27PB28PB29PB30PB31
SPI0_MISOSPI0_MOSISPI0_SPCK
TXD1SPI0_NPCS0
RXD1BP5_LEFT
ISI_D8BP4_RIGHT
ISI_D9ISI_D10ISI_D11DRXDDTXDBP3_LEFTBP3_RIGHT
BP3_UPBP3_DOWNBP3_PUSH
ISI_D0ISI_D1ISI_D2ISI_D3ISI_D4ISI_D5ISI_D6ISI_D7ISI_PCKISI_VSYNCISI_HSYNCISI_MCK
VBUS
PIOA USAGEPA0PA1PA2PA3PA4PA5PA6PA7PA8PA9PA10PA11PA12PA13PA14PA15
PIOA USAGEPA16PA17PA18PA19PA20PA21PA22PA23PA24PA25PA26PA27PA28PA29PA30PA31
MCI0_CKMCI0_CDAMCI0_DA0
(MCI0_DA2)MCI0_DA1
(MCI0_DA3)TXD2
RXD2TXD3
RXD3TXD0TXD1RXD0RXD1TX_ENRX_DV
RX_ERTX_CLKMDC
TWDOTWCK0MCI1_CDAMCI1_DA0MCI1_DA1MCI1_DA2MCI1_DA3MCI1_DA4/TX_ERMCI1_DA5/RX_CLKMCI1_DA6/CRSMCI1_DA7/COLMCI1_CK
MDIO
PIO MUXINGPIOE USAGEPE0PE1PE2PE3PE4PE5PE6PE7PE8PE9PE10PE11PE12PE13PE14PE15
PIOE USAGEPE16PE17PE18PE19PE20PE21PE22PE23PE24PE25PE26PE27PE28PE29PE30PE31
LCDPWRLCDMODLCDCC
LCDHSYNCLCDVSYNC
LCDDOTCKLCDDEN
R1R0
R2R3R4R5R6R7G0
G1G2G3
G5G6G7B0B1B2B3B4B5B6B7EXT_CLK
G4
PIOD USAGEPD0PD1PD2PD3PD4PD5PD6PD7PD8PD9PD10PD11PD12PD13PD14PD15
PIOD USAGEPD16PD17PD18PD19PD20PD21PD22PD23PD24PD25PD26PD27PD28PD29PD30PD31
USER LED D6ENAFLGA
FLGBENB
MDINTRAC97RX
AC97FSAC97TX
AC97CKMCI0_CD(MCI1_CD)CTRL1CTRL2GPIO1GPIO2
RTS1CTS1
AD0XpAD1XmAD2YpAD3Ym
IDUSB(MCI1_WP)POWER_LEDUSER LED D7
PIOC USAGEPC0PC1PC2PC3PC4PC5PC6PC7PC8PC9PC10PC11PC12PC13PC14PC15
PIOC USAGEPC16PC17PC18PC19PC20PC21PC22PC23PC24PC25PC26PC27PC28PC29PC30PC31
A19
NANDALE/A21A20
NANDCLE
RDY/BSY
NCS3
REV DATEMODIF. DES. DATE VER.
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REV DATEMODIF. DES. DATE VER.
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8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FORCEPOWERON
VOUT = 0.8V x (Rtop + Rbottom)/Rbottom
VOUT = 0.8V x (Rtop + Rbottom)/Rbottom
VOUT = 0.8V x (Rtop + Rbottom)/Rbottom
REGULATED5V ONLY
VOUT = 0.8V x (Rtop + Rbottom)/Rbottom
POWER LED
RIGHT CLICK
WAKE UP
NRST
GND TEST POINT
ADHESIVE FEET
LEFT CLICK
USER INTERFACE
UPRIGHTDOWNPUSH
LEFT
PWR_EN
1V_VDDUTMIC
VDDBU
PB17
PB18PB14
PB15PB16
5V
3V3
1V
1V
5V
1V8
1V8
5V
3V3
3V3
5V
3V3
3V3
1V
1V8
3V3
3V33V3
1V_VDDUTMIC
3V3
VDDUTMII {3}
VDDANA {3}
VDDOSC {3}
VDDIOP0 {3}
VDDIOP1 {3}
VDDIOP2 {3,12}
VDDISI {3,12}
VDDUTMIC {3}
VDDPLLUTMI {3}
VDDPLLA {3}
VDDCORE {3}
VDDIOM0 {3}
VDDIOM1 {3}
VDDBU {3}
SHDN{3}
PD0 {3}
PD31 {3}
NRST {3,7,8,9,10,12}
WAKE UP {3}
PB7 {3}
PB6 {3}
PD30 {3}
PB[14..18]{3}REV DATEMODIF. DES. DATE VER.
SCALE 1/1 REV. SHEET
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11-FEB-10Derek PP
POWER SUPPLY
05-Feb-1008-apr-10PPA2
REV DATEMODIF. DES. DATE VER.
SCALE 1/1 REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
A
AT91SAM9M10-G45-EK212A2
11-FEB-10Derek PP
POWER SUPPLY
05-Feb-1008-apr-10PPA2
REV DATEMODIF. DES. DATE VER.
SCALE 1/1 REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
A
AT91SAM9M10-G45-EK212A2
11-FEB-10Derek PP
POWER SUPPLY
05-Feb-1008-apr-10PPA2
MN4RT9018AMN4RT9018A
PGOOD1
EN2
VIN3
VDD4
NC5VOUT6ADJ7GND8
EP
9
J3J3
JP3JP31
2
3
C910uC910u
C1210uC1210u
C294.7uC294.7u
J1-1J1-11 2
TP3TP3BP5BP5
C24.7uC24.7u
R9100kR9100k
C3610n
C3610n
R1812kR1812k
C111uC111u
JP1JP11
2
3
C261uC261u
D2
Green
D2
Green
1 2
R11100kR11100k
C2310uC2310u
C3410n
C3410n
R1610kR1610k
C3 10nC3 10n
C144.7uC144.7u
R201RR201R
MN1RT9186AMN1RT9186A
VIN1
VIN2
PGOOD3
EN4
GND5ADJ6VOUT7VOUT8
EP
9
R2100kR2100k
R28100RR28100R
C221uC221u
TP1TP1
JP2JP21
2
3
R22 470RR22 470R
C16 10nC16 10n
Z3
Bumpon
Z3
Bumpon
C510nC510n
C1100nC1100n
J1-3J1-35 6
Z2
Bumpon
Z2
Bumpon
R25
470R
R25
470R
R13
100k
R13
100k
+C433u
+C433u
C37
10n
C37
10n
R10100kR10100k
C152.2uC152.2u
R121RR121R
JP7JP71
2
3
R4 47kR4 47k R612kR612k
D1Green
D1Green
1 2
C18100nC18100n
C17
15p
C17
15p
JP6JP61
2
3
R241kR241k
C251uC251u
Q2IRLML2402
Q2IRLML2402 1
3
2
C204.7uC204.7u
BP2BP2
R15 15kR15 15k
D3RedD3Red
12
C71uC71u
TP2TP2
MN3RT9186AMN3RT9186A
VIN1
VIN2
PGOOD3
EN4
GND5ADJ6VOUT7VOUT8
EP
9
R715kR715k
C30100nC30100n
JP4
SIP2
JP4
SIP2
12
C3310n
C3310n
Z5
Bumpon
Z5
Bumpon
CR15VCR15V
JP5JP51
2
3
BP3
JoyStick
BP3
JoyStick
123
456
C28100nC28100n
R29
100R
R29
100R
MN2RT9018AMN2RT9018A
PGOOD1
EN2
VIN3
VDD4
NC5VOUT6ADJ7GND8
EP
9
C3210n
C3210n
Q1Si1563EDH
Q1Si1563EDH
1 32
456
L4 10uHL4 10uH
R51RR51R
J1-2J1-23 4
C3510n
C3510n
TP4TP4
C610uC610u
R23100kR23100k
R199
100k
R199
100k
C2110uC2110u
BP4BP4R26100kR26100k
C19
10n
C19
10n
L3 10uHL3 10uH
J2
DC POWER JACK
J2
DC POWER JACK
1
23
L1 10uHL1 10uH
R27
100R
R27
100R
R847kR847k
C131uC131u
R1710kR1710k
R1947kR1947k
BP1BP1
C2710uC2710u
R1412kR1412k
Z6
Bumpon
Z6
Bumpon
C101uC101u
C241uC241u
C8100nC8100n
J1-4J1-47 8
C31
10n
C31
10n
L2 10uHL2 10uH
R11RR11R
Z4
Bumpon
Z4
Bumpon
R3100kR3100k
R21 470RR21 470R
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BOOT MODE SELECTOpenedClosed NCS0=
Internal ROM BOOT=
PA6
PA1
PA8
PA29
PA14
PA4
PA13
PA26
PA11
PA25
PA2
PA30
PA27
PB5
PB10
PB7
PB19
PB16
PB21
PB17
PB15
PB0
PB18
PB24
PB20
PB23PB22
PB28
PB9
PB31
PB12
PB6
PB1
PB8
PB29
PB14
PB4
PB13
PB26
PB11
PB25
PB2
PB30
PB27
PC5
PC3
PC8
PC14
PC4
PC2PA5
PA10
PA7
PA3
PA19
PA16
PA21
PA17
PA15
PA0
PA18
PA24
PA20
PA23PA22
PA28
PA9
PA31
PA12
PE10
PE7
PE3
PE19
PE16
PE21
PE17
PE15
PE0
PE18
PE24
PE20
PE23PE22
PE28
PE9
PE31
PE12
PE6
PE1
PE8
PE29
PE14
PE4
PE13
PE26
PE11
PE25
PE2
PE30
PE27
PD5
PD10
PD7
PD3
PD19
PD16
PD21
PD17
PD15
PD0
PD18
PD24
PD20
PD23PD22
PD28
PD9
PD31
PD12
PD6
PD1
PD8
PD29
PD14
PD4
PD13
PD26
PD11
PD25
PD2
PD30
PD27
EBI1_A5
EBI1_A10
EBI1_A7
EBI1_A3
EBI1_A15
EBI1_A0
EBI1_A9
EBI1_A12
EBI1_A6
EBI1_A1
EBI1_A8
EBI1_A14
EBI1_A4
EBI1_A13
EBI1_A11
EBI1_A2
EBI1_A16EBI1_A17EBI1_A18
EBI1_D5
EBI1_D10
EBI1_D7
EBI1_D3
EBI1_D15
EBI1_D0
EBI1_D9
EBI1_D12
EBI1_D6
EBI1_D1
EBI1_D8
EBI1_D14
EBI1_D4
EBI1_D13
EBI1_D11
EBI1_D2
TDI
RTCKTDO
TMS
NTRST
PB3
VDDBU
NRST
EBI0_D0EBI0_D1EBI0_D2
EBI0_D5
EBI0_D3EBI0_D4
EBI0_D8
EBI0_D11EBI0_D10EBI0_D9
EBI0_D6EBI0_D7
EBI0_D14EBI0_D15
EBI0_D12EBI0_D13
EBI0_A2
EBI0_A5EBI0_A4EBI0_A3
EBI0_A10EBI0_A11
EBI0_A8EBI0_A7EBI0_A6
EBI0_A9
EBI0_A12EBI0_A13
EBI0_A0EBI0_A1
TCK
EBI1_A0
PE5
3V3
PA[0..31]{7,10,12}
PC[2..5]{4,6}
EBI0_D[0..15]{4}
EBI0_A[0..13]{4}
EBI1_A[1..18] {4}
EBI1_D[0..15] {4}
PB[0..31] {2,7,9,12}
EBI0_BA0{4}EBI0_BA1{4}
EBI0_CKE{4}EBI0_CLK{4}EBI0_NCLK{4}
EBI0_CS{4}
EBI0_CAS{4}EBI0_RAS{4}
EBI0_WE{4}
EBI0_DQM0{4}EBI0_DQM1{4}
EBI0_DQS0{4}EBI0_DQS1{4}
EBI1_DQM0 {4}EBI1_DQM1 {4}EBI1_DQS0 {4}EBI1_DQS1 {4}
EBI1_RAS {4}EBI1_CAS {4}EBI1_SDWE {4}EBI1_SDA10 {4}EBI1_SDCKE {4}
EBI1_SDCK {4}EBI1_NSDCK {4}
EBI1_NCS0 {6}EBI1_NCS1/SDCS {4}
EBI1_NRD/CFOE {6}EBI1_NWE/NWR0/CFWE {6}
EBI1_NANDOE {6}EBI1_NANDWE {6}
DDR_VREF{5,6}
NTRST{9}TDI{9}TMS{9}TCK{9}RTCK{9}TDO{9}NRST{2,7,8,9,10,12}
WAKE UP{2}
SHDN{2}
HDPA{9}HDMA{9}
HDPB{9}HDMB{9}
VDDOSC{2}
PC8{6}
PC14{6}
PE[0..31]{8,11,12}
PD[0..31] {2,7,8,9,10,11,12}
VDDBU {2}
VDDPLLUTMI {2}
VDDUTMIC {2}
VDDUTMII {2}
VDDIOP0 {2}
VDDIOP1 {2}
VDDIOP2 {2,12}
VDDCORE {2}
VDDIOM0 {2}
VDDIOM1 {2}
VDDPLLA {2}
VDDANA {2}
REV DATEMODIF. DES. DATE VER.
SCALE 1/1 REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
A
AT91SAM9M10-G45-EK312A2
11-FEB-10Derek PP
AT91SAM9M10 chip
05-Feb-1008-apr-10PPA2
REV DATEMODIF. DES. DATE VER.
SCALE 1/1 REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
A
AT91SAM9M10-G45-EK312A2
11-FEB-10Derek PP
AT91SAM9M10 chip
05-Feb-1008-apr-10PPA2
REV DATEMODIF. DES. DATE VER.
SCALE 1/1 REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
A
AT91SAM9M10-G45-EK312A2
11-FEB-10Derek PP
AT91SAM9M10 chip
05-Feb-1008-apr-10PPA2
R37
6.8k
R37
6.8k
R33 39RR33 39RR32 39RR32 39R
MN5GMN5G
EBI0_DDR_D0R16
EBI0_DDR_D1R15
EBI0_DDR_D2T14
EBI0_DDR_D3P15
EBI0_DDR_D4P16
EBI0_DDR_D5P17
EBI0_DDR_D6R14
EBI0_DDR_D7P14
EBI0_DDR_D8N15
EBI0_DDR_D9N16
EBI0_DDR_D10P18
EBI0_DDR_D11N17
EBI0_DDR_D12N18
EBI0_DDR_D13N14
EBI0_DDR_D14M15
EBI0_DDR_D15M16
EBI0_DDR_A0M17
EBI0_DDR_A1L14
EBI0_DDR_A2M18
EBI0_DDR_A3L15
EBI0_DDR_A4L16
EBI0_DDR_A5L18
EBI0_DDR_A6L17
EBI0_DDR_A7K14
EBI0_DDR_A8K15
EBI0_DDR_A9K16
EBI0_DDR_A10K18
EBI0_DDR_A11K17
EBI0_DDR_A12J14
EBI0_DDR_A13J15
EBI0_DDR_VREFA16
EBI0_DDR_DQM0G14
EBI0_DDR_DQM1H16
EBI0_DDR_DQS0G18
EBI0_DDR_DQS1G15
EBI0_DDR_CSH14
EBI0_DDR_CLKJ18
EBI0_DDR_NCLKH18
EBI0_DDR_CKEJ16
EBI0_DDR_RASJ17 EBI0_DDR_CASH17
EBI0_DDR_WEH15
EBI0_DDR_BA0G17
EBI0_DDR_BA1G16
R31 39RR31 39R
C50 22pC50 22p
C40100nC40100n
MN5EMN5E
PE0/LCDPWR/PCK0G4
PE1/LCDMODF4
PE2/LCDCCG5
PE3/LCDVSYNCF5
PE4/LCDHSYNCG7
PE5/LCDDOTCKH5
PE6/LCDDENG3
PE7/LCDD0/LCDD2H6
PE8/LCDD1/LCDD3G6
PE9/LCDD2/LCDD4H7
PE10/LCDD3/LCDD5H8
PE11/LCDD4/LCDD6G8
PE12/LCDD5/LCDD7J5
PE13/LCDD6/LCDD10H4
PE14/LCDD7/LCDD11J3
PE15/LCDD8/LCDD12J4
PE16/LCDD9/LCDD13J2
PE17/LCDD10/LCDD14J6
PE18/LCDD11/LCDD15J7
PE19/LCDD12/LCDD18J1
PE20/LCDD13/LCDD19J8
PE21/LCDD14/LCDD20K1
PE22/LCDD15/LCDD21K4
PE23/LCDD16/LCDD22K2
PE24/LCDD17/LCDD23K5
PE25/LCDD18K6
PE26/LCDD19K3
PE27/LCDD20K7
PE28/LCDD21K8
PE29/LCDD22L3
PE30/LCDD23L2
PE31/PWM2/PCK1L4
C65
100n
C65
100n
C60 100nC60 100n
MN5CMN5C
PC0/DQM2A8
PC1/DQM3E9
PC2/A19B8
PC3/A20C8
PC4/A21/NANDALEF9
PC5/A22/NANDCLEA7
PC6/A23D8
PC7/A24A6
PC8/CFCE1E8
PC9/CFCE2/RTS2C7
PC10/NCS4/CFCS0/TCLK2B6
PC11/NCS5/CFCS1/CTS2B7
PC12/A25/CFRNWA5
PC13/NCS2D7
PC14/NCS3/NANDCSF8
PC15/NWAITC6
PC16/D16E7
PC17/D17B5
PC18/D18D6
PC19/D19F7
PC20/D20A4
PC21/D21C5
PC22/D22B4
PC23/D23E6
PC24/D24D5
PC25/D25A3
PC26/D26C4
PC27/D27A1
PC28/D28A2
PC29/D29B2
PC30/D30B3
PC31/D31B1
C64
100n
C64
100n
MN5DMN5D
PD0/TK0/PWM3R7
PD1/TF0T7
PD2/TD0L8
PD3/RD0V6
PD4/RK0M8
PD5/RF0V7
PD6/AC97RXN8
PD7/AC97TX/TIOA5U7
PD8/AC97FS/TIOB5P8
PD9/97CK/TCLK5R8
PD10/TD1U8
PD11/RD1T8
PD12/TK1/PCK0V8
PD13/RK1L9
PD14/TF1U9
PD15/RF1M9
PD16/RTS1N9
PD17/CTS1V9
PD18/SPI1_NPCS2/IRQR9
PD19/SPI0_NPCS3/FIQT9
PD20/TIOA0D2
PD21/TIOA1E1
PD22/TIOA2F1
PD23/TCLK0G2
PD24/SPI0_NPCS1/PWM0F2
PD25/SPI0_NPCS2/PWM1G1
PD26/PCK0/PWM2H1
PD27/PCK1/SPI0_NPCS3H2
PD28/TSADTRG/SPI1_NPCS1P9
PD29/TCLK1/SCK1L10
PD30/TIOB0/SCK2T10
PD31/TIOB1/PWM1L11
C38 100nC38 100n
R394.7kR394.7k
C59 100nC59 100n
C42 100nC42 100n
R30 39RR30 39R
C43 100nC43 100nC44100nC44100n
MN5HMN5H
NTRSTN10
TDIR10
TMSP10
TCKU10
RTCKR11
TDOV10
JTAGSELE4
NRSTM10
WK
UP
C3
SHDNF3
VDDBUD4
GNDBUD3
GN
DC
OR
EJ1
0
GN
DC
OR
EG
9
HHSDMAR17 HHSDPAT17
HFSDMAR18 HFSDPAT18
DFSDP/HFSDPBV15
VB
GV
18
VDDOSCU11
VDDPLLAP11
DFSDM/HFSDMBV16
XOUTV11
XINV12
XOUT32D1
XIN32C1
VDDCOREE18
VDDCOREH11VDDCOREG13
VDDIOM0M14VDDIOM0L13VDDIOM0L12VDDIOM0K13
VDDIOM1G11VDDIOM1G10VDDIOM1F6VDDIOM1D16
VDDIOP0K10VDDIOP0K9
VDDIOP1H3
GN
DC
OR
EH
9
GN
DC
OR
EJ9
GN
DIO
MC
16
GN
DIO
MH
12
GN
DIO
MH
13
GN
DIO
MJ1
2
GN
DIO
MJ1
3
GN
DIO
MK
11
GN
DIO
MK
12
GN
DIO
PJ1
1G
ND
IOP
H10
TST
E5
DHSDP/HHSDPBU15
BM
ST1
1
DHSDM/HHSDMBU16
TSADVREFE2
VDDANAE3
GNDANAC2
VDDCOREG12
VDDIOP2V14
GNDOSCU12
VDDPLLUTMIV13
GNDUTMIU17
VDDUTMICU18
VDDUTMIIV17
C62 100nC62 100n
Y1
12MHz
Y1
12MHz13
2 4
SUP1
SG-BGA-CA89405MF
DNPSUP1
SG-BGA-CA89405MF
DNP
C66
10p
C66
10p
C56 100nC56 100n
C63 100nC63 100n
C48 100nC48 100n
C39 100nC39 100n
TP5
TP pad
TP5
TP pad
MN5FMN5F
EBI1_D0A17
EBI1_D1D15
EBI1_D2C15
EBI1_D3B16
EBI1_D4B15
EBI1_D5D14
EBI1_D6C14
EBI1_D7A15
EBI1_D8B14
EBI1_D9D13
EBI1_D10C13
EBI1_D11E13
EBI1_D12B13
EBI1_D13E12
EBI1_D14D12
EBI1_D15C12
EBI1_NBS0/A0F13
EBI1_NBS2/NWR2/A1F14
EBI1_A2F18
EBI1_A3F15
EBI1_A4E14
EBI1_A5F17
EBI1_A6F16
EBI1_A7E17
EBI1_A8E15
EBI1_A9E16
EBI1_A10D18
EBI1_A11D17
EBI1_A12C18
EBI1_A13B18
EBI1_A14A18
EBI1_A15B17
EBI1_BA0/A16C10
EBI1_BA1/A17B10
EBI1_A18C17
EBI1_DQM0B11
EBI1_DQM1D11
EBI1_DQS0A11
EBI1_DQS1E11
EBI1_RASA12
EBI1_CASC11
EBI1_SDWEF12
EBI1_SDA10B9
EBI1_SDCKEB12
EBI1_SDCKA13
EBI1_NCS0A10
EBI1_NCS1/SDCSF10
EBI1_NRD/CFOEF11
EBI1_NWE/NWR0/CFWEC9
EBI1_NBS1/NWR1/CFIORD9
EBI1_NBS3/NWR3/CFIOWA9
EBI1_NANDOED10
EBI1_NANDWEE10
EBI1_NSDCKA14
C54 100nC54 100n
C52 100nC52 100n
R38
10k
R38
10k
C53 15pC53 15p
C57 15pC57 15p
R360RR360R
C61 100nC61 100n
C49 100nC49 100nC51 100nC51 100n
C46 22pC46 22p
C41 100nC41 100n
MN5BMN5B
PB0/SPI0_MISOT4
PB1/SPI0_MOSIV2
PB2/SPI0_SPCKV3
PB3/SPI0_NPCS0U4
PB4/TXD1R5
PB5/RXD1V4
PB6/TXD2T5
PB7/RXD2U5
PB8/TXD3/ISI_D8T12
PB9/RXD3/ISI_D9N11
PB10/TWD1/ISI_D10U13
PB11/TWCK1/ISI_D11M11
PB12/DRXDP6
PB13/DTXDR6
PB14/SPI1_MISOM7
PB15/SPI1_MOSI/CTS0V5
PB16/SPI1_SPCK/SCK0T6
PB17/SPI1_NPCS0/RTS0U6
PB18/RXD0/SPI0_NPCS1N7
PB19/TXD0/SPI0_NPCS2P7
PB20/ISI_D0P12
PB21/ISI_D1T15
PB22/ISI_D2R12
PB23/ISI_D3T16
PB24/ISI_D4N12
PB25/ISI_D5M12
PB26/ISI_D6U14
PB27/ISI_D7M13
PB28/ISI_D8N13
PB29/ISI_VSYNCR13
PB30/ISI_HSYNCT13
PB31/ISI_MCK/PCK1P13
C55 100nC55 100n
R35
0R
R35
0R
C45 100nC45 100n
R34 0RDNP
R34 0RDNP
Y232.768KHzY232.768KHz
MN5AMN5A
PA0/MCI0_CK/TCLK3L1
PA1/MCI0_CDA/TIOA3M1
PA2/MCI0_DA0/TIOB3L5
PA3/MCI0_DA1/TCKL4N1
PA4/MCI0_DA2/TIOA4L6
PA5/MCI0_DA3/TIOB4M2
PA6/MCI0_DA4/ETX2M3
PA7/MCI0_DA5/ETX3M4
PA8/MCI0_DA6/ERX2L7
PA9/MCI0_DA7/ERX3N2
PA10/ETX0M5
PA11/ETX1P1
PA12/ERX0N3
PA13/ERX1P2
PA14/ETXENM6
PA15/ERXDVN4
PA16/ERXERN5
PA17/ETXCKN6
PA18/EMDCR1
PA19/EMDIOP3
PA20/TWD0R2
PA21/TWCK0P4
PA22/MCI1_CDA/SCK3T1
PA23/MCI1_DA0/RTS3P5
PA24/MCI1_DA1/CTS3R3
PA25/MCI1_DA2/PWM3T2
PA26/MCI1_DA3/TIOB2T3
PA27/MCI1_DA4/ETXERU1
PA28/MCI1_DA5/ERXCKU3
PA29/MCI1_DA6/ECRSU2
PA30/MCI1_DA7/ECOLR4
PA31/MCI1_CK/PCK0V1
C58 100nC58 100n
JP8
SIP2
JP8
SIP2
12
C47 100nC47 100n
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
(A19)
(A20)
(A21)
(SDA10)
EBI0EBI1
EBI Bus Impedance Adaptor
EBI1_DDR_A3
EBI1_FLASH_A3
EBI1_FLASH_A19
DDR_A3
DDR_A2
DDR_A0
DDR_A1
EBI1_FLASH_A20
EBI1_A15
EBI1_FLASH_A17
EBI1_A7
EBI0_D10
DDR_A7
DDR_A5
DDR_A4
DDR_A6
EBI0_D12
DDR_A11
EBI1_D5
DDR_A9
DDR_A8
DDR_A10
EBI0_D13
EBI1_FLASH_A5
EBI1_DDR_A5
EBI1_DDR_A4
EBI1_FLASH_A4
EBI1_FLASH_D1
EBI1_NAND_FSH_D1
EBI1_FLASH_D0
EBI1_NAND_FSH_D0
EBI1_NAND_FSH_D2
EBI1_FLASH_D2
EBI1_NAND_FSH_D3
EBI1_FLASH_D3
DDR_A13
DDR_A12
EBI1_NAND_FSH_D4
EBI1_FLASH_D5
EBI1_NAND_FSH_D5
EBI1_FLASH_D4
EBI1_FLASH_D6EBI1_FLASH_D6
EBI1_FLASH_A20
EBI1_FLASH_D7
EBI1_NAND_FSH_D6
EBI1_FLASH_D9
EBI1_NAND_FSH_D9
EBI1_FLASH_D8
EBI1_NAND_FSH_D8
EBI1_NAND_FSH_D10
EBI1_FLASH_D10
EBI1_NAND_FSH_D11
EBI1_FLASH_D11
EBI1_FLASH_D13
EBI1_NAND_FSH_D13
EBI1_FLASH_D12
EBI1_NAND_FSH_D12
EBI1_NAND_FSH_D14
EBI1_FLASH_A18
EBI1_FLASH_D14
EBI1_NAND_FSH_D15
EBI1_FLASH_D15
EBI1_FLASH_A21
EBI1_A10
EBI1_DDR_A15
EBI1_A2
EBI1_FLASH_A7
EBI1_DDR_A7
EBI1_FLASH_A9
EBI1_FLASH_A8
EBI1_DDR_A8
EBI1_DDR_A9
EBI1_DDR_A6
EBI1_FLASH_A6
EBI0_D1
EBI1_DDR_D7
SDA10
EBI1_FLASH_A21
EBI0_D7
EBI1_A14
EBI1_D0
EBI1_D1
EBI1_D2
EBI1_D3
EBI1_DDR_D6
EBI0_D2
EBI1_A16
EBI1_A17
EBI1_A18
EBI1_FLASH_A11
EBI1_DDR_A11
EBI1_FLASH_A13
EBI1_FLASH_A12
EBI1_DDR_A12
EBI1_DDR_A13
EBI1_FLASH_A16
EBI1_FLASH_A17
EBI1_FLASH_A15
EBI1_FLASH_A14
EBI1_DDR_A10
EBI1_FLASH_A10
EBI1_A1
EBI0_D3
EBI0_D5
EBI0_D6
EBI0_D4EBI1_DDR_D5
EBI1_DDR_D1
EBI1_DDR_D0
EBI1_DDR_D3
EBI1_DDR_D2
EBI1_A11
EBI0_A6
EBI0_A11
EBI0_A12
EBI0_A7
EBI0_A5
EBI0_A3
EBI0_A13
EBI0_A8
EBI0_A9
EBI0_A0
EBI0_A2
EBI0_A4
EBI0_A10
EBI0_A1
EBI1_A13
EBI0_D15
EBI1_A3
EBI1_A16
EBI1_A17
EBI1_NAND_FSH_D7
EBI1_A8
EBI1_D13
EBI1_D12
EBI1_D15
EBI1_D14
EBI1_D11
EBI1_D7
EBI1_D0
EBI1_D3
EBI1_D10
EBI1_D8
EBI1_D9
EBI1_D4
EBI1_D1
EBI1_D2
EBI1_D6
EBI1_A4
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D7
DDR_D6
DDR_D5
DDR_D4
DDR_D8
DDR_D11
DDR_D10
DDR_D9
DDR_D12
DDR_D15
DDR_D14
DDR_D13
EBI1_DDR_A14
EBI0_D14
EBI1_FLASH_A1EBI1_FLASH_A2EBI1_FLASH_A3EBI1_FLASH_A4EBI1_FLASH_A5
EBI1_FLASH_A7EBI1_FLASH_A6
EBI1_FLASH_A9EBI1_FLASH_A8
EBI1_FLASH_A10EBI1_FLASH_A11
EBI1_FLASH_A13EBI1_FLASH_A12
EBI1_FLASH_A14EBI1_FLASH_A15
EBI1_FLASH_A1
EBI1_D5
EBI1_D4
EBI1_D7
EBI1_D6
EBI1_FLASH_A18
EBI1_DDR_D4
EBI1_A6
EBI1_D9
EBI1_D8
EBI1_D11
EBI1_D10 EBI1_DDR_D10
EBI1_DDR_D11
EBI1_DDR_D8
EBI1_DDR_D9EBI1_DDR_A2
EBI1_FLASH_A2
EBI1_FLASH_A19
EBI1_D13
EBI1_D12
EBI1_D15
EBI1_D14 EBI1_DDR_D14
EBI1_DDR_D15
EBI1_DDR_D12
EBI1_DDR_D13
EBI1_A12
EBI1_FLASH_A16
EBI1_A9
EBI1_A5
EBI0_D11
EBI0_D9
EBI0_D8
EBI1_NAND_FSH_D1EBI1_NAND_FSH_D0
EBI1_NAND_FSH_D2EBI1_NAND_FSH_D3EBI1_NAND_FSH_D4EBI1_NAND_FSH_D5
EBI1_NAND_FSH_D7EBI1_NAND_FSH_D6
SDA10
EBI1_NAND_FSH_D9EBI1_NAND_FSH_D8
EBI1_NAND_FSH_D10
EBI0_D0
EBI1_NAND_FSH_D11
EBI1_NAND_FSH_D13EBI1_NAND_FSH_D12
EBI1_NAND_FSH_D14EBI1_NAND_FSH_D15
EBI0_D[0..15]{3} DDR_D[0..15] {5}
EBI1_D[0..15]{3}
EBI1_DDR_D[0..15] {6}
EBI1_NAND_FSH_D[0..15] {6}
EBI0_A[0..13]{3}
EBI0_CKE{3}
EBI0_CLK{3}
EBI0_NCLK{3}
EBI0_BA0{3}
EBI0_BA1{3}
EBI0_WE{3}
EBI0_CS{3}
EBI0_RAS{3}
EBI0_CAS{3}
EBI0_DQM0{3}
EBI0_DQM1{3}
EBI0_DQS0{3}
EBI0_DQS1{3}
DDR_CKE {5}
DDR_CLK {5}
DDR_NCLK {5}
DDR_BA0 {5}
DDR_BA1 {5}
DDR_WE {5}
DDR_CS {5}
DDR_RAS {5}
DDR_CAS {5}
DDR_DQM0 {5}
DDR_DQM1 {5}
DDR_DQS0 {5}
DDR_DQS1 {5}
CKE_EBI1 {6}
CLK_EBI1 {6}
NCLK_EBI1 {6}
BA0_EBI1 {6}
BA1_EBI1 {6}
CS_EBI1 {6}
WE_EBI1 {6}
RAS_EBI1 {6}
CAS_EBI1 {6}
DQM0_EBI1 {6}
DQM1_EBI1 {6}
DQS0_EBI1 {6}
DQS1_EBI1 {6}
EBI1_FLASH_D[0..15] {6}
DDR_A[0..13] {5}
EBI1_SDCKE{3}
EBI1_SDCK{3}
EBI1_NSDCK{3}
EBI1_NCS1/SDCS{3}
EBI1_SDWE{3}
EBI1_RAS{3}
EBI1_CAS{3}
EBI1_DQM0{3}
EBI1_DQM1{3}
EBI1_DQS0{3}
EBI1_DQS1{3}
EBI1_SDA10{3}
EBI1_FLASH_A[1..21] {6}
EBI1_DDR_A[2..15] {6}
EBI1_A[1..18]{3}
PC2{3}
PC3{3}
PC4{3,6}
REV DATEMODIF. DES. DATE VER.
SCALE 1/1 REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
A
AT91SAM9M10-G45-EK412A2
11-FEB-10Derek PP
RES.ARRAYS-EBI0_EBI1
05-Feb-1008-apr-10PPA2
REV DATEMODIF. DES. DATE VER.
SCALE 1/1 REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
A
AT91SAM9M10-G45-EK412A2
11-FEB-10Derek PP
RES.ARRAYS-EBI0_EBI1
05-Feb-1008-apr-10PPA2
REV DATEMODIF. DES. DATE VER.
SCALE 1/1 REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
A
AT91SAM9M10-G45-EK412A2
11-FEB-10Derek PP
RES.ARRAYS-EBI0_EBI1
05-Feb-1008-apr-10PPA2
RR29DRR29D4 5
RR23CRR23C3 6
RR9DRR9D4 5
RR15ARR15A1 8
RR9CRR9C3 6
RR10DRR10D4 5
RR3ARR3A1 8
RR33DRR33D4 5
RR27CRR27C3 6
RR3DRR3D4 5
RR33ARR33A1 8
RR7ARR7A1 8
RR28DRR28D4 5
RR29ARR29A1 8
R47 27RR47 27R
RR12CRR12C3 6
RR19BRR19B2 7
RR18BRR18B2 7
RR7DRR7D4 5
R45 27RR45 27R
RR11CRR11C3 6
RR16CRR16C3 6
RR14ARR14A1 8
RR4CRR4C3 6
R42 27RR42 27R
RR4ARR4A1 8
RR17CRR17C3 6
RR3CRR3C3 6
R48 27RR48 27R
RR7BRR7B2 7
RR4BRR4B2 7
RR2ARR2A1 8
RR21CRR21C3 6
RR20BRR20B2 7
RR16DRR16D4 5
RR29CRR29C3 6
RR24DRR24D4 5
RR29BRR29B2 7
RR6DRR6D4 5
RR6CRR6C3 6
R44 27RR44 27R
RR33BRR33B2 7
RR20DRR20D4 5
RR25ARR25A1 8
RR12ARR12A1 8
RR1BRR1B2 7
RR10BRR10B2 7
RR6ARR6A1 8
RR8DRR8D4 5RR30BRR30B2 7
RR5BRR5B2 7
R40 27RR40 27R
RR31DRR31D4 5
RR30CRR30C3 6
RR16ARR16A1 8
RR10CRR10C3 6
RR13ARR13A1 8
RR31CRR31C3 6
RR12BRR12B2 7
RR27ARR27A1 8
RR8ARR8A1 8
RR13CRR13C3 6
RR2BRR2B2 7
RR13DRR13D4 5
RR23ARR23A1 8
RR15DRR15D4 5
RR31BRR31B2 7
RR14BRR14B2 7
RR21BRR21B2 7
RR5ARR5A1 8
RR19DRR19D4 5
RR18DRR18D4 5
RR6BRR6B2 7
RR18CRR18C3 6
RR15CRR15C3 6
RR14DRR14D4 5
RR26ARR26A1 8
RR21ARR21A1 8
RR2CRR2C3 6
RR23DRR23D4 5
RR23BRR23B2 7
RR25DRR25D4 5
RR1DRR1D4 5
R49 27RR49 27R
RR30ARR30A1 8
RR32CRR32C3 6
RR3BRR3B2 7
RR15BRR15B2 7
RR26DRR26D4 5
RR31ARR31A1 8
RR25BRR25B2 7
RR2DRR2D4 5
RR20ARR20A1 8
RR22ARR22A1 8
RR9ARR9A1 8
RR4DRR4D4 5
RR16BRR16B2 7
RR8CRR8C3 6
RR11ARR11A1 8
RR28ARR28A1 8
RR1ARR1A1 8
RR7CRR7C3 6
RR27DRR27D4 5
RR28BRR28B2 7
RR24BRR24B2 7
RR12DRR12D4 5
R41 27RR41 27R
R46 27RR46 27R
RR32ARR32A1 8
RR9BRR9B2 7
RR8BRR8B2 7
RR32BRR32B2 7
RR10ARR10A1 8
RR19CRR19C3 6
RR17DRR17D4 5
RR22BRR22B2 7
RR21DRR21D4 5
RR11DRR11D4 5
RR24CRR24C3 6
RR17ARR17A1 8
RR13BRR13B2 7
RR33CRR33C3 6
RR14CRR14C3 6
RR22DRR22D4 5
RR5CRR5C3 6
RR22CRR22C3 6
RR17BRR17B2 7
RR19ARR19A1 8
RR1CRR1C3 6
RR18ARR18A1 8
RR24ARR24A1 8
RR30DRR30D4 5
RR5DRR5D4 5
R43 27RR43 27R
RR25CRR25C3 6
RR26CRR26C3 6
RR11BRR11B2 7
RR32DRR32D4 5
RR28CRR28C3 6
RR27BRR27B2 7
RR26BRR26B2 7
RR20CRR20C3 6
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RASCAS
NWE
CKE
DDR_D7
DDR_D3DDR_D2
DDR_D4
DDR_D0DDR_D1
DDR_D5DDR_D6
BA0BA1
DDR_A0DDR_A1DDR_A2DDR_A3DDR_A4DDR_A5DDR_A6DDR_A7DDR_A8DDR_A9DDR_A10DDR_A11DDR_A12DDR_A13
CKNCK
CS
DDR_VREF
DDR_VREF DDR_VREF
CKNCK
CS
BA0BA1
RASCAS
NWE
CKE
DDR_D15
DDR_D11DDR_D10
DDR_D12
DDR_D8DDR_D9
DDR_D13DDR_D14
DDR_A0DDR_A1DDR_A2DDR_A3DDR_A4DDR_A5DDR_A6DDR_A7DDR_A8DDR_A9DDR_A10DDR_A11DDR_A12DDR_A13
1V8
1V8
1V8
DDR_D[0..15]{4}
DDR_BA0{4}DDR_BA1{4}
DDR_CKE{4}
DDR_CLK{4}DDR_NCLK{4}
DDR_CS{4}
DDR_CAS{4}DDR_RAS{4}
DDR_WE{4}
DDR_A[0..13]{4}
DDR_DQS0 {4}
DDR_DQM0 {4}
DDR_DQS1 {4}
DDR_DQM1 {4}
DDR_VREF {3,6}
REV DATEMODIF. DES. DATE VER.
SCALE 1/1 REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
A
AT91SAM9M10-G45-EK512A2
11-FEB-10Derek PP
EBI0_DDR2
05-Feb-1008-apr-10PPA2
REV DATEMODIF. DES. DATE VER.
SCALE 1/1 REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
A
AT91SAM9M10-G45-EK512A2
11-FEB-10Derek PP
EBI0_DDR2
05-Feb-1008-apr-10PPA2
REV DATEMODIF. DES. DATE VER.
SCALE 1/1 REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
A
AT91SAM9M10-G45-EK512A2
11-FEB-10Derek PP
EBI0_DDR2
05-Feb-1008-apr-10PPA2
C78 100nC78 100n
C71 100nC71 100n
C80 100nC80 100n
C72 100nC72 100n
C81 100nC81 100n
C69 100nC69 100n
DDR2 SDRAM
MN6
MT47H64M8CF-3 -F
DDR2 SDRAM
MN6
MT47H64M8CF-3 -F
A0H8
A1H3
A2H7
A3J2
A4J8
A5J3
A6J7
A7K2
A8K8
A9K3
A10H2
BA0G2
ODTF9
DQ0C8
DQ1C2
DQ2D7
DQ3D3
DQ4D1
DQ5D9
DQ6B1
DQ7B9
DQSB7
DQSA8
RDQS/DMB3
RDQS/NUA2
VDDH9
VDDL1
VDDLE1
VREFE2
VDDQC9
VSSA3
VSSE3
VDDQA9
VDDE9
RFU1G1
RFU2L3
CKEF2
CKE8
CKF8
CASG7
RASF7
WEF3
CSG8
VDDQC1
VDDQC3
VDDQC7
VSSQB2
VSSQB8
VSSQD2
VSSQD8
VDDA1
VSSJ1
A11K7
BA1G3
A12L2
A13L8
VSSK9
VSSDLE7
VSSQA7
RFU3L7
C85 100nC85 100nC84 100nC84 100n
C91100nC91100n
C76 100nC76 100n
R521.5kR521.5k
C87100nC87100n
C67 100nC67 100n
L5 10uHL5 10uH
C79 100nC79 100n
C68 100nC68 100n
C83 100nC83 100nC82 100nC82 100n
C70 100nC70 100n
C77 100nC77 100n
C73 100nC73 100n
R511.5kR511.5k
DDR2 SDRAM
MN7
MT47H64M8CF-3 -F
DDR2 SDRAM
MN7
MT47H64M8CF-3 -F
A0H8
A1H3
A2H7
A3J2
A4J8
A5J3
A6J7
A7K2
A8K8
A9K3
A10H2
BA0G2
ODTF9
DQ0C8
DQ1C2
DQ2D7
DQ3D3
DQ4D1
DQ5D9
DQ6B1
DQ7B9
DQSB7
DQSA8
RDQS/DMB3
RDQS/NUA2
VDDH9
VDDL1
VDDLE1
VREFE2
VDDQC9
VSSA3
VSSE3
VDDQA9
VDDE9
RFU1G1
RFU2L3
CKEF2
CKE8
CKF8
CASG7
RASF7
WEF3
CSG8
VDDQC1
VDDQC3
VDDQC7
VSSQB2
VSSQB8
VSSQD2
VSSQD8
VDDA1
VSSJ1
A11K7
BA1G3
A12L2
A13L8
VSSK9
VSSDLE7
VSSQA7
RFU3L7
C904.7uC904.7u
C88100nC88100n
C74 100nC74 100n
R501RR501R
C89100nC89100n
C75 100nC75 100n
C86 100nC86 100n
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
(SDA10) (SDA10)
(NCS3)
(RDY/BSY)
(NANDALE)(NANDCLE)
(NCS1)
IMPORTANT note about system booting: The bootROM allows booting from the block 0 of a NandFlash connectedon CS3. However, the bootROM does not feature ECC (Error Checking and Correction) on NandFlash. Most of the NandFlash vendors do not guarantee anymore that block 0 is error free. Therefore we advise the bootstrap program to be located into another device supported by the bootrom (DataFlash, Serial Flash, SDCARD or EEPROM) and implement NandFlash access with ECC.
WP
REWECE
RB EBI1_NAND_FSH_D6
EBI1_NAND_FSH_D0
EBI1_NAND_FSH_D3EBI1_NAND_FSH_D4
EBI1_NAND_FSH_D2EBI1_NAND_FSH_D1
EBI1_NAND_FSH_D5
EBI1_NAND_FSH_D7
EBI1_NAND_FSH_D14
EBI1_NAND_FSH_D8
EBI1_NAND_FSH_D11EBI1_NAND_FSH_D12
EBI1_NAND_FSH_D10EBI1_NAND_FSH_D9
EBI1_NAND_FSH_D13
EBI1_NAND_FSH_D15
EBI1_DDR_D15
EBI1_DDR_D11EBI1_DDR_D10
EBI1_DDR_D12
EBI1_DDR_D8EBI1_DDR_D9
EBI1_DDR_D13EBI1_DDR_D14
EBI1_DDR_D7
EBI1_DDR_D3EBI1_DDR_D2
EBI1_DDR_D4
EBI1_DDR_D0EBI1_DDR_D1
EBI1_DDR_D5EBI1_DDR_D6
EBI1_FLASH_D4
EBI1_FLASH_D2
EBI1_FLASH_D10
EBI1_FLASH_D5
EBI1_FLASH_D12
EBI1_FLASH_D9
EBI1_FLASH_D14EBI1_FLASH_D15
EBI1_FLASH_D3
EBI1_FLASH_D0
EBI1_FLASH_D6EBI1_FLASH_D7EBI1_FLASH_D8
EBI1_FLASH_D1
EBI1_FLASH_D13
EBI1_FLASH_D11
EBI1_DDR_A2EBI1_DDR_A3EBI1_DDR_A4EBI1_DDR_A5EBI1_DDR_A6EBI1_DDR_A7EBI1_DDR_A8EBI1_DDR_A9EBI1_DDR_A10EBI1_DDR_A11EBI1_DDR_A12EBI1_DDR_A13
EBI1_DDR_A15EBI1_DDR_A14
EBI1_DDR_A2EBI1_DDR_A3EBI1_DDR_A4EBI1_DDR_A5EBI1_DDR_A6EBI1_DDR_A7EBI1_DDR_A8EBI1_DDR_A9EBI1_DDR_A10EBI1_DDR_A11EBI1_DDR_A12EBI1_DDR_A13
EBI1_DDR_A15EBI1_DDR_A14
NCLK_EBI1
CS_EBI1
BA0_EBI1BA1_EBI1
RAS_EBI1CAS_EBI1
WE_EBI1
CKE_EBI1
CLK_EBI1NCLK_EBI1
CS_EBI1
BA0_EBI1BA1_EBI1
RAS_EBI1CAS_EBI1
WE_EBI1
CKE_EBI1
VREF1
EBI1_FLASH_A1EBI1_FLASH_A2EBI1_FLASH_A3EBI1_FLASH_A4EBI1_FLASH_A5EBI1_FLASH_A6EBI1_FLASH_A7EBI1_FLASH_A8EBI1_FLASH_A9EBI1_FLASH_A10EBI1_FLASH_A11EBI1_FLASH_A12
EBI1_FLASH_A15EBI1_FLASH_A14EBI1_FLASH_A13
EBI1_FLASH_A16
EBI1_FLASH_A18EBI1_FLASH_A17
VREF1
VREF1
EBI1_FLASH_A19EBI1_FLASH_A20EBI1_FLASH_A21
CLK_EBI1
1V8
1V8
1V8
1V8 1V8
1V8
1V8
1V8
EBI1_FLASH_D[0..15]{4}
BA0_EBI1{4}
PC8{3}
EBI1_DDR_D[0..15]{4}
EBI1_FLASH_A[1..21]{4}
EBI1_DDR_A[2..15]{4}
BA1_EBI1{4}
CKE_EBI1{4}
CLK_EBI1{4}NCLK_EBI1{4}
CS_EBI1{4}
CAS_EBI1{4}RAS_EBI1{4}
WE_EBI1{4}
DQS0_EBI1 {4}
DQM0_EBI1 {4}
DQS1_EBI1 {4}
DQM1_EBI1 {4}
DDR_VREF{3,5}
PC5{3}PC4{3,4}
EBI1_NANDOE{3}EBI1_NANDWE{3}
PC14{3}
EBI1_NAND_FSH_D[0..15]{4}
EBI1_NRD/CFOE{3}EBI1_NWE/NWR0/CFWE{3}
EBI1_NCS0{3}
REV DATEMODIF. DES. DATE VER.
SCALE 1/1 REV. SHEET
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A
AT91SAM9M10-G45-EK612A2
11-FEB-10Derek PP
EBI1_MEMORY
05-Feb-1008-apr-10PPA2
REV DATEMODIF. DES. DATE VER.
SCALE 1/1 REV. SHEET
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A
AT91SAM9M10-G45-EK612A2
11-FEB-10Derek PP
EBI1_MEMORY
05-Feb-1008-apr-10PPA2
REV DATEMODIF. DES. DATE VER.
SCALE 1/1 REV. SHEET
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A
AT91SAM9M10-G45-EK612A2
11-FEB-10Derek PP
EBI1_MEMORY
05-Feb-1008-apr-10PPA2
DDR2 SDRAM
MN8
MT47H64M8CF-3 -F
DDR2 SDRAM
MN8
MT47H64M8CF-3 -F
A0H8
A1H3
A2H7
A3J2
A4J8
A5J3
A6J7
A7K2
A8K8
A9K3
A10H2
BA0G2
ODTF9
DQ0C8
DQ1C2
DQ2D7
DQ3D3
DQ4D1
DQ5D9
DQ6B1
DQ7B9
DQSB7
DQSA8
RDQS/DMB3
RDQS/NUA2
VDDH9
VDDL1
VDDLE1
VREFE2
VDDQC9
VSSA3
VSSE3
VDDQA9
VDDE9
RFU1G1
RFU2L3
CKEF2
CKE8
CKF8
CASG7
RASF7
WEF3
CSG8
VDDQC1
VDDQC3
VDDQC7
VSSQB2
VSSQB8
VSSQD2
VSSQD8
VDDA1
VSSJ1
A11K7
BA1G3
A12L2
A13L8
VSSK9
VSSDLE7
VSSQA7
RFU3L7
R58 0RR58 0R
R55 100kR55 100k
C92 100nC92 100n C93 100nC93 100nC94 100nC94 100n
C119 100nC119 100n
JP9JP9
1 2
C116100nC116100n
C114 100nC114 100n
R57 0RR57 0R
C99 100nC99 100n
NAND FLASH
MN11
MT29F2G08ABDHC:D
NAND FLASH
MN11
MT29F2G08ABDHC:D
WEC7
N.C6B9
VCCH8
CEC6
RED4
N.C11E3
WPC3
N.C5B1
N.C1A1
N.C2A2
N.C3A9
N.C4A10
N.C12E4
N.C13E5
N.C14E6
N.C15E7
R/BC8
N.C17F3
N.C36M1
I/O0H4
N.C34L9
N.C25L2
VSSF7
N.C29J5
VCCJ6
VSSK3
ALEC4
N.C8D6 N.C7
B10
N.C9D7
N.C10D8
CLED5
N.C16E8
N.C35L10
I/O1J4
I/O3K5I/O2K4
N.C28H5
N.C30H6
N.C32H7
I/O7J8I/O6K7I/O5J7I/O4K6
N.C27J3N.C26H3
VSSC5
N.C24L1
VSSK8
LOCKG5
VCCD3
VCCG4
N.C31G6
N.C18F4
N.C19F5
N.C20F6
N.C22G3 N.C21F8
N.C33G7
N.C23G8
N.C37M2
N.C38M9
N.C39M10
MN10
M58WR032KT_VFBGA56
DNPMN10
M58WR032KT_VFBGA56
DNP
A1D8
A2C8
A3B8
A4A8
A5B7
A6A7
A7C7
A8A2
A9B2
A10C2
A11A1
A12B1
A13C1
A14D2
A15D1
A16D4
A17B6
A18A6
A19C6
A20B3
DQ0F7
DQ1E6
DQ2E5
DQ3G5
DQ4E4
DQ5G3
DQ6E3
DQ7G1
DQ8G7
DQ9F6
DQ10F5
DQ11F4
DQ12D5
DQ13F3
DQ14F2
DQ15E2
VDDA4
VDDG4
VDDQE1
VDDQG6
VPPA5
VSSA3
VSSF1
VSSQG2
VSSQG8
NC/A21C3
NCD7
CEE7
OEF8
WEC5
RESETB5
WPD6
CLKB4
LATCHC4
WAITD3
A0E8
C106 100nC106 100n
C113 100nC113 100n
R56
470k
R56
470k
C105 100nC105 100n
R61 1kR61 1k
R53 100kR53 100kR54 0RR54 0R
C95 100nC95 100n
C104 100nC104 100n
C107 100nC107 100nR200 0RR200 0R
C100 100nC100 100n
JP10
SIP2
JP10
SIP2
1 2
C118 100nC118 100n
C102 100nC102 100n
C121 100nC121 100n
C101 100nC101 100n
R630RDNP
R630RDNP
C117100nC117100n
C108 100nC108 100n
R60 0RR60 0R
DDR2 SDRAM
MN9
MT47H64M8CF-3 -F
DDR2 SDRAM
MN9
MT47H64M8CF-3 -F
A0H8
A1H3
A2H7
A3J2
A4J8
A5J3
A6J7
A7K2
A8K8
A9K3
A10H2
BA0G2
ODTF9
DQ0C8
DQ1C2
DQ2D7
DQ3D3
DQ4D1
DQ5D9
DQ6B1
DQ7B9
DQSB7
DQSA8
RDQS/DMB3
RDQS/NUA2
VDDH9
VDDL1
VDDLE1
VREFE2
VDDQC9
VSSA3
VSSE3
VDDQA9
VDDE9
RFU1G1
RFU2L3
CKEF2
CKE8
CKF8
CASG7
RASF7
WEF3
CSG8
VDDQC1
VDDQC3
VDDQC7
VSSQB2
VSSQB8
VSSQD2
VSSQD8
VDDA1
VSSJ1
A11K7
BA1G3
A12L2
A13L8
VSSK9
VSSDLE7
VSSQA7
RFU3L7
C109 100nC109 100nC112 100nC112 100n
R59 470kR59 470k
C111 100nC111 100n
C120 100nC120 100n
C103 100nC103 100n
C98 100nC98 100n
C110 100nC110 100n
C96 100nC96 100n
C115 100nC115 100n
C97 100nC97 100n
R62 470kR62 470k
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SERIAL EEPROMSERIAL DATAFLASH
SD/MMCPlus CARD INTERFACE - MCI1SD/MMC CARD INTERFACE - MCI0
Test point
(MCI0_DA1)(MCI0_DA0)
(MCI0_CK)
(MCI0_CDA)(MCI0_DA3)(MCI0_DA2)
(MCI0_CD)
(MCI1_DA1)(MCI1_DA0)
(MCI1_CK)
(MCI1_CDA)(MCI1_DA3)(MCI1_DA2)
(MCI1_DA4)(MCI1_DA5)
(MCI1_DA7)(MCI1_DA6)
(MCI1_CD)(MCI1_WP)
(SPI0_MISO)(SPI0_MOSI)(SPI0_SPCK)(SPI0_NPCS0)
(TWCK0)(TWDO)
PA1PA5PA4
PA3PA2
PA0
PA26PA25
PA27PA28PA29PA30
PA24PA23
PA31
PA22
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
PB1{3}PB2{3}PB3{3}
PA21{3,12}PB0{3}
PD29{3}PD11{3}PD10{3}
PA20{3,12}
PA[22..31]{3,10}PA[0..5]{3}
NRST{2,3,8,9,10,12}
REV DATEMODIF. DES. DATE VER.
SCALE 1/1 REV. SHEET
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A
AT91SAM9M10-G45-EK712A2
11-FEB-10Derek PP
MCI & TWI
05-Feb-1008-apr-10PPA2
REV DATEMODIF. DES. DATE VER.
SCALE 1/1 REV. SHEET
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A
AT91SAM9M10-G45-EK712A2
11-FEB-10Derek PP
MCI & TWI
05-Feb-1008-apr-10PPA2
REV DATEMODIF. DES. DATE VER.
SCALE 1/1 REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
A
AT91SAM9M10-G45-EK712A2
11-FEB-10Derek PP
MCI & TWI
05-Feb-1008-apr-10PPA2
JP12SIP2JP12SIP2
1 2
RR3610kRR3610k
1 2 3 45678
JP13
SIP2
JP13
SIP2
12
C124100nC124100n
R192
68k
R192
68k
RR39
27R
RR39
27R
1234 5
678
R6610kR6610k
R193
68k
R193
68k
C123100nC123100n
R194
68k
R194
68k
R188
68k
R188
68k
RR41 27RRR41 27R1234 5
678
R189
68k
R189
68k
R187
68k
R187
68k
R195
68k
R195
68k
RR42 27RRR42 27R1234 5
678
R6410kR6410k
R196
68k
R196
68k
R190
68k
R190
68k
R6510kR6510k R197
68k
R197
68k
RR38 27RRR38 27R1234 5
678
JP11DNPJP11DNP
1
2
3
R198
68k
R198
68k
C125 100nC125 100n
J5
7SDMM-B0-2211
J5
7SDMM-B0-2211
8
5
76
43219
141516
13121110
J6
FPS009-3202-BL
J6
FPS009-3202-BL
8
5
76
43219
101112
R67470kR67470k
MN12
AT24C512BN
MN12
AT24C512BN
A01
A12
WP7
SCL6
VCC8 A3
3SDA5
GND4
RR40 27RRR40 27R
1234 5
678
C122 100nC122 100n
MN13
AT45DB321D-SU
MN13
AT45DB321D-SU
RESET3
GND7
VCC6
CS4 SCK2 SI1 SO8
WP5
R680RDNP
R680RDNP
R191
68k
R191
68k
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LINE-IN
MONO / STEREOMICROPHONE INPUT
HEADPHONELINE-OUT
8 Ohm SPEAKEROUTPUT
(AC97TX)(AC97CK)
(AC97RX)
(AC97FS)
(EXT_CLK)
JP17/JP18 are usedas Testpoint
AGND_AC97
AGND_AC97
AGND_AC97
AGND_AC97
AGND_AC97
AGND_AC97
AGND_AC97
3V3 AVDD_AC97
AVDD_AC97
3V3
AVDD_AC97
AGND_AC97
AGND_AC97
3V3
AGND_AC97
NRST{2,3,7,9,10,12}
PD6{3}
PD9{3}
PD8{3}
PD7{3}
PE31{3}
REV DATEMODIF. DES. DATE VER.
SCALE 1/1 REV. SHEET
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A
AT91SAM9M10-G45-EK812A2
11-FEB-10Derek PP
AUDIO AC97
05-Feb-1008-apr-10PPA2
REV DATEMODIF. DES. DATE VER.
SCALE 1/1 REV. SHEET
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A
AT91SAM9M10-G45-EK812A2
11-FEB-10Derek PP
AUDIO AC97
05-Feb-1008-apr-10PPA2
REV DATEMODIF. DES. DATE VER.
SCALE 1/1 REV. SHEET
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A
AT91SAM9M10-G45-EK812A2
11-FEB-10Derek PP
AUDIO AC97
05-Feb-1008-apr-10PPA2
C15410u10V
C15410u10V
C1471uC1471u
C129470pC129470p
JP18 DNPJP18 DNP12
C141100nC141100n
L1110uHL1110uH
R7247kR7247k
JP14
DNP
JP14
DNP
1 2
Y3
24.576MHz
Y3
24.576MHz13
2 4
R73 10kR73 10k
L12220ohm at 100MHzL12220ohm at 100MHz
1 2
R83680RR83680R
R76 0RR76 0R
C14410u10V
C14410u10V
C13410u10V
C13410u10V
C131
100n
C131
100n
JP15DNP
JP15DNP
12
R69 0RR69 0R
C136100nC136100n
C137 22pC137 22p
J7
STEREO_3.5mm
J7
STEREO_3.5mm
1
3 4
2 5
C14010u10V
C14010u10V
L7220ohm at 100MHzL7220ohm at 100MHz
1 2
R79 8.2KR79 8.2K
J8
STEREO_3.5mm
J8
STEREO_3.5mm
1
3 4
2 5
C145100nC145100n
+C127 100u/6.3V+C127 100u/6.3V
R818.2KR818.2K
C138100nC138100n
L9
220ohm at 100MHz
L9
220ohm at 100MHz
1 2
+C126 100u/6.3V+C126 100u/6.3V
R75 0RDNP
R75 0RDNP
JP17 DNPJP17 DNP12
C153100nC153100n
C1501uC1501u
J9
STEREO_3.5mm
J9
STEREO_3.5mm
1
3 4
2 5
C155470pC155470p
R84680RR84680R
C148470pC148470p
C1461uC1461u
R7147kR7147k
MN14
WM9711L
MN14
WM9711L
OU
T337
HP
_OU
T_L
39H
P_O
UT_
R41
LOUT235ROUT236
SDATAIN8
GP
IO5/
SP
DIF
48
XTLOUT3
COMP129COMP230COMP331CAP232
VREF27MICBIAS28
GP
IO4
47
CREF12
AG
ND
242
AVDD125
SP
KV
DD
38
HP
VD
D43
SPKGND34
DBVDD1
DCVDD9
NC
114
NC
215
PH
ON
E20
PC
BE
EP
19A
GN
D1
18
LIN
E_I
N_L
23
LIN
E_I
N_R
24
MIC
121
MIC
222
AV
DD
213
GP
IO2/
IRQ
45G
PIO
346
SDATAOUT5
RESET11 SYNC10
XTLIN2
BITCLK6
NC
417
NC
316
AGND26
HP
_GN
D40
GP
IO1
44
MONOOUT33
DGND14
DGND27
THE
RM
AL
49
C13210u10V
C13210u10V
C135
100n
C135
100n
R77 0RR77 0R
C128470pC128470p
C14210u10V
C14210u10V
L10220ohm at 100MHzL10220ohm at 100MHz
1 2
C143100nC143100n
R78 49.9RR78 49.9R
R70 0RR70 0R
R828.2KR828.2K
C130
100n
C130
100n
C139100nC139100n
R74 100kR74 100k
L6220ohm at 100MHzL6220ohm at 100MHz
1 2
R85 0RR85 0R
C1511uC1511u
L8220ohm at 100MHzL8220ohm at 100MHz
1 2
C133 22pC133 22p
C149470pC149470p
R80 8.2KR80 8.2K
C156470pC156470p
C15210u10V
C15210u10V
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SERIAL DEBUG PORTRS232 COM PORT
USB HOST/DEVICE INTERFACE
USB HOST INTERFACE
ICE INTERFACE
(ENA)
(ENB)
(FLGA)
(FLGB)
(VBUS)
(IDUSB)
TDI
RTCKTDO
TMSTCK
NTRST
NRST
5V
3V3
3V3
3V3
3V3
3V3 3V3
3V3
3V3
PD2 {3}
PD4 {3}
PB13 {3}
PD1 {3}
PB12 {3} PB5{3}
PD17{3}
PB4{3}
PD16{3}
HDMA {3}
HDPA {3}
PD3 {3}
HDMB {3}HDPB {3}PD28 {3,11}
NTRST {3}
RTCK {3}
TDI {3}TMS {3}TCK {3}
TDO {3}NRST {2,3,7,8,10,12}
PB19 {3}
REV DATEMODIF. DES. DATE VER.
SCALE 1/1 REV. SHEET
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A
AT91SAM9M10-G45-EK912A2
11-FEB-10Derek PP
SERIAL INTERFACES
05-Feb-1008-apr-10PPA2
REV DATEMODIF. DES. DATE VER.
SCALE 1/1 REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
A
AT91SAM9M10-G45-EK912A2
11-FEB-10Derek PP
SERIAL INTERFACES
05-Feb-1008-apr-10PPA2
REV DATEMODIF. DES. DATE VER.
SCALE 1/1 REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
A
AT91SAM9M10-G45-EK912A2
11-FEB-10Derek PP
SERIAL INTERFACES
05-Feb-1008-apr-10PPA2
R92 0RR92 0R
C161100nC161100n
C1+
V+
VCC
C1-C2+
C2-V-
T
T
R
R
GND
MN15
ADM3202ARNZ
C1+
V+
VCC
C1-C2+
C2-V-
T
T
R
R
GND
MN15
ADM3202ARNZ
116
34
5
15
11
10
12
98
13
7
14
2
6 C166 100nC166 100n
C159100nC159100n
C1+
V+
VCC
C1-C2+
C2- V-
T
T
R
R
GND
MN16
ADM3202ARNZ
C1+
V+
VCC
C1-C2+
C2- V-
T
T
R
R
GND
MN16
ADM3202ARNZ
1 16
34
5
15
11
10
12
9 8
13
7
14
2
6
R9668kR9668k
R87100kR87100k
C17110pC17110p
C162 100nC162 100n
R95 47kR95 47k
+ C17033u
+ C17033u
C163100nC163100n
R90 0RR90 0R
C160100nC160100n
C157 100nC157 100n
C169100nC169100n
+ C16833u
+ C16833u
VBUS
SHD DM
DPID
GND
J14
G3515-09010101-00
VBUS
SHD DM
DPID
GND
J14
G3515-09010101-00
12345
7
6
R88100kR88100k
J11J11
5
4
3
2
1
9
8
7
6
10 11
�����
J12G3505-4NBT1S1W
�����
J12G3505-4NBT1S1W
1
4
5
2
3
6
R940RDNP
R940RDNP
J13
HTST-110-01-SM-D
J13
HTST-110-01-SM-D
12345678910111213151719
14161820
R93 0RR93 0R
L14
220ohm at 100MHz
L14
220ohm at 100MHz
1 2
R9747kR9747k
C158 100nC158 100n
J10J10
5
4
3
2
1
9
8
7
61011
R91 0RDNP
R91 0RDNP
R86100kR86100k
MN17
AIC1526-0GS
MN17
AIC1526-0GS
ENA1
FLGA2
ENB4
OUTA8
GNG6
FLGB3
IN7
OUTB5
R89100kR89100k
C167100nC167100n
C164100nC164100n
C165 100nC165 100n
L13
220ohm at 100MHz
L13
220ohm at 100MHz
1 2
RR43100k
RR43100k
12345 6 7 8
C172100nC172100n
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SPEED 100
FULL DUPLEX
LINK&ACT
(TX_CLK)
(TXD3)(TXD2)
(RXD1)(RXD0)
(RX_CLK)(RX_DV)
RJ45 ETHERNET CONNECTOR
(RXD2)
(TXD1)(TXD0)(TX_EN)
(RXD3)
(COL)(CRS)
(MDC)(MDIO)(MDINTR)
(TX_ER)(RX_ER)
GND_ETH
GND_ETH
GND_ETH
GND_ETH
GND_ETH
3V3
3V3
3V3
3V33V3
3V3
AVDDT
AVDDT
AVDDT
3V3
PA10{3}PA14{3}
PA27{3,7}
PA18{3}
NRST{2,3,7,8,9,12}
PA19{3}PD5{3}
PA29{3,7}PA30{3,7}
PA16{3}
PA15{3}PA28{3,7}
PA12{3}PA13{3}PA8{3}PA9{3}
PA17{3}
PA7{3}PA6{3}PA11{3}
REV DATEMODIF. DES. DATE VER.
SCALE 1/1 REV. SHEET
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RMII_MII ETHERNET
05-Feb-1008-apr-10PPA2
REV DATEMODIF. DES. DATE VER.
SCALE 1/1 REV. SHEET
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REV DATEMODIF. DES. DATE VER.
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RMII_MII ETHERNET
05-Feb-1008-apr-10PPA2
JP16JP16
12
RR4710kRR4710k
1 2 3 45678
C176100nC176100n
C186 100nC186 100n
R108 0R DNPR108 0R DNP
R106 0R DNPR106 0R DNP
C17422pDNP
C17422pDNP
R10749.9RR10749.9R
C185 100nC185 100n
C182 100nC182 100n
C184 100nC184 100n
R98 10kR98 10k
C18110u10V
C18110u10V
R121470R
R121470R
C183100nC183100n
L15
2200R
L15
2200R
1 2
MN18
DM9161AEP
MN18
DM9161AEP
TX_ER/TXD416
COL/RMII36
MDC24
RX-4
RX+3
TX-8
TX+7
XT143
REF_CLK/XT242
RX_CLK/10BTSER34
RX_DV/TESTMODE37
RX_ER/RXD4/RPTR38
TX_EN21
BGRES48
AVDDR1
AVDDR2
DVDD41
DGND44
DGND15
AGND5
AGND6
LED2/OP213LED1/OP112LED0/OP011
TXD317
TXD218
TXD020 TXD119
TX_CLK/ISOLATE22
RXD0/PHYAD029 RXD1/PHYAD128 RXD2/PHYAD227 RXD3/PHYAD326
CRS/PHYAD435
MDIO25
MDINTR32
PWRDWN10
DGND33
RESET40
AVDDT9
DISMDIX39
DVDD30
DVDD23
AGND46
BGRESG47
CABLESTS/LINKSTS14
N.C45
LEDMODE31
Y5
25MHzDNP
Y5
25MHzDNP
1 3
24
1
2
3
6
4
5
7
8
75
75
7575
1nF
TD+
TD-
CT
NC
RD-
CT
TX+
TX-
RX+
RX-
RD+
J15
J00-0061NL
1
2
3
6
4
5
7
8
75
75
7575
1nF
TD+
TD-
CT
NC
RD-
CT
TX+
TX-
RX+
RX-
RD+
J15
J00-0061NL
1
2
7
8
3
6
5
4
15 16
R100 0RDNP
R100 0RDNP
R10249.9RR10249.9R
R116 0RR116 0R
D6 GreenD6 Green12
R110 0R DNPR110 0R DNP
R112 0R DNPR112 0R DNPR114 0R DNPR114 0R DNP
R119470R
R119470R
C179 100nC179 100n
C173100nC173100n
D4 YellowD4 Yellow12
R11349.9RR11349.9R
C18010u10V
C18010u10V
R103 0R DNPR103 0R DNP
R104 0R DNPR104 0R DNP
R990RR990R
R105 0R DNPR105 0R DNP
R123 0RR123 0R
R101 0RR101 0R
R109 0R DNPR109 0R DNP
C178100nC178100n
D5 GreenD5 Green12
R115 1.5kR115 1.5k
R1176.8kR1176.8k
R118470R
R118470R
R120 0RR120 0R
RR4410kRR4410k
1 2 3 45678
C177 100nC177 100n
RR4510kRR4510k
1 2 3 45678
R122 0RR122 0R
R11149.9RR11149.9R
C17522pDNP
C17522pDNP
C18710u10V
C18710u10V
VDD
VSS OUT
OE
Y4
50MHz
VDD
VSS OUT
OE
Y4
50MHz
41
32
RR4610kRR4610k
1 2 3 45678
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
4.3" 480x272 TFT LCD DISPLAY
(LCDPWR)
(LCDDEN)
(G4)
(R6)
(B3)
(LCDPWR)
(G5)
(LCDDEN)
(LCDCC)
(R7)(G0)
(B4)
(G6)
(B5)
(R2)
(G7)(B0)
(G1)
(B6)
(R3)
(G2)
(B7)
(R1)
(R4)
(B1)
(G3)
(LCDDOTCK)
(R5)
(R0)
(B2)
2*15mA, 12.6+/-0.6V MAX
2 x 4 LEDs Back Light
300mV
BL_SHDN#
LCDVSYNC
LCDD10
LCDD23
LCDD11LCDD12LCDD13
LCDD16
LCDD2
LCDD17
LCDD14
LCDD8
LCDD3
LCDD9
LCDD15
LCDD0
LCDD4
LCDD1
LCDD18LCDD19
LCDD5
LCDD20
LCDD6
LCDD21
LCDD7
LCDD22
G0
B5
G1
DEVSYNCHSYNCDISP
G2
PCLK
G3
B6
R0
B7
G4
LCDDEN
G6
R1
G7
G5
R6
R2
R7
B0B1
R3
LCDDOTCK
B2
R4
B3
R5
B4
AD3YmAD2YpAD1XmAD0Xp
TSADTRG
LCDHSYNC
(LCDHSYNC)(LCDVSYNC)
LCDHSYNC
BLUE6BLUE7
RED0
BLUE2BLUE3BLUE4BLUE5
BLUE0BLUE1
GREEN5GREEN6GREEN7
GREEN2GREEN3GREEN4
RED6RED7GREEN0GREEN1
RED2RED3RED4RED5
RED1
PE0
RED3PE8PE10
RED4PE9PE11
RED5PE10PE12
RED6PE11PE13
RED7PE12PE14
GREEN2PE13PE17
PE14GREEN3 PE18
PE19GREEN4PE15
PE20GREEN5PE16
PE21GREEN6PE17
PE22GREEN7PE18
PE26PE20
BLUE3
PE27BLUE4PE21
PE28BLUE5PE22
PE29BLUE6PE23
PE30BLUE7PE24
PE7PE8PE9
PE15PE16
PE23PE24PE25
PE6
PE17
PE12
PE28
PE23
PE7
PE1
PE18
PE13
PE29
PE24
PE8
PE2
PE0
PE19
PE3
PE14
PE25
PE9
PE20
PE15
PE26
PE10
PE21
PE5
PE16
PE11
PE27
PE30
PE22
VLED-
VLED+
LCDVSYNCPE6
Y_UPX_LEFT
LCDHSYNC
Y_LOWX_RIGHT
VLED-VLED+
LCDDOTCK
PE4
Y_UPX_RIGHTX_LEFT
Y_LOW
LCDHSYNCLCDVSYNC
PE4
LCDDOTCK
5V
3V3
PE[0..30] {3,12}
PD22 {3,12}PD21 {3,12}
PD23 {3,12}
PD20 {3,12}
LCDDOTCK{12}
PE2{3,12}
PD28 {3,9}
LCDHSYNC{12}LCDVSYNC{12}
TV_HSYNC{12}TV_XCLK{12}
TV_VSYNC{12}
REV DATEMODIF. DES. DATE VER.
SCALE 1/1 REV. SHEET
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REV DATEMODIF. DES. DATE VER.
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DISPLAY
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RR54ARR54A1 8
RR4927RRR4927R
1234 5
678
R134 0RR134 0R
R16410RR16410R
R171 0R DNPR171 0R DNP
Con
duct
ors
o
nTO
P S
IDE
PIN 1
PIN 40
TRU
LY
M1
TFT1N4633-E
Con
duct
ors
o
nTO
P S
IDE
PIN 1
PIN 40
TRU
LY
M1
TFT1N4633-E
R155 0R DNPR155 0R DNP
RR5127RRR5127R
1234 5
678
J24
54104-4031
J24
54104-4031
123456789
10111213141516171819202122232425262728293031323334353637383940
R153 0RR153 0R
R204 10RR204 10R
C194
10n
DNP
C194
10n
DNP
R151 0R DNPR151 0R DNP
C193
10n
DNP
C193
10n
DNP
R203 10RR203 10R
RR54DRR54D4 5
R128 0RR128 0R
R146 0R DNPR146 0R DNP
R157 0RR157 0R
R150 0R DNPR150 0R DNP
R166 0RR166 0R
C188100nC188100n
R202 10RR202 10R
RR5227RRR5227R
1234 5
678
R143 0RR143 0R
R130 0RR130 0RR131 0RR131 0R
R147 0RR147 0R
D7
RB160M-60
D7
RB160M-60
C18910uC18910u
MN19
CP2122ST
MN19
CP2122ST
SW1
GND2
FB3
SHDN#4
VIN5
R165 0R DNPR165 0R DNP
RR5327RRR5327R
1234 5
678
R201 10RR201 10R
R173 0R DNPR173 0R DNP
R149 0RR149 0R
R154 0RR154 0R
RR54BRR54B2 7
R161 0R DNPR161 0R DNPR163 0RR163 0R
R160 0RR160 0R
R125 27RR125 27R
C1912.2uC1912.2u
R133 0RR133 0R
R129 0RR129 0R
R132 0RR132 0R
LCD1
LCM_fix
LCD1
LCM_fix
C19010uC19010u
R159 0R DNPR159 0R DNP
R139 0RR139 0RR138 0R DNPR138 0R DNP
R145 0RR145 0R
R16210kR16210k
R158 0RR158 0R
R126
4.7k
R126
4.7k
R172 0RR172 0R
R170 0RR170 0RR169 0R DNPR169 0R DNP
R141 0RR141 0R
R127 0RR127 0R
R174 0RR174 0R
R205220KR205220K
R140 0R DNPR140 0R DNP
R144 0R DNPR144 0R DNP
R148 0R DNPR148 0R DNP
RR54CRR54C3 6
R142 0R DNPR142 0R DNP
R152 0RR152 0R
R137 0RR137 0R
L1622uHL1622uH
C192
10n
DNP
C192
10n
DNPR167 0R DNPR167 0R DNP
RR4827RRR4827R
1234 5
678
R136 0R DNPR136 0R DNP
R168 0RR168 0R
R156 0RR156 0R
RR5027RRR5027R
1234 5
678
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
IMAGE SENSOR CONNECTOR
Composite Video Output
CONNECTOR EXTENSION FOR LARGE LCD
(LCDMOD)
(G4)
(R6)
(B3)
(LCDPWR)
(G5)
(LCDDEN)
(LCDCC)
(R7)(G0)
(B4)
(G6)
(B5)
(R2)
(G7)(B0)
(G1)
(B6)
(R3)
(G2)
(B7)
(R1)
(R4)
(B1)
(G3)
(LCDDOTCK)
(R5)
(R0)
(B2)
(HSYNC)(VSYNC)
(TWDO)(TWCK0)
(AD1Xm)(AD3Ym) (AD2Yp)
(AD0Xp)
(GPIO2)(GPIO1)
(ISI_PCK)
(ISI_D2)
(ISI_VSYNC)
(ISI_D8)
(ISI_D3)
(ISI_D0)
(ISI_HSYNC)
(ISI_D10)
(ISI_D4)
(ISI_MCK)
(ISI_D09)
(ISI_D5)
(ISI_D11)
(ISI_D6)(ISI_D7)
(ISI_D1)
(CTRL1) (CTRL2)
PE27PE29
PE25PE23
PE2PE1
PE16
PE20PE18
PE14
PE22
PE10PE12
PE26
PE30PE28
PE24
PE6
PE7
PE0
PE9PE8
PE11PE13PE15PE17
PE21PE19
PE23PE24PE25PE26PE27PE28PE29PE30PE15PE16PE17PE18PE19PE20PE21PE22PE7PE8PE9PE10PE11PE12PE13PE14
PE6
PE6
PE17
PE12
PE28
PE23
PE7
PE1
PE18
PE13
PE29
PE24
PE8
PE2
PE0
PE19
PE3
PE14
PE25
PE9
PE20
PE4
PE15
PE26
PE10
PE21
PE5
PE16
PE11
PE27
PE30
PE22
PB28
PB23
PB11
PB24
PB29
PB25
PB8
PB30
PB26
PB21PB20
PB9
PB31
PB27
PB22
PB10
PB21PB23PB25PB27PB9PB11
PA21PB31PB29PB30PB28PB20PB22PB24PB26PB8PB10
PA20
3V3
3V3
1V8
3V3
3V3
3V3
3V3
3V3
3V3
5V
3V3
PE[0..30]{3,11}
PA21{3,7}
NRST{2,3,7,8,9,10}
VDDISI{2,3}
PD25{3}PD27{3}PD19{3}
PD24 {3}PD26 {3}PD18 {3}
PD15 {3}PD14{3}
PD21{3,11}PD23{3,11}
PD20 {3,11}PD22 {3,11}
PA20{3,7}
PB[8..11]{3}
PB[20..31]{3}
PD12{3} PD13 {3}
LCDDOTCK{11}
TV_XCLK{11}TV_HSYNC{11}TV_VSYNC{11}
LCDHSYNC{11} LCDVSYNC {11}
REV DATEMODIF. DES. DATE VER.
SCALE 1/1 REV. SHEET
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05-Feb-1008-apr-10PPA2
REV DATEMODIF. DES. DATE VER.
SCALE 1/1 REV. SHEET
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05-Feb-1008-apr-10PPA2
REV DATEMODIF. DES. DATE VER.
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05-Feb-1008-apr-10PPA2
L212200RL212200R
1 2
C197100nC197100n
J17
HDR_2x15_SMT
J17
HDR_2x15_SMT
1 23 45 67 89 10
11 1213151719
14161820
21 2223 2425 2627 2829 30
C212100nC212100n
MN20 CH7024BMN20 CH7024B
D71
D82
D93
D104
D115
D126
D137
D148
D159
D1610
D1711
D1812
D1913
D2014
D2115
D2217
D2319
D042
D143
D244
D345
D446
D547
D648
V39
H40
XCLK41
DE20
RESET23
VDDIO38
AVDD_DAC25
DVDD16
AVDD_PLL32
AVDD33
DGND18
AGND_DAC29
AGND_PLL31
AGND36
SPD21
SPC22
NC24
C/CVBS26
Y27
CVBS28
ISET30
XI/F
IN34
XO
35
P-OUT37
D8
BAT54SLT1G
D8
BAT54SLT1G
1 2
3R180 4.7kR180 4.7k
C204 33pC204 33p
C206100pC206100p
C200100nC200100n
R183 75RR183 75R
C205100pC205100p
C20810pC20810p
R178 1.2k
1%
R178 1.2k
1%
L182200RL182200R
1 2
J20
RCA JACk
J20
RCA JACk3
1
J23
HDR_2x20_SMT
DNPJ23
HDR_2x20_SMT
DNP1 23 45 67 89 10
11 1213151719
14161820
21 2223 2425 2627 2829 3031 3233 3435 3637 3839 40
C203100nC203100n
C19910u10V
C19910u10V
C202100nC202100n
R186 0RDNP
R186 0RDNP
VDD
VSS OUT
OE
Y6
13MHz
DNP
VDD
VSS OUT
OE
Y6
13MHz
DNP
41
32
C210100nC210100n
C207100nDNP
C207100nDNP
C21110u10V
C21110u10V
R181 75RR181 75R
TP6TP6
J18
HDR_2x10_SMTDNP
J18
HDR_2x10_SMTDNP
1 23 45 67 89 10
11 1213151719
14161820
R1850RR1850R
L172200RL172200R
1 2
L22
1.8uH
L22
1.8uHR179 4.7kR179 4.7k
R18275RR18275R
C19810u10V
C19810u10V
L192200RL192200R
1 2
R175 0R
DNP
R175 0R
DNP
R176 0RDNP
R176 0RDNP
L202200RL202200R
1 2
C196100nC196100n
Y7
13MHz
Y7
13MHz
1 3
24
C20910pC20910p
R184 10k DNPR184 10k DNP
C20110u10V
C20110u10V
Section 8
Revision History
8.1 Revision History
Table 8-1.
Document CommentsChange Request Ref.
6495B
Main edits:- Most Figures updated
- Hyperlinks to PDFs updated
- ‘Serial Synchronous Controller (SSC)’ removed- ‘JTAG’ added
- ‘RJ45 crossed cable’ added
- Dimensions updated- Most configuration tables (with LEDs, pins and connectors) updated
- ‘LG/Philips’ reference removed
6990
New Figure 4-4, ” EBI1 - DDR2 + Flash” and new Schematics in Section 7.1 ”Schematics” 7169
6495A First issue.
AT91SAM9M10-G45-EK User Guide 8-1
6495B–ATARM–21-Apr-10
6495B–ATARM–21-Apr-10
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