1

Asymmetric Doherty Power Amplifier DesignedUsing Model-Based Nonlinear Embedding

Haedong Jang, Member, IEEE, Patrick Roblin, Member, IEEE, Christophe Quindroit, Member, IEEE, Yiqiao Lin,Robert D. Pond

Abstract—A novel procedure is introduced for designing Do-herty amplifiers using the model-based nonlinear-embeddingtechnique. First, the Doherty intrinsic load matching networkis designed at the transistor current-source reference-plane withthe main and auxiliary devices interconnected. Identical deviceswith different biasing are used for realizing an asymmetricDoherty implementation with 9 dB back-off. The required multi-harmonic impedances at the package planes are then obtainedusing the embedding device model for both devices and thecomplex load impedance at the fundamental is projected backto resistive loads using an offset line. An even-number multi-section impedance transformers and a reduced drain voltage ofthe main amplifier are used to design the asymmetric Dohertyload network while providing the necessary loads to the mainand auxiliary devices. The optimization of the drain efficiencyand gain curves of the asymmetric Doherty operation for theproposed design is further investigated by adjusting the auxiliarygate-bias. An efficiency above 50% over an 11 dB power range isexperimentally observed with 41.8 dBm peak output power usingcontinuous wave at 2 GHz. Using a dual-input implementationof the designed Doherty power amplifier (PA) a systematic dual-input continuous wave characterization of the Doherty operationis performed to establish the relative auxiliary-to-main phase-offsets and power-offsets yielding a maximum-efficiency underconstant gain. From this dual-input characterization it is foundthat the optimal gate-bias for single-input Doherty operationis the one for which the constant-gain maximum-efficiency isachieved for a quasi-constant auxiliary-to-main input power-ratiocorresponding to the one implemented in the input divider in thesingle-input Doherty PA.

Index Terms—Asymmetric, Doherty, embedding, load modu-lation, nonlinear, power amplifier.

I. INTRODUCTION

H IGH data rate communication environment requiresspectrally efficient modulation schemes with a high peak

to average power ratio (PAPR). Typical RF power amplifiershave peak efficiency only at peak power and the efficiencyis reduced at backed off power levels resulting in a degradedaverage efficiency. Doherty amplifiers have attracted RF poweramplifier designers due to their improved average efficiencyrealized with a relatively simple structure [1][2]. The con-ventional Doherty amplifier provides only 6 dB back-off levelwhile the signals such as long term evolution (LTE) or multiplecarrier wide-band code division multiple access (WCDMA)exhibit PAPR over 10 dB. Asymmetric Doherty amplifiers

This paper is an expanded version from the IEEE MTT-S InternationalMicrowave Symposium, Tampa Bay, FL, USA, June 1-6 2014. This workwas supported in part by the National Science Foundation under Grant ECS1129013

H. Jang, P. Roblin, C. Quindroit are with the Department of Electrical andComputer Engineering, The Ohio State University, Columbus, OH 43210,USA (email:jang.131@osu.edu; roblin@ece.osu.edu).

Ia

λ/4

I’m

IaIm

V

R’L.m RL.aRL

ZT

A

(a)

Ia

λ/4

I’mI”aV

RL

ZTI”m

A ParasiticsParasitics

C B

(b)

Fig. 1: Conceptual Doherty amplifier without parasitics (a)and with parasitics (b). The effective loads seen by the mainand auxiliary amplifiers are varied by the current contributionsfrom each amplifier.

have been demonstrated to extend the back-off range whileyielding higher average efficiency [2]-[5].

A conceptual diagram of the Doherty amplifier is shownin Fig. 1 (a). The main and auxiliary amplifiers are modeledas current sources. The power combining junction, markedas A in the figure, is ideally located at the current sourcereference plane of the auxiliary amplifier [6]. The modulatedload R′L.m controlled by the auxiliary current Ia, is invertedby a quarter wave transformer of impedance ZT and appliedto the main-device current-source (intrinsic IV characteristics)at the current-source reference plane.

Accurately providing modulated-loads to the devices iscritical for obtaining Doherty operation. However, high powerpackaged devices have non-negligible linear/nonlinear para-sitic components as shown in Fig. 1 (b). The junction A is nolonger the same as node B and the electrical distance betweenthe junction A and C is longer than a quarter-wave length.Proper matching network and impedance inverters are thus

2

required to absorb those parasitic components. Introducingadditional transmission lines between the junction A and nodeB was proposed in [6] to bring the auxiliary device intrinsicnode out of the device while accounting for the dominatingparasitic components. Typically, a significant amount of sim-ulation optimization or device characterization efforts whendevice models are not available, is required from designers tocompensate for the parasitic components.

A more systematic method would be to start the design atthe current-source reference-plane and then predict the externalloads or excitations at the fundamental or harmonics requiredto maintain the intended intrinsic operation using the hybridnonlinear/linear embedding/de-embedding techniques [8]-[14].An embedding device-model has been recently reported forthe Angelov model which facilitate this approach when anAngelov device model is available [7]. Applying this techniquefor designing the matching network of amplifiers using asingle device can be straight-forward. However, the design of aDoherty amplifier would be expected to be more complicatedthan that of a single-device amplifier because of the interactionbetween the main and auxiliary transistors via their parasiticnetworks, matching network and the Doherty combiner net-work. Furthermore, the nonlinear embedding technique canonly be applied after the intrinsic operation of both transistorshas been first defined.

To address the above issues and greatly simplify the designprocedure, we propose to first implement a Doherty PA usingonly the current sources of both the devices. The advantage ofsynthesizing first the Doherty operation at the current planesas proposed in this paper compared to the conventional designapproach with the full device model, is that the interactionbetween the two transistors can be optimized to implementthe Doherty load-modulation matching the device IV char-acteristics. The matching network and the offset lines thenrequired to implement this effective Doherty operation at thecurrent source plane can then be synthesized using the recentlyproposed nonlinear-embedding device model. To this order theauthors developed a modified Doherty design procedure usingtwo ideal transformers, for the intrinsic Doherty load matchingnetwork design before the nonlinear embedding techniqueis applied. This approach was demonstrated experimentallyin the first-pass design and realization of a 16.7 W peakpower asymmetric GaN Doherty PA [5]. A 51.86% averagedrain efficiency was observed after linearization maintaining-51.46 dBc adjacent channel power ratio excited for 10 MHzbandwidth LTE signals with 8.85 dB PAPR. In this expandedversion of the paper the step by step design procedure ispresented in details and the Doherty design equations arefurther generalized for arbitrary maximum current ratios andmaximum voltage ratios for the main and auxiliary transistors.Further new work reported in this paper are also describednext.

The turn-on time of the auxiliary amplifier can be controlledby the gate bias. Continuous wave (CW) large-signal measure-ments were conducted at multiple auxiliary amplifier gate biaspoints to investigate the Doherty operation realized throughthe proposed design procedure. Of particular interest is theobservation of both the efficiency at various power back-off

and the gain flatness. However a gate bias variation in class-Coperation affects the peak current of the auxiliary amplifierrequiring a corresponding power division ratio adjustmentof the input power divider [15]. The Doherty amplifier in[5] has a fixed power ratio divider at the input. Thus toaddress this issue in this expanded version of [5], a dualinput Doherty amplifier without the fixed power-ratio divider[16][17] was also designed and fabricated using the samenonlinear embedding technique. The operations with variedauxiliary gate bias conditions are then investigated without thefixed power-division constraint. A systematic characterizationmethod for the dual-input Doherty amplifier is presented in thehigh power region where load-modulation is taking place. Analgorithm for extracting the optimal constant-gain maximum-efficiency (CGME) from the systematic characterization datais also proposed. The optimal operation with varied auxiliarygate-bias conditions is then investigated and compared tothe single input fixed power-ratio Doherty power amplifieroperation reported in [5].

Even-section quarter wave transformers were introduced in[5] to facilitate the use of identical devices for both the mainand auxiliary amplifiers. It provides the necessary loads tothe devices so as to realize the adjustable load-modulationmatching. In this expanded work, the bandwidth characteristicprovided by the transformers is analyzed. It is established thatthe major bandwidth constraint is dominated by the Dohertyquarter wave impedance inverter instead of the added even-section impedance transformers. Further bandwidth improve-ment can thus be pursued by adopting advanced wide-bandinverter structures such as the ones proposed in [18]-[20].

The adjustable matching network for asymmetrical Dohertyamplifier design using identical devices is briefly reviewedin section II. The Doherty amplifier design process usingnonlinear embedding is elaborated in section III togetherwith the bandwidth analysis of the even-section transformers.The single input Doherty amplifier measurements results areanalyzed for the auxiliary gate bias adjustment in sectionIV. The dual-input Doherty amplifier is introduced in sectionV together with the systematic characterization method, theCGME algorithm and an analysis of the measured results.Finally a summary of the results obtained is presented in theconclusion VI.

II. MATCHING NETWORK FOR ASYMMETRIC DOHERTYPA USING IDENTICAL DEVICES

The efficiency of Doherty power amplifiers is well derivedin [21] assuming that the auxiliary amplifier is linear andapproaching a class-B operation condition. The efficiency forthe high power region where the load-modulation is takingplace can be approximated by (1) which can be re-derivedusing the power ratio notation n between the auxiliary andmain amplifiers, i.e., the auxiliary amplifier provides n timesmore power than the main amplifier:

ηhigh =π(n+ 1)|vin.norm|2

4[(n+ 2)|vin.norm| − 1],

1

n+ 1≤ |vin.norm| ≤ 1,

(1)

3

0 0.2 0.4 0.6 0.8 10

0.004

0.008

0.012

norm

aliz

ed n

umbe

r of

sam

ples

|vin

/Vin.de−crest.max

|

Symmetric (n=1)

Asymmetric (n=2)

LTE 10MHz

PAPR = 8.85 dB

0 0.2 0.4 0.6 0.8 10

20

40

60

80

Effi

cien

cy (

%)

0 0.2 0.4 0.6 0.8 10

20

40

60

80

Effi

cien

cy (

%)

Fig. 2: Asymmetric Doherty amplifier efficiency.

where, vin.norm is the RF input voltage amplitude normalizedto the peak input amplitude of the example input signals de-crested to have 8.85 dB PAPR. α in [21] is equivalent to1/(n + 1). The efficiency in the lower power region, whereonly the main amplifier is turned on, is assumed to be the sameas a class-B power amplifier as shown in Fig. 2 [21][24]. Theefficiency curve can be shifted to the left by using n largerthan 1 resulting in higher average efficiency for high peak toaverage signals. For example, the efficiency calculated usingLTE 10 MHz signal with 8.85 dB PAPR for the asymmetricstructure (n=2) shows 7.7% higher average efficiency than thesymmetric case (n = 1).

The effective load seen by each amplifier in Fig. 1 (a) isvaried by the current contribution of the other amplifier. Thoseloads can be expressed using the power ratio n assuming bothcurrents are in-phase. The power delivered from the auxiliaryamplifier side is assumed to be n times larger than the powerdelivered from the main amplifier side (Pa = nP ′m). Sincethe voltage V at node A is common, the auxiliary current is ntimes larger than the main (Ia = nI ′m). The voltage developedat node A by the summed currents is V = (I ′m + Ia)RL.Therefore the effective loads seen from each amplifier are:

R′L.m =V

I ′m= (n+ 1)RL

RL.a =V

Ia=

(n+ 1)

nRL. (2)

A. Preferred loads by devices

An optimal load Ropt for the peak power is decided bythe device maximum current Imax and the maximum voltageVmax considering the breakdown voltage as illustrated inFig. 3. The solid lines are ideal class-B load-lines at threedifferent power levels. The efficiency during load-modulationcan be shown to remain constant by selecting loads inverselyproportional to power levels [24]:

η =π(Vdd − Von)

4Vdd, (3)

Imax

1/Ropt

VmaxVddVon

1/Rmax

Imin

Fig. 3: The preferred loads for the auxiliary device under idealclass-B operation are shown in the shaded region.

where, Von is the knee voltage in the figure. However, forpractical devices, it is observed that the efficiency at lowpowers with high impedances degrades in the presence of on-resistance [7]. Therefore, the load-modulation range is limitedby the device characteristics to a maximum practical loadRmax. So, the preferred load modulation range for both ofthe devices is:

Ropt.m ≤ RL.m.preferred ≤ Rmax.m (4)Ropt ≤ RL.a.preferred ≤ ∞.

The load seen by the main amplifier through the quarterwave impedance inverter of the Doherty amplifiers are (n +1)2RL and (n+ 1)RL for the backed-off power level and thepeak power level, respectively. So, designers can choose thoseloads to fall into the devices’ preferred range.

In the symmetrical Doherty design, the loads seen by themain and auxiliary amplifiers at the peak power are the sameR′L.m = RL.a when n = 1 from (2). However, in theasymmetric Doherty design where n 6= 1, the two loadsseen by the both amplifiers are different (R′L.m 6= RL.a)which is not desirable when using identical devices. Therefore,in this work, additional impedance transform ratios (α, β)are introduced for both the main and auxiliary amplifiers toallow for using identical devices. Among the many possibletransformer implementations, multi-section impedance trans-formers were introduced in this work as shown in Fig. 4.Multi-section impedance transformers provide a convenientway of implementing the impedance transformation by choos-ing the characteristic impedances of the lines with broaderbandwidth and also controlled passband shaping by usingbinomial polynomials or Chebyshev polynomials. It shouldbe noted that the quarter wave transformers introduce anadditional phase shift of e−jkπ , where the k is the number ofsections used. Therefore an even number of sections shouldbe used to maintain the proper Doherty load-modulation.

4

HMN

RFC

Vds1

RL

λ/4ZT

HMN

λ/4

RFC Vds2

λ/4 λ/4

λ/4λ/4

Zm1 Zm2

Za1 Za2

α [(n+1)2RL, (n+1)RL ] Ω

β[∞, ](n+1)

RL Ωn

Intrinsic

IV model

Fig. 4: Adjustable Doherty amplifier matching network at thecurrent source reference plane. HMN stands for harmonicmatching network. Harmonics are ideally terminated at thecurrent source reference plane.

Imax

1/Ropt

VmaxVdd.reducedVon

1/Rmax

Imin

1/Ropt.m

1/Rmax.m

Fig. 5: The preferred loads (shaded area) for the main deviceare effectively reduced by the lowered drain bias voltage.

B. Peak power rescaling

The auxiliary amplifier provides n times more power thanthe main amplifier at the peak power. Therefore typically alarger device is used for the auxiliary of the asymmetric Do-herty power amplifiers [3]. However, as is shown in Appendix1, different voltage ratios γV and current ratios γI can befound to yield the same power ratio n if we select them toverify n = 1/(γIγV ). In this work, a reduced drain voltage(γV = 0.5) was used to reduce the main amplifier poweras shown in Fig. 5 while using identical devices (γI = 1).When using a reduced drain voltage for the main amplifier, itis still possible to have the main and auxiliary loads varyingin the preferred load range of the device with the help of twotransformers. The impedance variation ratio can be definedas:

γV =Vdd.reduced − Von

Vdd − Von(5)

leading to the following effective optimal and maximum loadsfor the main amplifier when identical devices (γI = 1) are

used:

Ropt.m = γVRopt and Rmax.m = γVRmax

As indicated in Fig. 4 the loads seen by the main and auxiliaryamplifiers vary under load modulation in the range:

α(n+ 1)RL < RL.m < α(n+ 1)2RL (6)

βn+ 1

nRL < RL.a <∞ (7)

The design equations can then be expressed in terms of theoptimal and maximum loads as follow:

Ropt.m = α(n+ 1)RL (8)Rmax.m ≥ α(n+ 1)2RL (9)

Ropt = βn+ 1

nRL (10)

From these equations we deduced that the max load mustverify Rmax.m ≥ (n + 1)Ropt.m. Equations (6-10) still holdfor non unity γI as can be verified using the general equationRopt.m = γV /γIRopt. The transformer ratio β must verify√β =

√α/γV while we have γI = 1/(nγV ) (see Appendix

1). In summary, designers can choose the design parameters,RL, α, and β to provide the preferred load ranges to thedevices for a given power ratio n [5], while adjusting themaximum voltage and current ratios γV and γI according to(see Appendix 1):

γV =|Vm.max||Va.max|

=

√α

βand γI =

|Im.max||Ia.max|

=1

n

√β

α

The generalized asymmetric Doherty design equations reduceto the classic asymmetric Doherty design equations [3] whenselecting γV = α = β = 1.

III. INTRINSIC DOHERTY LOAD-NETWORK DESIGN

A. Intrinsic Doherty load-network design

The model-based nonlinear embedding technique from [7]allows designers to start the PA design at the current sourcereference plane using the intrinsic IV model while accountingfor the leading memory effects such as group delay and self-heating. With this approach, designers can tailor the intrinsicoperation modes as close as possible to the ideal waveformusing ideal intrinsic harmonic terminations. Once the intrinsicoperation is defined using a certain number of harmonics,the external multi-harmonic voltages and currents at the ex-ternal (package) reference planes sustaining it are calculatedin a single simulation using the embedding device modelaccounting for all the device nonlinear/linear parasitic/chargecomponents [7]. Using those external voltages and currents,the external harmonic terminations and input excitations tokeep the intrinsic intended operation can be predicted [8].

ZL(nω) = −VeDS(nω)

IeD(nω),

ZS(nω) = −VeGS(nω)

IeG(nω), n > 2,

ZS(ω) = conj(V eGS(ω)/IeG(ω)), (11)

5

0 5 10 15 20 25

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

vDS

(t) (V)

i D(t

) (A

)

34.2 dBm36.0 dBm38.0 dBm39.9 dBm41.9 dBm

(a)

0 10 20 30 40 50

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

vDS

(t) (V)

i D(t

) (A

)

34.2 dBm36.0 dBm38.0 dBm39.9 dBm41.9 dBm

(b)

Fig. 6: Intrinsic loadlines of class-F main amplifier (a) andclass-C auxiliary amplifier (b) for varied input drive powers

where, n is the harmonic index, V eDS(nω), IeD(nω), V eGS(nω)and IeG(nω) are the predicted external drain and gate voltagesand currents at corresponding harmonic components. Currentsare assumed to flow into the device. The fundamental inputcan be conjugate matched using the predicted input impedancein large signal condition [8][25]. For the harmonic a smallload renormalization is required as usually the load reflectioncoefficients ΓL(nω) are slightly outside the Smith Chart [7].Using this technique, the design is significantly simplifiedremoving the need for time-consuming harmonic source/loadpull measurements or simulations.

The intrinsic IV model of a 15 W peak power GaNdevice(CGH27015F, CREE Inc.) was used for both main andauxiliary amplifiers. The drain bias of the main device wasreduced from 28 V to 14 V and the gate voltage was -2.9 Vresulting in 89 mA intrinsic quiescent current. The secondharmonic was shorted and the third kept open for class-F

operation. The auxiliary device was bias at 28 V for the drainand -3.9 V for the gate and the second and third harmonicswere shorted for class-C operation. The load network in Fig.4 was designed using RL = 12.27 Ω, α = 0.5 and β = 1.5.The methodology followed is explained next.

The device characterization for the CGH27015F in [7]showed that output loads of Ropt = 27.6 Ω to Rmax = 85.8 Ωwere optimal for 9.6 W and 3.0 W output power respectively.About 57% power added efficiency (PAE) was reported atthe peak power and was maintained over high power rangeat class-B operating condition and it was gradually degradeddown to 51% at low powers. In this design, it is targeted tohave 10 W provided by the auxiliary amplifier and 5 W by themain amplifier at the peak power in order to obtain the desired9.54 dB back-off (n=2). Note that the power ratio n is a designparameter which can be decided considering the PAPR of thesignals of interests. In this work, n = 2 which is 9.54 dBback-off was chosen for demonstration purpose consideringhigh PAPR signals such as WCDMA and LTE signals.

Note that the load variation is approximately 3 timeswhich is necessary for 9.54 dB back off asymmetric design(n+ 1 = 3). The three unknown variables, α, β and RL weredecided using the load range from the device characteristicsand (8)-(10). First of all, the auxiliary amplifier peak powerwas optimized using (10). Substituting (10) in (6) we obtain

γ2V nRopt < RL.m < γ2V n(n+ 1)Ropt

This selected range of load for the main PA should be includedin the preferred ranged defined by (5):

γ2V [nRopt, n(n+ 1)Ropt] ⊂ γV [Ropt, Rmax]

yielding the requirement:

γV [nRopt, n(n+ 1)Ropt] ⊂ [Ropt, Rmax]. (12)

For our particular design this gives:√α

β[55.2 Ω, 165.6 Ω] ⊂ [27.6 Ω, 85.8 Ω].

using γV =√α/β. Among many solutions, α = 0.4, β = 1.5

can be chosen resulting in a load range γ2V [nRopt, n(n +1)Ropt] of γV [28.5 Ω, 85.5 Ω] within the required rangeγV [27.6 Ω, 85.8 Ω] but in the practical design α = 0.5 waschosen for ease of the design of the even section transformer.Therefore, more saturated operation is expected with higherimpedance loads. Finally the load RL is evaluated from (10)to be RL = 12.27 Ω.

The designed intrinsic load lines are shown in Fig. 6 for themain (a) and auxiliary (b) devices. The main amplifier load-lines with swept power exhibit clear switching operation inclass-F mode. The auxiliary amplifier load-lines show class-Coperation in the linear IV region. The reduced drain voltageswing of the main amplifier can be noticed when compared tothe auxiliary amplifier.

The key point is that the Doherty load network is intrin-sically designed using the IV model without considering theparasitic components at the initial design stage. This allows thedefinition of an effective intrinsic Doherty operation through

6

1.0

−1.0

0.0 1.0 Inf

1.0

−1.0

0.0 1.0 Inf

1.0

−1.0

0.0 1.0 Inf

1.0

−1.0

0.0 1.0 Inf

1.0

−1.0

0.0 1.0 Inf

1.0

−1.0

0.0 1.0 Inf

1.0

−1.0

0.0 1.0 Inf

ΓL(ω)

ΓL(2ω)

ΓL(3ω)

IntrinsicExternal

(a)

1.0

−1.0

0.0 1.0 Inf

1.0

−1.0

0.0 1.0 Inf

1.0

−1.0

0.0 1.0 Inf

1.0

−1.0

0.0 1.0 Inf

1.0

−1.0

0.0 1.0 Inf

1.0

−1.0

0.0 1.0 Inf

1.0

−1.0

0.0 1.0 Inf

ΓL(ω)

ΓL(2ω)

ΓL(3ω)

IntrinsicExternal

(b)

Fig. 7: ΓL(nω) obtained at the current source reference planes(gray circles), the package reference planes (red circles) andthe Doherty combiner planes after the compensation network(black crosses) for the main (a) and auxiliary (b) amplifiers at2 GHz.

the interaction of both the main and auxiliary amplifiers beforeeven considering the parasitic and compensation networkdesign. This intrinsically defined Doherty operation can bethen used by the nonlinear embedding technique as will bedetailed in the next section.

B. Intrinsic to Extrinsic mode projection using nonlinearembedding

The intrinsic operations defined in the previous sectionfor both the main and auxiliary amplifiers were individuallyprojected to the package reference planes as shown in Fig.7. The intrinsic fundamental and harmonics are shown withgray dots. The intrinsic loads are on the real load line and

the harmonics were ideal short (ΓL.m.int(2ω) = −1) andopen (ΓL.m.int(3ω) = 1) positions. The projected fundamentaland harmonic loads through nonlinear/linear parasitics andpackage are also indicated in the figure. It can be noticedthat the projected third harmonic locations for the main andauxiliary are different due to the difference intrinsic class-F and class-C operation as expected. It also can be noticedthat the projected harmonic loads through the lossy parasiticnetwork are slightly out of Smith chart [7]. Consideringpractically realizable passive matching network, the harmonicterminations can be renormalized using the maximum avail-able harmonic terminations [7]:

Γ′L(nω) =ΓL(nω)

|ΓL(nω)|· ΓL.max.available(nω). (13)

Therefore, the intrinsic operation modes are no longer idealdue to the lossy harmonic terminations and the performance isexpected to be slightly degraded. This slight degradation couldbe partially compensated using harmonic injection techniques[26]-[28] at the cost of increased circuit complexity [7].

C. Harmonic terminations and offset line designIt can be noted in Fig. 7 that the required external harmonic

loads for the asymmetric Doherty amplifier at the packagereference plane defined using the nonlinear embedding tech-nique are independent of the load modulation. The harmonicscan then be terminated using microstrip open (or short) stubswhich have λ/12 and λ/8 lengths for the third and secondharmonics, respectively as illustrated in Fig. 8. The thirdharmonic must be terminated first since it has shorter physicallength. For example, an electrical short is implemented at nodeA using the λ/12 stub at 3f0, then ΓL.m(3ω) is obtained fromthe short position using a transmission line with an appropriateelectrical length θ7 and the characteristic impedance Zm.OL.It should be noted that the magnitude of the implementedharmonic shorts may be less than unity due to lossy microstriplines while the predicted ones are outside of the Smith chart:

|ΓL.implemented(nω)| ≤ |ΓL.predicted(nω)|. (14)

Therefore performance degradation is expected due to thepractical harmonic termination implementation. The third har-monic termination affects the second ΓL(2ω) and fundamentalΓL(ω) terminations. If the adjusted second harmonic termina-tion of the main amplifier is designated as Γ′L.m(2ω), thenit is terminated in a similar way using the λ/8 open stuband the transmission line with the electrical length of θ8 andthe characteristic impedance of Zm.OL. The characteristicimpedance Z5 of the open stubs affects both the bandwidthand the fundamental loads ΓL(ω). A narrower width exhibitssmaller bandwidth but affects less ΓL(ω) and vise versa. Inthis work for matching convenience a 100 Ω impedance wasused for reducing the impact on ΓL(ω).

Those variations can be accurately calculated in simulationas shown in Fig. 9 (a) in order to account for the practicalfabrication parameters of the microstrip lines. The voltagewaves injected into the matching circuit in Fig. 9 (a) are:

Vs1.m = V1.m.p − 50 · I1.m.p,V ′s1.m = V1.m.i + 50 · I1.m.i, (15)

7

RFCVds1

50Ω

λ/4ZT

RFC Vds2

λ/4 λ/4

λ/4λ/4

Zm1 Zm2

Za1 Za2

λ/4

Zm.OL

Za.OL

ɵm.OL

ɵa.OL

ETNλ/12 λ/8

ETN λ/12λ/8

Zm.OL Zm.OL

Za.OLZa.OL Z6

Z5

λ/12λ/8

λ/12λ/8

Z1

λ/4

Z4 Z3 Z3

Z3Z3Z4

Z5

Z5 Z5

Z5 Z5

Z5Z5

ɵ1ɵ2

Vgs2

Vgs1

ɵ3ɵ4

ɵ5

ɵ6

ɵ7 ɵ8

ɵ9 ɵ10

A1m

A1a

A B

ГL.m (ω,Pout) Г’L.m (ω,Pout) Г”L.m (ω,Pout)

Fig. 8: Dual input asymmetric Doherty amplifier schematic

where, V1.m.p and I1.m.p are the fundamental voltage andcurrent predicted by the embedding network at the mainamplifier output package reference plane. V1.m.i and I1.m.i arethe fundamental voltage and current predicted at the referenceplane before the impedance inverter. The direction of bothcurrents I1.m.p and I1.m.i is flowing into the device drain node.The fundamental load variations at each reference plane aredepicted in Fig. 9 (b). The arrows indicate the direction wherethe loads provide high output power. ΓL.m.inv(ω, Pout) areloads seen right before the output impedance inverter whichare the intended loads after the harmonic matching. Note thatthe loads ΓL.m(ω, Pout) and ΓL.m.inv(ω, Pout) in this figureare slightly different from the loads in Fig. 7 (a) due to thedifference between the models used. The extracted Angelovmodel was used in Fig. 7 while the manufacturer model (CREEInc.) was used in 9. Also, the harmonic terminations in Fig.7 are ideal.

The fundamental load variation versus swept power mayno longer be a straight line when they are rotated back tothe real axis of the Smith chart. Therefore, the characteristicimpedance and the length of the offset line can be selectedfor the Γ′′L(ω, Pout.peak) and Γ′′L(ω, Pout.back) to best fit thoseloads, i.e., for the main amplifier:

Γ′′L(ω, Pout.peak) =Zin.peak − Zm.OLZin.peak + Zm.OL

Γ′′L(ω, Pout.back) =Zin.back − Zm.OLZin.back + Zm.OL

(16)

where,

Zin.peak = Zm.OLα(n+ 1)RL + jZm.OL tan θm.OLZm.OL + jα(n+ 1)RL tan θm.OL

Zin.back = Zm.OLα(n+ 1)2RL + jZm.OL tan θm.OLZm.OL + jα(n+ 1)2RL tan θm.OL

.(17)

An offset line of 19 Ω with 154 before the harmonicmatching, was used in this work to rotate the fundamentalloads at the package reference plane for it to lie on the realline before the load-side quarter wave transformer. The sameoffset line was used for the auxiliary amplifier although itwas fine tuned in the final design stage. The resulting loadreflection coefficients measured after the offset lines for the

main and auxiliary amplifiers are shown in Fig. 7 using crosssymbol (black). It is noticed that the real loads have shifted tohigher and lower values for the main and auxiliary amplifiersrespectively. This would indicate that to sustain the virtualintrinsic Doherty operation targeted at the current plane amodified Doherty transformer/combiner may be potentiallyneeded at the external reference planes. However in thisparticular design the original Doherty transformer/combinerwas found to still perform well due to the correlated resistiveload variation of the main and auxiliary amplifiers.

D. Load matching network bandwidth analysis

The fractional bandwidth of the proposed two-sectionimpedance transformers can be analyzed and compared to thebandwidth of the Doherty impedance inverter. The fractionalbandwidth for a single section quarter-wave transformer is[29]:

∆f

f0= 2− 4

πcos−1

[ Γm√1− Γ2

m

2√Z0ZL

|ZL − Z0|

](18)

where, Γm is the magnitude of the tolerable reflection coeffi-cient.

Since, the transformer converts RL to (n + 1)2RL at thebacked-off power level, this can be rearranged as:

∆f

f0= 2− 4

πcos−1

[ Γm√1− Γ2

m

2(n+ 1)

n2 + 2n

](19)

In this work, n = 2 and if we assume a tolerable reflectioncoefficient Γm = 0.05 for analysis purpose, the fractionalbandwidth is 4.78%. It should be noted that there is nobandwidth limitation of the impedance inverter at the peakpower because the characteristic impedance of the inverter isthe same as the modulated load at the peak power and alsothe same as Ropt of the device.

The two-section quarter wave transformer used in thiswork is a binomial transformer which fractional bandwidthbe expressed as [29]:

∆f

f0= 2− 4

πcos−1

[1

2

(Γm|A|

)1/N], (20)

8

RFCVds1

λ/4 λ/4

Zm1 Zm2Zm.OL

ɵm.OL

λ/12 λ/8

Zm.OL Zm.OL

Z5 Z5

ɵ7 ɵ8

A B

ГL.m (ω,Pout) Г’L.m (ω,Pout) Г”L.m (ω,Pout)

50Ω 50Ω

Vs1.m V’s1.m

ГL.m.inv (ω,Pout)

(a)

1.0

−1.0

0.0 1.0 Inf

1.0

−1.0

0.0 1.0 Inf

1.0

−1.0

0.0 1.0 Inf

1.0

−1.0

0.0 1.0 Inf

1.0

−1.0

0.0 1.0 Inf

1.0

−1.0

0.0 1.0 Inf

1.0

−1.0

0.0 1.0 Inf

ΓL.m

Γ’L.m

Γ’’L.m

ΓL.m.inv

(b)

Fig. 9: Fundamental load (ΓL(ω, Pout)) variation versuspower (b) after the harmonic matching at each reference plane(a). The arrows indicate loads providing high output power.

1.96 1.97 1.98 1.99 2 2.01 2.020

10

20

30

40

50

60

70

80

Frequency (GHz)

Gp (

dB),

Pou

t (dB

m),

PA

E (

%)

PAEsim@peak

PAEsim@back

PAEmeas@peak

PAEmeas@back

Pout.sim@peak

Pout.sim@back

Pout.meas@peak

Pout.meas@back

Gainmeas@peak

Gainmeas@back

Fig. 10: Frequency dependence of the PAE, output power, andpower gain.

where, N is the number of sections used and the constant Adefined as:

A = 2−NZL − Z0

ZL + Z0. (21)

The impedance transform ratios for the main and auxiliaryare 0.5 and 1.5, respectively. Therefore, Amain = 1/12 and

(a)

(b)

Fig. 11: The fixed power ratio divider Doherty PA (a) from[5] and the companion dual input Doherty PA (b).

Aaux = 1/20. Assuming the same Γm = 0.05, the fractionalbandwidth for the main and auxiliary amplifiers are 50.6% and66.7%, respectively. The transformer of the auxiliary amplifiershows wider bandwidth with less impedance transform ratio asexpected. According to the analysis, the two-section transform-ers have a much wider bandwidth than the Doherty impedanceinverter which provides the major bandwidth constraint in thisload matching network. Also, the harmonic short stubs areexpected to have a bandwidth limitation similar to the singlesection quarter-wave transformer inverter.

The simulated and measured bandwidth of the implementedDoherty amplifier in terms of gain, output power and drainefficiency versus frequency is shown in Fig. 10. The outputpower, gain, and drain efficiency were measured for twodifferent operating conditions. One is at the peak poweroperating condition and the other one is at the back-off poweroperating condition. The high performance of the PA (>50%PAE) is seen in Fig. 10 to be maintained for a bandwidthof 50 MHz. A reduced efficiency (>40% PAE) operationwas verified to hold for a bandwidth in excess of 100 MHz.Note that these results do not reflect on the limitation of thenonlinear embedding PA design technique but rather on theparticular design selected for the matching networks, inverterand offset lines. For example the bandwidth improvementtechniques proposed in [18]-[20] for the inverter could beimplemented as needed for broadband design.

IV. SINGLE INPUT DOHERTY

A single input fixed power ratio divider Doherty poweramplifier was built in [5] as shown in Fig. 11 (a). Themodel used for the nonlinear embedding was replaced withthe manufacturer (CREE Inc.) model at the final stage andthe design was fine tuned using electro-magnetic simulationresults. More power was provided to the auxiliary amplifier

9

to keep the peak current with the reduced gate voltage forclass-C operation. The input coupler exhibited in simulationthe following S-parameters |S21| = 0.652 and |S31| = 0.749,where 2 and 3 are the inputs of the main and auxiliaryamplifiers respectively. This yields an input power divisionratio of 1.2 dB.

0 0.2 0.4 0.6 0.8 10

2

4

6

8

10

Out

put p

ower

(W

)

Normalized incident power

MainAuxilaryn

Fig. 12: Simulated output powers of both main and auxiliaryamplifiers and power division ratio n are plotted versusnormalized incident power.

The power ratio n = 2 between the main and auxiliary am-plifiers is a design goal which is selected to obtain the intendedback-off operation. This power ratio can be observed in thefinal stage nonlinear circuit simulation using the manufacturermodel and electromagnetic simulation results as depicted inFig. 12. As the input incident power is increased the powerratio n approaches the intended design goal of 2.

The measurement results in Fig. 13 are repeated from [5]for readers’ reference. The output power and drain currents forthe main and auxiliary amplifiers were measured with sweptinput power at 2 GHz using continuous waves. Three differentauxiliary amplifier gate voltages (Vgs.a = −3.4 V,−3.6 Vand −3.8 V) were used to investigate the trade off betweenefficiency and linearity.

Fig. 13 compares the measured drain efficiency and powergain (symbols) to the simulated data (solid lines). It wasobserved that increasing the auxiliary gate voltage reduces thesecond peak efficiency while flattening the gain curves. It isinteresting to note that reducing the main amplifier quiescentcurrent from 74 mA to 23 mA slightly shifts the efficiencycurves to the left resulting in a wider back-off and flatter gaincurves. Thus the most flat gain was obtained at -3.4 V forthe auxiliary gate voltage and 23 mA for the main amplifierquiescent current but yielded reduced efficiency.

A lower auxiliary gate bias reduces the conduction angleof the class-C operation and the device turn-on is retarded.The main amplifier is expected to be more saturated duringthis delayed turn-on and reaches higher efficiency level at thebacked-off peak efficiency point. Since the main amplifier issaturated the gain is reduced as well and the auxiliary amplifierproduces less power in this deeper class-C bias operation

25 30 35 400

10

20

30

Gai

n (d

B)

Output power (dBm)

Vgs.aux

= −3.8V

Vgs.aux

= −3.6V

Vgs.aux

= −3.4V

25 30 35 4010

30

50

70

25 30 35 4010

30

50

70

25 30 35 4010

30

50

70

25 30 35 4010

30

50

70

Dra

in e

ffici

ency

(%

)

25 30 35 4010

30

50

70

Dra

in e

ffici

ency

(%

)

25 30 35 4010

30

50

70

Dra

in e

ffici

ency

(%

)

25 30 35 4010

30

50

70

Dra

in e

ffici

ency

(%

)

25 30 35 4010

30

50

70

Dra

in e

ffici

ency

(%

)

25 30 35 4010

30

50

70

Dra

in e

ffici

ency

(%

)

Simulated at Ids

= 74mA

Measured at Ids

= 74mAMeasured at I

ds= 23mA

Fig. 13: Measured (solid and blank symbols) drain efficiencyand gain at 2 GHz are compared to simulation (solid lines)with swept input powers at three different auxiliary amplifiergate voltages. Reduced main amplifier bias current from 74mA (solid symbols) to 23 mA (blank symbols) shifts theefficiency curves to the left. 74 mA drain current was usedin the simulations. (Repeated from [5])

1950 1970 1990 2010 2030 2050−100

−90

−80

−70

−60

−50

−40

−30

With no DPD

With DPD

Frequency (MHz)

PS

D (

dBm

/Hz)

0 0.5 10

0.5

1

Norm. Input

Nor

m. O

utpu

t

With no DPD

With DPD

Fig. 14: Spectrum of normalized output and AM-AM distor-tion were measured at -3.6 V for the auxiliary gate voltageand 23 mA main amplifier bias current. PSD stands for powerspectral density.

[15]. The measured drain efficiency at -3.8 V of the auxiliary(square symbol, , red) is, therefore, the highest among thethree biases and the gain is the lowest. As the auxiliary gatebias is increased, the conduction angle is increased in theclass-C operation and the device turn-on time is advanced.In summary, the lowest gate bias -3.8 V where the auxiliaryamplifier turns on late, exhibited the highest efficiency with thelowest gain. On the contrary, the highest gate bias -3.4 V wherethe auxiliary amplifier turns on early, exhibited the lowestefficiency with the highest gain. However, this experiment wasconducted with a fixed power ratio divider at the input. Whenthe gate bias of class-C operation is varied, the peak currentis also expected to be varied requiring additional input powerand different power division ratio. To investigate the impactof the auxiliary gate bias in more details we will characterizein the next section a dual input Doherty power amplifier builtwithout the fixed power ratio divider as shown in Fig. 11 (b).

10

It is interesting to notice when the output power is between30 and 35 dBm, the drain efficiency measured at 74 mA isslight lower than the one measured at 23 mA for both casesof Vgs.a = -3.8 V and -3.6 V. But, when Vgs.a = -3.4 V, thedrain efficiency with 74 mA is higher than the one with 23mA. Therefore further investigation would be necessary forthe mechanism after the auxiliary device is turned on but theinvestigation of the mechanism at the transitional range is outof the scope of this paper.

It should be mentioned that the CW gain in Fig. 13was calculated using the incident power instead of the inputpower to be consistent with the linearization measurementsystem used for modulated signal excitations. Above 50%drain efficiency was maintained over a 11.4 dB output powerrange at -3.6 V for the auxiliary gate voltage and 23 mAfor the main amplifier quiescent current depicted by magentablank triangles in Fig. 13. 71% drain efficiency at the peakpower of 41.8 dBm and 62.7% at the second peak of 32.8dBm (9 dB back-off) were observed. For these operatingconditions, the digital predistortion (DPD) from [22] using afield-programmable gate array (FPGA) test-bed in [23] wasapplied for demonstration purposes. A 10 MHz bandwidthLTE signal with 8.85 dB PAPR was used. The same averageoutput power of 33.55 dBm was used before and after applyingDPD for a fair comparison. Thus in this DPD experimentusing modulated signals the PA reaches a peak power of 42.4dBm (16.7 W) which is 0.6 dB above the measured 41.8 dBmpeak power using CW signals. 51.86% average efficiency wasobserved after linearization maintaining -51.47 dBc adjacentchannel power ratio (ACPR) and -37.37 dB normalized meansquare error (NMSE). The nonlinearity order was 15 andthe memory depth 7. The measured linearization results aresummarized in table I and illustrated in Fig. 14.

TABLE I: Average efficiency before and after linearization.

Po.avg DEavg ACPR NMSE(dBm) (%) (dBc) (dB)

Before DPD 33.55 54.28 -28.42 -13.11After DPD 33.55 51.86 -51.47 -37.37

V. DUAL INPUT DOHERTY

In this section, a dual input Doherty power amplifier withouta fixed power-ratio divider is built and measured to investigatethe impact of the auxiliary gate bias. A systematic large-signal characterization method for the dual input Dohertyis presented. An algorithm to determine the constant-gainmaximum-efficiency conditions from the systematic character-ization data is also proposed. Simulation and measured dataare then discussed and compared to the single input fixedpower ratio divider Doherty measurements.

A. Constant-gain maximum efficiency algorithm

An algorithm to determine the input conditions using theadditional degrees of freedom of the amplitude and phase ofthe auxiliary amplifier is introduced. This algorithm selectsthe best efficiency while maintaining a constant power gain

in the high power Doherty load-modulation range. The threeindependent variables of the |A1m|, |A1a| and ∠A1a associ-ated with the main A1m and auxiliary A1a incident waves aresystematically swept. It should be mentioned that the auxiliaryamplifier is off in the low power region ignoring soft turn-on.The magnitude and phase of the auxiliary amplifier can benormalized relative to the main amplifier input according to:

∆Pa = 10 log(|A1a|/|A1m|)2, (22)∆∠A1a = ∠(A1a/A1m) (23)

The reference gain for the dual-input Doherty PA is definedfor convenience as the ratio between the Doherty output powerPout, and the main amplifier incident power, Pinc.m. Thegain surface can be plotted in the ∆Pa and ∆∠A1a spaceat each incident main amplifier power level as shown in Fig.15 (a). A set of input conditions,((∆Pa.k,∠A1a.k), k =1, · · · ,K), for the auxiliary amplifier can be selected for agiven constant gain as illustrated by the solid line (black)in this 2D plot. K is the number of points used. The drainefficiency can then be calculated at these points as shown bythe solid line (black) in Fig. 15 (b) on the efficiency surfacegenerated at the same incident main amplifier power level inthe same ∆Pa and ∆∠A1a space. Finally the input conditiongiving the maximum drain efficiency can be selected along theline. A set of input conditions,((∆Pa.m,∠A1a.m), m =1, · · · ,M) can be selected at each incident main amplifierpower level. M is the number of incident main amplifier powerlevels.

B. Simulation resultsThe dual input Doherty amplifier was simulated in Agilent

ADS using the CREE CGH27015F model at 2 GHz withcontinuous waves. The passive networks were simulated usingthe Momentum simulation and the simulated data was used forthe amplifier circuit simulations. The incident main amplifierpower was swept from 17.1 dBm to 28.1 dBm. The relativeincident power of the auxiliary amplifier, ∆Pa, was sweptfrom -15 dBc to 0 dBc. The relative phase of the auxiliaryamplifier, ∆∠A1a, was swept from 0 to 100. It should benoted that the simulation results showed symmetry around 0.Therefore only one side (from 0 to 100) was selected forapplying the algorithm to avoid multiple maximums.

Fig. 16 shows the simulated drain efficiency versus outputpower at Vgs.a =-3.4 V for all the systematically sweptinput conditions. The fixed power divider Doherty amplifiersimulation (solid line, black) and measured (square symbol, ,black) results are plotted for references. The CGME algorithmwas applied to the simulated data and the selected points bythe algorithm are shown with square symbols (blue) in thefigure. The simulated results show that there is a possibilitythat the drain efficiency can be further improved by controllingthe main and auxiliary inputs separately even keeping constantgain. It should be noted that AM to PM nonlinearity is notconsidered in the CGME algorithm.

C. Measurement SetupThe dual input Doherty power amplifier was fabricated as

shown in Fig. 11 (b) with the fixed power divider shown in Fig.

11

0 20 40 60 80 100−15

−10

−5

0

10

12

14

16

18

∆ Pa (dB)

∆ ∠ A1.a ( °)

Ga

in (

dB

)

11

12

13

14

15

16

(a)

0

20

40

60

80

100

−15

−10

−5

0

20

40

60

80

∆ ∠ A1.a ( °)

∆ Pa (dB)

DE

(%

)

30

40

50

60

70

(b)

Fig. 15: Simulated gain (a) and drain efficiency (b) surfaces atmain amplifier at the incident power of 22.1 dBm at 2 GHz.The black line corresponds to a 14 dB constant gain locus.The red dot corresponds the maximum efficiency along theconstant gain locus.

11 (a) removed. A 90 delay line was added to the auxiliaryinput. Continuous waveform (CW) was performed at 2 GHzusing a large-signal network analyzer (LSNA, MT4463A)configured as shown in Fig. 17. Since the amplifier has twoinputs and a single output, the two calibrated LSNA input andoutput ports were used for the dual inputs. Another couplerconnected with an attenuator was calibrated using the LSNAand connected between the output port of the amplifier and apower meter (HP E4418). The two signal sources used at theinput (Agilent ESG 4438C, MXG N5183A) were synchronizedsharing a 10 MHz reference signals. The auxiliary inputamplitude and phase were automatically synchronized to theinput of the main amplifier before each parameter-sweep toavoid any amplitude and phase drift during the measurementsweep. The amplitude (∆Pa) and phase (∆∠A1a) of theauxiliary amplifier were varied to the intended values rightafter the synchronization. The three inputs were systematicallyswept, the incident main amplifier power Pinc.m varying from18.2 dBm to 28.2 dBm, the relative auxiliary incident power∆Pa from -9 dBc to 1 dBc and the relative auxiliary phase∆∠A1a from −70 to 20.

20 25 30 35 40 4510

20

30

40

50

60

70

80

Pout (dBm)

DE

(%

)

Fixed divider simulationFixed divider measurementDual input simulationDual input iso−gain (14 dB)

(a)

20 25 30 35 40 458

9

10

11

12

13

14

15

16

17

Pout (dBm)

Gai

n (d

B)

Fixed divider simulationFixed divider measurementDual input simulationDual input iso−gain (14 dB)

(b)

Fig. 16: Simulated drain efficiencies (a) and gain (b) for all thesystematically swept input conditions at Vgs.a =-3.4 V werecompared to fixed power divider Doherty and the constant gainalgorithm.

LSNA(MT4463A)

PM

ESG

4438CMXG

N5183A

50Ω

a1 b1 a2b2

DUT

50Ω -24.55 dB

ScopePS1

PS2

HP E4418

Fig. 17: Dual input Doherty PA characterization setup

The main amplifier was biased at 14.3 V, 74 mA forthe drain voltage and currents, respectively. The auxiliaryamplifier was biased at 28 V for the drain voltage. Themeasurements were performed at three different auxiliary gatevoltages of -3.4 V, -3.6 V and -3.8 V.

12

20 25 30 35 40 4510

20

30

40

50

60

70

80

Pout (dBm)

DE

(%

)

Fixed divider simulationFixed divider measurementDual input simulated iso−gainDual input measuredDual input iso−gain (12.5 dB)

(a)

20 25 30 35 40 456

8

10

12

14

16

18

Pout (dBm)

Gai

n (d

B)

Fixed divider simulationFixed divider measurementDual input simulated iso−gainDual input measuredDual input iso−gain (12.5 dB)

(b)

Fig. 18: Measured drain efficiency (a) and gain (b) using CWsignals for the three input variables swept at Vgs.a =-3.4 V.

D. Measured results and discussion

The measured drain efficiencies at Vgs.a =-3.4 V areplotted in Fig. 18 for all the swept dual input conditions.The fixed power divider Doherty amplifier simulation (solidline, black) and measurement (square symbol, , black) arerepeated for references. The CGME algorithms was applied tothe measured data and shown with solid squares (blue). Thesimulated CGME result is also shown as a dashed line (black)for a reference. The CW measured results also predicts thepossibility of an efficiency improvement by dynamically con-trolling the dual input Doherty amplifier while maintaining aconstant gain. As a result simultaneous efficiency and linearityimprovements are expected for such dual input operation.

The optimal offset power and phase (∆Pa,∆∠A1.a) forthe maximum drain efficiency are plotted in Fig. 19 for thethree different auxiliary bias conditions (Vgs.a =-3.4 V, -3.6 V,and -3.8 V) using three different constant gain values of 12.5,11.8 and 11.4 dB respectively. The achievable constant gainis determined by the auxiliary gate bias. Also the measureddata fluctuation affects the achievable constant gain in theapplication of CGME algorithm. Therefore, the constant gainswere manually selected by observing the measured data. The

32 34 36 38 40−8

−6

−4

−2

0

2

Pout (dBm)

∆ P

aux (

dB)

−3.4V−3.6V−3.8Vfixed

(a)

32 34 36 38 40−60

−50

−40

−30

−20

−10

0

Pout (dBm)

∆ P

hase

(°)

−3.4V−3.6V−3.8V

(b)

Fig. 19: Relative power (a) and phase (b) yielding an optimalefficiency for three different gate biases. These results areextracted from the measured data using the CGME algorithmfor a constant gain of 12.5, 11.8 and 11.4 dB at the gate biasof -3.4, -3.6 and -3.8 V respectively.

relative power offset yielding the optimal drain efficient isseen to vary with the output power. The phase inputs exhibita smaller variation centered around −30 as the output powervaries. The CGME efficiency results for the three cases arealso plotted in Fig. 20. To test the sensitivity of the efficiencyto the offset phase, the offset phase was held constant at −30

at its optimum value and only the amplitude was varied (notshown here). In this experiment, the same level of efficiencywas obtained confirming that the relative insensitivity of theCGME efficiency to the offset phase for this particular Dohertyamplifier.

The slope of the offset power versus output power curvesin Fig. 19 (a) implies that a nonlinear control on the auxiliaryinput power relative to the main input power is necessaryto achieve the optimal constant-gain and maximum-efficiencyoperation condition. As can be seen, for the three gate-biascases shown, the higher the auxiliary gate bias (earlier turn-on) the larger the slope and the requirement for a nonlinearcontrol for the auxiliary input power. At a lower gate voltage

13

32 34 36 38 4054

56

58

60

62

64

66

68

Pout (dBm)

DE

(%

)

−3.4V−3.6V−3.8V

Fig. 20: The optimal drain efficiencies obtained for the threeauxiliary gate biases (Vgs.a =-3.4 V, -3.6 V, -3.8 V) using theproposed CGME algorithm.

(-3.8 V) with a slower turn-on, a flatter slope was observedresulting in a larger power offset. An approximate fixedunequal power divider could then be used avoiding the needfor the nonlinear control of the auxiliary input power. Thisresults indeed justifies the improved efficiency performanceachieved by the single input Doherty PA for the −3.8 Vgate bias as shown in Fig. 13. Note that in the single inputDoherty PA, a fixed unequal power divider with 1.2 dB powerdivision was used which is represented in Fig. 19 (a) usinga dashed line. This dashed line is seen to be well centeredon the −3.8 V optimal offset line (red line) predicted bythe CGME algorithm. To bring theoretical support to thisexperimental results, it is demonstrated in Appendix 2 forthe case of an ideal transistor with constant transconductanceand abrupt cutoff at the threshold voltage, that there existsa unique optimal coupler ratio kmax for which the requiredDoherty operation is achieved at peak power and at back-offwhen using a class C amplifier for the auxiliary amplifier.

The above characterization using continuous wave impliesthat if a fixed bias is used without dual input control,Vgs.a = −3.8 V should give the highest efficiency than theother two cases which require nonlinear dual input control.To validate the efficiency performance predicted above, theaverage efficiency was measured for a single carrier WCDMAsignal with 9.75 dB PAPR with the PA biased with IDS.m =23mA, VDS.m =14.3 V, VDS.a = 28 V using the same threegate bias voltages. The experiment results are summarizedin table II. The fixed power ratio ∆Paux was manually setto be approximately equal to 1.2 dB. The phase difference∆Phase was set to 0 for experimental convenience. A DPDlinearization was performed using a nonlinear order of 15 andmemory length of 7 while keeping the average output powerat 1.0 W. As expected, it is obtained that under the samecondition, the lower the gate voltage the higher efficiency atthe cost of a slightly degraded NMSE due to the increase PAnonlinearity. An average efficiency of 57.9% was obtained at-3.8 V. The spectrum of normalized outputs before and afterthe DPD with the three different auxiliary gate voltages are

TABLE II: Average drain efficiency, ACPR and NMSE versusthe auxiliary PA gate bias with a constant power division ratio.The presented values are after DPD was applied. ∆Phase = 0

Vgs.a Pout.avg ∆Paux ACPRl ACPRh NMSE DE(V) (W) (dBc) (dBc) (dBc) (dB) (%)-3.8 1.01 1.22 -44.3 -45.4 -31.0 57.9-3.6 1.00 1.45 -49.5 -50.1 -37.8 54.6-3.4 1.00 1.47 -50.1 -50.3 -36.5 46.8

1990 1995 2000 2005 2010

−90

−80

−70

−60

−50

−40

−30

Frequency (MHz)P

SD

(dB

m/H

z)

Before DPD

After DPD

Vgs.a

=−3.4V

Vgs.a

=−3.6V

Vgs.a

=−3.8V

Fig. 21: The spectrum of normalized outputs before and afterthe DPD with the three different auxiliary gate voltages.

shown in Fig. 21.

VI. CONCLUSION

A novel design procedure for asymmetric Doherty poweramplifier using the model-based nonlinear embedding tech-nique has been introduced and demonstrated. The nonlin-ear embedding technique accurately synthesizes the requiredwaveforms at the external reference planes given the de-sired intrinsic Doherty operation targeted. This technique cansignificantly simplify the design process by removing theneed for extensive harmonic source/load-pull measurements orsimulations. The proposed design procedure demonstrates theuse of the nonlinear embedding technique when the intrinsiccircuit operation involves the interaction between multipleactive devices. A matching network technique allowing for theimplementation of an asymmetric Doherty PA using the samedevice is proposed. Finally a methodology for simultaneouslyprojecting the intrinsic waveforms of both device to thepackage reference planes using the nonlinear embedding anddesigning the compensation networks is demonstrated.

Using this above procedure a 9 dB back-off asymmetric Do-herty amplifier has been designed. An even-numbered multi-section impedance transformers and a reduced drain voltage ofthe main amplifier are also used to implement the asymmetricDoherty operation for the case where identical devices areused. A bandwidth analysis of the design demonstrated thatthe primary bandwidth limitation of the Doherty amplifieris limited by the quarter wave length impedance invertergiven the added multi-section impedance transformers exhibita wider bandwidth.

14

Ia

ZT

jZ

jYT

T

00

(n+1)RL

+V V

+VI

R R

I’ I’

amm L L

am

L.m L.aR’ R’L.aInverter

K =

21

+R

L.m

λ/4 1: βα:1

Fig. 22: Generalized Doherty circuits using two transformerswith turn ratios α and β respectively.

Asymmetric Doherty operation was investigated with vari-ous auxiliary amplifier gate bias voltages. A single input Do-herty amplifier with a fixed power ratio divider was comparedto a dual input Doherty amplifier without fixed power ratiodivider. A systematic dual input Doherty amplifier character-ization method was proposed, and a constant-gain maximum-efficiency algorithm was proposed for optimizing the inputpower division between the main and auxiliary amplifiers. Theoptimal performance obtained with the dual input Doherty PAfor the various gate voltages were found to be consistent withthe results obtained for the single input Doherty PA. Thesemeasurements points also toward the potential benefit in usingnonlinear power division to maximize the efficiency whilemaintaining a constant gain. The PA performance obtainedwith the CW signals for the various auxiliary gate biases werefurther verified using WCDMA waveforms in terms of averageefficiency and NMSE for the constant input power divisioncase.

APPENDIX 1Consider the generalized asymmetric Doherty circuit in Fig.

22. The matrix K represents the ABCD matrix of the ZTinverter between port 1 and 2. The following generalizedDoherty equations for Im and I ′a accounts for the transformerturn ratios α and β introduced in this paper:

Im =1

2gm.mVGS.m

I ′a = −j√α(n+ 1)

[Im −

Im.maxn+ 1

]=√βIa.

A factor 1/2 for Im arises assuming the main operates inclass B. It is also assumed that the main phase is selectedsuch that Im = |Im| and VGS.m = |VGS.m|. Note that themaximum main RF drain current Ia.max at the fundamentalfrequency verifies Ia.max = Imax.a/2 where Imax.a is thepeak drain current sustained in class F/B operation. With theuse of the additional weighting factor

√α one can easily verify

that the main voltage Vm verifies (using YT = 1/ZT ):

Vm =ImZ

2T

RL+

I ′ajYT

= gm.mVGS.m

[Z2T

RL−√α(n+ 1)

YT

]+√αZT Im.max.

To obtain a constant voltage Vm at the main transistor, theinverter impedance must be selected to be:

ZT =√α(n+ 1)RL.

This yields in turns a modified constant main RF voltage Vm:

Vm.max = Vm =√αZT Im.max

= α(n+ 1)RLIm.max =

√α

β|Va.max|.

The Doherty operation imposes then the following designequation expressed in terms of the voltage and current ratiosγV and γI at the transistor current sources:

γV =|Vm.max||Va.max|

=

√α

βand γI =

|Im.max||Ia.max|

=1

n

√β

α

where n is the maximum auxiliary-to-main PA power-ratiodelivered:

n =PRF.aPRF.m

=RVa.maxI∗a.maxRVm.maxI∗m.max

=1

γV γI.

It becomes evident that a continuum of Doherty solutionsin terms of maximum voltage and current ratios γV andγI is possible for a given targeted power ratio n to satisfyn = 1/(γV γI). For example for n = 2, (γV = 1, γI = .5)and (γV = .5, γI = 1) are two possible solutions. Thelatter one is adopted in this paper whereas the former isthe classic asymmetric design [3]. Further for the voltageratio γV selected we have the design equation α/β = γ2V .Again a continuum of design solutions with α = γ2V β is thenpossible. The impedances range reported in Section II for thisgeneralized design provides then a design guide to achieve thepreferred load ranges for the main and auxiliary transistors.The generalized asymmetric Doherty design equations reduceto the classic asymmetric Doherty design equations [3] whenselecting γV = α = 1 which leads to β = 1 and γI = 1/n.

APPENDIX 2

In this appendix we derive the design equation for theselection of the optimal coupler coefficient kmax. Accordingto the generalized Doherty theory presented in Appendix 1 theRF fundamental current of the auxiliary transistor should beof the form (assuming Im = |Im|):

Ia = −j(n+ 1)

√α

β

[Im −

Im.maxn+ 1

]such that we have |Ia.max| = n

√α/β · Im.max.

Let us assume the main transistor exhibits the followinglinear transfer characteristics when operating in class B:

Im =1

2gm.mVGS.m (24)

with VGS.m = |VGS.m|. It results that the required auxiliarycurrent can be expressed as:

Ia = −j[n+ 1

2

√α

βgm.m|VGS.m| −

√α

βIm.max

]. (25)

The auxiliary PA is implemented with a transistor operatingin class C which ideally yields the RF fundamental current(assuming VGS.a = −j|VGS.a|):

Ia = −jW(θ)gm.a (|VGS.a|+ VGS.dc.a − VT ) (26)

15

with VGS.dc.a the dc gate bias for the auxiliary transistor andwith W (θ) a weighting factor dependent on the conductionangle θ. W is given by [24]:

W(θ) =1

2π

θ − sin θ

1− cos(θ/2)

where θ the class C conduction angle, is defined as:

cos (θ/2) =VT − VGS.dc.a|VGS.a|

.

For large |VGS.a|, the conduction angle approaches θ = π ofthe class B operation and the weighting factor W (θ) convergestoward 1/2 like in (24).

Equating the required Doherty current (25) with the class Ccurrent provided in (26), we obtain the required auxiliary RFgate voltage amplitude |VGS.a| in terms of the main RF gatevoltage VGS.m:

|VGS.a| =n+ 1

2W(θ)

√α

β

gm.mgm.a

|VGS.m|

−√α

β

Im.maxW(θ)gm.a

+ VT − VGS.dc.a.

We shall select the dc gate bias voltage VGS.dc.a such that:

VT − VGS.dc.a =

√α

β

Im.maxW(θmax)gm.a

,

with θmax the conduction angle at which the auxiliary currentreaches its peak current Ia.max. We can then easily verify thatthe two edge boundary conditions are satisfied:

|VGS.a(θ=0)| = kmax|VGS.m(θ =0)| = kmax2

gm.m

Im.maxn+ 1

= VT − VGS.dc.a ⇒ Ia(θ=0) = 0

|VGS.a(θmax)| = kmax|VGS.m(θmax)| ⇒ Ia(θmax) = Ia.max,

with the coupler ratio kmax given by:

kmax =n+ 1

2W(θmax)

√α

β

gm.mgm.a

.

Clearly there exits a unique coupler ratio kmax for which therequired generalized Doherty operation specified by (25) isexactly achieved by the auxiliary transistor operating in classC at both θ = 0 (back-off) and θmax (peak power).

ACKNOWLEDGMENT

The authors are also grateful to the anonymous reviewersfor in depth feedback and invaluable suggestions for improvingthe manuscript.

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16

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PLACEPHOTOHERE

Haedong Jang (S’09-M’14) was born in Wonju,Korea, in 1971. He received the B.S. degree inelectrical engineering from Kangwon National Uni-versity, Chuncheon, Korea, in 1994. He joined a non-profit governmental organization, Small BusinessCorporation, Shiheung, Korea, in 1996. He servedas a product development assistant consultant until2007 and had involved in more than 100 com-mercialized consumer product developments. Duringthat time, he received M.S. and Ph.D. (ABD) degreesin electrical and computer engineering from Inha

University, Incheon, Korea, in 2005 and 2008, respectively. He received Ph.D.degree in electrical and computer engineering from The Ohio State University,Columbus, OH in 2014. He joined Infineon Technologies North AmericaCorp., Morgan Hill, CA as an advanced development RF engineer in 2014.

His main interests include advanced RF power amplifier architecture, non-linear devices characterization, modeling, and power amplifier linearization.

Dr. Jang was a co-recipient of the first place in 2012 IEEE MicrowaveTheory and Techniques Society (IEEE MTT-S) International MicrowaveSymposium (IMS) student development of a Large-Signal-Network-Analyzer-Round-Robin Design Competition.

PLACEPHOTOHERE

Patrick Roblin (M’85) was born in Paris, France,in September 1958. He received the Maitrise dePhysics degree from the Louis Pasteur University,Strasbourg, France, in 1980, and the M.S. and D.Sc.degrees in electrical engineering from WashingtonUniversity, St. Louis, MO, in 1982 and 1984, re-spectively. In 1984, he joined the Department ofElectrical Engineering, at The Ohio State University(OSU), Columbus, OH, as an Assistant Professorand is currently a Professor. His present researchinterests include the measurement, modeling, design

and linearization of non-linear RF devices and circuits such as oscillators,mixers, and power-amplifiers. He is the first author of a textbook on High-Speed Heterostructure Devices published by Cambridge University Press. Heis the founder of the Non-Linear RF research lab at OSU. He has developedat OSU two educational RF/microwave laboratories and associated curriculumfor training both undergraduate and graduate students.

PLACEPHOTOHERE

Yiqiao Lin is a doctoral candidate at The OhioState University, Columbus, OH, USA. Her currentresearch interests are in microwave circuit design forwireless communication systems. Her current workfocuses on the development of concurrent dual bandenvelope tracking power amplifier for basestations.

PLACEPHOTOHERE

Robert D. Pond received the B.S. Degree in elec-trical engineering from The Ohio State University,Columbus, OH, USA, in 2013. He is currently work-ing toward the M.S. degree in electrical engineeringfrom The Ohio State University, Columbus, OH,USA, under the advisement of Professor PatrickRoblin.

His research interest include design of UWB, highefficiency, MMIC power amplifiers.