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ASSIGNMENT NO:1

CHAPTER NO-1

Compare microprocessors 8085 and 8086

List any four features of 8086.

1) It is a 16 bit μp.

2) 8086 has a 20 bit address bus can access up to 220 memory locations (1MB).

3) It can support up to 64K I/O ports.

4) It provides 16-bit registers. AX,BX,CX,DX,CS,SS,DS,ES,BP,SP,SI,DI,IP &

FLAG REGISTER.

5) It has multiplexed address and data bus AD0-AD15 and A16 – A19.

6) 8086 is designed to operate in two modes, Minimum and Maximum.

7) It can prefetches up to 6 instruction bytes from memory and queues them in order

to speed up instruction execution.

8) Interrupts:-8086 has 256 vectored interrupts.

9) Provides separate instructions for string manipulation.

10) Operating clock frequencies 5MHz, 8MHz, 10MHz.

Draw the functional block diagram of 8086 microprocessor and describe instruction queue in

detail.

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To implement any instruction first it is to be fetched, then decoded and then executed. The fetching of

an instruction involves its address to be sent out to the system memory and then the memory sending

back the instruction.

While the EU is busy decoding or executing certain instructions which do not need the buses, the BIU

fetches next six instruction bytes and stores them in a first-in-first-out (FIFO) register set called queue.

The processor doesn't have to wait for the next instruction to be fetched as it is already made available

in the queue registers. Thus, the speed of operation is enhanced. This prefetching of next instruction

while another instruction is still being executed is known as pipelining.

Draw the pin diagram of 8086. (4M)

Describe functions of following pins of μP 8086:

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Pin Discription: AD15-AD0:-These pins acts as multiplexed address and data bus of the

microprocessor. Whenever the ALE pin is high these pins carry the

address, when the ALE pin is low it carry the data.

A19/S6-A16/S3:- These pins are multiplexed to provide the address signals A19-A16

and the status bits S6-S3. When ALE=1 these pins carry the

address and when ALE=0, they carry the status lines.

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Most imp pins are:-

Describe Register Organization of 8086 :-

All the registers of 8086 are 16-bit registers. The general purpose registers can be

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used as either 8-bit registers or 16-bit registers.

The register set of 8086 can be categorized into 4 different groups. The register

organization of 8086 is shown in the figure.

General Data Registers:

(i) General Purpose Registers of 8086 1. AX is used as 16-bit accumulator. The lower 8-bit is designated as AL and higher 8-bit

is designated as AH. AL can be used as an 8-bit accumulator for 8-bit operation.

2. BX is a 16 bit register, but BL indicates the lower 8-bit of BX and BH indicates the higher 8-bit

of BX.

3. CX acts as a counter for repeating or looping instructions.

4. DX Used with AX to hold 32 bit values during multiplication and division.

Used to hold address of I/O port in indirect addressing mode.

5. BP Base Pointer BP can hold offset address of any location in the stack segment. It is used to

access random locations of stack.

6. SP Stack Pointer – Contains the offset of the top of the stack.

SP is used with SS register to calculate 20-bit physical address.

Used during instructions like PUSH,POP,CALL,RET etc.

7. SI Source Index – Used in string movement instructions. Holds offset address

of source data in Data segment during string operations. Used to hold offset address of data segment.

8.DI Destination Index – acts as the destination for string movement instructions

Used to hold offset address of Extra segment.

9.IP – Instruction Pointer – Contains 16 bit offset address of instruction that is to

Be executed in code segment

Segment Registers:

The 8086 architecture uses the concept of segmented memory. 8086 able to address to

address a memory capacity of 1 megabyte and it is byte organized. This 1 megabyte

memory is divided into 16 logical segments. Each segment contains 64 kbytes of

memory.

There are four segment register in 8086

1. CS – Code Segment – holds base address for all executable instructions in a program

2. SS - Stack Segment- holds the Base address of the stack

3. DS – Data Segment – default base address for variables.

4. ES – Extra Segment – additional base address for memory variables in extra segment

Pointers and Index Registers.

The pointers contain offset within the particular segments.

- The pointer register IP contains offset within the code segment.

- The pointer register BP contains offset within the data segment.

- He pointer register SP contains offset within the stack segment.

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The index registers are used as general purpose registers as well as for offset storage

in case of indexed, base indexed and relative base indexed addressing modes.

The register SI is used to store the offset of source data in data segment.

The register DI is used to store the offset of destination in data or extra segment.

The index registers are particularly useful for string manipulation.

Flag Register:

The 8086 flag register contents indicate the results of computation in the ALU. It also

contains some flag bits to control the CPU operations.

Flag Register:

A 16 flag register is used in 8086. It is divided into two parts .

(a) Condition code or status flags

(b) Machine control flags

The condition code flag register is the lower byte of the 16-bit flag register. The

condition code flag register is identical to 8085 flag register, containing CF carry flag,

PF parity flag, AF auxiliary carry flag, ZF zero flag, SF Sign flag ,OF overflow flag.

The control flag register is the higher byte of the flag register. It contains three flags

namely direction flag (D), interrupt flag (I) and trap flag (T).

Draw the flag register format of microprocessor 8086 and explain any two flags.

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6 ARE STATUS FLAG AND 3 ARE CONTROL FLAGS

Carry flag: This flag is set when there is a carry out of MSB in case of addition or a borrow in case of

subtraction.

Parity flag: This flag is set, if the lower byte of the result contains even numbers of 1s

Auxiliary carry flag : this is set if there is a carry from the lowest nibble, i.e. bit three during

addition or borrow for the lowest nibble i.e. bit three during subtraction.

Zero flag: This flag is set if the result of the computation or comparison performed by previous

instruction is zero.

Sign flag: this flag is set when the result of any computation is negative. For signed computations

the sign flag equals the MSB of the result.

Trap flag if this flag is set the processor enters the single step execution mode.

ignored.

Direction flag: This flag is used by string manipulation instructions. If this flag bit is „0‟ the string

is processed beginning from the lowest address to the highest address, otherwise the string is

processed from the highest address towards lowest address.

Overflow flag: This flag is set if an overflow occurs.

State the concept of pipelining of 8086.

Ans.: concept of pipeline: (2 Mark)

parallel.

instructions code is fetches. When first

instruction is getting executed, second ones is decoded and third instruction code is fetches from

memory. This process is known as pipelining. It improves speed of operation to great extent.

Explain the concept of pipelining in 8086 microprocessor with diagram. OR (4MARKS)

Description: Process of fetching the next instruction while the current instruction is executing is

called pipelining which will reduce the execution time. The technique used to enable an instruction to

complete with each clock cycle. Normally, on a non – pipelined processor, nine clock cycles are

required for fetch, decode and execute cycles for the three instructions as shown in Fig (a).

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This takes longer time when compared to pipelined processor. In this ,the fetch, decode and execute

operations are performed in parallel, so only five clock cycles are required to execute the same three

instructions as shown Fig(b).

In 8086, pipelining is implemented by providing 6 byte queue where as long as 6 one byte instructions

can be stored well in advance and then one by one instruction goes for decoding and executions. So,

while executing first instruction in a queue, processor decodes second instruction and fetches 3rd

instruction from the memory In this way, 8086 perform fetch, decode and execute operation in parallel

i.e. in single clock cycle as shown in above fig (b)

What is pipelining? How it is implemented in 8086 microprocessor. Definition:

which will reduce the execution time.

Description:

8086, pipelining is the technique of overlapping instruction fetch and execution mechanism.

from memory.

bytes.

execution unit to receive other instruction.

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BIU stores the fetched instructions in a 6 byte FIFO queue. The BIU can be fetching instructions bytes

while the EU is decoding an instruction or executing an instruction which does not require use of the

buses.

BIU.

ding out an address to the system memory and waiting for memory to

send back the next instruction byte or bytes.

Describe concept of memory segmentation of 8086.

Memory Segmentation:

The memory in an 8086 microprocessor is organized as a segmented memory. The physical memory is

divided into 4 segments namely,-

Data segment, Code Segment, Stack Segment and Extra Segment.

Description:

Data segment is used to hold data, Code segment for the executable program, Extra

segment also holds data specifically in strings and stack segment is used to store

stack data.

Each segment is 64Kbytes & addressed by one segment register.

The 16 bit segment register holds the starting address of the segment.

The offset address to this segment address is specified as a 16-bit displacement (offset) between

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0000 to FFFFH.

Since the memory size of 8086 is 1Mbytes, total 16 segments are possible with each

having 64Kbytes.

Give the steps in physical address generation in 8086 microprocessor.

Generation of 20 bit physical address in 8086 :- 1. Segment registers carry 16 bit data, which is also known as base address.

2. BIU appends four 0 bits to LSB of the base address. This address becomes 20-bit address.

3. Any base/pointer or index register carries 16 bit offset.

4. Offset address is added into 20-bit base address which finally forms 20 bit physical address of

memory location.

With the help of diagram, describe physical memory address generation of 8086.

Formation of a physical address OR Generation of 20 bit physical address in 8086 :-

1. Segment registers carry 16 bit data, which is also known as base address.

2. BIU appends four 0 bits to LSB of the base address. This address becomes 20-bit address.

3. Any base/pointer or index register carries 16 bit offset.

4. Offset address is added into 20-bit base address which finally forms 20 bit physical address of

memory location.

Example:- Assume DS= 2632H, SI=4567H

DS : 26320H ……...0 added by BIU(or Hardwired 0)

+ SI : 4567H ----------------------------

2A887H

Physical:

Calculate physical address in the following cases: (2M each)

i) CS: 1200H, IP:DE00H

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ii) DS: 1F00, BX:1A00 for MOV AX,[BX]

Calculate the physical address for given :

(i) DS = 73A2H SI =3216H

(ii) CS = 7370H IP = 561EH

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What will be the content of register BX after execution of instruction ?

4 M

MOV BX 2050H

MOV CL 05H

SHL BX CL

Draw and explain interface of 8284 clock generated with 8086

1. Generate system clock: The Clock logic results in three different frequencies required for the

system. These outputs are CLOCK, OSC and PCLK.

2. Generate READY signal: The Ready logic has a READY output which is connected to the

processor. When this is low, wait states are added in the bus cycle.

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3. Generate RESET signal: The Reset logic generates a RESET input for the microprocessor. When

this signal is High, processor performs reset sequence.

Compare maximum mode and minimum mode configurations of 8086(any four points).

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Draw and explain the timing diagram of 8086 in minimum mode.

In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by

strapping its MN/ pin to logic 1.

timing diagrams.

-code fetch and read cycles are similar. Hence the timing diagram can be categorized in two

parts, the first is the timing diagram for read cycle and the second is the timing diagram for write

cycle.

ess latch enable (ALE) signal and also M / signal. During the negative going edge of this signal, the valid address is latched on the local bus.

a memory or I/O operation.

The read ( ) control signal is also activated in T2.

) signal causes the address device to enable its data bus drivers. After goes low, the

valid data is available on the data bus.

to high level, the addressed device will again tri-state its bus drivers

A write cycle also begins with the assertion of ALE and the emission of the address. The M/ signal

is again asserted to indicate a memory or I/O operation.

addressed

location.

The data remains on the bus until middle of T 4 state. The WR becomes active at the beginning of T 2

(unlike is somewhat delayed in T 2 to provide time for floating).

and A0 signals are used to select the proper byte or bytes of memory or I/O word to be

read or write.

, and signals indicate the type of data transfer.

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State the maximum size of memory that can be interfaced with microprocessor 8086. Why? Ans.: In 8086 microprocessor the total memory addressing capability is 1 mega bytes

For representing 1 MB there are minimum 4 hex digits are required i.e., 20 bits. but 8086 has

fourteen 16-bit registers. That is there are no registers for representing 20 bit address. So, the total

memory is divided into 16 logical segments and each segment capacity is 64 KB (kilo bytes). That is

16*64kb=1 MB. So, for representing 64 kb only 16 bit register is sufficient.

State all control signal generated by S0, S1, S2 with their function of 8086

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Draw and describe the maximum mode diagram of 8086.

Maximum mode Configuration: