asic design engineer/ vlsi desing engineer cv

SYED SOOBAAN MOHIUDDIN QUADRI -CV [email protected] +971 566 108 469

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SYED SOOBAAN MOHIUDDIN QUADRI Mobile No UAE : +971-56-610-8469

Email : [email protected]

Visa Status : Visit Visa till 4th may, 2016

PROFESSIONAL SUMMARY:

Versatile advanced Research Assistant VLSI Design Engineer with exceptional skills and more than two years of experience in analyzing, designing, verifying and debugging of test cases on System Verilog, System Verilog Assertion &Verilog modelling. Highly-skilled in SOC, CMOS digital design flow, ASIC flow: RTL Coding and Verification, FPGA, CPLD, CMOS VLSI Designs.

PROFESSIONAL WORK EXPERIENCE:

Company Name : E-Systems Pvt. Ltd.

Tenure : Nov 2013 – Jan 2016 Designations : VLSI Design Engineer (Nov’13 - Jan’16) Hardware Description Language: VHDL, Verilog. Hardware Verification Language: System Verilog. Scripting Language : Perl. Programming Language : Matlab, C. Responsibilities : Design and Verification on Block and Full Chip Level RTL Verification Sy st em o n

C h i p , ASIC flow: RTL Design and Verification, Synthesis, layout and schematics, timing constraints, FPGA, CPLD, Logic Design, CMOS digital design flow VLSI Designs, IP core.

Simulating and synthesizing using EDA tools like Cadence, Modelsim and Xilinx ISE respectively. Work with team as well as an independent on writing behavioral codes in VHDL and Verilog and fixing bugs for RTL and Test Bench failures. Provide assistance to Design teams in fixing bugs for RTL and TB at client side.

Develop new test cases for missing scenarios and supporting the customers.

Training/Certification : VLSI Design / ASIC Design Institute : E-Systems Pvt. Ltd., Hyderabad Tenure : July 2013 – Oct 2013 Aspects Covered : ASIC Design Flow.

Combinational and Sequential Logic Circuits Modeling.

System Verilog, VHDL and Verilog Fundamentals.

Dataflow, Structural and Behavioral Modeling. Verilog Synthesis and FPGA Applications. Tools and Projects Explanations.

Training/Certification : Programming in C, Core JAVA, Advanced JAVA and J2EE Institute : Orbit Technology Research Pvt. Ltd., Hyderabad Tenure : Aug 2012 – Nov 2012 Aspects Covered in C : Loops, strings, Structures, Unions, Arrays and Pointers etc. Aspects Covered in JAVA Class, Object Concepts, Variables, Operators, Loops, Methods, Constructors. GUI (Swing, AWT, Applets), File, Input, String Handling, Multi-Threading.

Networking in java, Serialization, Exception Handling. JSP, Servlet, Hibernate, Spring, Struts, Web Services.

PROJECT SUMMARY:

FRONTEND PROJECTS ORGANIZATION : Esystems, Hyderabad. EDA TOOLS : Modelsim, Xilinx.

mailto:[email protected]



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LANGUAGE : Verilog. PROJECTS DURATION : 2 - 4 Months (for each Project). MEMBERS INVOLVED : 2 - 5 (for each Project). ROLE : Develop function design of module in system-on-chip(SOC), using software and design

tools, and implement it in coordination with other design teams in SOC design PROJECT 1 : PIPELINED ARCHITECTURES FOR REAL-VALUED FFT AND HERMITIAN-SYMMETRIC IFFT

WITH REAL DATAPATHS PROJECT DESRIPTION : This is a key requirement for the design of architectures that are based on real data-paths.

This structure is then mapped to pipelined architectures. PROJECT 2 : A FUSED FLOATING-POINT THREE-TERM ADDER PROJECT DESRIPTION : The fused floating-point three-term adder performs two additions in a single unit to

achieve better performance and better accuracy compared to a network of traditional floating-point two-term adders.

PROJECT 3 : DESIGN OF CACHE CONTROLLER WITH CACHE MEMORY USING VHDL LANGUAGE : VHDL. PROJECT DESRIPTION : We investigate the configuration of productive cache controller suitable for use in FPGA-

based processors. Semiconductor memory which can work at velocities comparable with the operation of the processor exists; it is not sparing to give all the fundamental memory with fast semiconductor memory.

PROJECT 4 : DESIGN AND SIMULATION OF 32-POINT FFT USING RADIX-2 ALGORITHM FOR FPGA

IMPLIMENTATION PROJECT DESRIPTION : This paper concentrates on the development of the Fast Fourier Transform (FFT), based on

Decimation-In-Time (DIT) domain, Radix-2 algorithm.

BACKEND PROJECTS ORGANIZATION : Esystems, Hyderabad. EDA TOOLS : DSRC, Microwind ROLE : Develop logic design of circuit in system-on-chip(SOC), using design tools, and implement it

in coordination with other design teams in SOC design PROJECT 1 : FULLY REUSED VLSI ARCHITECTURE OF FM0/MANCHESTER ENCODING USING SOLS

TECHNIQUE FOR DSRC APPLICATIONS. PROJECT DESRIPTION : The DSRC standards generally adopt FM0 and Manchester codes to reach dc-balance,

enhancing the signal reliability. This paper not only develops a fully reused VLSI architecture, but also exhibits an efficient performance compared with the existing works.

PROJECT 2 : RECURSIVE APPROACH TO THE DESIGN OF A PARRALLEL SELF-TIMED ADDER. PROJECT DESRIPTION : This brief presents a parallel single-rail self-timed adder. It is based on a recursive

formulation for performing multibit binary addition Simulations have been performed using an industry standard toolkit that verify the practicality and superiority of the proposed approach over existing asynchronous adders.

ACADEMIC QUALIFICATION:

Graduation (Degree) : Bachelor of Technology [Electronics and Communication Engineering] - 2013 University : Jawaharlal Nehru Technological University Hyderabad, India.

Intermediate : Board of Intermediate – 2009 University/College : Neo Quantum Junior College, Hyderabad, India.

ACADEMIC PROJECTS:



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MAJOR PROJECT: Company Name : Amyatech, Hyderabad, India. Project : Secured Wireless Communication for Industrial

Automation. Project Description : The PC will continuously monitor all the data from remote

processing unit and compare with value preloaded process structure. If any error is found the PC takes necessary actions. All the ZigBee’s are interconnected with processing unit through RS232 protocol.

MINI PROJECT:

Company Name : Amyatech, Hyderabad, India.

Project : Solar Tracking System. Project Description : Microcontroller tracks and generates power from sunlight the power generates from this

process is then stored in a lead acid battery and is made to charge an emergency light to glow with the help of solar panel.

INTERPERSONAL COMMUNICATION SKILLS:

Flair to organize & prioritize tasks to meet deadlines Have a good level command over English, Hindi and Urdu Languages. Outstanding command over verbal and non-verbal communicative & interpersonal skills. Strong problem solving, interpersonal and negotiation skills. Ability to manage multiple projects with minimal supervision. Confidently able to work independently or in a team to deal effectively with educators & employees. Ability to write research papers

SOFTWARE SKILLS:

Xilinx ISE (Synthesis). ModelSim (Synopsys). Microwind. DSCH. Cadence. Tanner. VCS. MS office. Mac OSX. Windows OS. Linux.

HOBBIES:

Designing, Drawing, Cricket, PC Games, Chess.

PERSONAL PROFILE:

Father’s name : Syed Chiragh Mohiuddin Quadri

Marital Status : Single

Date of Birth : 11-Jun-1993

Nationality : Indian

Passport No. : M4476994

Religion : Islam

Languages Known : English, Hindi and Urdu

DECLARATION:

I, hereby declare and confirm that the information provided above is true and correct to the best of my knowledge.

SYED SOOBAAN MOHIUDDIN QUADRI
