Reg. No. :

M.E. DEGREE EXAMINATION, APRIL/MAY 2011

Elective

VLSI Design

VL 9261 — ASIC DESIGN

(Common to M.E. Computer and Communication and M.E. Applied Electronics)

(Regulation 2009)

Time : Three hours Maximum : 100 marks

Answer ALL questions

PART A — (10 × 2 = 20 marks)

1. Draw a symbol for a transmission gate and list its features.

2. Compare Wallace tree multiplier with Dadda multiplier.

3. Draw a static RAM cell.

4. What do you mean by supply source and ground bounce?

5. Compare Altera Max 9000 and Altera Flex interconnect architectures.

6. What is a schematic screener? Specify its purpose.

7. What are the commonly used FSM encoding options?

8. What is the difference between logic synthesis and simulation?

9. List out the goals and objectives of global routing.

10. Distinguish between constructive placement and iterative placement.

PART B — (5 × 16 = 80 marks)

Question Paper Code : 77914

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77914 2

11. (a) (i) Write short notes on standard cells and gate arrays. (10)

(ii) Design a 4-bit carry look ahead adder. (6)

Or

(b) (i) Explain the various parasitic capacitances in a MOS transistor.(8)

(ii) Show that for a small VDS, an NMOS transistor look like a

resistor with ( )

tnDDnVVB

R−

=1

. (4)

(iii) If DDGSVV = and OV

DS= , 2

200 vAKn

µ= . Find the pull

resistance R for a 6.06 transistor is linear region. (4)

12. (a) (i) Write short notes on EPROM and EEPROM technologies used in Xilinx EPLD and Altera Max 5000 EPLD. (8)

(ii) Consider the junction DCBBAF +⋅′+⋅= . Use Shannon’s

expansion theorem to expand F with respect to B 21 FBFBF ⋅′+⋅= . (8)

Or

(b) (i) Write short notes on meta stability. (8)

(ii) Draw and explain the block diagram of a Xilinx 4000 series IO Block. (8)

13. (a) (i) Discuss in detail about low level design languages. (8)

(ii) Write short notes on EDIF. (8)

Or

(b) (i) Draw and explain the block diagram of an Altera Max Interconnect scheme. (8)

(ii) Discuss in detail about logic synthesis. (8)

14. (a) What is Built in Self test? Discuss any three BIST architectures in detail.

Or

(b) (i) Explain the different categories of simulation. (8)

(ii) Discuss step involved in a D-algorithm to detect struck at faults with a suitable example. (8)

15. (a) Explain in detail about Kernighan-Lin partitioning algorithm.

Or

(b) (i) Explain Left Edge algorithm that is employed for restricted channel routing. (8)

(ii) Write short notes on SPF, RSPF and DSPF. (8)

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