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Date: Jan 2016

Revision: 1.0

Arria 10 Low Latency Ethernet 10G MAC and XAUI

PHY Design Example User Guide

2

Table of Contents

Introduction .................................................................................................................................................. 3

System Architecture ...................................................................................................................................... 4

Design Components ...................................................................................................................................... 6

Low Latency Ethernet 10G MAC ............................................................................................................... 6

XAUI PHY ................................................................................................................................................... 6

Traffic Controller ....................................................................................................................................... 6

Ethernet Packet Generator ................................................................................................................... 6

Ethernet Packet Monitor ...................................................................................................................... 6

MDIO ......................................................................................................................................................... 7

JTAG to Avalon Master Bridge .................................................................................................................. 7

Reset Controller ........................................................................................................................................ 7

Avalon-ST Single clock FIFO ...................................................................................................................... 7

Avalon-ST Adapter .................................................................................................................................... 7

PLL ............................................................................................................................................................. 8

System Register Map .................................................................................................................................... 9

Generator Register Map ........................................................................................................................... 9

Monitor Register Map ............................................................................................................................. 10

Interface Signals .......................................................................................................................................... 11

Clock and Reset Signals ........................................................................................................................... 11

Using the Design Example ........................................................................................................................... 12

Hardware Requirements ......................................................................................................................... 12

Software Requirements .......................................................................................................................... 12

Setting up the Arria 10® FPGA Development Kit .................................................................................... 12

Setting up the Dual XAUI to SFP+ HSMC board ...................................................................................... 13

TCL Commands........................................................................................................................................ 14

Hardware Test on the Design Example ................................................................................................... 15

Simulation Test on the Design Example .................................................................................................. 17

Document Revision History ......................................................................................................................... 20

3

Introduction This design example demonstrates Low Latency Ethernet 10G IP solution for Arria

10® device using Altera® Low Latency Ethernet 10G Media Access Controller

(MAC) and Altera® XAUI PHY IP cores with a Dual XAUI small form factor pluggable

plus (SFP+) high-speed mezzanine card (HSMC) board and FPGA mezzanine card

(FMC) to high-speed mezzanine card (HSMC) adapter board on Altera® Arria 10®

FPGA development kit. It provides flexible test and demonstration platforms on

which you can control, test, and monitor the Ethernet operations using system

loopback at various points.

This reference design offers the following features:

Loopback points that include XGMII and serial physical medium attachment

(PMA) interface in the Arria 10® GX FPGA development board, and PMA

interface in the Broadcom® PHY BCM8727 chip on the Dual XAUI to SFP+

HSMC board.

External optical loopback test at HSMC board SFP+ modules.

Sequential random bursts tests. You can configure the number of packets,

payload-data type, and payload size for each burst.

Packet statistics for traffic generator, monitor, MAC transmitter (TX) and

MAC receiver (RX).

Packet classification for different frame sizes transmitted and received by

the MAC.

Throughput for the traffic received by the traffic monitor.

System Console user interface. This TCL-based user interface allows you to

dynamically configure and monitor any registers in the reference design.

4

System Architecture Figure 1 shows a high level overview of the system architecture and Figure 2

shows the block diagrams on clocking and reset scheme for Ethernet subsystem.

Figure 1: System Architecture Overview

Arria 10® FPGA Development Kit

Arria 10® GX FPGA

10GBASE-X Ethernet Subsystem

JTAG

PC and System

Console Subsystem

FMCB

FMC to HSMC adapter board

Dual XAUI to SFP+ HSMC Board

BCM8727 SFP+

SFP+

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Figure 2: Clocking and reset scheme of Ethernet Subsystem

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Design Components

Low Latency Ethernet 10G MAC The Low Latency Ethernet 10G MAC IP core handles the flow of data through the

XAUI PHY IP core. On the transmit path, the MAC accepts client frames and

constructs Ethernet frames before forwarding them to the PHY layer. Similarly on

the receive path, the MAC accepts Ethernet frames via PHY, perform checks and

removed the relevant fields before forwarding the frames to the client. The MAC

used the memory-based statistics counters for this reference design.

XAUI PHY The XAUI PHY IP core is set to soft XAUI type by default.

Traffic Controller The traffic controller consists of traffic generator and traffic monitor. The traffic

generator injects client packet bursts into MAC TX and traffic monitor received

packet bursts from MAC RX. This traffic controller connects to the Avalon single-

clock FIFO in Ethernet subsystem through Avalon-ST interface.

Ethernet Packet Generator

This module consists of Avalon-MM registers, Ethernet packet generation block,

CRC generator and shift register.

Ethernet Packet Monitor

This module will verifies the payload of received packets and collect the statistic

counter information. It consists of CRC checker and Avalon-MM registers.

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MDIO The MDIO IP core enables you to control the Broadcom® PHY BCM8727 chip on

the dual XAUI to SFP+ HSMC board. You can access the external PHY registers

through a pair of indirect registers to specify read or write operation, register

address, port address and device address.

JTAG to Avalon Master Bridge This IP core provides a connection between the System Console and Qsys system

through the physical interfaces. The System Console can initiate Avalon Memory-

Mapped (Avalon-MM) transactions by sending encoded streams of bytes through

the bridge’s physical interfaces.

Reset Controller This module is used to synchronize and generate signals as per design

requirements.

Avalon-ST Single clock FIFO The Avalon-ST single-clock FIFO buffer receives and transmits data between the

MAC and the client. The buffer operates in store-and-forward mode by default.

Avalon-ST Adapter This adapter used to convert the 32-bit interface of Avalon ST to 64 bit and vice

versa.

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PLL Arria 10® ATX PLL takes an input clock from a 156.25MHz from on-board oscillator

as the clock source for the XAUI PHY. Arria 10® fPLL takes an input clock 100MHz

from on-board oscillator and act as the clock source for the others components in

this reference design.

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System Register Map Table 1 lists all the base addresses for components on the subsystems. Traffic

controller register map details show on table 2 and table 3.

Component Base Address

Low Latency 10G MAC 0x00000000

XAUI PHY 0x00008000

Generator 0x0000C000

Monitor 0x0000C400

Ethernet MDIO 0x0000B000

Avalon-ST Single-Clock FIFO (RX) 0x00009400

Avalon-ST Single-Clock FIFO (TX) 0x00009600

Table 1: System Register Map

Generator Register Map

Table 2: Generator Register Map

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Monitor Register Map

Table 3: Monitor Register Map

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Interface Signals This section describes the signals available on the top level for the reference

design.

Clock and Reset Signals Signal Direction Width Description

csr_clk Input 1 Configuration clock for AVMM interface, frequency is 100MHz.

csr_rst_n Input 1 Reset AVMM interface.

tx_312_5_clk Input 1 312.5MHz clock for MAC TX data path.

rx_312_5_clk Input 1 312.5MHz clock for MAC RX data path.

tx_156_25_clk Input 1 156.25MHz clock for MAC TX data path.

rx_156_5_clk Input 1 156.25MHz clock for MAC RX data path.

tx_rst_n Input 1 Active-low reset for MAC TX data path.

rx_rst_n Input 1 Active-low reset for MAC RX data path.

xgmii_156_25_clk Output 1 156.25MHz output clock from fPLL.

mac_312_5_clk Output 1 312.5MHz output clock from fPLL.

pll_ref_clk Input 1 Reference clock for ATXPLL, fPLL, and

XAUI PHY.

Table 4: Clock and reset signals

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Using the Design Example This section describes the required hardware and software setup.

Hardware Requirements To run this reference design, you need the following hardware available:

Arria 10® FPGA development kit (board revision rev D)

Dual XAUI to SFP+ HSMC board

FMC to HSMC adapter board

USB-Blaster cable

SFP+ module with loopback cable

Software Requirements To run this reference design, you also require the following software:

Quartus II® version 15.1

Windows or Linux based system console

USB-Blaster driver

ModelSim® Simulator

Setting up the Arria 10® FPGA Development Kit Figure 3 shows the Arria 10® FPGA development kit. The development kit has a

stop button for system console testing operation purpose, reset button for the

Ethernet subsystem and reset button for the Dual XAUI to SFP+ HSMC board.

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Figure 3: Arria 10® FPGA Development Kit

Setting up the Dual XAUI to SFP+ HSMC board Figure 4 shows the Dual XAUI to SFP+ HSMC board. You need the FMC to HSMC

adapter board to connect between the Arria 10® FPGA development kit and the

Dual XAUI to SFP+ HSMC board. Install jumper at J13 and J14 shows on figure 4.

You must plug the adapter board and HSMC board into the FMCB of Arria 10®

FPGA development kit and install an SFP+ module with a loopback cable in the

upper SFP+ slot (CH2). The HSMC board does not require a separate power supply

as it draws power from Arria 10® FPGA development kit.

Reset button for Ethernet

subsystem

Reset button for Dual XAUI to SFP+

HSMC board

Stop button for traffic controller

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Figure 4: Full Hardware System

TCL Commands This reference design provides various Tcl commands to test the Arria 10® FPGA

development board and the Dual XAUI to SFP+ HSMC board in various loopback

modes. Table 5 lists all the Tcl commands that supported for this reference

design.

Command Mode/Values Description

LPBK_POINT

SFPP Loopback at SFP+ cable

BCMPMA Loopback at BCM8727 PMA

BCMXGXS Loopback at BCM8727 XGXS

ALTPMA Loopback at Altera® serial PMA

BURST_SIZE Any integer Number of packets in the burst.

NUM_BURSTS Number greater than 0 Specifies the intended number of bursts.

Table 5: Commands to Test the reference design

Ensure that jumpers are

installed on J13 and J14

SFP+ module with

loopback cable on CH2 Dual XAUI to

SDP+ HSMC

board

FMC to HSMC

adapter board

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Hardware Test on the Design Example To perform hardware rest, follow these steps:

1. Download and restore the design example from Design Store.

2. Launch the Quartus II software and open the project file (top.qpf).

3. Click Start Compilation on the Processing menu to compile the design

example.

4. Configure the FPGA using the generated configuration file (top.sof).

5. After configuration done, open the Clock Control tool to change the

frequency for U14 CLK2 to 156.25 MHz.

Figure 5: Clock Controller GUI

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6. Reset the Ethernet system and HSMC board using the push button

mentioned on Figure 3. (Note: System must be reset for the beginning of a

new test stated at step 10)

7. On Quartus II menu, click on Tools>System Debugging Tools and then

launch the System Console.

8. In the System Console command shell, change the directory to

“system_console” directory.

9. Run the command : source demo.tcl

10. Perform the following tests by running the command in the command shell.

Refer to Table 5 for all the modes supported for this design:

a. The format for the tcl command test is TEST <LPBK_POINT>

<BURST_SIZE> <NUM_BURSTS>

b. To perform SFP+ loopback test (External loopback at the SFP+ cable)

i. Command: TEST SFPP 10000 1

Each test generates a log file in text file format. View the

log to ensure that the traffic monitor does not receive

bad packets. It also provides packet classification and

statistics by the MAC TX and RX.

Perform step 5 reset using push buttons after the test is

completed.

c. To perform BCM8727 PMA loopback test

i. Command: TEST BCMPMA 10000 1

Each test generates a log file in text file format. View the

log to ensure that the traffic monitor does not receive

bad packets. It also provides packet classification and

statistics by the MAC TX and RX.

Perform step 5 reset using push buttons after the test is

completed.

d. To perform BCM8727 XGXS loopback test

i. Command: TEST BCMXGXS 10000 1

Each test generates a log file in text file format. View the

log to ensure that the traffic monitor does not receive

17

bad packets. It also provides packet classification and

statistics by the MAC TX and RX.

Perform step 5 reset using push buttons after the test is

completed.

e. To perform PMA serial loopback test

i. Command: TEST ALTPMA 10000 1

Each test generates a log file in text file format. View the

log to ensure that the traffic monitor does not receive

bad packets. It also provides packet classification and

statistics by the MAC TX and RX.

Perform step 5 reset using push buttons after the test is

completed.

Simulation Test on the Design Example To run simulation on this reference design, follow these steps:

1. Download and restore the design example from Design Store.

2. Start the ModelSim® SE 10.4b simulator software.

3. Go to the “testbench” directory.

4. In the TCL Console window, type the following commands:

a. Command: do tb_run.tcl

5. At the end of the simulation, ModelSim simulator will generate statistics of

transmitted packets and received packets in the Transcript window.

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Figure 6: TX statistics

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Figure 7: RX statistics

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Document Revision History

Date Version Changes

Jan 2016 1.0 Initial release