IF-3531Pengantar Arsitektur Komputer

PENDAHULUAN

FULL ADDER 1 - Bit

MULTIPLIER 2/4 - Bit

ALU 1 - Bit

ALU 1-Bit and Table

Representasi ALU

ALU1-bit

ALU1-bit

ALU1-bit

ALU1-bit

ALU1-bit

ALU1-bit

ALU1-bit

ALU1-bit

ALUSimbol ALU

CPU and Internal Bus

CPU - Internal Architecture System

MainMemory

Arithmetic and Logic Unit

Program Control Unit

InputOutputEquipment

MBR

Arithmetic & Logic Circuits

MQAccumulator

MAR

ControlCircuits

IBR

IR

PC

Address

Instructions& Data

Central Processing Unit (CPU)

IBR : Instruction Buffer RegisterMBR : Memory Buffer RegisterPC : Program Counter IR : Instruction Register MAR : Memory Address RegisterMQ : Memory Queue

MQ : Multiplier QuotientMBR : Memory Buffer Register

Computer ComponentsTop Level View

Three Memory Management Model

Basic Execution Environment – Intel 32 bit

Model InstruksiTwo Step

INSTRUCTION POINTER

CONTROL UNIT

INSTRUCTION DECODER

CODE CACHE

DATA CACHE

Register Set

CODE

Memory

DATA

FLOATING POINT UNIT

Simplified CPU Block Diagram

Addres Bus

Data Bus

i-CACHE

d-CACHE

Instruction Execution Cycle

• Fetch: Control Unit mengaktifkan instruction berikutnya yang ada dalam antrian instruksi (instruction queue) dan menaikkan angka penunjuk pointer instruksi IP kadang disebut dengan istilah lain program counter (PC).

• Decode: Control Unit memeriksa code instruksi (Decode) yang artinya untuk mengetahui apa yang ingin dilakukan oleh code instruksi tsb. Code instruksi kemudian dilepas ke ALU, dengan melepas signal tertentu ke ALU yang mengindijasikan operasi ALU yang harus dikerjakan.

• Fetch operands: Jika code instruksi memiliki operand yang berlokasi di memory, Control Unit beraksi membaca dan mengambil operand dan mengcopy ke internal registers processor.

• Execute: ALU mengksekusi instruction, internal registers berisi operand dan hasil operasi ALU, dapat pula hasil ALU disimpan ke memory. ALU meng-update status flags untuk menyediakan info bagi OS atau User tentang processor state.

• Store output operand: If the output operand is in memory, the control unit uses a write operation to store the data.

Model InstruksiMulti Step

InstructionFetch

OperandFetch

OperandStore

OperandAddressCalculation

InstructionOperationDecoding

DataOperation

OperandAddressCalculation

InstructionAddressCalculation

Multiple Operand

Multiple Operand

Return for String or vector data

Instruction Complete Fetch Next Instruction

CPU

MEMORY

Processor Instructions Set

Instruction Set : ada 3 Class yang umum• 1. Data movement instructions

– Move data from a memory location or register to another memory location or register without changing its form

– Load—source is memory and destination is register– Store—source is register and destination is memory

• 2. Arithmetic and logic (ALU) instructions– Change the form of one or more operands to produce a result

stored in another location– Add, Sub, Shift, etc.

• 3. Branch instructions (control flow instructions)– Alter the normal flow of control from executing the next

instruction in sequence– Br Loc, Brz Loc2,—unconditional or conditional branches

Data Movement Instruction Instruction Meaning Machine

MOV A, B

LDA A, Addr

LWZ R3, A

LI $3, 455MOV R4, doutIN AL, KBDLEA. L (A0), A2

Move 16 bits from memory location A to Location BLoad accumulator A with the byte at memorylocation AddrMove 32-bit data from memory location A toregister R3Load the 32-bit integer 455 into register $3Move 16-bit data from R4 to output port doutLoad a byte from in port KBD to accumulatorLoad the address pointed to by A0 into A2

VAX11M6800

PPC601

MIPS R3000DEC PDP11Intel PentiumM6800

ALU InstructionInstruction Meaning Machine

MULF A, B, C

nabs r3, r1ori $2, $1, 255DEC R2SHL AX, 4

multiply the 32-bit floating point values at mem loc’ns. A and B, store at CStore abs value of r1 in r3Store logical OR of reg $ 1 with 255 into reg $2Decrement the 16-bit value stored in reg R2Shift the 16-bit value in reg AX left by 4 bit pos’ns.

VAX11

PPC601MIPS R3000DEC PDP11Intel 8086

Instruction Meaning Machine

BLSS A, Tgt

bun r2

beq $2, $1, 32

SOB R4, LoopJCXZ Addr

Branch to address Tgt if the least significantbit of mem loc’n. A is set (i.e. = 1)Branch to location in R2 if result of previousfloating point computation was Not a Number(NAN)Branch to location (PC + 4 + 32) if contents of $1 and $2 are equalDecrement R4 and branch to Loop if R4 ¹ 0Jump to Addr if contents of register CX ¹ 0.

VAX11

PPC601

MIPS R3000

DEC PDP11Intel 8086

Branch Instruction

Format dan pseudo code Instruksi, BERBEDA antar masing-masing mesin prosessor.Namun beberapa pabrikan Processor yang berbeda kadang-kadang menyepakati satu model ISA tertentu.

INSTRUCTION POINTER

CONTROL UNIT

INSTRUCTION DECODER

CODE CACHE

DATA CACHE

Register Set

CODE

Memory

DATA

FLOATING POINT UNIT

Simplified CPU Block Diagram

Addres Bus

Data Bus

i-CACHE

d-CACHE

Format ISA

Operand Address

n bit m bit ; n < m

• Opcode : jenis instruksi operasi processor• Operand Address : Alamat Operand ( Register atau Memory )• Jumlah operand address ISA yang dikenal adalah :

– 4 Address– 3 Address– 2 Address– 1 Address– 0 Address

opcode

4 Address ISA

opcode OpAdd1

n bit 4 x m bit

OpAdd2 OpAdd3 OpAdd4

Contoh :

ADD R3, R1, R2, R4 artinya : R3 R1 + R2

R1, R2, R3, dan R4 adalah Register

Biasanya digunakan dengan urutan sebagai berikut : R3 R1 + R2 R4 berisi alamat instruksi berikutnya (PC PC + 1)

3 Address ISA

OpAdd1

n bit 3 x m bit

OpAdd2 OpAdd3

Contoh :

SUB R3, R1, R2 artinya : R3 R1 – R2

opcode

2 Address ISA

OpAdd1

n bit 2 x m bit

OpAdd2

Contoh :

MOV R1, R2 artinya : salin isi R2 ke R1 : R1 R2

Untuk menghtung : R3 R1 * R2, digunakan dengan urutan sebagai berikut : MOV R3, R1 MUL R3, R2 jika diperhatikan perintahnya menjadi 2 baris ….!

opcode

1 Address ISA

n bit 4 x m bit

Operand Address

Contoh :

MUL R4

Bagaimana dengan : R3 R1 + R2

LOAD R1 ADD R2 STORE R3

perhatikan jumlah instruksi menjadi 3 baris

opcode

0 Address ISA

opcode

n bit

Contoh : C A + B

PUSH A PUSH B ADD POP C

Machine View 4 Address

Machine View 3 Address

Machine View 2 Address

Machine View 1 Address

Machine View 0 Address

Instruction Set Principles

TOS

ALUALU ALU ALU

AccumulatorStack Reg. Set Reg. Set

Memory Memory Memory Memory

(a) Stack (b) Accumulator (c) Register-Memory (d) Reg-Reg/Load-Store

Push APush BAddPop C

Load AAdd BStore C

Load R1,AAdd R3,R1,BStore R3,C

Load R1,ALoad R2,BAdd R3,R1,R2Store R3,C

ALU

Memory

Add C,A,B

(e) Memory-Memory

Y = (A-B)/(C+D*E)

3 Op Address 2 Op Address 1 Op Address 0 Op Address

SUB Y,A,BMUL T,D,EADD T,T,CDIV Y,Y,T

MOV Y,ASUB Y,BMOV T,DMUL T,EADD T,CDIV Y,T

LOAD DMUL EADD CSTORE YLOAD ASUB BDIV YSTORE Y

PUSH APUSH BSUBPUSH CPUSH DPUSH EMULADDDIVPOP Y