arithmetic blocks

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Arithmetic Blocks Sudhir , Vinita 2007/02/22

Arithmetic Blocks…An insight

Sudhir Rao RupanagudiVinita Rupanagudi

Advanced Digital IC Design


Highlights

AddersMultipliersDivisionSquare RootSome Miscellaneous Topics


Adders

Basic Blocks of an Adder

In electronics, an adder is a digital circuit that performs addition of numbers.

Full adderINCBASUM ⊕⊕=

ININ CBCABACARRY ⋅+⋅+⋅=

Half Adder


Adders

Ripple Carry AdderCarry Look Ahead AdderCarry Skip AdderManchester Carry Chain Adder

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Ripple Carry Adder

Multiple full adders with carry ins and carry outs chained togetherSmall Layout area Large delay time


Carry Look Ahead Adder

First computes propagate, generate and then computes SUM and CARRY from them.Reduces delay in Computation.Logic gets complicated for > 4 bits.


Carry Skip Adder

Module bypasses the carry-in based on Propagate signals.Improves delay of Ripple Carry Adder.


Manchester Carry chain Adder

Utilizes a Pre charged Carry chain, along with Propagate and Generate SignalsReduced Area.Each internal Node must be pre charged.

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A few comparisons…

In terms of area efficiency the - Ripple Carry adder is the most efficient.- Carry Look ahead adder is the least.

In terms of speed - Carry Look ahead adder is the fastest.- Ripple carry adder has the largest delay

In terms of power- Ripple carry adder has the least power consumption.- Manchester consumes more power due to precharge

phase.


Multipliers

A multiplier is a hardware circuit dedicated to multiplying two binary values.

The Basic Blocks are the full adders and half adders

Multiplication involves Partial Product generationAccumulating the partial products.


Types of Multipliers

Array MultiplierCarry Save MultiplierBooths AlgorithmWalace tree Structure


Array Multiplier

Consists of Identical cells each forming partial product.This is added to previously accumulated partial product.

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Carry Save Multiplier

•Gain in speed

•More area


Carry Save Multiplier

Uses same blocks as Array multiplier.Carry ripples column-wise.Used for high speed, low power DSP processors.


Booth’s Algorithm

This algorithm serves two purposes

- Fast multiplication when there are consecutive 0’s or 1’s in the multiplier.

- Can be used for signed multiplication.


Booth’s Algorithm cont..

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Example.

4 bits

0110 6

X 0010 2

---------------------

00000000

- 0110

--------------------

11110100

+ 0110

---------------------

(1) 00001100

8 bits

•If the current multiplier digit is 1 and earlier digit is 0 (i.e. a 10 pair) shift and sign extend the multiplicand, subtract with previous result.

•If it is a 01 pair, add to the previous result.

•If it is a 00 pair, or 11 pair, do nothing.


Wallace tree

It is a column adder tree.

Combines products into 2 vectors- sum and carry.

Designed for minimum propagation delay.


Wallace tree cont…

FAs


Wallace tree cont..

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A few comparisons…

In terms of area efficiency- Array multipliers have compact and easy layouts

carry select > carry skip> ripple carry- Wallace tree structures have greater areas.

In terms of speed.- Wallace tree structures are faster than array multipliers.

In terms of power- Wallace tree structures have 10% energy advantage over

array multipliers due to shallower partial product reduction.


Division

Several algorithms exist to perform Division in digital designs.

Two types of Division are:Slow Division-RestoringNon-Restoring

Fast division-Newton-RaphsonGoldshmidt


Restoring division

Operates on fixed point fractional numbers

AlgorithmRi+1 = 2Ri-V is performedIf result of Subtraction is negativeRestoring addition is performed.

Ri+1 = Ri+1+V

Partial remainder is restored to correct value if quotient bit is 0


Restoring Division (Example)

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Non Restoring Division

Steps of Restoring division are merged to form a single operation- Non restoring Division.

Ri+1 = 2Ri + V

When quotient bit is 1Partial Remainder is computed by subtraction

When quotient bit is 0NO RESTORATIONHalf the divisor is added to partial Remainder.


Non Restoring Division (Example)

To divide 436 by 480

436- 480 Subtract

-44 Negative

- 44 240 Shift 480 (halve it) & add196


A few comparisons

Restoring division is most efficient for- floating-point division- for integer division when the divisor is not small.

easy to implement.

Non Restoring Division-The main advantage is the compatibility with 2's complement notation for dividend and divisor.


Square root operation

Square root of a number x is a number whose square is x.

One method for implementation is the Non restoring Method

Algorithm:r0 = D × 2^−32, q0 = 0, Iterate for 15 bitsIf ri > 0 ri+1 = 4ri − (4qi + 1)

else ri+1 = 4ri + (4qi + 3)If ri+1 >0 qi+1 = 2qi + 1

else qi+1 = 2qi

If r16 < 0 r16 = r16 + (2q16 + 1)

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Example

To find square root of D = 01111111Q= q5 q4 …. q0 the final output.

r0 = 0.01111111q0 = 0

r0 > 0 r1 = 001.111111 − 001 = 000.111111

r1 >0 q1 = 1r2 = 0011.1111 − 0101 = 1110.1111

r2 < 0 q2 = 10r3 = 11011.11 + 01011 = 00110.11

r3 >0 q3 = 101r4 = 011011 − 010101 = 000110

r4 >0 q4 = 1011


Vedic Mathematics

System of performing Arithmetic operations in a fast and efficient way

Utilizes effective methods mentioned in the ancient Indian scriptures in the form of Sutras(or Rules).

Developed by Jagadguru Swami Sri BharatiKrishna Tirthaji Maharaja

Research being carried out by- Himanshu Thapliyal and M.B Srinivas in

Hyderabad.- MSRSAS, Bangalore.


Multiplication using Vedic Math

Example:16x16 MultplierSutra used: Urdhva Tiryakbhyam

Step1: split the 16 bits into sets of 4 with 4 bits each

Step 2: To find the Cross Products (Using Vertical and crosswise method)

Step 3: Bringing the cross Products together to form the Final Product


Vedic Multiplication Algorithm

GFEDCBA gives us the final product!

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Example

0010

X 01101100

Consider 2 numbers A = 0010 and B=0110

0 0 1 0

0 1 1 0P1: 0+0 = 0

P2: (1*0)+(1+0)= 0

P3: (0*0)+(1*1)+(1*0)=1

P4: (0*0)+(0*0)+(1*0)+(1*1)=1

P5: (0*1)+(0*1)+(0*1)=0

P6: (0*1)+(0*1)=0

P7: (0*1)=0

P7 P6 P5 P4 P3 P2 P1

0 0 0 1 1 0 0


Advantages

It has been found:

Vedic multipliers and dividers are more efficient in area/speed.

They have provided gate delays of 1.507 us.as compared to a gate delay 2.838 us for a normal multiplier and divider.

Source: Himanshu Thapliyal and M.B Srinivas


References

Yamin Li and Wanming Chu, “A New Non-Restoring Square Root Algorithm and Its VLSI Implementations”.

Israel Koren, “High-Speed Multiplication – III”

Himanshu Thapliyal and M.B Srinivas, “VLSI Implementation of RSA Encryption System Using Ancient Indian Vedic Mathematics”

Bhagya, Deepthi Reddy, Shilpa H Daddi,“Implementationof 4-Bit ALU in VLSI, Bachelors Thesis Project, Atria Institute of Technology, Bangalore”


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