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A R C H I V E 2 0 0 6A R C H I V E 2 0 0 6Hot Topics Session
A Trio Of Trends And Challenges
COPYRIGHT NOTICECOPYRIGHT NOTICE• The papers in this publication comprise the proceedings of the 2006 BiTS Workshop. They reflect the authors’ opinions and are reproduced as presented , without change. Their inclusion in this publication does not constitute an endorsement by the BiTS Workshop, the sponsors, BiTS Workshop LLC, or the authors.• There is NO copyright protection claimed by this publication or the authors. However, each presentation is the work of the authors and their respective companies: as such, it is strongly suggested that any use reflect proper acknowledgement to the appropriate source. Any questions regarding the use of any materials presented should be directed to the author/s or their companies.• The BiTS logo and ‘Burn-in & Test Socket Workshop’ are trademarks of BiTS Workshop LLC.
“Test Handling Challenges Associated With Socket Designs”John Pollock — Aetrium Incorporated
“Optimization Of Interconnects”Ho Peng Ching — Micron Semiconductor Asia
“Thermal Considerations In Testing Very High Performance Devices”Thomas Di Stefano — Centipede Systems
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #1
1
A Trio Of Trends And Challenges
Test Handling Challenges Associated with Socket Designs
2006 Burn-in and Test Socket WorkshopMarch 12 - 15, 2006
John PollockVice President & General Manager
March 2006 Test Handling Challenges 2
Handler Purchase Criteria
End User Wants:• Lowest Cost of Test
– Dedicated High Volume– Flexible Small Lots– Quick Change Over– Tri-temperature
18%
24%
29%
38%
53%
71%
Temperature
Changeover
Customization
Price
Jam Rate
Throughput
Source: Booz Allen & Hamilton
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #1
2
A Trio Of Trends And Challenges
March 2006 Test Handling Challenges 3
Complete Solution
ITCBITS
Semicon
March 2006 Test Handling Challenges 4
What’s Driving the Socket Designs
• Increasing Device Performance• Increasing Device Power (Thermal)• Increasing Package Proliferation• Increasing Package Assembly Methods• Decreasing Geometries
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #1
3
A Trio Of Trends And Challenges
March 2006 Test Handling Challenges 5
Device Performance Challenges
• Analog Accuracy of Measurements• Logic Signal Speed & Thermal• Mixed Signal Speed & Accuracy• Memory Massively Parallel Contacts
March 2006 Test Handling Challenges 6
Handler Evolution• Gravity
– DIP, SOIC & QFN• Pick & Place
– QFP, PGA & BGA• Turret
– SOT• Strip
– SOIC & QFN• Wafer
– KGD
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #1
4
A Trio Of Trends And Challenges
March 2006 Test Handling Challenges 7
Package Evolution
• Analog Devices– DIP, SOIC & QFN
• Logic, Memory & Mixed Signal– QFP, PGA & BGA
• Discrete– SOT
March 2006 Test Handling Challenges 8
Package Proliferation Challenges
• Leaded• Pads (Leadless)• BGA• Array• Pitch • Dimensional
Tolerances
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #1
5
A Trio Of Trends And Challenges
March 2006 Test Handling Challenges 9
QFN Dimensional Tolerences
• Rough edges – Punch – Sawn
• Thickness
Punch Sawn
Rough edge
0.55, 0.75, 0.90 mm
March 2006 Test Handling Challenges 10
Load Board Challenges
• Contactor Mounting • Handler Alignment• Multi Site• Signal Conditioning
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #1
6
A Trio Of Trends And Challenges
March 2006 Test Handling Challenges 11
Docking Challenges
• Direct Docking • Cable Up Docking • Dimensional Stack Ups
– Socket– Load Board– Support Rings– Test Head Manipulators
March 2006 Test Handling Challenges 12
Tolerance Stack Ups
• X Direction• Y Direction• Z Direction
– example
Tolerance Analysis - 5x5 MLF/QFN
COMPONENTS Tolerance Nominal Feature
Plate: 0.0015 0.1975
Leadbacker: 0.001 0.198
Device: 0.0005 0.0341 Actual0.003 0.0354 Print
Socket 0.0008 0.039 Surface 10.0008 0.031 Groove 10.0002 0.027 Elastomer0.0005 0.017 Contact
dimensions in inches
Nominal Tolerance: Nominal Compression: 0.0086
Maximum Tolerance Minimum Compression: 0.0033
Minimum Tolerance:Maximum Compression: 0.0139
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #1
7
A Trio Of Trends And Challenges
March 2006 Test Handling Challenges 13
Contacting Measurement Challenges
• Performance• Lead Length• Signal Conditioning • Non Kelvin• Kelvin
March 2006 Test Handling Challenges 14
Kelvin Contacting Challenges
• Pogo Pins – Cleaning Issues– Shorter Life
• Wires (fingers) – Scrub
• Elastomers– Capacitance and Inductance
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #1
8
A Trio Of Trends And Challenges
March 2006 Test Handling Challenges 15
Kelvin Pogo Pin Contacting
March 2006 Test Handling Challenges 16
Kelvin Wire Finger Contacting
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #1
9
A Trio Of Trends And Challenges
March 2006 Test Handling Challenges 17
Thermal Challenges• Temperature Range
– +155°C to -55°C
• Convection vs Conduction• Test Site Accuracy
– ± 1°C or less
• Environmental Sealing– Frosting
March 2006 Test Handling Challenges 18
Going Forward
Can not lose sight of continuing to provide the most simple and cost effective total solution
Requires a joint effort
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #1
10
A Trio Of Trends And Challenges
March 2006 Test Handling Challenges 19
Steps For Going Forward
• Propose Test Socket Committee– Define Best Practices– Members From
• IDM• Handlers Manufacturers• Socket Manufacturers• Load Board Manufacturers• Tester Manufacturers
Thank You
Questions?
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #2
1
A Trio Of Trends And Challenges
Optimization of
Interconnects
2006 Burn-in and Test Socket WorkshopMarch 12–15, 2006
Ho Peng ChingMicron Semiconductor Asia
3/2006 2
Agenda
• Background• Design Review
– Board-to-Board Interposer Design– Signal-Gnd Via Structure
• System-Level Performance • Conclusions• References• Acknowledgments
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #2
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A Trio Of Trends And Challenges
3/2006 3
Background• Recap of the Flexi-Interface Test Interface
Fixture [1]
Universal Base Assembly
Changeover kits (Device Specific)
Socket Board
InterconnectAdaptor BoardSocket
3/2006 4
Background• Extracts from their conclusion
– The concept was proven to be viable for device testing (for SDRAM). There is, however, still room for improvement on the interface between board-to-board.
– The next challenge would be to prove the Flexi-interface concept for higher speed device testing (DDR2 and beyond).
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #2
3
A Trio Of Trends And Challenges
3/2006 5
Interconnect
Background
What’s next?Extending the speed envelope of the current design by focusing on improving the electrical performance of the board-to-board interconnect.
Socket Board
Adaptor BoardSocket
3/2006 6
How ?
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #2
4
A Trio Of Trends And Challenges
3/2006 7
Design Review
Area of Focus:1. Board-to-Board Interposer2. Signal-Gnd Via Structure
Board
Board
Interposer
SigGnd Via Structures
3/2006 8
Design Review
Let’s begin with the
Board-to-Board Interposer
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #2
5
A Trio Of Trends And Challenges
3/2006 9
Design Review(Board-to-Board Interposer)
Board
Board
Interposer
Unshielded!
Proposed Design Change: To minimize the unshielded signal path
Current design shortfall:
3/2006 10
Design Review(Board-to-Board Interposer)
• Simulation results of original interposer design (using Ansoft HFSS software)
S11
S12
Observations:• 1dB insertion loss at 4.6 GHz• 10dB return loss at 3.4 GHz
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #2
6
A Trio Of Trends And Challenges
3/2006 11
Design Review(Board-to-Board Interposer)
• Simulation results of optimized interposer design
S11
S12
Observations:• 1dB insertion loss at >5 GHz• 10dB return loss >5 GHz
3/2006 12
Design Review(Board-to-Board Interposer)
S12
Original Design Optimized Design
E-Fi
eld
H-F
ield
• Field Plot
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #2
7
A Trio Of Trends And Challenges
3/2006 13
Design Review(Board-to-Board Interposer)
• Tester Shmoo Data: Original vs Optimized Interposer Design
Orig
inal
In
terp
oser
Opt
imiz
ed
Inte
rpos
erDATE: 07-Sep-2005 TIME: 10:27:17
9.300nS 9.600nS 9.900nS 10.20nS 10.50nS +---------+---------+---------+---------+
950.0mV +. . . . . . . .**************************+940.0mV |. . **************************|930.0mV |. . *************** * *** ***|920.0mV |. . ****.******* *** .|910.0mV |. . * ****** ** * .|900.0mV +. . . . . . . . ******.*. . . . . . . . .+890.0mV |. . **** . .|880.0mV |. . * * . .|870.0mV |. . ** . .|860.0mV |. . . . .|850.0mV +. . . . . . . . . . . . . . . . . . . . .+840.0mV |. . . . .|830.0mV |. . . . .|820.0mV |. . . . .|810.0mV |. . . . .|800.0mV +. . . . . . . . . . . . . . . . . . . . .+790.0mV |. . . . .|780.0mV |. . . . .|770.0mV |. . . . .|760.0mV |. . . . .|750.0mV +. . . . . . . . . . . . . . . . . . . . .+
+---------+---------+---------+---------+9.300nS 9.600nS 9.900nS 10.20nS 10.50nS
DATE: 07-Sep-2005 TIME: 12:19:20
9.300nS 9.600nS 9.900nS 10.20nS 10.50nS +---------+---------+---------+---------+
950.0mV +. . . . . . . . . . . . . . . . . . . . .+940.0mV |. . . . .|930.0mV |. . . . .|920.0mV |. . . . .|910.0mV |. . . . .|900.0mV +. . . . . . . . . . . . . . . . . . . . .+890.0mV |. . . . .|880.0mV |. . . . .|870.0mV |. . . . .|860.0mV |. . . . .|850.0mV +. . . . . . . . . . . . . . . . . . . . .+840.0mV |. . . . .|830.0mV |. . . . .|820.0mV |. . . . .|810.0mV |. . . . .|800.0mV +. . . . . . . . . . **. . . . . . . . . .+790.0mV |. . ** .* . .|780.0mV |. . ****** ** *. .|770.0mV |. . * *.************ ** .|760.0mV |. . ******************* ****|750.0mV +. . . . . . . . .************************+
+---------+---------+---------+---------+9.300nS 9.600nS 9.900nS 10.20nS 10.50nS
DATE: 07-Sep-2005 TIME: 11:09:33
9.300nS 9.600nS 9.900nS 10.20nS 10.50nS +---------+---------+---------+---------+
950.0mV +. . . . . .******************************+940.0mV |. . *****************************|930.0mV |. . *****************************|920.0mV |. . *****************************|910.0mV |. . ****************************|900.0mV +. . . . . . .****************************+890.0mV |. . ****************************|880.0mV |. . ****************************|870.0mV |. . ****************************|860.0mV |. . ****************************|850.0mV +. . . . . . .****************************+840.0mV |. . ****************************|830.0mV |. . ***************************|820.0mV |. . ***************************|810.0mV |. . ***************************|800.0mV +. . . . . . . ***************************+790.0mV |. . ***************************|780.0mV |. . ***************************|770.0mV |. . ***************************|760.0mV |. . ***************************|750.0mV +. . . . . . . ***************************+
+---------+---------+---------+---------+9.300nS 9.600nS 9.900nS 10.20nS 10.50nS
DATE: 07-Sep-2005 TIME: 12:35:53
9.300nS 9.600nS 9.900nS 10.20nS 10.50nS +---------+---------+---------+---------+
950.0mV +. . . . . .******************************+940.0mV |. . *****************************|930.0mV |. . ****************************|920.0mV |. . ****************************|910.0mV |. . ****************************|900.0mV +. . . . . . .****************************+890.0mV |. . ****************************|880.0mV |. . ****************************|870.0mV |. . ****************************|860.0mV |. . ****************************|850.0mV +. . . . . . .****************************+840.0mV |. . ****************************|830.0mV |. . ****************************|820.0mV |. . ***************************|810.0mV |. . ***************************|800.0mV +. . . . . . .****************************+790.0mV |. . ***************************|780.0mV |. . ***************************|770.0mV |. . ***************************|760.0mV |. . ***************************|750.0mV +. . . . . . . ***************************+
+---------+---------+---------+---------+9.300nS 9.600nS 9.900nS 10.20nS 10.50nS
Observations:
Larger PASSregion for the optimized interposer design
- DUT Passing Point
3/2006 14
Design Review(Board-to-Board Interposer)
Summary • From the simulation results, the optimized
Board-to-board interposer has shown significant improvement over the original design in terms of Insertion Loss and Return Loss over a 5 GHz BW.
• The improvement seen from the simulation results was validated with Tester’s shmoodata.
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #2
8
A Trio Of Trends And Challenges
3/2006 15
Design Review(Board-to-Board Interposer)
Summary • This has helped to establish a good
confidence level of using simulation for design assessment prior to actual prototype build.
3/2006 16
Design Review
Next let’s look at
Signal-Gnd Via Structure
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #2
9
A Trio Of Trends And Challenges
3/2006 17
Design Review(Signal-Gnd Via Structure)
• Original via structure- Offset signal via
3/2006 18
Design Review(Signal-Gnd Via Structure)
• Simulation results of original via design
S11
S12
Observations:• 0.48dB insertion loss at 5 GHz• 11dB return loss at 5 GHz
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #2
10
A Trio Of Trends And Challenges
3/2006 19
Design Review(Signal-Gnd Via Structure)
• Optimized via structure- Centered signal via
3/2006 20
Design Review(Signal-Gnd Via Structure)
• Simulation results of optimized via design
S12
S11
Observations:• 0.35dB insertion loss at 5 GHz• 13dB return loss at 5 GHz
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #2
11
A Trio Of Trends And Challenges
3/2006 21
Design Review(Signal-Gnd Via Structure)
Summary • The simulation results show 27 percent
improvement on insertion loss and 18 percent on return loss for the optimized signal-gndvia design as compared to original.
• However, this may need to be compromised with the mechanical requirement of having a larger signal pad, which the original design can provide. A larger landing pad is preferred for ease of contacting with the signal probes on the interposer.
3/2006 22
Design Review(Signal-Gnd Via Structure)
Summary • So does it justify a design change?
Unless the impact of optimized via design can be quantified from a system-level perspective, no decision can be adequately made with respect to the final choice of design options. This will be dealt with in the next session on system-level performance.
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #2
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A Trio Of Trends And Challenges
3/2006 23
How to model
System-Level Performance
3/2006 24
System-Level Performance• Objective:
– Assessment of individual design gain from a system-level perspective
• Advantages:– Help to provide a matrix of merits on the
various design combinations– Facilitate decision-making process on the
selection of the most viable design combination with consideration to practicality and cost (expense versus performance index)
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #2
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A Trio Of Trends And Challenges
3/2006 25
System-Level Performance• Explore a low-cost approach that can
sufficiently provide the first order assessment. How?
– Cascade the S-parameter matrices of individual network
– Mathematically manipulate the matrices to obtain the system-level S-parameters [2]
3/2006 26
System-Level Performance
S-parameters for system level
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20062006 Hot Topics Session
March 12 - 15, 2006
Paper #2
14
A Trio Of Trends And Challenges
3/2006 27
System-Level Performance
Original ViaStructure(Org_Via)
Optimize Via Structure
(Optm_Via)
Original Interposer(Org_Int)
Design assessment matrix at system level
Optimized Interposer(Optm_Int)
Worstcase
Bestcase
??
??
3/2006 28
System-Level PerformanceInsertion Loss (dB)
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Frequency (GHz)
Org_Via + Org_Int Optm_Via + Optm_Int Org_Via + Optm_Int Optm_Via + Org_Int
Observations:• As expected, a complete, optimized
design gives the best performance (as shown by the curve Optm_Via+Optm_Int)
• However, sufficient performance can also be achieved with only the optimized interposer design (as shown by the curve Org_Via+Optm_Int)
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #2
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A Trio Of Trends And Challenges
3/2006 29
Summary: • The system-level S-parameters can be
obtained mathematically by manipulating the S-parameter matrices of individual networks (the interposer and via structure).
• As such, the system-level performance of various combinations of the interposer and via designs can be compared.
System-Level Performance
3/2006 30
Summary: • The results show that the optimized
interposer design has the biggest impact to the system-level performance.
• Thus, decision-making on the final choice of design combination is made much easier.
System-Level Performance
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #2
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A Trio Of Trends And Challenges
3/2006 31
In essence…
3/2006 32
Conclusions• The simulation tool is used to assess the
merits of design change during the design optimization cycle.
• The simulation result is validated using the tester’s shmoo data. This has enhanced the confidence level of the simulation model.
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #2
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A Trio Of Trends And Challenges
3/2006 33
Conclusions
• Simulation data of individual network can be cascaded to provide an overall assessment of performance at a system level.
• The ability to obtain the system-level performance can be shown to aid decision making on the final choice of design combination.
3/2006 34
References[1] Koh Tuan Meng and Lim Kok Lay, “A FLEXIBLE
ELECTRICAL INTERFACE DESIGN FOR THE FIXTURE BETWEEN TESTER AND DUT TO ACHIEVE REDUCED COST AND LEADTIME INATE TOOLINGS”, BiTS 2003 Workshop.
[2] Agilent AN 154, S-Parameter Design, Application Note.
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #2
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A Trio Of Trends And Challenges
3/2006 35
Acknowledgments
Special thanks to the following people for their support on this project:
Seah Yee Choon, Koh Tuan Meng, Lim Kok Lay, Ong Boon Ngoh, Calvin Lim, Richard Teo and Yap Khai Tian from MSA Test Equipment R&D. Chia Yong Poo from MSA AssyPkg R&D.
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #3
1
A Trio Of Trends And Challenges
1 BiTS 2006
Thermal Considerations Thermal Considerations in Testing Very High in Testing Very High Performance DevicesPerformance Devices
Thomas Di StefanoCentipede Systems
2110 Ringwood AvenueSan Jose, CA 95131
2 BiTS 2006
Thermal Considerations Thermal Considerations ……
What’s New ?• More Thermal Gradients (Hot Spots)*
• Higher Power Densities
• Increased Testing of Bare Flip-Chips
* Dave Gardell, Thermal Characterization and Specification for Test and Burn-in, BiTS 2005
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #3
2
A Trio Of Trends And Challenges
3 BiTS 2006
Debendra Malek, Thermal Issues from ITRS Perspective, MEPTEC The Heat is On 2006
BiTS 2006
4 BiTS 2006
Bidyut Sen & Jim Jones, Thermal Challenges for Sparc Based Microprocessors, MEPTEC The Heat is On 2006
BiTS 2006
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #3
3
A Trio Of Trends And Challenges
5 BiTS 2006
Thermal Considerations Thermal Considerations ……
What’s New ?• More Thermal Gradients (Hot Spots)*
• Higher Power Densities
• Increased Testing of Bare Flip-Chips
* Dave Gardell, Thermal Characterization and Specification for Test and Burn-in, BiTS 2005
6 BiTS 2006
Thermal Considerations Thermal Considerations ……State of the Art• TIM Materials Θ ~ 0.15 ºC-cm² / W• Temperature Control ! 2 ºC average
Emerging Problem – “Hot Spots”• Thermal Error Yield Loss• Increased Re-test Rates
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #3
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A Trio Of Trends And Challenges
7 BiTS 2006
Hot SpotsHot Spots
Reduced IC PerformanceReduced IC Performance
Thermal Error Yield LossThermal Error Yield LossLocal Heating:• Degrades Switching Time of Critical Nets,
• Reduces Performance ~ 0.5 % per ºC at 25 ºC
• Leads to Unnecessary Yield Loss
8 BiTS 2006
“Every 15ºC increase locally causes a delay or skew to increase roughly 10 to 15%”
- Andrew Yang, TSMC EDN Sept /2005
Hot Spots Cause Performance Degradation– Reduction of Surface Channel Mobility
ص / ØΤ = - Κµ0 / Τ Κ ~ 1.5 to 2.5– Increased RC Delays
ØRC / ØΤ = 0.0038 RC
Yield Loss due to Hot SpotsYield Loss due to Hot Spots
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #3
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A Trio Of Trends And Challenges
9 BiTS 2006
Thermal Error Yield LossThermal Error Yield LossSimplified Model Assumptions*• Switching time is temperature dependent
τ ∼ 1.13 x10−4 τ0 Τ 1.6 (Τ in ºK)
• Worst case performance is determined by hot spot δΤ
δτ / δΤ = 0.0055 τ0 Delay Time
δf / δΤ = - 0.0055 f0 Frequency
* Precise model depends upon specific details
10 BiTS 2006
Simplified Model Assumptions*• IC performance is a normal distribution around f0
* Precise model depends upon specific details
Thermal Error Yield LossThermal Error Yield Loss
f0
f
P ( f )
fC
PerformanceYield Loss δΥ
σ
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #3
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A Trio Of Trends And Challenges
11 BiTS 2006
Simplified Model Assumptions*• Performance yield curve is shifted by hot spot
* Precise model depends upon specific details
Thermal Error Yield LossThermal Error Yield Loss
f
P ( f )
f0f0
fC
δΥ
σ
12 BiTS 2006
Thermal Error Yield LossThermal Error Yield LossSimplified Model*
• Performance yield curve is shifted by hot spot
Υ = ½ + ½ erf { (f0(Τ) – fC) / (σ√2) }
• Yield loss due to hot spot
δΥ/δΤ = - 0.00242 (f0/σ) { 1 – 1.03 (Υ0 – 0.5) - … }δΤ = Hot Spot Temperature above Τ0
* Precise model depends upon specific details
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #3
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13 BiTS 2006
Thermal Error Yield LossThermal Error Yield Loss
δΥ/δΤYield Loss
(% / ºC)
2 4 6 8
1.0
0.5
0.0
1.5
ΥP = 98%
ΥP = 95%
ΥP = 90%
ΥP = 80%ΥP = 70%
f0 /σPerformance Yield Distribution
14 BiTS 2006
Test MethodsTest Methods can Introduce can Introduce Thermal Errors Thermal Errors ::
• Insufficient Thermal Conductivity in TIM• Errors due to Single Point Sensing• Temperature Non-Uniformities on Heat Sink
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #3
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A Trio Of Trends And Challenges
15 BiTS 2006
Flip ChipIllustrative Model #1Illustrative Model #1
+ 1.
0 cm
+ 0.
5 cm
Hot Spot δΤδP = 250 W/cm2 (10 W in 0.2 cm x 0.2 cm)δΤ = Error Temperature (ºC)
TIM 1
Heat Sink = 0º C
+ 0.
1 cm
16 BiTS 2006
Illustrative Model #1Illustrative Model #1Flip Chip
0.20 ºC
20 ºC
40 ºC
60 ºC
0.40.0
TIM (ºC-cm2 / W)
δΤ (ºC)
Hot Spot Hot Spot ΤΤ (above Average (above Average ΤΤ))
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #3
9
A Trio Of Trends And Challenges
17 BiTS 2006
Illustrative Model #1Illustrative Model #1Flip Chip Parameters
Hot Spot 10 W in 0.2 x 0.2 cm areaPerformance Yield YP = 95 %Yield Distribution σ = 0.33 f0
TIM Material 0.2 ºC-cm2 / W
Temperature ErrorTemperature Error δΤδΤ = 33= 33ººCCTThermal Error Yield Loss = 5.9%hermal Error Yield Loss = 5.9%
18 BiTS 2006
Illustrative Model #2Illustrative Model #2
TIM 1 = 0.1 ºC-cm² / W
+ 10
mm
+ 5
mm
-5
mm
-10
mm
-1
mm
+ 1
mm
Thermal Spreader
Heat Sink = 0º C
TIM 20.1 cm W-Cu Spreader
Hot SpotδP = 250 W/cm2 (10 W in 0.2 cm x 0.2 cm)δΤ = Error Temperature (ºC)
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #3
10
A Trio Of Trends And Challenges
19 BiTS 2006
Thermal SpreaderIllustrative Model #2Illustrative Model #2
0.20 ºC
20 ºC
40 ºC
60 ºC
0.40.0TIM (ºC-cm2 / W)
δΤ (ºC)
Hot Spot Hot Spot ΤΤ (above Average (above Average ΤΤ))
20 BiTS 2006
Illustrative Model #2Illustrative Model #2Thermal Spreader Parameters
Hot Spot 10 W in 0.2 x 0.2 cm areaPerformance Yield YP = 95 %Yield Distribution σ = 0.33 f0
TIM Material 0.2 ºC-cm2 / W
Temperature ErrorTemperature Error δΤδΤ = 36= 36ººCCTThermal Error Yield Loss = 6.4 %hermal Error Yield Loss = 6.4 %
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #3
11
A Trio Of Trends And Challenges
21 BiTS 2006
Caveat Caveat ……
Thermal Error Yield Loss Model Must Take into Account the Actual:• Impact of Temperature on IC Performance• Thermal Properties of Materials• IC Performance Yield
22 BiTS 2006
Local Heat Generation in IC• Hot Spots Degrade Measured Chip Performance
Single Point Temperature Measurement• Local Variations Induce Errors in Control Temperature
Thermal Gradients on Heat Sink• Degrade Measured Chip Performance
Thermal Considerations Thermal Considerations ……
20062006 Hot Topics Session
March 12 - 15, 2006
Paper #3
12
A Trio Of Trends And Challenges
23 BiTS 2006
Conclusions Conclusions ……
Improvements Needed to Avoid Unnecessary Thermal Error Yield Loss• Thermal Head Performance• Temperature Detection and Control• Temperature Uniformity of Thermal Head