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2 2 0 0 1 1 0 0 TechTalk BiTS Workshop 2010 Archive ARCHIVE 2010 PCB DESIGN, FABRICATION AND ASSEMBLY by Tom Bresnan Sales Manager R&D Circuits Guy Ramsey Assembly Division GM R&D Circuits ABSTRACT his TechTalk will cover producing the printed circuits boards you want - from start (Design) to (Fabrication) finish (Assembly)”. With escalating electrical performance demands, the Printed Circuit Board is not only an essential part of a package test and/or burn-in solution, but has become an integral component for success. This TechTalk offers attendees an interactive, across the board examination of those PCBs sitting under your socket. The focus will be on learning about the challenges to properly select materials, layout, manufacture and assemble the PCB. In ‘bringing the Printed Circuit Board shop to the ‘classroom’, a better understanding of the challenges you and your PCB vendors face is discussed. First a brief history of the PCB or PWB (Printed Circuit/Wiring Board) industry will be covered, specifically in relation to the ATE industry. Next the talk will address the common challenges the industry deals with in the layout of a high yielding, yet lower volume process flow. Once designed, the discussion will cover the main cost and technical drivers of the PCB. Those being the pitch, layer count, board thickness and via drill hole diameter (to name but a few of the critical attributes of today’s interface boards). Once built, the presentation will explain the assembly challenges and tricks that are required to complete the final PCB assembly. Last, but certainly not least, the quality and performance characteristics you can demand of your supplier(s) will be analyzed. Even with today’s boards becoming more crowded (with components) and pitch and pin counts driving attributes ever smaller, there are ways to verify and validate the quality of your interface boards with your suppliers. Attendees will learn how, with samples of data gathered over years of process development, characterization and verification. T COPYRIGHT NOTICE The papers in this publication comprise the proceedings of the 2010 BiTS Workshop. They reflect the authors’ opinions and are reproduced as presented , without change. Their inclusion in this publication does not constitute an endorsement by the BiTS Workshop, the sponsors, BiTS Workshop LLC, or the authors. There is NO copyright protection claimed by this publication or the authors. However, each presentation is the work of the authors and their respective companies: as such, it is strongly suggested that any use reflect proper acknowledgement to the appropriate source. Any questions regarding the use of any materials presented should be directed to the author/s or their companies. All photographs in this archive are copyrighted by BiTS Workshop LLC. The BiTS logo and ‘Burn-in & Test Socket Workshop’ are trademarks of BiTS Workshop LLC.

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Page 1: ARCHIVE 2010 - TestConX · Once built, the presentation will explain the assembly challenges and tricks that are required to complete the final PCB assembly. ... March 7 - 10, 2010

22001100 TechTalk

BiTS Workshop 2010 Archive

ARCHIVE 2010

PCB DESIGN, FABRICATION AND ASSEMBLY by

Tom Bresnan Sales Manager R&D Circuits

Guy Ramsey Assembly Division GM

R&D Circuits

ABSTRACT

his TechTalk will cover producing the printed circuits boards you want - from start (Design) to (Fabrication) finish (Assembly)”.

With escalating electrical performance demands, the Printed Circuit Board is not only an essential part of a package test and/or burn-in solution, but has become an integral component for success. This TechTalk offers attendees an interactive, across the board examination of those PCBs sitting under your socket. The focus will be on learning about the challenges to properly select materials, layout, manufacture and assemble the PCB. In ‘bringing the Printed Circuit Board shop to the ‘classroom’, a better understanding of the challenges you and your PCB vendors face is discussed.

First a brief history of the PCB or PWB (Printed Circuit/Wiring Board) industry will be covered, specifically in relation to the ATE industry. Next the talk will address the common challenges the industry deals with in the layout of a high yielding, yet lower volume process flow. Once designed, the discussion will cover the main cost and technical drivers of the PCB. Those being the pitch, layer count, board thickness and via drill hole diameter (to name but a few of the critical attributes of today’s interface boards). Once built, the presentation will explain the assembly challenges and tricks that are required to complete the final PCB assembly.

Last, but certainly not least, the quality and performance characteristics you can demand of your supplier(s) will be analyzed. Even with today’s boards becoming more crowded (with components) and pitch and pin counts driving attributes ever smaller, there are ways to verify and validate the quality of your interface boards with your suppliers. Attendees will learn how, with samples of data gathered over years of process development, characterization and verification.

T

COPYRIGHT NOTICE The papers in this publication comprise the proceedings of the 2010 BiTS Workshop. They reflect the authors’ opinions and are reproduced as presented , without change. Their inclusion in this publication does not constitute an endorsement by the BiTS Workshop, the sponsors, BiTS Workshop LLC, or the

authors.

There is NO copyright protection claimed by this publication or the authors. However, each presentation is the work of the authors and their respective companies: as such, it is strongly suggested that any use

reflect proper acknowledgement to the appropriate source. Any questions regarding the use of any materials presented should be directed to the author/s or their companies.

All photographs in this archive are copyrighted by BiTS Workshop LLC. The BiTS logo and ‘Burn-in &

Test Socket Workshop’ are trademarks of BiTS Workshop LLC.

Page 2: ARCHIVE 2010 - TestConX · Once built, the presentation will explain the assembly challenges and tricks that are required to complete the final PCB assembly. ... March 7 - 10, 2010

20102010 TechTalk

March 7 - 10, 2010 1

PCB Design, Fabrication and AssemblyBiTS 2010 Tech Talk

Tom BresnanSales Manager, R&D Circuits

Guy Ramsey

General Manager, R&D CircuitsAssembly Division

2010 BiTS Workshop2010 BiTS WorkshopMarch 7 March 7 -- 10, 201010, 2010

©© 2010 R&D Circuits2010 R&D Circuits

©© 2010 R&D Circuits2010 R&D Circuits

3/20103/2010 BiTS 2010 Tech Talk: PCB Design, Fabrication and AssemblyBiTS 2010 Tech Talk: PCB Design, Fabrication and Assembly 22

What you came here for…

A little bit about PWB’s– The marketplace

Fabrication– The Attributes

– Materials and more

– The Process

Assembly

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20102010 TechTalk

March 7 - 10, 2010 2

©© 2010 R&D Circuits2010 R&D Circuits

3/20103/2010 BiTS 2010 Tech Talk: PCB Design, Fabrication and AssemblyBiTS 2010 Tech Talk: PCB Design, Fabrication and Assembly 33

Printed Circuit Boards

A PWB consists of a non‐conducting substrate (typically woven fiberglass with epoxy resin) upon which a conductive pattern or circuitry is formed.Wikipedia…A printed circuit board, or PCB, is used to mechanically support and electrically connect electronic components using conductive pathways, on a non‐conductive substrate. 

©© 2010 R&D Circuits2010 R&D Circuits

3/20103/2010 BiTS 2010 Tech Talk: PCB Design, Fabrication and AssemblyBiTS 2010 Tech Talk: PCB Design, Fabrication and Assembly 44

Marketplace

2007– US$50B

2012– US$76B

US Market in 2007– US$13B

ATE– US$.5B to US$1B (difficult to estimate)

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20102010 TechTalk

March 7 - 10, 2010 3

©© 2010 R&D Circuits2010 R&D Circuits

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What’s in a name?

PCB

PWB

DUT board, DIB, PIB, Load board, ATE board

Interface Board– Between Device Under Test and Tester

©© 2010 R&D Circuits2010 R&D Circuits

3/20103/2010 BiTS 2010 Tech Talk: PCB Design, Fabrication and AssemblyBiTS 2010 Tech Talk: PCB Design, Fabrication and Assembly 66

Attributes

Pitch– Device, line, space, hole to copper

Layers– rows

Hole Diameter– Function of device pitch

Aspect Ratio– Ratio of thickness to hole diameter

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20102010 TechTalk

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©© 2010 R&D Circuits2010 R&D Circuits

3/20103/2010 BiTS 2010 Tech Talk: PCB Design, Fabrication and AssemblyBiTS 2010 Tech Talk: PCB Design, Fabrication and Assembly 77

Attributes ‐ Pitch

Device Pitch– 1.0mm, 0.8mm, 0.5mm, 0.4mm ….

– Translates to other attributesLine width

Spacing

Dielectric spacing

Hole to copper feature dimensions

©© 2010 R&D Circuits2010 R&D Circuits

3/20103/2010 BiTS 2010 Tech Talk: PCB Design, Fabrication and AssemblyBiTS 2010 Tech Talk: PCB Design, Fabrication and Assembly 88

Pitch Translation

1.0mm1.0mm 0.8mm0.8mm 0.5mm0.5mm 0.4mm0.4mm

PadPad 0.76mm0.76mm 0.66mm0.66mm 0.35mm0.35mm 0.3mm0.3mm

HoleHole 0.37mm0.37mm 0.3mm0.3mm 0.15mm0.15mm 0.1mm0.1mm

LineLine 0.2mm0.2mm 0.2/0.120.2/0.12 0.2/0.080.2/0.08 0.2/0.070.2/0.07

Hole2CuHole2Cu 0.25mm0.25mm 0.18mm0.18mm 0.12mm0.12mm 0.1mm0.1mm

A/RA/R LowLow Med.Med. HighHigh ExtremeExtreme

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Hole to Copper

©© 2010 R&D Circuits2010 R&D Circuits

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Attributes ‐ Layers

Rows = Signal Layers

Signal Layers need ground planes– Impedance control

Additional routing layers

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Rows = Layers

©© 2010 R&D Circuits2010 R&D Circuits

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Attributes – Hole Diameter

Drill / Hole diameter

Human hair – 0.04 to 0.25mm

0.1mm ‘average’

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Attributes – Aspect Ratio

1.0mm– 13:1

0.8mm– 16:1

0.5mm– 31:1

0.4mm– 47:1

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Materials & More

Wikipedia…A printed circuit board, or PCB, is used to mechanically support and electrically connect electronic components using conductive pathways, on a non‐conductive substrate.

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Materials & More

Laminate– Pre‐preg

Glass cloth (woven)

Resin

– Copper foilElectrodeposited (ED)– 1 ounce per square foot (305g/M2) (35 microns thick)

– ½ ounce per square foot (153g/M2) (17 microns thick)– ¼ ounce per square foot (80g/M2) (9 microns thick)

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Materials

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Laminates

Fr‐4

Enhanced Fr‐4’s

HF laminates

Teflon

Hybrids

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Glass Styles

Style Glass Dia. Yarn Ct. Yarn Pitch

106 1.4 56x56 17.9x17.9

1080 2.3 60x40 16.7x21.3

2113 2.9 60x56 16.7x17.9

2116 3.8 60x58 16.7x17.2

7628 6.8 44x32 22.7x31.3

©© 2010 R&D Circuits2010 R&D Circuits

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ConstructionsThickness Tolerance Construction Resin

ContentEr @1 MHz

Er @10 GHz

0.008 0.001 1 7628 44.4% 4.55 4.12

0.008 0.001 2 2116 43.0% 4.54 4.11

0.008 0.001 1 21161 2113

48.6% 4.36 4.02

0.008 0.001 1 7629 42.6% 4.38 4.12

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Constructions

Know what you’re getting

Understand the implications

Electrically insignificant?

Mechanically significant

©© 2010 R&D Circuits2010 R&D Circuits

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Material Properties

Mechanical & Thermal– Peel strength

– X‐Y CTE

– Z CTE

– TgDSC

TMA

DMA

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Material Properties

Electrical– Dielectric Constant or

– εr  (or relative permittivity)The dielectric constant is a ratio of the capacitance of a capacitor in which a particular insulating material is the dielectric, to the capacitance of the capacitor in which a vacuum is the dielectric.

– Effective Permittivity

©© 2010 R&D Circuits2010 R&D Circuits

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Inner Layer Imaging

Photo‐resist application

UV Exposure– Film and collimated light

– LDI or Laser Direct ImagingPolymerizes photo‐resist

– DevelopRemoval of non‐polymerized resist

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Inner Layer Imaging

©© 2010 R&D Circuits2010 R&D Circuits

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Inner Layer Imaging

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Inner Layer Etch

Remove base copper– Non‐polymerized area

– Various chemistries availableAmmonia based

Cupric chloride based

Resist removal (stripping)

©© 2010 R&D Circuits2010 R&D Circuits

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Inner Layer Etch

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AOI

Post‐Etch Punch– Registers all layers to optical targets

Automated Optical Inspection– Data download from CAM

– Core layer scanned

– Compared to CAM data

– Verification

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AOI

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Oxide Treatment

Copper Surface Preparation

Adhesion promoter– Added bond strength

Reduced Oxide– Pink ring elimination

Alternative Oxide– Variety of materials

– Multiple or sequential laminations

©© 2010 R&D Circuits2010 R&D Circuits

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Layup and Lamination

Registration and stacking of cores

Combines cores, pre‐preg, Cu foil

Pin lamination– Registration or layer to layer alignment

Vacuum chamber

Heat, pressure, time

Controlled process window

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Stack up

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Drill

Mechanical hole formation– 0.1mm

Opto‐mechanical positioning– Glass scales

Real‐time analysis– Diameter– Run‐out– Broken bit

Stub Drilling (back‐drilling)

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Drill

©© 2010 R&D Circuits2010 R&D Circuits

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Drill

Laser hole formation– Microvia’s

Down to 25 micron

Opto‐mechanical positioning

Blind via’s

Buried via’s

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Hole Prep & Copper Plate

Desmear– Removes epoxy smear from interconnects

– Drilling operations

– Chemical removal

©© 2010 R&D Circuits2010 R&D Circuits

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Hole Prep & Copper Plate

Etchback– Different from desmear

– Removes epoxy from dielectric space

– Glass etch

– Three point connection

– Some materials resistant to chemical removal

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Hole Prep & Copper Plate

Copper Deposition

Seed layer– Prepares dielectric and interconnects for subsequent plating operations

– 30‐40 µ followed by copper plate

– 75‐125 µ to prep for imaging process

Unfriendly chemistry

Inherently unstable

©© 2010 R&D Circuits2010 R&D Circuits

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Hole Prep & Copper Plate

Carbon  (Black Hole®)

Graphite (Shadow®)

Palladium

Electroless Nickel (Ultra‐Plate®)

Conductive Polymer

Non‐Formaldehyde‐Based Electroless Copper

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Hole Fill

Fill to create flat surface– Need for socket touchdown

Vacuum assist

Compressed air– Thru system & thru holes

High aspect ratio

Blind via’s

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Hole Fill

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Outer Layer Imaging

Reversed from inner layer imagingPlating resist, not etch resistPhoto‐resist applicationUV Exposure– Film and collimated light– LDI or Laser Direct Imaging

Polymerizes photo‐resist

– DevelopRemoval of non‐polymerized resist

©© 2010 R&D Circuits2010 R&D Circuits

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Cu Ni Au Plating

Electroplating– Chemistry (electrolyte solution)

– Power rectifierRectifier converts AC to DC

– Anode (copper)

– Cathode (PCB panel)

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Cu Ni Au Plating

©© 2010 R&D Circuits2010 R&D Circuits

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Cu Ni Au Plating

1 mil minimum thickness in holes

Minimize surface buildup

Aspect ratio– Thru holes and / or micro‐via’s

Robust and survivable

Etch Resist

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Outer Layer Etch

Define the outer layer(s) pattern– Removal of base copper

– Lines, pads, other features

– Impedance control

Nickel / Hard Gold typical ATE finish

Etch factors and overhang

Other finishes available

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Outer Layer Etch

Overhang– Depends on finish

– 1:1 thickness

– Surface thickness critical

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Electrical Test

Direct measurement for first board

Indirect Measurement all others– Isolation and continuity

– Capacitive or electromagnetic couplingBroken trace = reduced coupling

Shorted trace = increased coupling

Trace to ground (↑ degree of confidence)

– Adjacency analysis

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Electrical Test

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Soldermask

Epoxy based coating– Available in colors and clear

Surface protection

Solder resist, as the name implies

Identification

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Soldermask

Screen‐flood

Liquid Photo‐imageable (LPI)– Spray coated

– consistency

Via Plugging

Dry Film

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Silkscreen

Assembly nomenclature or legend

Available Colors

Product identification

Screen print

Inkjet

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De‐panelization

Routing

Secondary Drill

Back / Stub Drill

Counterbores / countersinks

Slots

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Final Inspection

Visual and dimensional– Cosmetic defects

Impedance Testing

Cross sectioning

Other measurements and certifications

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Environment

Manpower

Understands materials

Trained on Machines

Properly interprets inspection results

Storage Control

High Quality

Solder Bond

Ishikawa diagram: Soldering

Temperature

Methods

Control of Solder

deposition

Clean Dry Substrates

Appropriate Alloy

Appropriate Flux

Machines

Lighting Aids Inspection Equipment

Cleaning Equipment

SMT Placement Equipment

Control of Fluxing

Soldering Equipment

Solder Paste Application Equipment

Materials

Air currents

Humidity Cleaning

Fresh Paste Control of Heat

©© 2010 R&D Circuits2010 R&D Circuits

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Good Results GuaranteedGiven:

Solderable parts and boards

Appropriate solder and solder quantity

Proper Fluxing action

Proper temperature profile

It is simple really!

Anyone can do it.

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Easy Does it

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Easy Does it

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Or Not !!

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Or Not: Two 

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Materials

Parts: J‐STD‐002

Boards: J‐STD‐003

Flux: J‐STD‐004

Solder Paste: J‐STD‐005

Solder: J‐STD‐006– Solvents: Must be compatible

– Flux

– Cleaning method

– Parts

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Non‐solderable Parts

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Non Solderable Board

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Flux Classification

Low Activity

Medium Activity

High Activity

All levels: – Halide activators

May produce metal salts

– Non‐halide activatorsLess likely to produce corrosion

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Corrosion: Flux Residue

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Corrosion: Dendrite

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Corrosion : Dendrite two

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Cleaning Materials

Solvent based

Water based– In any event cleaning is really happening when we remove the contaminated carrier of the dissolved flux. 

Rinsing

Blow Drying

Extraction with absorbent material or force. 

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“Lint Free Wipes”

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Solder

Solder is not an adhesive– Not Adhesion, 

attachment by mechanical means, 

electrostatic forces, as in static electricity, hold the substances together

Van Der Waals forces that develop between molecules. 

moisture‐aided diffusion of the glue into the substrate, followed by hardening.

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Solder

Solder is not an adhesive– A process in which metals are joined by melting and flowing a filler metal, called solder, into the joint.

– The solder is drawn into the joint by capillary action. 

– A portion of the metals to be joined are dissolved into the solder forming a metallurgical  bond between the solder and metals to be joined.

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Solder joint structure

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Pb‐Free ball: SnPb Solder Diffusion

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Solder Paste

A mixture of snake oil and solder: – Thixotropy

The property of certain gels or fluids that are thick (viscous) under normal conditions, but flow (become thin, less viscous) over time when shaken, agitated, or otherwise stressed. 

– RheologyThe study of the flow of matter: mainly liquids but also soft solids or solids under conditions in which they flow rather than deform elastically.

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Solder Paste

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Solder Paste Failure

Powder oxidized 

Flux unable to reduce and permit “normal”behavior of solder. Coalescing of powder into a single fillet capable of wetting to the board and component terminations

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Methods ‐Machines

Solder Paste Deposition – Fluxing– Printing or Dispensing

Soldering– Reflow or Hand

Cleaning– Hand or Machines

Inspection– Visual or Automated

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Home Sweet Home

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Stencil Printing

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Dispensing

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Component Placement

Manual

Automated

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Automatic Component Placement

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Reflow Soldering

Convection and IR

Vapor Phase

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Hand Soldering

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Why did I break my board?

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Hand Cleaning

Spray cleaning

Steam Cleaning

Wipes get images

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Batch Cleaning

cleaning

Steam Cleaning

Wipes get images

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In‐Line Cleaning

Spray cleaning

Steam Cleaning

Wipes get images

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Vapor Phase Cleaning

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Inspection  ‐Visual

Standard Stereo Microscopes 

Ring lamps 

Mag rings probably not adequate

Machine vision 

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Manpower 

Certification

Training

Education

©© 2010 R&D Circuits2010 R&D Circuits

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Environment 

Temperature

Humidity

ESD

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Design for Assembly

Design is a series of compromises– Component Density

– Laminate Materials

– Layout

– Component Selection

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Surface Tension 

copper land patterns causing problems

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Gold Embrittlement

Gold in excess of about 4% of Solder

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PTH and SMT Land PatternDesign NO‐NO– Solder will drain down the hole leaving no solder fillet 

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Board Damage 

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Moisture Sensitive 

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Review

Overview of the Assembly Process

Using traditional Fish Bone Diagram – Materials

– Methods

– Machines

– Manpower

– Environment

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ATE Directions

New devices?

New chip manufacturing technology?– Flexibility

– Scalability

– Performance

– Support

– Cost

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Manufacturing Challenges

Flexibility– Variety of platforms

– Range of pin counts

– Pitch

– Multi‐site

– Process capabilities

©© 2010 R&D Circuits2010 R&D Circuits

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Manufacturing Challenges

Scalability– Manufacturing capability

Board to board

Lot to lot

– Multi‐site

– High pin count

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Manufacturing Challenges

Performance– Wider range of materials

– Controlled processImpedance

– Lot controls

©© 2010 R&D Circuits2010 R&D Circuits

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Manufacturing Challenges

Support– Vendor stability

– Vendor knowledge

– Vendor process capability

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Manufacturing Challenges

Cost– Layer counts (thicker boards?)

– Aspect ratio

– Line and space requirements

– Hole to copper dimensionsPitch

– Reliability

– DfA

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Sample Review

We have prepared and have available for review, a series of process panels 

representing each of the process steps we reviewed during today’s presentation. We can review and discuss any questions you may 

have.

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R&D Circuits

Founded in 1969

Privately Owned & Operated

~$15M in Sales, FY09

Full Turn‐Key Supplier– Design ‐ Layout

– Fabrication

– Assembly

– Sockets, Contactors, Interconnects

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R&D Circuits Locations

Mesa, AZ – Design Center

South Plainfield, NJ – PWB Fabrication

Allentown, PA – PWB Assembly

Singapore – Sales and Support, Asia

Penang, Malaysia